Add support for UEC to 8568
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
This commit is contained in:
Andy Fleming
Andrew Fleming-AFLEMING
parent
c59e4091ff
commit
da9d4610d7
3
Makefile
3
Makefile
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@ -212,6 +212,9 @@ LIBS += drivers/nand_legacy/libnand_legacy.a
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ifeq ($(CPU),mpc83xx)
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LIBS += drivers/qe/qe.a
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endif
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ifeq ($(CPU),mpc85xx)
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LIBS += drivers/qe/qe.a
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endif
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LIBS += drivers/sk98lin/libsk98lin.a
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LIBS += post/libpost.a post/drivers/libpostdrivers.a
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LIBS += $(shell if [ -d post/lib_$(ARCH) ]; then echo \
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@ -47,3 +47,10 @@ void disable_8568mds_flash_write()
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bcsr[9] &= ~(0x01);
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}
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void enable_8568mds_qe_mdio()
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{
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u8 *bcsr = (u8 *)(CFG_BCSR);
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bcsr[7] |= 0x01;
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}
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@ -95,5 +95,6 @@
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void enable_8568mds_duart(void);
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void enable_8568mds_flash_write(void);
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void disable_8568mds_flash_write(void);
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void enable_8568mds_qe_mdio(void);
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#endif /* __BCSR_H_ */
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@ -28,9 +28,65 @@
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#include <asm/immap_85xx.h>
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#include <spd.h>
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#include <i2c.h>
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#include <ioports.h>
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#include "bcsr.h"
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const qe_iop_conf_t qe_iop_conf_tab[] = {
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/* GETH1 */
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{4, 10, 1, 0, 2}, /* TxD0 */
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{4, 9, 1, 0, 2}, /* TxD1 */
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{4, 8, 1, 0, 2}, /* TxD2 */
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{4, 7, 1, 0, 2}, /* TxD3 */
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{4, 23, 1, 0, 2}, /* TxD4 */
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{4, 22, 1, 0, 2}, /* TxD5 */
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{4, 21, 1, 0, 2}, /* TxD6 */
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{4, 20, 1, 0, 2}, /* TxD7 */
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{4, 15, 2, 0, 2}, /* RxD0 */
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{4, 14, 2, 0, 2}, /* RxD1 */
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{4, 13, 2, 0, 2}, /* RxD2 */
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{4, 12, 2, 0, 2}, /* RxD3 */
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{4, 29, 2, 0, 2}, /* RxD4 */
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{4, 28, 2, 0, 2}, /* RxD5 */
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{4, 27, 2, 0, 2}, /* RxD6 */
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{4, 26, 2, 0, 2}, /* RxD7 */
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{4, 11, 1, 0, 2}, /* TX_EN */
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{4, 24, 1, 0, 2}, /* TX_ER */
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{4, 16, 2, 0, 2}, /* RX_DV */
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{4, 30, 2, 0, 2}, /* RX_ER */
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{4, 17, 2, 0, 2}, /* RX_CLK */
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{4, 19, 1, 0, 2}, /* GTX_CLK */
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{1, 31, 2, 0, 3}, /* GTX125 */
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/* GETH2 */
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{5, 10, 1, 0, 2}, /* TxD0 */
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{5, 9, 1, 0, 2}, /* TxD1 */
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{5, 8, 1, 0, 2}, /* TxD2 */
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{5, 7, 1, 0, 2}, /* TxD3 */
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{5, 23, 1, 0, 2}, /* TxD4 */
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{5, 22, 1, 0, 2}, /* TxD5 */
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{5, 21, 1, 0, 2}, /* TxD6 */
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{5, 20, 1, 0, 2}, /* TxD7 */
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{5, 15, 2, 0, 2}, /* RxD0 */
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{5, 14, 2, 0, 2}, /* RxD1 */
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{5, 13, 2, 0, 2}, /* RxD2 */
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{5, 12, 2, 0, 2}, /* RxD3 */
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{5, 29, 2, 0, 2}, /* RxD4 */
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{5, 28, 2, 0, 2}, /* RxD5 */
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{5, 27, 2, 0, 3}, /* RxD6 */
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{5, 26, 2, 0, 2}, /* RxD7 */
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{5, 11, 1, 0, 2}, /* TX_EN */
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{5, 24, 1, 0, 2}, /* TX_ER */
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{5, 16, 2, 0, 2}, /* RX_DV */
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{5, 30, 2, 0, 2}, /* RX_ER */
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{5, 17, 2, 0, 2}, /* RX_CLK */
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{5, 19, 1, 0, 2}, /* GTX_CLK */
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{1, 31, 2, 0, 3}, /* GTX125 */
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{4, 6, 3, 0, 2}, /* MDIO */
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{4, 5, 1, 0, 2}, /* MDC */
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{0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */
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};
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
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extern void ddr_enable_ecc(unsigned int dram_size);
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@ -50,6 +106,9 @@ int board_early_init_f (void)
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enable_8568mds_duart();
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enable_8568mds_flash_write();
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#if defined(CONFIG_QE) && !defined(CONFIG_eTSEC_MDIO_BUS)
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enable_8568mds_qe_mdio();
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#endif
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#ifdef CFG_I2C2_OFFSET
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/* Enable I2C2_SCL and I2C2_SDA */
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@ -335,6 +394,6 @@ pci_init_board(void)
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{
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#ifdef CONFIG_PCI
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pib_init();
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pci_mpc85xx_init(&hose);
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pci_mpc85xx_init(hose);
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#endif
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}
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@ -30,7 +30,7 @@ LIB = $(obj)lib$(CPU).a
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START = start.o resetvec.o
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COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o \
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pci.o serial_scc.o commproc.o ether_fcc.o spd_sdram.o
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pci.o serial_scc.o commproc.o ether_fcc.o spd_sdram.o qe_io.o
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SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
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@ -280,7 +280,7 @@ ft_cpu_setup(void *blob, bd_t *bd)
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if (p != NULL)
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*p = cpu_to_be32(clock);
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#if defined(CONFIG_TSEC1)
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#if defined(CONFIG_HAS_ETH0)
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p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len);
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if (p)
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memcpy(p, bd->bi_enetaddr, 6);
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@ -308,6 +308,17 @@ ft_cpu_setup(void *blob, bd_t *bd)
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p = ft_get_prop(blob, "/" OF_SOC "/ethernet@26000/local-mac-address", &len);
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if (p)
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memcpy(p, bd->bi_enet2addr, 6);
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#ifdef CONFIG_UEC_ETH
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p = ft_get_prop(blob, "/" OF_QE "/ucc@2000/mac-address", &len);
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if (p)
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memcpy(p, bd->bi_enet2addr, 6);
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p = ft_get_prop(blob, "/" OF_QE "/ucc@2000/local-mac-address", &len);
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if (p)
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memcpy(p, bd->bi_enet2addr, 6);
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#endif
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#endif
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#if defined(CONFIG_HAS_ETH3)
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@ -318,6 +329,17 @@ ft_cpu_setup(void *blob, bd_t *bd)
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p = ft_get_prop(blob, "/" OF_SOC "/ethernet@27000/local-mac-address", &len);
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if (p)
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memcpy(p, bd->bi_enet3addr, 6);
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#ifdef CONFIG_UEC_ETH
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p = ft_get_prop(blob, "/" OF_QE "/ucc@3000/mac-address", &len);
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if (p)
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memcpy(p, bd->bi_enet3addr, 6);
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p = ft_get_prop(blob, "/" OF_QE "/ucc@3000/local-mac-address", &len);
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if (p)
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memcpy(p, bd->bi_enet3addr, 6);
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#endif
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#endif
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}
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@ -34,6 +34,29 @@
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_QE
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extern qe_iop_conf_t qe_iop_conf_tab[];
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extern void qe_config_iopin(u8 port, u8 pin, int dir,
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int open_drain, int assign);
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extern void qe_init(uint qe_base);
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extern void qe_reset(void);
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static void config_qe_ioports(void)
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{
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u8 port, pin;
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int dir, open_drain, assign;
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int i;
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for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
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port = qe_iop_conf_tab[i].port;
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pin = qe_iop_conf_tab[i].pin;
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dir = qe_iop_conf_tab[i].dir;
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open_drain = qe_iop_conf_tab[i].open_drain;
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assign = qe_iop_conf_tab[i].assign;
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qe_config_iopin(port, pin, dir, open_drain, assign);
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}
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}
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#endif
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#ifdef CONFIG_CPM2
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static void config_8560_ioports (volatile immap_t * immr)
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@ -181,6 +204,11 @@ void cpu_init_f (void)
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#if defined(CONFIG_CPM2)
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m8560_cpm_reset();
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#endif
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#ifdef CONFIG_QE
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/* Config QE ioports */
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config_qe_ioports();
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#endif
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}
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@ -262,6 +290,11 @@ int cpu_init_r(void)
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#else
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printf("L2 cache: disabled\n");
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#endif
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#ifdef CONFIG_QE
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uint qe_base = CFG_IMMR + 0x00080000; /* QE immr base */
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qe_init(qe_base);
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qe_reset();
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#endif
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return 0;
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}
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@ -0,0 +1,85 @@
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/*
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* Copyright (C) 2006 Freescale Semiconductor, Inc.
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*
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* Dave Liu <daveliu@freescale.com>
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* based on source code of Shlomi Gridish
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include "common.h"
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#include "asm/errno.h"
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#include "asm/io.h"
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#include "asm/immap_85xx.h"
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#if defined(CONFIG_QE)
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#define NUM_OF_PINS 32
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void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign)
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{
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u32 pin_2bit_mask;
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u32 pin_2bit_dir;
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u32 pin_2bit_assign;
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u32 pin_1bit_mask;
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u32 tmp_val;
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volatile immap_t *im = (volatile immap_t *)CFG_IMMR;
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volatile par_io_t *par_io = (volatile par_io_t *)
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&(im->im_gur.qe_par_io);
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/* Caculate pin location and 2bit mask and dir */
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pin_2bit_mask = (u32)(0x3 << (NUM_OF_PINS-(pin%(NUM_OF_PINS/2)+1)*2));
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pin_2bit_dir = (u32)(dir << (NUM_OF_PINS-(pin%(NUM_OF_PINS/2)+1)*2));
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/* Setup the direction */
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tmp_val = (pin > (NUM_OF_PINS/2) - 1) ? \
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in_be32(&par_io[port].cpdir2) :
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in_be32(&par_io[port].cpdir1);
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if (pin > (NUM_OF_PINS/2) -1) {
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out_be32(&par_io[port].cpdir2, ~pin_2bit_mask & tmp_val);
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out_be32(&par_io[port].cpdir2, pin_2bit_dir | tmp_val);
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} else {
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out_be32(&par_io[port].cpdir1, ~pin_2bit_mask & tmp_val);
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out_be32(&par_io[port].cpdir1, pin_2bit_dir | tmp_val);
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}
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/* Calculate pin location for 1bit mask */
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pin_1bit_mask = (u32)(1 << (NUM_OF_PINS - (pin+1)));
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/* Setup the open drain */
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tmp_val = in_be32(&par_io[port].cpodr);
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if (open_drain)
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out_be32(&par_io[port].cpodr, pin_1bit_mask | tmp_val);
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else
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out_be32(&par_io[port].cpodr, ~pin_1bit_mask & tmp_val);
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/* Setup the assignment */
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tmp_val = (pin > (NUM_OF_PINS/2) - 1) ?
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in_be32(&par_io[port].cppar2):
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in_be32(&par_io[port].cppar1);
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pin_2bit_assign = (u32)(assign
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<< (NUM_OF_PINS - (pin%(NUM_OF_PINS/2)+1)*2));
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/* Clear and set 2 bits mask */
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if (pin > (NUM_OF_PINS/2) - 1) {
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out_be32(&par_io[port].cppar2, ~pin_2bit_mask & tmp_val);
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out_be32(&par_io[port].cppar2, pin_2bit_assign | tmp_val);
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} else {
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out_be32(&par_io[port].cppar1, ~pin_2bit_mask & tmp_val);
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out_be32(&par_io[port].cppar1, pin_2bit_assign | tmp_val);
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}
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}
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#endif /* CONFIG_QE */
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@ -391,17 +391,17 @@ static int uec_set_mac_if_mode(uec_private_t *uec, enet_interface_e if_mode)
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return 0;
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}
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static int init_mii_management_configuration(uec_t *uec_regs)
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static int init_mii_management_configuration(uec_mii_t *uec_mii_regs)
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{
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uint timeout = 0x1000;
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u32 miimcfg = 0;
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miimcfg = in_be32(&uec_regs->miimcfg);
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miimcfg = in_be32(&uec_mii_regs->miimcfg);
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miimcfg |= MIIMCFG_MNGMNT_CLC_DIV_INIT_VALUE;
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out_be32(&uec_regs->miimcfg, miimcfg);
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out_be32(&uec_mii_regs->miimcfg, miimcfg);
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/* Wait until the bus is free */
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while ((in_be32(&uec_regs->miimcfg) & MIIMIND_BUSY) && timeout--);
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while ((in_be32(&uec_mii_regs->miimcfg) & MIIMIND_BUSY) && timeout--);
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if (timeout <= 0) {
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printf("%s: The MII Bus is stuck!", __FUNCTION__);
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return -ETIMEDOUT;
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@ -413,13 +413,13 @@ static int init_mii_management_configuration(uec_t *uec_regs)
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static int init_phy(struct eth_device *dev)
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{
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uec_private_t *uec;
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uec_t *uec_regs;
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uec_mii_t *umii_regs;
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struct uec_mii_info *mii_info;
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struct phy_info *curphy;
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int err;
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uec = (uec_private_t *)dev->priv;
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uec_regs = uec->uec_regs;
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umii_regs = uec->uec_mii_regs;
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uec->oldlink = 0;
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uec->oldspeed = 0;
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@ -451,19 +451,19 @@ static int init_phy(struct eth_device *dev)
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mii_info->mii_id = uec->uec_info->phy_address;
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mii_info->dev = dev;
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mii_info->mdio_read = &read_phy_reg;
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mii_info->mdio_write = &write_phy_reg;
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mii_info->mdio_read = &uec_read_phy_reg;
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mii_info->mdio_write = &uec_write_phy_reg;
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uec->mii_info = mii_info;
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if (init_mii_management_configuration(uec_regs)) {
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if (init_mii_management_configuration(umii_regs)) {
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printf("%s: The MII Bus is stuck!", dev->name);
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err = -1;
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goto bus_fail;
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}
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/* get info for this PHY */
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curphy = get_phy_info(uec->mii_info);
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curphy = uec_get_phy_info(uec->mii_info);
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if (!curphy) {
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printf("%s: No PHY found", dev->name);
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err = -1;
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@ -989,6 +989,13 @@ static int uec_startup(uec_private_t *uec)
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/* Setup MAC interface mode */
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uec_set_mac_if_mode(uec, uec_info->enet_interface);
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/* Setup MII management base */
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#ifndef CONFIG_eTSEC_MDIO_BUS
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uec->uec_mii_regs = (uec_mii_t *)(&uec_regs->miimcfg);
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#else
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uec->uec_mii_regs = (uec_mii_t *) CONFIG_MIIM_ADDRESS;
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#endif
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/* Setup MII master clock source */
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qe_set_mii_clk_src(uec_info->uf_info.ucc_num);
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@ -675,6 +675,7 @@ typedef struct uec_private {
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ucc_fast_private_t *uccf;
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struct eth_device *dev;
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uec_t *uec_regs;
|
||||
uec_mii_t *uec_mii_regs;
|
||||
/* enet init command parameter */
|
||||
uec_init_cmd_pram_t *p_init_enet_param;
|
||||
u32 init_enet_param_offset;
|
||||
|
|
|
|||
|
|
@ -60,14 +60,14 @@ void phy_write (struct uec_mii_info *mii_info, u16 regnum, u16 val);
|
|||
/* Write value to the PHY for this device to the register at regnum, */
|
||||
/* waiting until the write is done before it returns. All PHY */
|
||||
/* configuration has to be done through the TSEC1 MIIM regs */
|
||||
void write_phy_reg (struct eth_device *dev, int mii_id, int regnum, int value)
|
||||
void uec_write_phy_reg (struct eth_device *dev, int mii_id, int regnum, int value)
|
||||
{
|
||||
uec_private_t *ugeth = (uec_private_t *) dev->priv;
|
||||
uec_t *ug_regs;
|
||||
uec_mii_t *ug_regs;
|
||||
enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e) regnum;
|
||||
u32 tmp_reg;
|
||||
|
||||
ug_regs = ugeth->uec_regs;
|
||||
ug_regs = ugeth->uec_mii_regs;
|
||||
|
||||
/* Stop the MII management read cycle */
|
||||
out_be32 (&ug_regs->miimcom, 0);
|
||||
|
|
@ -87,15 +87,15 @@ void write_phy_reg (struct eth_device *dev, int mii_id, int regnum, int value)
|
|||
/* Reads from register regnum in the PHY for device dev, */
|
||||
/* returning the value. Clears miimcom first. All PHY */
|
||||
/* configuration has to be done through the TSEC1 MIIM regs */
|
||||
int read_phy_reg (struct eth_device *dev, int mii_id, int regnum)
|
||||
int uec_read_phy_reg (struct eth_device *dev, int mii_id, int regnum)
|
||||
{
|
||||
uec_private_t *ugeth = (uec_private_t *) dev->priv;
|
||||
uec_t *ug_regs;
|
||||
uec_mii_t *ug_regs;
|
||||
enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e) regnum;
|
||||
u32 tmp_reg;
|
||||
u16 value;
|
||||
|
||||
ug_regs = ugeth->uec_regs;
|
||||
ug_regs = ugeth->uec_mii_regs;
|
||||
|
||||
/* Setting up the MII Mangement Address Register */
|
||||
tmp_reg = ((u32) mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg;
|
||||
|
|
@ -521,7 +521,7 @@ void phy_write (struct uec_mii_info *mii_info, u16 regnum, u16 val)
|
|||
/* Use the PHY ID registers to determine what type of PHY is attached
|
||||
* to device dev. return a struct phy_info structure describing that PHY
|
||||
*/
|
||||
struct phy_info *get_phy_info (struct uec_mii_info *mii_info)
|
||||
struct phy_info *uec_get_phy_info (struct uec_mii_info *mii_info)
|
||||
{
|
||||
u16 phy_reg;
|
||||
u32 phy_ID;
|
||||
|
|
|
|||
|
|
@ -249,10 +249,10 @@ struct phy_info {
|
|||
void (*close) (struct uec_mii_info * mii_info);
|
||||
};
|
||||
|
||||
struct phy_info *get_phy_info (struct uec_mii_info *mii_info);
|
||||
void write_phy_reg (struct eth_device *dev, int mii_id, int regnum,
|
||||
struct phy_info *uec_get_phy_info (struct uec_mii_info *mii_info);
|
||||
void uec_write_phy_reg (struct eth_device *dev, int mii_id, int regnum,
|
||||
int value);
|
||||
int read_phy_reg (struct eth_device *dev, int mii_id, int regnum);
|
||||
int uec_read_phy_reg (struct eth_device *dev, int mii_id, int regnum);
|
||||
void mii_clear_phy_interrupt (struct uec_mii_info *mii_info);
|
||||
void mii_configure_phy_interrupt (struct uec_mii_info *mii_info,
|
||||
u32 interrupts);
|
||||
|
|
|
|||
|
|
@ -71,16 +71,16 @@ typedef struct global_data {
|
|||
u32 lclk_clk;
|
||||
u32 ddr_clk;
|
||||
u32 pci_clk;
|
||||
#if defined(CONFIG_MPC8360)
|
||||
u32 ddr_sec_clk;
|
||||
#endif /* CONFIG_MPC8360 */
|
||||
#endif
|
||||
#if defined(CONFIG_QE)
|
||||
u32 qe_clk;
|
||||
u32 brg_clk;
|
||||
uint mp_alloc_base;
|
||||
uint mp_alloc_top;
|
||||
#endif /* CONFIG_QE */
|
||||
#if defined (CONFIG_MPC8360)
|
||||
u32 ddr_sec_clk;
|
||||
#endif /* CONFIG_MPC8360 */
|
||||
#endif
|
||||
#if defined(CONFIG_MPC5xxx)
|
||||
unsigned long ipb_clk;
|
||||
unsigned long pci_clk;
|
||||
|
|
|
|||
|
|
@ -281,6 +281,17 @@ typedef struct ucc_slow {
|
|||
u8 res4[0x200 - 0x091];
|
||||
} __attribute__ ((packed)) ucc_slow_t;
|
||||
|
||||
typedef struct ucc_mii_mng {
|
||||
u32 miimcfg; /* MII management configuration reg */
|
||||
u32 miimcom; /* MII management command reg */
|
||||
u32 miimadd; /* MII management address reg */
|
||||
u32 miimcon; /* MII management control reg */
|
||||
u32 miimstat; /* MII management status reg */
|
||||
u32 miimind; /* MII management indication reg */
|
||||
u32 ifctl; /* interface control reg */
|
||||
u32 ifstat; /* interface statux reg */
|
||||
} __attribute__ ((packed))uec_mii_t;
|
||||
|
||||
typedef struct ucc_ethernet {
|
||||
u32 maccfg1; /* mac configuration reg. 1 */
|
||||
u32 maccfg2; /* mac configuration reg. 2 */
|
||||
|
|
@ -540,14 +551,21 @@ typedef struct qe_immap {
|
|||
u8 res14[0x300];
|
||||
u8 res15[0x3A00];
|
||||
u8 res16[0x8000]; /* 0x108000 - 0x110000 */
|
||||
#if defined(CONFIG_MPC8568)
|
||||
u8 muram[0x10000]; /* 0x1_0000 - 0x2_0000 Multi-user RAM */
|
||||
u8 res17[0x20000]; /* 0x2_0000 - 0x4_0000 */
|
||||
#else
|
||||
u8 muram[0xC000]; /* 0x110000 - 0x11C000 Multi-user RAM */
|
||||
u8 res17[0x24000]; /* 0x11C000 - 0x140000 */
|
||||
u8 res18[0xC0000]; /* 0x140000 - 0x200000 */
|
||||
#endif
|
||||
} __attribute__ ((packed)) qe_map_t;
|
||||
|
||||
extern qe_map_t *qe_immr;
|
||||
|
||||
#if defined(CONFIG_MPC8360)
|
||||
#if defined(CONFIG_MPC8568)
|
||||
#define QE_MURAM_SIZE 0x10000UL
|
||||
#elif defined(CONFIG_MPC8360)
|
||||
#define QE_MURAM_SIZE 0xc000UL
|
||||
#elif defined(CONFIG_MPC832X)
|
||||
#define QE_MURAM_SIZE 0x4000UL
|
||||
|
|
|
|||
|
|
@ -28,20 +28,21 @@
|
|||
|
||||
/* High Level Configuration Options */
|
||||
#define CONFIG_BOOKE 1 /* BOOKE */
|
||||
#define CONFIG_E500 1 /* BOOKE e500 family */
|
||||
#define CONFIG_E500 1 /* BOOKE e500 family */
|
||||
#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/68 */
|
||||
#define CONFIG_MPC8568 1 /* MPC8568 specific */
|
||||
#define CONFIG_MPC8568MDS 1 /* MPC8568MDS board specific */
|
||||
|
||||
#define CONFIG_PCI
|
||||
#define CONFIG_TSEC_ENET /* tsec ethernet support */
|
||||
#undef CONFIG_QE /* Enable QE */
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
|
||||
#define CONFIG_DDR_DLL /* possible DLL fix needed */
|
||||
/*#define CONFIG_DDR_2T_TIMING Sets the 2T timing bit */
|
||||
|
||||
/*#define CONFIG_DDR_ECC*/ /* only for ECC DDR module */
|
||||
/*#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER*/ /* DDR controller or DMA? */
|
||||
/*#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER*/ /* DDR controller or DMA? */
|
||||
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
|
||||
|
||||
|
||||
|
|
@ -297,6 +298,7 @@ extern unsigned long get_clock_freq(void);
|
|||
|
||||
#define OF_CPU "PowerPC,8568@0"
|
||||
#define OF_SOC "soc8568@e0000000"
|
||||
#define OF_QE "qe@e0080000"
|
||||
#define OF_TBCLK (bd->bi_busfreq / 8)
|
||||
#define OF_STDOUT_PATH "/soc8568@e0000000/serial@4600"
|
||||
|
||||
|
|
@ -311,7 +313,7 @@ extern unsigned long get_clock_freq(void);
|
|||
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
|
||||
#define CFG_I2C_EEPROM_ADDR 0x52
|
||||
#define CFG_I2C_SLAVE 0x7F
|
||||
#define CFG_I2C_NOPROBES {0,0x69} /* Don't probe these addrs */
|
||||
#define CFG_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */
|
||||
#define CFG_I2C_OFFSET 0x3000
|
||||
#define CFG_I2C2_OFFSET 0x3100
|
||||
|
||||
|
|
@ -340,6 +342,44 @@ extern unsigned long get_clock_freq(void);
|
|||
#define CONFIG_NET_MULTI
|
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */
|
||||
|
||||
#ifdef CONFIG_QE
|
||||
/*
|
||||
* QE UEC ethernet configuration
|
||||
*/
|
||||
#define CONFIG_UEC_ETH
|
||||
#ifndef CONFIG_TSEC_ENET
|
||||
#define CONFIG_ETHPRIME "Freescale GETH"
|
||||
#endif
|
||||
#define CONFIG_PHY_MODE_NEED_CHANGE
|
||||
#define CONFIG_eTSEC_MDIO_BUS
|
||||
|
||||
#ifdef CONFIG_eTSEC_MDIO_BUS
|
||||
#define CONFIG_MIIM_ADDRESS 0xE0024520
|
||||
#endif
|
||||
|
||||
#define CONFIG_UEC_ETH1 /* GETH1 */
|
||||
|
||||
#ifdef CONFIG_UEC_ETH1
|
||||
#define CFG_UEC1_UCC_NUM 0 /* UCC1 */
|
||||
#define CFG_UEC1_RX_CLK QE_CLK_NONE
|
||||
#define CFG_UEC1_TX_CLK QE_CLK16
|
||||
#define CFG_UEC1_ETH_TYPE GIGA_ETH
|
||||
#define CFG_UEC1_PHY_ADDR 7
|
||||
#define CFG_UEC1_INTERFACE_MODE ENET_1000_GMII
|
||||
#endif
|
||||
|
||||
#define CONFIG_UEC_ETH2 /* GETH2 */
|
||||
|
||||
#ifdef CONFIG_UEC_ETH2
|
||||
#define CFG_UEC2_UCC_NUM 1 /* UCC2 */
|
||||
#define CFG_UEC2_RX_CLK QE_CLK_NONE
|
||||
#define CFG_UEC2_TX_CLK QE_CLK16
|
||||
#define CFG_UEC2_ETH_TYPE GIGA_ETH
|
||||
#define CFG_UEC2_PHY_ADDR 1
|
||||
#define CFG_UEC2_INTERFACE_MODE ENET_1000_GMII
|
||||
#endif
|
||||
#endif /* CONFIG_QE */
|
||||
|
||||
#undef CONFIG_EEPRO100
|
||||
#undef CONFIG_TULIP
|
||||
|
||||
|
|
@ -348,13 +388,12 @@ extern unsigned long get_clock_freq(void);
|
|||
|
||||
#endif /* CONFIG_PCI */
|
||||
|
||||
|
||||
#if defined(CONFIG_TSEC_ENET)
|
||||
|
||||
#ifndef CONFIG_NET_MULTI
|
||||
#define CONFIG_NET_MULTI 1
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_TSEC_ENET)
|
||||
|
||||
#define CONFIG_MII 1 /* MII PHY management */
|
||||
#define CONFIG_TSEC1 1
|
||||
#define CONFIG_TSEC1_NAME "eTSEC0"
|
||||
|
|
@ -460,12 +499,15 @@ extern unsigned long get_clock_freq(void);
|
|||
*/
|
||||
|
||||
/* The mac addresses for all ethernet interface */
|
||||
#if defined(CONFIG_TSEC_ENET)
|
||||
#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_UEC_ETH)
|
||||
#define CONFIG_HAS_ETH0
|
||||
#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
|
||||
#define CONFIG_HAS_ETH1
|
||||
#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
|
||||
#define CONFIG_HAS_ETH2
|
||||
#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
|
||||
#define CONFIG_HAS_ETH3
|
||||
#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD
|
||||
#endif
|
||||
|
||||
#define CONFIG_IPADDR 192.168.1.253
|
||||
|
|
|
|||
Loading…
Reference in New Issue