Add generic support for samsung s3c2440

This patch adds generic support for the Samsung s3c2440 processor.

Global s3c24x0 changes to struct members converting from upper case to
lower case.

Signed-off-by: Craig Nauman <cnauman@diagraph.com>
Cc: kevin.morfitt@fearnside-systems.co.uk
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This commit is contained in:
C Nauman 2010-10-26 23:04:31 +09:00 committed by Minkyu Kang
parent 1628cfc4fe
commit d9abba8254
22 changed files with 1006 additions and 730 deletions

View File

@ -54,9 +54,9 @@ static ulong get_PLLCLK(int pllreg)
ulong r, m, p, s;
if (pllreg == MPLL)
r = readl(&clk_power->MPLLCON);
r = readl(&clk_power->mpllcon);
else if (pllreg == UPLL)
r = readl(&clk_power->UPLLCON);
r = readl(&clk_power->upllcon);
else
hang();
@ -64,7 +64,12 @@ static ulong get_PLLCLK(int pllreg)
p = ((r & 0x003F0) >> 4) + 2;
s = r & 0x3;
#if defined(CONFIG_S3C2440)
if (pllreg == MPLL)
return 2 * m * (CONFIG_SYS_CLK_FREQ / (p << s));
#endif
return (CONFIG_SYS_CLK_FREQ * m) / (p << s);
}
/* return FCLK frequency */
@ -77,8 +82,23 @@ ulong get_FCLK(void)
ulong get_HCLK(void)
{
struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
return (readl(&clk_power->CLKDIVN) & 2) ? get_FCLK() / 2 : get_FCLK();
#ifdef CONFIG_S3C2440
switch (readl(&clk_power->clkdivn) & 0x6) {
default:
case 0:
return get_FCLK();
case 2:
return get_FCLK() / 2;
case 4:
return (readl(&clk_power->camdivn) & (1 << 9)) ?
get_FCLK() / 8 : get_FCLK() / 4;
case 6:
return (readl(&clk_power->camdivn) & (1 << 8)) ?
get_FCLK() / 6 : get_FCLK() / 3;
}
#else
return (readl(&clk_power->clkdivn) & 2) ? get_FCLK() / 2 : get_FCLK();
#endif
}
/* return PCLK frequency */
@ -86,7 +106,7 @@ ulong get_PCLK(void)
{
struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
return (readl(&clk_power->CLKDIVN) & 1) ? get_HCLK() / 2 : get_HCLK();
return (readl(&clk_power->clkdivn) & 1) ? get_HCLK() / 2 : get_HCLK();
}
/* return UCLK frequency */

View File

@ -43,7 +43,7 @@ static inline ulong READ_TIMER(void)
{
struct s3c24x0_timers *timers = s3c24x0_get_base_timers();
return readl(&timers->TCNTO4) & 0xffff;
return readl(&timers->tcnto4) & 0xffff;
}
static ulong timestamp;
@ -56,7 +56,7 @@ int timer_init(void)
/* use PWM Timer 4 because it has no output */
/* prescaler for Timer 4 is 16 */
writel(0x0f00, &timers->TCFG0);
writel(0x0f00, &timers->tcfg0);
if (timer_load_val == 0) {
/*
* for 10 ms clock period @ PCLK with 4 bit divider = 1/2
@ -68,13 +68,13 @@ int timer_init(void)
}
/* load value for 10 ms timeout */
lastdec = timer_load_val;
writel(timer_load_val, &timers->TCNTB4);
/* auto load, manual update of Timer 4 */
tmr = (readl(&timers->TCON) & ~0x0700000) | 0x0600000;
writel(tmr, &timers->TCON);
/* auto load, start Timer 4 */
writel(timer_load_val, &timers->tcntb4);
/* auto load, manual update of timer 4 */
tmr = (readl(&timers->tcon) & ~0x0700000) | 0x0600000;
writel(tmr, &timers->tcon);
/* auto load, start timer 4 */
tmr = (tmr & ~0x0700000) | 0x0500000;
writel(tmr, &timers->TCON);
writel(tmr, &timers->tcon);
timestamp = 0;
return (0);
@ -181,6 +181,7 @@ ulong get_tbclk(void)
tbclk = timer_load_val * 100;
#elif defined(CONFIG_SBC2410X) || \
defined(CONFIG_SMDK2410) || \
defined(CONFIG_S3C2440) || \
defined(CONFIG_VCMA9)
tbclk = CONFIG_SYS_HZ;
#else
@ -206,13 +207,13 @@ void reset_cpu(ulong ignored)
watchdog = s3c24x0_get_base_watchdog();
/* Disable watchdog */
writel(0x0000, &watchdog->WTCON);
writel(0x0000, &watchdog->wtcon);
/* Initialize watchdog timer count register */
writel(0x0001, &watchdog->WTCNT);
writel(0x0001, &watchdog->wtcnt);
/* Enable watchdog timer; assert reset at timer timeout */
writel(0x0021, &watchdog->WTCON);
writel(0x0021, &watchdog->wtcon);
while (1)
/* loop forever and wait for reset to happen */;

View File

@ -39,14 +39,14 @@ int usb_cpu_init(void)
* Set the 48 MHz UPLL clocking. Values are taken from
* "PLL value selection guide", 6-23, s3c2400_UM.pdf.
*/
writel((40 << 12) + (1 << 4) + 2, &clk_power->UPLLCON);
writel((40 << 12) + (1 << 4) + 2, &clk_power->upllcon);
/* 1 = use pads related USB for USB host */
writel(readl(&gpio->MISCCR) | 0x8, &gpio->MISCCR);
writel(readl(&gpio->misccr) | 0x8, &gpio->misccr);
/*
* Enable USB host clock.
*/
writel(readl(&clk_power->CLKCON) | (1 << 4), &clk_power->CLKCON);
writel(readl(&clk_power->clkcon) | (1 << 4), &clk_power->clkcon);
return 0;
}
@ -55,14 +55,14 @@ int usb_cpu_stop(void)
{
struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
/* may not want to do this */
writel(readl(&clk_power->CLKCON) & ~(1 << 4), &clk_power->CLKCON);
writel(readl(&clk_power->clkcon) & ~(1 << 4), &clk_power->clkcon);
return 0;
}
int usb_cpu_init_fail(void)
{
struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
writel(readl(&clk_power->CLKCON) & ~(1 << 4), &clk_power->CLKCON);
writel(readl(&clk_power->clkcon) & ~(1 << 4), &clk_power->clkcon);
return 0;
}

View File

@ -1666,13 +1666,13 @@ int usb_lowlevel_init(void)
* Set the 48 MHz UPLL clocking. Values are taken from
* "PLL value selection guide", 6-23, s3c2400_UM.pdf.
*/
clk_power->UPLLCON = ((40 << 12) + (1 << 4) + 2);
gpio->MISCCR |= 0x8; /* 1 = use pads related USB for USB host */
clk_power->upllcon = ((40 << 12) + (1 << 4) + 2);
gpio->misccr |= 0x8; /* 1 = use pads related USB for USB host */
/*
* Enable USB host clock.
*/
clk_power->CLKCON |= (1 << 4);
clk_power->clkcon |= (1 << 4);
memset(&gohci, 0, sizeof(struct ohci));
memset(&urb_priv, 0, sizeof(struct urb_priv));
@ -1709,7 +1709,7 @@ int usb_lowlevel_init(void)
if (hc_reset(&gohci) < 0) {
hc_release_ohci(&gohci);
/* Initialization failed */
clk_power->CLKCON &= ~(1 << 4);
clk_power->clkcon &= ~(1 << 4);
return -1;
}
@ -1722,7 +1722,7 @@ int usb_lowlevel_init(void)
err("can't start usb-%s", gohci.slot_name);
hc_release_ohci(&gohci);
/* Initialization failed */
clk_power->CLKCON &= ~(1 << 4);
clk_power->clkcon &= ~(1 << 4);
return -1;
}
#ifdef DEBUG
@ -1748,7 +1748,7 @@ int usb_lowlevel_stop(void)
/* call hc_release_ohci() here ? */
hc_reset(&gohci);
/* may not want to do this */
clk_power->CLKCON &= ~(1 << 4);
clk_power->clkcon &= ~(1 << 4);
return 0;
}

View File

@ -0,0 +1,161 @@
/*
* (C) Copyright 2003
* David Mueller ELSOFT AG Switzerland. d.mueller@elsoft.ch
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/************************************************
* NAME : s3c2440.h
* Version : 31.3.2003
*
* Based on S3C2440 User's manual Rev x.x
************************************************/
#ifndef __S3C2440_H__
#define __S3C2440_H__
#define S3C24X0_UART_CHANNELS 3
#define S3C24X0_SPI_CHANNELS 2
/* S3C2440 only supports 512 Byte HW ECC */
#define S3C2440_ECCSIZE 512
#define S3C2440_ECCBYTES 3
enum s3c24x0_uarts_nr {
S3C24X0_UART0,
S3C24X0_UART1,
S3C24X0_UART2
};
/* S3C2440 device base addresses */
#define S3C24X0_MEMCTL_BASE 0x48000000
#define S3C24X0_USB_HOST_BASE 0x49000000
#define S3C24X0_INTERRUPT_BASE 0x4A000000
#define S3C24X0_DMA_BASE 0x4B000000
#define S3C24X0_CLOCK_POWER_BASE 0x4C000000
#define S3C24X0_LCD_BASE 0x4D000000
#define S3C2440_NAND_BASE 0x4E000000
#define S3C24X0_UART_BASE 0x50000000
#define S3C24X0_TIMER_BASE 0x51000000
#define S3C24X0_USB_DEVICE_BASE 0x52000140
#define S3C24X0_WATCHDOG_BASE 0x53000000
#define S3C24X0_I2C_BASE 0x54000000
#define S3C24X0_I2S_BASE 0x55000000
#define S3C24X0_GPIO_BASE 0x56000000
#define S3C24X0_RTC_BASE 0x57000000
#define S3C2440_ADC_BASE 0x58000000
#define S3C24X0_SPI_BASE 0x59000000
#define S3C2440_SDI_BASE 0x5A000000
/* include common stuff */
#include <asm/arch/s3c24x0.h>
static inline struct s3c24x0_memctl *s3c24x0_get_base_memctl(void)
{
return (struct s3c24x0_memctl *)S3C24X0_MEMCTL_BASE;
}
static inline struct s3c24x0_usb_host *s3c24x0_get_base_usb_host(void)
{
return (struct s3c24x0_usb_host *)S3C24X0_USB_HOST_BASE;
}
static inline struct s3c24x0_interrupt *s3c24x0_get_base_interrupt(void)
{
return (struct s3c24x0_interrupt *)S3C24X0_INTERRUPT_BASE;
}
static inline struct s3c24x0_dmas *s3c24x0_get_base_dmas(void)
{
return (struct s3c24x0_dmas *)S3C24X0_DMA_BASE;
}
static inline struct s3c24x0_clock_power *s3c24x0_get_base_clock_power(void)
{
return (struct s3c24x0_clock_power *)S3C24X0_CLOCK_POWER_BASE;
}
static inline struct s3c24x0_lcd *s3c24x0_get_base_lcd(void)
{
return (struct s3c24x0_lcd *)S3C24X0_LCD_BASE;
}
static inline struct s3c2440_nand *s3c2440_get_base_nand(void)
{
return (struct s3c2440_nand *)S3C2440_NAND_BASE;
}
static inline struct s3c24x0_uart
*s3c24x0_get_base_uart(enum s3c24x0_uarts_nr n)
{
return (struct s3c24x0_uart *)(S3C24X0_UART_BASE + (n * 0x4000));
}
static inline struct s3c24x0_timers *s3c24x0_get_base_timers(void)
{
return (struct s3c24x0_timers *)S3C24X0_TIMER_BASE;
}
static inline struct s3c24x0_usb_device *s3c24x0_get_base_usb_device(void)
{
return (struct s3c24x0_usb_device *)S3C24X0_USB_DEVICE_BASE;
}
static inline struct s3c24x0_watchdog *s3c24x0_get_base_watchdog(void)
{
return (struct s3c24x0_watchdog *)S3C24X0_WATCHDOG_BASE;
}
static inline struct s3c24x0_i2c *s3c24x0_get_base_i2c(void)
{
return (struct s3c24x0_i2c *)S3C24X0_I2C_BASE;
}
static inline struct s3c24x0_i2s *s3c24x0_get_base_i2s(void)
{
return (struct s3c24x0_i2s *)S3C24X0_I2S_BASE;
}
static inline struct s3c24x0_gpio *s3c24x0_get_base_gpio(void)
{
return (struct s3c24x0_gpio *)S3C24X0_GPIO_BASE;
}
static inline struct s3c24x0_rtc *s3c24x0_get_base_rtc(void)
{
return (struct s3c24x0_rtc *)S3C24X0_RTC_BASE;
}
static inline struct s3c2440_adc *s3c2440_get_base_adc(void)
{
return (struct s3c2440_adc *)S3C2440_ADC_BASE;
}
static inline struct s3c24x0_spi *s3c24x0_get_base_spi(void)
{
return (struct s3c24x0_spi *)S3C24X0_SPI_BASE;
}
static inline struct s3c2440_sdi *s3c2440_get_base_sdi(void)
{
return (struct s3c2440_sdi *)S3C2440_SDI_BASE;
}
#endif /*__S3C2440_H__*/

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@ -33,12 +33,12 @@
/* Memory controller (see manual chapter 5) */
struct s3c24x0_memctl {
u32 BWSCON;
u32 BANKCON[8];
u32 REFRESH;
u32 BANKSIZE;
u32 MRSRB6;
u32 MRSRB7;
u32 bwscon;
u32 bankcon[8];
u32 refresh;
u32 banksize;
u32 mrsrb6;
u32 mrsrb7;
};
@ -72,40 +72,38 @@ struct s3c24x0_usb_host {
/* INTERRUPT (see manual chapter 14) */
struct s3c24x0_interrupt {
u32 SRCPND;
u32 INTMOD;
u32 INTMSK;
u32 PRIORITY;
u32 INTPND;
u32 INTOFFSET;
#ifdef CONFIG_S3C2410
u32 SUBSRCPND;
u32 INTSUBMSK;
u32 srcpnd;
u32 intmod;
u32 intmsk;
u32 priority;
u32 intpnd;
u32 intoffset;
#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
u32 subsrcpnd;
u32 intsubmsk;
#endif
};
/* DMAS (see manual chapter 8) */
struct s3c24x0_dma {
u32 DISRC;
#ifdef CONFIG_S3C2410
u32 DISRCC;
u32 disrc;
#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
u32 disrcc;
#endif
u32 DIDST;
#ifdef CONFIG_S3C2410
u32 DIDSTC;
u32 didst;
#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
u32 didstc;
#endif
u32 DCON;
u32 DSTAT;
u32 DCSRC;
u32 DCDST;
u32 DMASKTRIG;
#ifdef CONFIG_S3C2400
u32 dcon;
u32 dstat;
u32 dcsrc;
u32 dcdst;
u32 dmasktrig;
#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) \
|| defined(CONFIG_S3C2440)
u32 res[1];
#endif
#ifdef CONFIG_S3C2410
u32 res[7];
#endif
};
struct s3c24x0_dmas {
@ -116,90 +114,111 @@ struct s3c24x0_dmas {
/* CLOCK & POWER MANAGEMENT (see S3C2400 manual chapter 6) */
/* (see S3C2410 manual chapter 7) */
struct s3c24x0_clock_power {
u32 LOCKTIME;
u32 MPLLCON;
u32 UPLLCON;
u32 CLKCON;
u32 CLKSLOW;
u32 CLKDIVN;
u32 locktime;
u32 mpllcon;
u32 upllcon;
u32 clkcon;
u32 clkslow;
u32 clkdivn;
#if defined(CONFIG_S3C2440)
u32 camdivn;
#endif
};
/* LCD CONTROLLER (see manual chapter 15) */
struct s3c24x0_lcd {
u32 LCDCON1;
u32 LCDCON2;
u32 LCDCON3;
u32 LCDCON4;
u32 LCDCON5;
u32 LCDSADDR1;
u32 LCDSADDR2;
u32 LCDSADDR3;
u32 REDLUT;
u32 GREENLUT;
u32 BLUELUT;
u32 lcdcon1;
u32 lcdcon2;
u32 lcdcon3;
u32 lcdcon4;
u32 lcdcon5;
u32 lcdsaddr1;
u32 lcdsaddr2;
u32 lcdsaddr3;
u32 redlut;
u32 greenlut;
u32 bluelut;
u32 res[8];
u32 DITHMODE;
u32 TPAL;
#ifdef CONFIG_S3C2410
u32 LCDINTPND;
u32 LCDSRCPND;
u32 LCDINTMSK;
u32 LPCSEL;
u32 dithmode;
u32 tpal;
#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
u32 lcdintpnd;
u32 lcdsrcpnd;
u32 lcdintmsk;
u32 lpcsel;
#endif
};
#ifdef CONFIG_S3C2410
/* NAND FLASH (see S3C2410 manual chapter 6) */
struct s3c2410_nand {
u32 NFCONF;
u32 NFCMD;
u32 NFADDR;
u32 NFDATA;
u32 NFSTAT;
u32 NFECC;
u32 nfconf;
u32 nfcmd;
u32 nfaddr;
u32 nfdata;
u32 nfstat;
u32 nfecc;
};
#endif
#ifdef CONFIG_S3C2440
/* NAND FLASH (see S3C2440 manual chapter 6) */
struct s3c2440_nand {
u32 nfconf;
u32 nfcont;
u32 nfcmd;
u32 nfaddr;
u32 nfdata;
u32 nfeccd0;
u32 nfeccd1;
u32 nfeccd;
u32 nfstat;
u32 nfstat0;
u32 nfstat1;
};
#endif
/* UART (see manual chapter 11) */
struct s3c24x0_uart {
u32 ULCON;
u32 UCON;
u32 UFCON;
u32 UMCON;
u32 UTRSTAT;
u32 UERSTAT;
u32 UFSTAT;
u32 UMSTAT;
u32 ulcon;
u32 ucon;
u32 ufcon;
u32 umcon;
u32 utrstat;
u32 uerstat;
u32 ufstat;
u32 umstat;
#ifdef __BIG_ENDIAN
u8 res1[3];
u8 UTXH;
u8 utxh;
u8 res2[3];
u8 URXH;
u8 urxh;
#else /* Little Endian */
u8 UTXH;
u8 utxh;
u8 res1[3];
u8 URXH;
u8 urxh;
u8 res2[3];
#endif
u32 UBRDIV;
u32 ubrdiv;
};
/* PWM TIMER (see manual chapter 10) */
struct s3c24x0_timer {
u32 TCNTB;
u32 TCMPB;
u32 TCNTO;
u32 tcntb;
u32 tcmpb;
u32 tcnto;
};
struct s3c24x0_timers {
u32 TCFG0;
u32 TCFG1;
u32 TCON;
u32 tcfg0;
u32 tcfg1;
u32 tcon;
struct s3c24x0_timer ch[4];
u32 TCNTB4;
u32 TCNTO4;
u32 tcntb4;
u32 tcnto4;
};
@ -207,9 +226,9 @@ struct s3c24x0_timers {
struct s3c24x0_usb_dev_fifos {
#ifdef __BIG_ENDIAN
u8 res[3];
u8 EP_FIFO_REG;
u8 ep_fifo_reg;
#else /* little endian */
u8 EP_FIFO_REG;
u8 ep_fifo_reg;
u8 res[3];
#endif
};
@ -217,29 +236,29 @@ struct s3c24x0_usb_dev_fifos {
struct s3c24x0_usb_dev_dmas {
#ifdef __BIG_ENDIAN
u8 res1[3];
u8 EP_DMA_CON;
u8 ep_dma_con;
u8 res2[3];
u8 EP_DMA_UNIT;
u8 ep_dma_unit;
u8 res3[3];
u8 EP_DMA_FIFO;
u8 ep_dma_fifo;
u8 res4[3];
u8 EP_DMA_TTC_L;
u8 ep_dma_ttc_l;
u8 res5[3];
u8 EP_DMA_TTC_M;
u8 ep_dma_ttc_m;
u8 res6[3];
u8 EP_DMA_TTC_H;
u8 ep_dma_ttc_h;
#else /* little endian */
u8 EP_DMA_CON;
u8 ep_dma_con;
u8 res1[3];
u8 EP_DMA_UNIT;
u8 ep_dma_unit;
u8 res2[3];
u8 EP_DMA_FIFO;
u8 ep_dma_fifo;
u8 res3[3];
u8 EP_DMA_TTC_L;
u8 ep_dma_ttc_l;
u8 res4[3];
u8 EP_DMA_TTC_M;
u8 ep_dma_ttc_m;
u8 res5[3];
u8 EP_DMA_TTC_H;
u8 ep_dma_ttc_h;
u8 res6[3];
#endif
};
@ -247,69 +266,69 @@ struct s3c24x0_usb_dev_dmas {
struct s3c24x0_usb_device {
#ifdef __BIG_ENDIAN
u8 res1[3];
u8 FUNC_ADDR_REG;
u8 func_addr_reg;
u8 res2[3];
u8 PWR_REG;
u8 pwr_reg;
u8 res3[3];
u8 EP_INT_REG;
u8 ep_int_reg;
u8 res4[15];
u8 USB_INT_REG;
u8 usb_int_reg;
u8 res5[3];
u8 EP_INT_EN_REG;
u8 ep_int_en_reg;
u8 res6[15];
u8 USB_INT_EN_REG;
u8 usb_int_en_reg;
u8 res7[3];
u8 FRAME_NUM1_REG;
u8 frame_num1_reg;
u8 res8[3];
u8 FRAME_NUM2_REG;
u8 frame_num2_reg;
u8 res9[3];
u8 INDEX_REG;
u8 index_reg;
u8 res10[7];
u8 MAXP_REG;
u8 maxp_reg;
u8 res11[3];
u8 EP0_CSR_IN_CSR1_REG;
u8 ep0_csr_in_csr1_reg;
u8 res12[3];
u8 IN_CSR2_REG;
u8 in_csr2_reg;
u8 res13[7];
u8 OUT_CSR1_REG;
u8 out_csr1_reg;
u8 res14[3];
u8 OUT_CSR2_REG;
u8 out_csr2_reg;
u8 res15[3];
u8 OUT_FIFO_CNT1_REG;
u8 out_fifo_cnt1_reg;
u8 res16[3];
u8 OUT_FIFO_CNT2_REG;
u8 out_fifo_cnt2_reg;
#else /* little endian */
u8 FUNC_ADDR_REG;
u8 func_addr_reg;
u8 res1[3];
u8 PWR_REG;
u8 pwr_reg;
u8 res2[3];
u8 EP_INT_REG;
u8 ep_int_reg;
u8 res3[15];
u8 USB_INT_REG;
u8 usb_int_reg;
u8 res4[3];
u8 EP_INT_EN_REG;
u8 ep_int_en_reg;
u8 res5[15];
u8 USB_INT_EN_REG;
u8 usb_int_en_reg;
u8 res6[3];
u8 FRAME_NUM1_REG;
u8 frame_num1_reg;
u8 res7[3];
u8 FRAME_NUM2_REG;
u8 frame_num2_reg;
u8 res8[3];
u8 INDEX_REG;
u8 index_reg;
u8 res9[7];
u8 MAXP_REG;
u8 maxp_reg;
u8 res10[7];
u8 EP0_CSR_IN_CSR1_REG;
u8 ep0_csr_in_csr1_reg;
u8 res11[3];
u8 IN_CSR2_REG;
u8 in_csr2_reg;
u8 res12[3];
u8 OUT_CSR1_REG;
u8 out_csr1_reg;
u8 res13[7];
u8 OUT_CSR2_REG;
u8 out_csr2_reg;
u8 res14[3];
u8 OUT_FIFO_CNT1_REG;
u8 out_fifo_cnt1_reg;
u8 res15[3];
u8 OUT_FIFO_CNT2_REG;
u8 out_fifo_cnt2_reg;
u8 res16[3];
#endif /* __BIG_ENDIAN */
struct s3c24x0_usb_dev_fifos fifo[5];
@ -319,18 +338,18 @@ struct s3c24x0_usb_device {
/* WATCH DOG TIMER (see manual chapter 18) */
struct s3c24x0_watchdog {
u32 WTCON;
u32 WTDAT;
u32 WTCNT;
u32 wtcon;
u32 wtdat;
u32 wtcnt;
};
/* IIC (see manual chapter 20) */
struct s3c24x0_i2c {
u32 IICCON;
u32 IICSTAT;
u32 IICADD;
u32 IICDS;
u32 iiccon;
u32 iicstat;
u32 iicadd;
u32 iicds;
};
@ -338,25 +357,25 @@ struct s3c24x0_i2c {
struct s3c24x0_i2s {
#ifdef __BIG_ENDIAN
u16 res1;
u16 IISCON;
u16 iiscon;
u16 res2;
u16 IISMOD;
u16 iismod;
u16 res3;
u16 IISPSR;
u16 iispsr;
u16 res4;
u16 IISFCON;
u16 iisfcon;
u16 res5;
u16 IISFIFO;
u16 iisfifo;
#else /* little endian */
u16 IISCON;
u16 iiscon;
u16 res1;
u16 IISMOD;
u16 iismod;
u16 res2;
u16 IISPSR;
u16 iispsr;
u16 res3;
u16 IISFCON;
u16 iisfcon;
u16 res4;
u16 IISFIFO;
u16 iisfifo;
u16 res5;
#endif
};
@ -365,87 +384,146 @@ struct s3c24x0_i2s {
/* I/O PORT (see manual chapter 9) */
struct s3c24x0_gpio {
#ifdef CONFIG_S3C2400
u32 PACON;
u32 PADAT;
u32 pacon;
u32 padat;
u32 PBCON;
u32 PBDAT;
u32 PBUP;
u32 pbcon;
u32 pbdat;
u32 pbup;
u32 PCCON;
u32 PCDAT;
u32 PCUP;
u32 pccon;
u32 pcdat;
u32 pcup;
u32 PDCON;
u32 PDDAT;
u32 PDUP;
u32 pdcon;
u32 pddat;
u32 pdup;
u32 PECON;
u32 PEDAT;
u32 PEUP;
u32 pecon;
u32 pedat;
u32 peup;
u32 PFCON;
u32 PFDAT;
u32 PFUP;
u32 pfcon;
u32 pfdat;
u32 pfup;
u32 PGCON;
u32 PGDAT;
u32 PGUP;
u32 pgcon;
u32 pgdat;
u32 pgup;
u32 OPENCR;
u32 opencr;
u32 MISCCR;
u32 EXTINT;
u32 misccr;
u32 extint;
#endif
#ifdef CONFIG_S3C2410
u32 GPACON;
u32 GPADAT;
u32 gpacon;
u32 gpadat;
u32 res1[2];
u32 GPBCON;
u32 GPBDAT;
u32 GPBUP;
u32 gpbcon;
u32 gpbdat;
u32 gpbup;
u32 res2;
u32 GPCCON;
u32 GPCDAT;
u32 GPCUP;
u32 gpccon;
u32 gpcdat;
u32 gpcup;
u32 res3;
u32 GPDCON;
u32 GPDDAT;
u32 GPDUP;
u32 gpdcon;
u32 gpddat;
u32 gpdup;
u32 res4;
u32 GPECON;
u32 GPEDAT;
u32 GPEUP;
u32 gpecon;
u32 gpedat;
u32 gpeup;
u32 res5;
u32 GPFCON;
u32 GPFDAT;
u32 GPFUP;
u32 gpfcon;
u32 gpfdat;
u32 gpfup;
u32 res6;
u32 GPGCON;
u32 GPGDAT;
u32 GPGUP;
u32 gpgcon;
u32 gpgdat;
u32 gpgup;
u32 res7;
u32 GPHCON;
u32 GPHDAT;
u32 GPHUP;
u32 gphcon;
u32 gphdat;
u32 gphup;
u32 res8;
u32 MISCCR;
u32 DCLKCON;
u32 EXTINT0;
u32 EXTINT1;
u32 EXTINT2;
u32 EINTFLT0;
u32 EINTFLT1;
u32 EINTFLT2;
u32 EINTFLT3;
u32 EINTMASK;
u32 EINTPEND;
u32 GSTATUS0;
u32 GSTATUS1;
u32 GSTATUS2;
u32 GSTATUS3;
u32 GSTATUS4;
u32 misccr;
u32 dclkcon;
u32 extint0;
u32 extint1;
u32 extint2;
u32 eintflt0;
u32 eintflt1;
u32 eintflt2;
u32 eintflt3;
u32 eintmask;
u32 eintpend;
u32 gstatus0;
u32 gstatus1;
u32 gstatus2;
u32 gstatus3;
u32 gstatus4;
#endif
#if defined(CONFIG_S3C2440)
u32 gpacon;
u32 gpadat;
u32 res1[2];
u32 gpbcon;
u32 gpbdat;
u32 gpbup;
u32 res2;
u32 gpccon;
u32 gpcdat;
u32 gpcup;
u32 res3;
u32 gpdcon;
u32 gpddat;
u32 gpdup;
u32 res4;
u32 gpecon;
u32 gpedat;
u32 gpeup;
u32 res5;
u32 gpfcon;
u32 gpfdat;
u32 gpfup;
u32 res6;
u32 gpgcon;
u32 gpgdat;
u32 gpgup;
u32 res7;
u32 gphcon;
u32 gphdat;
u32 gphup;
u32 res8;
u32 misccr;
u32 dclkcon;
u32 extint0;
u32 extint1;
u32 extint2;
u32 eintflt0;
u32 eintflt1;
u32 eintflt2;
u32 eintflt3;
u32 eintmask;
u32 eintpend;
u32 gstatus0;
u32 gstatus1;
u32 gstatus2;
u32 gstatus3;
u32 gstatus4;
u32 res9;
u32 dsc0;
u32 dsc1;
u32 mslcon;
u32 gpjcon;
u32 gpjdat;
u32 gpjup;
u32 res10;
#endif
};
@ -454,74 +532,74 @@ struct s3c24x0_gpio {
struct s3c24x0_rtc {
#ifdef __BIG_ENDIAN
u8 res1[67];
u8 RTCCON;
u8 rtccon;
u8 res2[3];
u8 TICNT;
u8 ticnt;
u8 res3[11];
u8 RTCALM;
u8 rtcalm;
u8 res4[3];
u8 ALMSEC;
u8 almsec;
u8 res5[3];
u8 ALMMIN;
u8 almmin;
u8 res6[3];
u8 ALMHOUR;
u8 almhour;
u8 res7[3];
u8 ALMDATE;
u8 almdate;
u8 res8[3];
u8 ALMMON;
u8 almmon;
u8 res9[3];
u8 ALMYEAR;
u8 almyear;
u8 res10[3];
u8 RTCRST;
u8 rtcrst;
u8 res11[3];
u8 BCDSEC;
u8 bcdsec;
u8 res12[3];
u8 BCDMIN;
u8 bcdmin;
u8 res13[3];
u8 BCDHOUR;
u8 bcdhour;
u8 res14[3];
u8 BCDDATE;
u8 bcddate;
u8 res15[3];
u8 BCDDAY;
u8 bcdday;
u8 res16[3];
u8 BCDMON;
u8 bcdmon;
u8 res17[3];
u8 BCDYEAR;
u8 bcdyear;
#else /* little endian */
u8 res0[64];
u8 RTCCON;
u8 rtccon;
u8 res1[3];
u8 TICNT;
u8 ticnt;
u8 res2[11];
u8 RTCALM;
u8 rtcalm;
u8 res3[3];
u8 ALMSEC;
u8 almsec;
u8 res4[3];
u8 ALMMIN;
u8 almmin;
u8 res5[3];
u8 ALMHOUR;
u8 almhour;
u8 res6[3];
u8 ALMDATE;
u8 almdate;
u8 res7[3];
u8 ALMMON;
u8 almmon;
u8 res8[3];
u8 ALMYEAR;
u8 almyear;
u8 res9[3];
u8 RTCRST;
u8 rtcrst;
u8 res10[3];
u8 BCDSEC;
u8 bcdsec;
u8 res11[3];
u8 BCDMIN;
u8 bcdmin;
u8 res12[3];
u8 BCDHOUR;
u8 bcdhour;
u8 res13[3];
u8 BCDDATE;
u8 bcddate;
u8 res14[3];
u8 BCDDAY;
u8 bcdday;
u8 res15[3];
u8 BCDMON;
u8 bcdmon;
u8 res16[3];
u8 BCDYEAR;
u8 bcdyear;
u8 res17[3];
#endif
};
@ -529,34 +607,34 @@ struct s3c24x0_rtc {
/* ADC (see manual chapter 16) */
struct s3c2400_adc {
u32 ADCCON;
u32 ADCDAT;
u32 adccon;
u32 adcdat;
};
/* ADC (see manual chapter 16) */
struct s3c2410_adc {
u32 ADCCON;
u32 ADCTSC;
u32 ADCDLY;
u32 ADCDAT0;
u32 ADCDAT1;
u32 adccon;
u32 adctsc;
u32 adcdly;
u32 adcdat0;
u32 adcdat1;
};
/* SPI (see manual chapter 22) */
struct s3c24x0_spi_channel {
u8 SPCON;
u8 spcon;
u8 res1[3];
u8 SPSTA;
u8 spsta;
u8 res2[3];
u8 SPPIN;
u8 sppin;
u8 res3[3];
u8 SPPRE;
u8 sppre;
u8 res4[3];
u8 SPTDAT;
u8 sptdat;
u8 res5[3];
u8 SPRDAT;
u8 sprdat;
u8 res6[3];
u8 res7[16];
};
@ -570,53 +648,53 @@ struct s3c24x0_spi {
struct s3c2400_mmc {
#ifdef __BIG_ENDIAN
u8 res1[3];
u8 MMCON;
u8 mmcon;
u8 res2[3];
u8 MMCRR;
u8 mmcrr;
u8 res3[3];
u8 MMFCON;
u8 mmfcon;
u8 res4[3];
u8 MMSTA;
u8 mmsta;
u16 res5;
u16 MMFSTA;
u16 mmfsta;
u8 res6[3];
u8 MMPRE;
u8 mmpre;
u16 res7;
u16 MMLEN;
u16 mmlen;
u8 res8[3];
u8 MMCR7;
u32 MMRSP[4];
u8 mmcr7;
u32 mmrsp[4];
u8 res9[3];
u8 MMCMD0;
u32 MMCMD1;
u8 mmcmd0;
u32 mmcmd1;
u16 res10;
u16 MMCR16;
u16 mmcr16;
u8 res11[3];
u8 MMDAT;
u8 mmdat;
#else
u8 MMCON;
u8 mmcon;
u8 res1[3];
u8 MMCRR;
u8 mmcrr;
u8 res2[3];
u8 MMFCON;
u8 mmfcon;
u8 res3[3];
u8 MMSTA;
u8 mmsta;
u8 res4[3];
u16 MMFSTA;
u16 mmfsta;
u16 res5;
u8 MMPRE;
u8 mmpre;
u8 res6[3];
u16 MMLEN;
u16 mmlen;
u16 res7;
u8 MMCR7;
u8 mmcr7;
u8 res8[3];
u32 MMRSP[4];
u8 MMCMD0;
u32 mmrsp[4];
u8 mmcmd0;
u8 res9[3];
u32 MMCMD1;
u16 MMCR16;
u32 mmcmd1;
u16 mmcr16;
u16 res10;
u8 MMDAT;
u8 mmdat;
u8 res11[3];
#endif
};
@ -624,29 +702,29 @@ struct s3c2400_mmc {
/* SD INTERFACE (see S3C2410 manual chapter 19) */
struct s3c2410_sdi {
u32 SDICON;
u32 SDIPRE;
u32 SDICARG;
u32 SDICCON;
u32 SDICSTA;
u32 SDIRSP0;
u32 SDIRSP1;
u32 SDIRSP2;
u32 SDIRSP3;
u32 SDIDTIMER;
u32 SDIBSIZE;
u32 SDIDCON;
u32 SDIDCNT;
u32 SDIDSTA;
u32 SDIFSTA;
u32 sdicon;
u32 sdipre;
u32 sdicarg;
u32 sdiccon;
u32 sdicsta;
u32 sdirsp0;
u32 sdirsp1;
u32 sdirsp2;
u32 sdirsp3;
u32 sdidtimer;
u32 sdibsize;
u32 sdidcon;
u32 sdidcnt;
u32 sdidsta;
u32 sdifsta;
#ifdef __BIG_ENDIAN
u8 res[3];
u8 SDIDAT;
u8 sdidat;
#else
u8 SDIDAT;
u8 sdidat;
u8 res[3];
#endif
u32 SDIIMSK;
u32 sdiimsk;
};
#endif /*__S3C24X0_H__*/

View File

@ -22,6 +22,8 @@
#include <asm/arch/s3c2400.h>
#elif defined CONFIG_S3C2410
#include <asm/arch/s3c2410.h>
#elif defined CONFIG_S3C2440
#include <asm/arch/s3c2440.h>
#else
#error Please define the s3c24x0 cpu type
#endif

View File

@ -78,42 +78,43 @@ int board_init(void)
struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
/* to reduce PLL lock time, adjust the LOCKTIME register */
clk_power->LOCKTIME = 0xFFFFFF;
clk_power->locktime = 0xFFFFFF;
/* configure MPLL */
clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
clk_power->mpllcon = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
/* some delay between MPLL and UPLL */
delay (4000);
/* configure UPLL */
clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
clk_power->upllcon = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
/* some delay between MPLL and UPLL */
delay (8000);
/* set up the I/O ports */
gpio->GPACON = 0x007FFFFF;
gpio->GPBCON = 0x002AAAAA;
gpio->GPBUP = 0x000002BF;
gpio->GPCCON = 0xAAAAAAAA;
gpio->GPCUP = 0x0000FFFF;
gpio->GPDCON = 0xAAAAAAAA;
gpio->GPDUP = 0x0000FFFF;
gpio->GPECON = 0xAAAAAAAA;
gpio->GPEUP = 0x000037F7;
gpio->GPFCON = 0x00000000;
gpio->GPFUP = 0x00000000;
gpio->GPGCON = 0xFFEAFF5A;
gpio->GPGUP = 0x0000F0DC;
gpio->GPHCON = 0x0028AAAA;
gpio->GPHUP = 0x00000656;
gpio->gpacon = 0x007FFFFF;
gpio->gpbcon = 0x002AAAAA;
gpio->gpbup = 0x000002BF;
gpio->gpccon = 0xAAAAAAAA;
gpio->gpcup = 0x0000FFFF;
gpio->gpdcon = 0xAAAAAAAA;
gpio->gpdup = 0x0000FFFF;
gpio->gpecon = 0xAAAAAAAA;
gpio->gpeup = 0x000037F7;
gpio->gpfcon = 0x00000000;
gpio->gpfup = 0x00000000;
gpio->gpgcon = 0xFFEAFF5A;
gpio->gpgup = 0x0000F0DC;
gpio->gphcon = 0x0028AAAA;
gpio->gphup = 0x00000656;
/* setup correct IRQ modes for NIC */
gpio->EXTINT2 = (gpio->EXTINT2 & ~(7<<8)) | (4<<8); /* rising edge mode */
/* rising edge mode */
gpio->extint2 = (gpio->extint2 & ~(7<<8)) | (4<<8);
/* select USB port 2 to be host or device (fix to host for now) */
gpio->MISCCR |= 0x08;
gpio->misccr |= 0x08;
/* init serial */
gd->baudrate = CONFIG_BAUDRATE;

View File

@ -52,30 +52,30 @@ int board_init (void)
/* memory and cpu-speed are setup before relocation */
/* change the clock to be 50 MHz 1:1:1 */
clk_power->MPLLCON = 0x5c042;
clk_power->CLKDIVN = 0;
clk_power->mpllcon = 0x5c042;
clk_power->clkdivn = 0;
/* set up the I/O ports */
gpio->PACON = 0x3ffff;
gpio->PBCON = 0xaaaaaaaa;
gpio->PBUP = 0xffff;
gpio->PECON = 0x0;
gpio->PEUP = 0x0;
gpio->pacon = 0x3ffff;
gpio->pbcon = 0xaaaaaaaa;
gpio->pbup = 0xffff;
gpio->pecon = 0x0;
gpio->peup = 0x0;
#ifdef CONFIG_HWFLOW
/*CTS[0] RTS[0] INPUT INPUT TXD[0] INPUT RXD[0] */
/* 10, 10, 00, 00, 10, 00, 10 */
gpio->PFCON=0xa22;
gpio->pfcon = 0xa22;
/* Disable pull-up on Rx, Tx, CTS and RTS pins */
gpio->PFUP=0x35;
gpio->pfup = 0x35;
#else
/*INPUT INPUT INPUT INPUT TXD[0] INPUT RXD[0] */
/* 00, 00, 00, 00, 10, 00, 10 */
gpio->PFCON = 0x22;
gpio->pfcon = 0x22;
/* Disable pull-up on Rx and Tx pins */
gpio->PFUP = 0x5;
gpio->pfup = 0x5;
#endif /* CONFIG_HWFLOW */
gpio->PGCON = 0x0;
gpio->PGUP = 0x0;
gpio->OPENCR = 0x0;
gpio->pgcon = 0x0;
gpio->pgup = 0x0;
gpio->opencr = 0x0;
/* arch number of SAMSUNG-Board to MACH_TYPE_SMDK2400 */
gd->bd->bi_arch_number = MACH_TYPE_SMDK2400;

View File

@ -73,36 +73,36 @@ int board_init (void)
struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
/* to reduce PLL lock time, adjust the LOCKTIME register */
clk_power->LOCKTIME = 0xFFFFFF;
clk_power->locktime = 0xFFFFFF;
/* configure MPLL */
clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
clk_power->mpllcon = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
/* some delay between MPLL and UPLL */
delay (4000);
/* configure UPLL */
clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
clk_power->upllcon = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
/* some delay between MPLL and UPLL */
delay (8000);