Blackfin: bf527-ezkit: new board port
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This commit is contained in:
Mike Frysinger
parent
76d21803dd
commit
d9a5d113b9
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@ -854,6 +854,7 @@ Yusuke Goda <goda.yusuke@renesas.com>
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Mike Frysinger <vapier@gentoo.org>
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Blackfin Team <u-boot-devel@blackfin.uclinux.org>
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BF527-EZKIT BF527
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BF533-EZKIT BF533
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BF533-STAMP BF533
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BF537-STAMP BF537
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1
MAKEALL
1
MAKEALL
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@ -788,6 +788,7 @@ LIST_avr32=" \
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#########################################################################
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LIST_blackfin=" \
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bf527-ezkit \
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bf533-ezkit \
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bf533-stamp \
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bf537-stamp \
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5
Makefile
5
Makefile
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@ -3336,7 +3336,8 @@ suzaku_config: unconfig
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#========================================================================
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# Analog Devices boards
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BFIN_BOARDS = bf533-ezkit bf533-stamp bf537-stamp bf548-ezkit bf561-ezkit
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BFIN_BOARDS = bf527-ezkit bf533-ezkit bf533-stamp bf537-stamp bf548-ezkit \
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bf561-ezkit
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$(BFIN_BOARDS:%=%_config) : unconfig
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@$(MKCONFIG) $(@:_config=) blackfin blackfin $(@:_config=)
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@ -3510,7 +3511,7 @@ clean:
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$(obj)board/netstar/{eeprom,crcek,crcit,*.srec,*.bin} \
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$(obj)board/trab/trab_fkt $(obj)board/voiceblue/eeprom \
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$(obj)board/armltd/{integratorap,integratorcp}/u-boot.lds \
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$(obj)board/bf5{33,48,61}-ezkit/u-boot.lds \
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$(obj)board/bf5{27,33,48,61}-ezkit/u-boot.lds \
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$(obj)board/bf5{33,37}-stamp/u-boot.lds \
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$(obj)cpu/blackfin/bootrom-asm-offsets.[chs]
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@rm -f $(obj)include/bmp_logo.h
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@ -0,0 +1 @@
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/u-boot.lds
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@ -0,0 +1,58 @@
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#
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# U-boot - Makefile
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#
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# Copyright (c) 2005-2008 Analog Device Inc.
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).a
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COBJS-y := $(BOARD).o
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COBJS-$(CONFIG_VIDEO) += video.o
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SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS-y))
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SOBJS := $(addprefix $(obj),$(SOBJS-y))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS) $(obj)u-boot.lds
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$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
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$(obj)u-boot.lds: u-boot.lds.S
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$(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P $^ > $@
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clean:
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rm -f $(SOBJS) $(OBJS)
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distclean: clean
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rm -f $(LIB) core *.bak $(obj).depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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@ -0,0 +1,77 @@
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/*
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* U-boot - main board file
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*
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* Copyright (c) 2005-2009 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later.
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*/
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#include <common.h>
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#include <config.h>
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#include <command.h>
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#include <net.h>
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#include <netdev.h>
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#include <asm/blackfin.h>
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#include <asm/net.h>
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#include <asm/mach-common/bits/otp.h>
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DECLARE_GLOBAL_DATA_PTR;
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int checkboard(void)
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{
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printf("Board: ADI BF527 EZ-Kit board\n");
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printf(" Support: http://blackfin.uclinux.org/\n");
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return 0;
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}
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phys_size_t initdram(int board_type)
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{
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gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
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gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
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return gd->bd->bi_memsize;
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}
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#ifdef CONFIG_BFIN_MAC
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static void board_init_enetaddr(uchar *mac_addr)
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{
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bool valid_mac = false;
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/* the MAC is stored in OTP memory page 0xDF */
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uint32_t ret;
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uint64_t otp_mac;
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ret = bfrom_OtpRead(0xDF, OTP_LOWER_HALF, &otp_mac);
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if (!(ret & OTP_MASTER_ERROR)) {
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uchar *otp_mac_p = (uchar *)&otp_mac;
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for (ret = 0; ret < 6; ++ret)
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mac_addr[ret] = otp_mac_p[5 - ret];
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if (is_valid_ether_addr(mac_addr))
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valid_mac = true;
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}
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if (!valid_mac) {
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puts("Warning: Generating 'random' MAC address\n");
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bfin_gen_rand_mac(mac_addr);
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}
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eth_setenv_enetaddr("ethaddr", mac_addr);
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}
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int board_eth_init(bd_t *bis)
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{
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return bfin_EMAC_initialize(bis);
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}
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#endif
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int misc_init_r(void)
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{
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#ifdef CONFIG_BFIN_MAC
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uchar enetaddr[6];
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if (!eth_getenv_enetaddr("ethaddr", enetaddr))
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board_init_enetaddr(enetaddr);
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#endif
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return 0;
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}
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@ -0,0 +1,32 @@
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#
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# Copyright (c) 2005-2008 Analog Device Inc.
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#
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# (C) Copyright 2001
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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# This is not actually used for Blackfin boards so do not change it
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#TEXT_BASE = do-not-use-me
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LDSCRIPT = $(obj)board/$(BOARDDIR)/u-boot.lds
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# Set some default LDR flags based on boot mode.
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LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
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@ -0,0 +1,124 @@
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/*
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* U-boot - u-boot.lds.S
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*
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* Copyright (c) 2005-2008 Analog Device Inc.
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*
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* (C) Copyright 2000-2004
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <asm/blackfin.h>
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#undef ALIGN
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#undef ENTRY
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#undef bfin
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/* If we don't actually load anything into L1 data, this will avoid
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* a syntax error. If we do actually load something into L1 data,
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* we'll get a linker memory load error (which is what we'd want).
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* This is here in the first place so we can quickly test building
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* for different CPU's which may lack non-cache L1 data.
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*/
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#ifndef L1_DATA_B_SRAM
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# define L1_DATA_B_SRAM CONFIG_SYS_MONITOR_BASE
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# define L1_DATA_B_SRAM_SIZE 0
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#endif
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OUTPUT_ARCH(bfin)
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MEMORY
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{
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ram : ORIGIN = CONFIG_SYS_MONITOR_BASE, LENGTH = CONFIG_SYS_MONITOR_LEN
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l1_code : ORIGIN = L1_INST_SRAM, LENGTH = L1_INST_SRAM_SIZE
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l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE
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}
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ENTRY(_start)
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SECTIONS
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{
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.text :
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{
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cpu/blackfin/start.o (.text .text.*)
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__initcode_start = .;
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cpu/blackfin/initcode.o (.text .text.*)
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__initcode_end = .;
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*(.text .text.*)
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} >ram
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.rodata :
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{
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. = ALIGN(4);
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*(.rodata .rodata.*)
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*(.rodata1)
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*(.eh_frame)
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. = ALIGN(4);
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} >ram
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.data :
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{
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. = ALIGN(256);
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*(.data .data.*)
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*(.data1)
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*(.sdata)
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*(.sdata2)
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*(.dynamic)
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CONSTRUCTORS
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} >ram
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.u_boot_cmd :
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{
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___u_boot_cmd_start = .;
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*(.u_boot_cmd)
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___u_boot_cmd_end = .;
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} >ram
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.text_l1 :
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{
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. = ALIGN(4);
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__stext_l1 = .;
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*(.l1.text)
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. = ALIGN(4);
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__etext_l1 = .;
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} >l1_code AT>ram
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__stext_l1_lma = LOADADDR(.text_l1);
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.data_l1 :
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{
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. = ALIGN(4);
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__sdata_l1 = .;
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*(.l1.data)
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*(.l1.bss)
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. = ALIGN(4);
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__edata_l1 = .;
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} >l1_data AT>ram
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__sdata_l1_lma = LOADADDR(.data_l1);
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.bss :
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{
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. = ALIGN(4);
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__bss_start = .;
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*(.sbss) *(.scommon)
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*(.dynbss)
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*(.bss .bss.*)
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*(COMMON)
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__bss_end = .;
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} >ram
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}
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@ -0,0 +1,317 @@
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/*
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* video.c - run splash screen on lcd
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*
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* Copyright (c) 2007-2008 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later.
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*/
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#include <stdarg.h>
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#include <common.h>
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#include <config.h>
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#include <malloc.h>
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#include <asm/blackfin.h>
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#include <asm/mach-common/bits/dma.h>
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#include <i2c.h>
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#include <linux/types.h>
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#include <devices.h>
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int gunzip(void *, int, unsigned char *, unsigned long *);
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#define DMA_SIZE16 2
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#include <asm/mach-common/bits/ppi.h>
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#include <asm/mach-common/bits/timer.h>
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#include <asm/bfin_logo_230x230.h>
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#define LCD_X_RES 320 /* Horizontal Resolution */
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#define LCD_Y_RES 240 /* Vertical Resolution */
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#define LCD_BPP 24 /* Bit Per Pixel */
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#define LCD_PIXEL_SIZE (LCD_BPP / 8)
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#define DMA_BUS_SIZE 16
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#define LCD_CLK (12*1000*1000) /* 12MHz */
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#define CLOCKS_PER_PIX 3
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/* HS and VS timing parameters (all in number of PPI clk ticks) */
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#define H_ACTPIX (LCD_X_RES * CLOCKS_PER_PIX) /* active horizontal pixel */
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#define H_PERIOD (408 * CLOCKS_PER_PIX) /* HS period */
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#define H_PULSE 90 /* HS pulse width */
|
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#define H_START 204 /* first valid pixel */
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#define U_LINE 1 /* Blanking Lines */
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#define V_LINES (LCD_Y_RES + U_LINE) /* total vertical lines */
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#define V_PULSE (3 * H_PERIOD) /* VS pulse width (1-5 H_PERIODs) */
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#define V_PERIOD (H_PERIOD * V_LINES) /* VS period */
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#define ACTIVE_VIDEO_MEM_OFFSET (U_LINE * H_ACTPIX)
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|
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#define PPI_TX_MODE 0x2
|
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#define PPI_XFER_TYPE_11 0xC
|
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#define PPI_PORT_CFG_01 0x10
|
||||
#define PPI_PACK_EN 0x80
|
||||
#define PPI_POLS_1 0x8000
|
||||
|
||||
/* enable and disable PPI functions */
|
||||
void EnablePPI(void)
|
||||
{
|
||||
*pPPI_CONTROL |= PORT_EN;
|
||||
}
|
||||
|
||||
void DisablePPI(void)
|
||||
{
|
||||
*pPPI_CONTROL &= ~PORT_EN;
|
||||
}
|
||||
|
||||
void Init_Ports(void)
|
||||
{
|
||||
*pPORTF_MUX &= ~PORT_x_MUX_0_MASK;
|
||||
*pPORTF_MUX |= PORT_x_MUX_0_FUNC_1;
|
||||
*pPORTF_FER |= PF0 | PF1 | PF2 | PF3 | PF4 | PF5 | PF6 | PF7;
|
||||
|
||||
*pPORTG_MUX &= ~PORT_x_MUX_1_MASK;
|
||||
*pPORTG_MUX |= PORT_x_MUX_1_FUNC_1;
|
||||
*pPORTG_FER |= PG5;
|
||||
}
|
||||
|
||||
void Init_PPI(void)
|
||||
{
|
||||
|
||||
*pPPI_DELAY = H_START;
|
||||
*pPPI_COUNT = (H_ACTPIX-1);
|
||||
*pPPI_FRAME = 0;
|
||||
|
||||
/* PPI control, to be replaced with definitions */
|
||||
*pPPI_CONTROL = PPI_TX_MODE | /* output mode , PORT_DIR */
|
||||
PPI_XFER_TYPE_11 | /* sync mode XFR_TYPE */
|
||||
PPI_PORT_CFG_01 | /* two frame sync PORT_CFG */
|
||||
PPI_PACK_EN | /* packing enabled PACK_EN */
|
||||
PPI_POLS_1; /* faling edge syncs POLS */
|
||||
}
|
||||
|
||||
void Init_DMA(void *dst)
|
||||
{
|
||||
*pDMA0_START_ADDR = dst;
|
||||
|
||||
/* X count */
|
||||
*pDMA0_X_COUNT = H_ACTPIX / 2;
|
||||
*pDMA0_X_MODIFY = DMA_BUS_SIZE / 8;
|
||||
|
||||
/* Y count */
|
||||
*pDMA0_Y_COUNT = V_LINES;
|
||||
*pDMA0_Y_MODIFY = DMA_BUS_SIZE / 8;
|
||||
|
||||
/* DMA Config */
|
||||
*pDMA0_CONFIG =
|
||||
WDSIZE_16 | /* 16 bit DMA */
|
||||
DMA2D | /* 2D DMA */
|
||||
FLOW_AUTO; /* autobuffer mode */
|
||||
}
|
||||
|
||||
|
||||
void EnableDMA(void)
|
||||
{
|
||||
*pDMA0_CONFIG |= DMAEN;
|
||||
}
|
||||
|
||||
void DisableDMA(void)
|
||||
{
|
||||
*pDMA0_CONFIG &= ~DMAEN;
|
||||
}
|
||||
|
||||
|
||||
/* Init TIMER0 as Frame Sync 1 generator */
|
||||
void InitTIMER0(void)
|
||||
{
|
||||
*pTIMER_DISABLE |= TIMDIS0; /* disable Timer */
|
||||
SSYNC();
|
||||
*pTIMER_STATUS |= TIMIL0 | TOVF_ERR0 | TRUN0; /* clear status */
|
||||
SSYNC();
|
||||
|
||||
*pTIMER0_PERIOD = H_PERIOD;
|
||||
SSYNC();
|
||||
*pTIMER0_WIDTH = H_PULSE;
|
||||
SSYNC();
|
||||
|
||||
*pTIMER0_CONFIG = PWM_OUT |
|
||||
PERIOD_CNT |
|
||||
TIN_SEL |
|
||||
CLK_SEL |
|
||||
EMU_RUN;
|
||||
SSYNC();
|
||||
}
|
||||
|
||||
void EnableTIMER0(void)
|
||||
{
|
||||
*pTIMER_ENABLE |= TIMEN0;
|
||||
SSYNC();
|
||||
}
|
||||
|
||||
void DisableTIMER0(void)
|
||||
{
|
||||
*pTIMER_DISABLE |= TIMDIS0;
|
||||
SSYNC();
|
||||
}
|
||||
|
||||
|
||||
void InitTIMER1(void)
|
||||
{
|
||||
*pTIMER_DISABLE |= TIMDIS1; /* disable Timer */
|
||||
SSYNC();
|
||||
*pTIMER_STATUS |= TIMIL1 | TOVF_ERR1 | TRUN1; /* clear status */
|
||||
SSYNC();
|
||||
|
||||
|
||||
*pTIMER1_PERIOD = V_PERIOD;
|
||||
SSYNC();
|
||||
*pTIMER1_WIDTH = V_PULSE;
|
||||
SSYNC();
|
||||
|
||||
*pTIMER1_CONFIG = PWM_OUT |
|
||||
PERIOD_CNT |
|
||||
TIN_SEL |
|
||||
CLK_SEL |
|
||||
EMU_RUN;
|
||||
SSYNC();
|
||||
}
|
||||
|
||||
void EnableTIMER1(void)
|
||||
{
|
||||
*pTIMER_ENABLE |= TIMEN1;
|
||||
SSYNC();
|
||||
}
|
||||
|
||||
void DisableTIMER1(void)
|
||||
{
|
||||
*pTIMER_DISABLE |= TIMDIS1;
|
||||
SSYNC();
|
||||
}
|
||||
|
||||
int video_init(void *dst)
|
||||
{
|
||||
|
||||
Init_Ports();
|
||||
Init_DMA(dst);
|
||||
EnableDMA();
|
||||
InitTIMER0();
|
||||
InitTIMER1();
|
||||
Init_PPI();
|
||||
EnablePPI();
|
||||
|
||||
/* Frame sync 2 (VS) needs to start at least one PPI clk earlier */
|
||||
EnableTIMER1();
|
||||
/* Add Some Delay ... */
|
||||
SSYNC();
|
||||
SSYNC();
|
||||
SSYNC();
|
||||
SSYNC();
|
||||
|
||||
/* now start frame sync 1 */
|
||||
EnableTIMER0();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void dma_bitblit(void *dst, fastimage_t *logo, int x, int y)
|
||||
{
|
||||
if (dcache_status())
|
||||
blackfin_dcache_flush_range(logo->data, logo->data + logo->size);
|
||||
|
||||
bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
|
||||
|
||||
/* Setup destination start address */
|
||||
bfin_write_MDMA_D0_START_ADDR(dst + ((x & -2) * LCD_PIXEL_SIZE)
|
||||
+ (y * LCD_X_RES * LCD_PIXEL_SIZE));
|
||||
/* Setup destination xcount */
|
||||
bfin_write_MDMA_D0_X_COUNT(logo->width * LCD_PIXEL_SIZE / DMA_SIZE16);
|
||||
/* Setup destination xmodify */
|
||||
bfin_write_MDMA_D0_X_MODIFY(DMA_SIZE16);
|
||||
|
||||
/* Setup destination ycount */
|
||||
bfin_write_MDMA_D0_Y_COUNT(logo->height);
|
||||
/* Setup destination ymodify */
|
||||
bfin_write_MDMA_D0_Y_MODIFY((LCD_X_RES - logo->width) * LCD_PIXEL_SIZE + DMA_SIZE16);
|
||||
|
||||
|
||||
/* Setup Source start address */
|
||||
bfin_write_MDMA_S0_START_ADDR(logo->data);
|
||||
/* Setup Source xcount */
|
||||
bfin_write_MDMA_S0_X_COUNT(logo->width * LCD_PIXEL_SIZE / DMA_SIZE16);
|
||||
/* Setup Source xmodify */
|
||||
bfin_write_MDMA_S0_X_MODIFY(DMA_SIZE16);
|
||||
|
||||
/* Setup Source ycount */
|
||||
bfin_write_MDMA_S0_Y_COUNT(logo->height);
|
||||
/* Setup Source ymodify */
|
||||
bfin_write_MDMA_S0_Y_MODIFY(DMA_SIZE16);
|
||||
|
||||
|
||||
/* Enable source DMA */
|
||||
bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_16 | DMA2D);
|
||||
SSYNC();
|
||||
bfin_write_MDMA_D0_CONFIG(WNR | DMAEN | WDSIZE_16 | DMA2D);
|
||||
|
||||
while (bfin_read_MDMA_D0_IRQ_STATUS() & DMA_RUN);
|
||||
|
||||
bfin_write_MDMA_S0_IRQ_STATUS(bfin_read_MDMA_S0_IRQ_STATUS() | DMA_DONE | DMA_ERR);
|
||||
bfin_write_MDMA_D0_IRQ_STATUS(bfin_read_MDMA_D0_IRQ_STATUS() | DMA_DONE | DMA_ERR);
|
||||
|
||||
}
|
||||
|
||||
void video_putc(const char c)
|
||||
{
|
||||
}
|
||||
|
||||
void video_puts(const char *s)
|
||||
{
|
||||
}
|
||||
|
||||
int drv_video_init(void)
|
||||
{
|
||||
int error, devices = 1;
|
||||
device_t videodev;
|
||||
|
||||
u8 *dst;
|
||||
u32 fbmem_size = LCD_X_RES * LCD_Y_RES * LCD_PIXEL_SIZE + ACTIVE_VIDEO_MEM_OFFSET;
|
||||
|
||||
dst = malloc(fbmem_size);
|
||||
|
||||
if (dst == NULL) {
|
||||
printf("Failed to alloc FB memory\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
#ifdef EASYLOGO_ENABLE_GZIP
|
||||
unsigned char *data = EASYLOGO_DECOMP_BUFFER;
|
||||
unsigned long src_len = EASYLOGO_ENABLE_GZIP;
|
||||
if (gunzip(data, bfin_logo.size, bfin_logo.data, &src_len)) {
|
||||
puts("Failed to decompress logo\n");
|
||||
free(dst);
|
||||
return -1;
|
||||
}
|
||||
bfin_logo.data = data;
|
||||
#endif
|
||||
|
||||
memset(dst + ACTIVE_VIDEO_MEM_OFFSET, bfin_logo.data[0], fbmem_size - ACTIVE_VIDEO_MEM_OFFSET);
|
||||
|
||||
dma_bitblit(dst + ACTIVE_VIDEO_MEM_OFFSET, &bfin_logo,
|
||||
(LCD_X_RES - bfin_logo.width) / 2,
|
||||
(LCD_Y_RES - bfin_logo.height) / 2);
|
||||
|
||||
video_init(dst); /* Video initialization */
|
||||
|
||||
memset(&videodev, 0, sizeof(videodev));
|
||||
|
||||
strcpy(videodev.name, "video");
|
||||
videodev.ext = DEV_EXT_VIDEO; /* Video extensions */
|
||||
videodev.flags = DEV_FLAGS_SYSTEM; /* No Output */
|
||||
videodev.putc = video_putc; /* 'putc' function */
|
||||
videodev.puts = video_puts; /* 'puts' function */
|
||||
|
||||
error = device_register(&videodev);
|
||||
|
||||
return (error == 0) ? devices : error;
|
||||
}
|
||||
|
|
@ -0,0 +1,172 @@
|
|||
/*
|
||||
* U-boot - Configuration file for BF537 STAMP board
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_BF527_EZKIT_H__
|
||||
#define __CONFIG_BF527_EZKIT_H__
|
||||
|
||||
#include <asm/blackfin-config-pre.h>
|
||||
|
||||
|
||||
/*
|
||||
* Processor Settings
|
||||
*/
|
||||
#define CONFIG_BFIN_CPU bf527-0.0
|
||||
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA
|
||||
|
||||
|
||||
/*
|
||||
* Clock Settings
|
||||
* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
|
||||
* SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
|
||||
*/
|
||||
/* CONFIG_CLKIN_HZ is any value in Hz */
|
||||
#define CONFIG_CLKIN_HZ 25000000
|
||||
/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
|
||||
/* 1 = CLKIN / 2 */
|
||||
#define CONFIG_CLKIN_HALF 0
|
||||
/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
|
||||
/* 1 = bypass PLL */
|
||||
#define CONFIG_PLL_BYPASS 0
|
||||
/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
|
||||
/* Values can range from 0-63 (where 0 means 64) */
|
||||
#define CONFIG_VCO_MULT 21
|
||||
/* CCLK_DIV controls the core clock divider */
|
||||
/* Values can be 1, 2, 4, or 8 ONLY */
|
||||
#define CONFIG_CCLK_DIV 1
|
||||
/* SCLK_DIV controls the system clock divider */
|
||||
/* Values can range from 1-15 */
|
||||
#define CONFIG_SCLK_DIV 4
|
||||
|
||||
|
||||
/*
|
||||
* Memory Settings
|
||||
*/
|
||||
#define CONFIG_MEM_ADD_WDTH 10
|
||||
#define CONFIG_MEM_SIZE 64
|
||||
|
||||
#define CONFIG_EBIU_SDRRC_VAL 0x03F6
|
||||
#define CONFIG_EBIU_SDGCTL_VAL (SCTLE | CL_3 | PASR_ALL | TRAS_6 | TRP_3 | TRCD_3 | TWR_2 | PSS)
|
||||
|
||||
#define CONFIG_EBIU_AMGCTL_VAL (AMCKEN | AMBEN_ALL)
|
||||
#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_15 | B1RAT_15 | B1HT_3 | B1RDYPOL | B0WAT_15 | B0RAT_15 | B0HT_3 | B0RDYPOL)
|
||||
#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_15 | B3RAT_15 | B3HT_3 | B3RDYPOL | B2WAT_15 | B2RAT_15 | B2HT_3 | B2RDYPOL)
|
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
|
||||
#define CONFIG_SYS_MALLOC_LEN (640 * 1024)
|
||||
|
||||
|
||||
/*
|
||||
* NAND Settings
|
||||
* (can't be used same time as ethernet)
|
||||
*/
|
||||
#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
|
||||
#define CONFIG_BFIN_NFC
|
||||
#endif
|
||||
#ifdef CONFIG_BFIN_NFC
|
||||
#define CONFIG_BFIN_NFC_CTL_VAL 0x0033
|
||||
#define CONFIG_DRIVER_NAND_BFIN
|
||||
#define CONFIG_SYS_NAND_BASE 0 /* not actually used */
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||
#define NAND_MAX_CHIPS 1
|
||||
#define CONFIG_CMD_NAND
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* Network Settings
|
||||
*/
|
||||
#if !defined(__ADSPBF522__) && !defined(__ADSPBF523__) && \
|
||||
!defined(__ADSPBF524__) && !defined(__ADSPBF525__) && !defined(CONFIG_BFIN_NFC)
|
||||
#define ADI_CMDS_NETWORK 1
|
||||
#define CONFIG_BFIN_MAC
|
||||
#define CONFIG_RMII
|
||||
#define CONFIG_NETCONSOLE 1
|
||||
#define CONFIG_NET_MULTI 1
|
||||
#endif
|
||||
#define CONFIG_HOSTNAME bf527-ezkit
|
||||
/* Uncomment next line to use fixed MAC address */
|
||||
/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
|
||||
|
||||
|
||||
/*
|
||||
* Flash Settings
|
||||
*/
|
||||
#define CONFIG_FLASH_CFI_DRIVER
|
||||
#define CONFIG_SYS_FLASH_BASE 0x20000000
|
||||
#define CONFIG_SYS_FLASH_CFI
|
||||
#define CONFIG_SYS_FLASH_PROTECTION
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 259
|
||||
|
||||
|
||||
/*
|
||||
* SPI Settings
|
||||
*/
|
||||
#define CONFIG_BFIN_SPI
|
||||
#define CONFIG_ENV_SPI_MAX_HZ 30000000
|
||||
#define CONFIG_SF_DEFAULT_HZ 30000000
|
||||
#define CONFIG_SPI_FLASH
|
||||
#define CONFIG_SPI_FLASH_STMICRO
|
||||
|
||||
|
||||
/*
|
||||
* Env Storage Settings
|
||||
*/
|
||||
#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
|
||||
#define CONFIG_ENV_IS_IN_SPI_FLASH
|
||||
#define CONFIG_ENV_OFFSET 0x4000
|
||||
#define CONFIG_ENV_SIZE 0x2000
|
||||
#define CONFIG_ENV_SECT_SIZE 0x2000
|
||||
#else
|
||||
#define CONFIG_ENV_IS_IN_FLASH
|
||||
#define CONFIG_ENV_OFFSET 0x4000
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
|
||||
#define CONFIG_ENV_SIZE 0x2000
|
||||
#define CONFIG_ENV_SECT_SIZE 0x2000
|
||||
#endif
|
||||
#define ENV_IS_EMBEDDED_CUSTOM
|
||||
|
||||
|
||||
/*
|
||||
* I2C Settings
|
||||
*/
|
||||
#define CONFIG_BFIN_TWI_I2C 1
|
||||
#define CONFIG_HARD_I2C 1
|
||||
#define CONFIG_SYS_I2C_SPEED 50000
|
||||
#define CONFIG_SYS_I2C_SLAVE 0
|
||||
|
||||
|
||||
/*
|
||||
* USB Settings
|
||||
*/
|
||||
#if !defined(__ADSPBF522__) && !defined(__ADSPBF523__)
|
||||
#define CONFIG_USB
|
||||
#define CONFIG_MUSB_HCD
|
||||
#define CONFIG_USB_BLACKFIN
|
||||
#define CONFIG_USB_STORAGE
|
||||
#define CONFIG_MUSB_TIMEOUT 100000
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* Misc Settings
|
||||
*/
|
||||
#define CONFIG_MISC_INIT_R
|
||||
#define CONFIG_RTC_BFIN
|
||||
#define CONFIG_UART_CONSOLE 1
|
||||
|
||||
/* Don't waste time transferring a logo over the UART */
|
||||
#if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_UART)
|
||||
# define CONFIG_VIDEO
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* Pull in common ADI header for remaining command/environment setup
|
||||
*/
|
||||
#include <configs/bfin_adi_common.h>
|
||||
|
||||
#include <asm/blackfin-config-post.h>
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue