phone-side
/
uboot-mt623x
9
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

ppc4xx: Fix problem in 44x cache POST routine 

As repoted by Larry Johnson, running "diag run cache" caused a crash
in U-Boot. This problem was introduced by a patch that removed the
TLB entry for the cache test after the test has completed. Since this
TLB was only setup once, a 2nd attempt to run this cache test
failed with a crash. Now this TLB entry is created every time the
routine is called.

Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Roese 2007-12-22 12:18:26 +01:00
parent b0265b576b
commit d91722102c
1 changed files with 18 additions and 21 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
post/cpu/ppc4xx/cache.c
View File

@ -51,8 +51,6 @@ int cache_post_test4 (int tlb, void *p, int size);
int cache_post_test5 (int tlb, void *p, int size);
int cache_post_test6 (int tlb, void *p, int size);
static int tlb = -1; /* index to the victim TLB entry */
#ifdef CONFIG_440
static unsigned char testarea[CACHE_POST_SIZE]
__attribute__((__aligned__(CACHE_POST_SIZE)));
@ -72,14 +70,14 @@ int cache_post_test (int flags)
*/
#ifdef CONFIG_440
int word0, i;
int tlb; /* index to the victim TLB entry */
if (tlb < 0) {
/*
* Allocate a new TLB entry, since we are going to modify
* the write-through and caching inhibited storage attributes.
*/
program_tlb((u32)testarea, (u32)virt,
CACHE_POST_SIZE, TLB_WORD2_I_ENABLE);
program_tlb((u32)testarea, (u32)virt, CACHE_POST_SIZE,
TLB_WORD2_I_ENABLE);
/* Find the TLB entry */
for (i = 0;; i++) {
@ -93,7 +91,6 @@ int cache_post_test (int flags)
break;
}
}
}
#endif
ints = disable_interrupts ();