powerpc/85xx: Removed support for ATUM8548 board
The ATUM8548 board is no longer maintained and thus we are removing support for it. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Kumar Gala
parent
c6b734f5ae
commit
d761fa6205
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@ -256,10 +256,6 @@ Sangmoon Kim <dogoil@etinsys.com>
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debris MPC8245
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KVME080 MPC8245
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Robert Lazarski <robertlazarski@gmail.com>
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ATUM8548 MPC8548
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The LEOX team <team@leox.org>
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ELPT860 MPC860T
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@ -1,57 +0,0 @@
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#
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# Copyright 2004 Freescale Semiconductor.
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# (C) Copyright 2001-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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ifneq ($(OBJTREE),$(SRCTREE))
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$(shell mkdir -p $(obj)../common)
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endif
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LIB = $(obj)lib$(BOARD).o
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COBJS-y += $(BOARD).o
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COBJS-y += law.o
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COBJS-y += tlb.o
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COBJS-$(CONFIG_FSL_DDR2) += ddr.o
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SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS-y))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS)
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$(call cmd_link_o_target, $(OBJS))
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clean:
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rm -f $(OBJS) $(SOBJS)
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distclean: clean
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rm -f $(LIB) core *.bak $(obj).depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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@ -1,297 +0,0 @@
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/*
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* Copyright 2007
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* Robert Lazarski, Instituto Atlantico, robertlazarski@gmail.com
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*
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* Copyright 2007 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <command.h>
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#include <pci.h>
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#include <asm/processor.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_pci.h>
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#include <asm/fsl_ddr_sdram.h>
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#include <asm/io.h>
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#include <asm/mmu.h>
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#include <spd_sdram.h>
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#include <miiphy.h>
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#include <libfdt.h>
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#include <fdt_support.h>
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long int fixed_sdram(void);
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int board_early_init_f (void)
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{
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return 0;
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}
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int checkboard (void)
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{
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
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volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
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if ((uint)&gur->porpllsr != 0xe00e0000) {
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printf("immap size error %lx\n",(ulong)&gur->porpllsr);
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}
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printf ("Board: ATUM8548\n");
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lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
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lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
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ecm->eedr = 0xffffffff; /* Clear ecm errors */
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ecm->eeer = 0xffffffff; /* Enable ecm errors */
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return 0;
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}
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#if !defined(CONFIG_SPD_EEPROM)
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/*************************************************************************
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* fixed sdram init -- doesn't use serial presence detect.
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************************************************************************/
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long int fixed_sdram (void)
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{
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volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
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ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
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ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
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ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
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ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
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ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
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ddr->sdram_mode = CONFIG_SYS_DDR_MODE;
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ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
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#if defined (CONFIG_DDR_ECC)
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ddr->err_disable = 0x0000000D;
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ddr->err_sbe = 0x00ff0000;
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#endif
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asm("sync;isync;msync");
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udelay(500);
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#if defined (CONFIG_DDR_ECC)
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/* Enable ECC checking */
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ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
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#else
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ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
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#endif
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asm("sync; isync; msync");
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udelay(500);
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return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
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}
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#endif /* !defined(CONFIG_SPD_EEPROM) */
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phys_size_t
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initdram(int board_type)
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{
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long dram_size = 0;
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puts("Initializing\n");
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#if defined(CONFIG_SPD_EEPROM)
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puts("fsl_ddr_sdram\n");
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dram_size = fsl_ddr_sdram();
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dram_size = setup_ddr_tlbs(dram_size / 0x100000);
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dram_size *= 0x100000;
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#else
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puts("fixed_sdram\n");
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dram_size = fixed_sdram ();
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#endif
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puts(" DDR: ");
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return dram_size;
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}
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#if defined(CONFIG_SYS_DRAM_TEST)
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int
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testdram(void)
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{
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uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
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uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
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uint *p;
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printf("Testing DRAM from 0x%08x to 0x%08x\n",
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CONFIG_SYS_MEMTEST_START,
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CONFIG_SYS_MEMTEST_END);
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printf("DRAM test phase 1:\n");
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for (p = pstart; p < pend; p++) {
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printf ("DRAM test attempting to write 0xaaaaaaaa at: %08x\n", (uint) p);
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*p = 0xaaaaaaaa;
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}
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for (p = pstart; p < pend; p++) {
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if (*p != 0xaaaaaaaa) {
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printf ("DRAM test fails at: %08x\n", (uint) p);
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return 1;
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}
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}
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printf("DRAM test phase 2:\n");
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for (p = pstart; p < pend; p++)
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*p = 0x55555555;
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for (p = pstart; p < pend; p++) {
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if (*p != 0x55555555) {
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printf ("DRAM test fails at: %08x\n", (uint) p);
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return 1;
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}
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}
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printf("DRAM test passed.\n");
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return 0;
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}
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#endif
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#ifdef CONFIG_PCI1
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static struct pci_controller pci1_hose;
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#endif
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#ifdef CONFIG_PCI2
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static struct pci_controller pci2_hose;
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#endif
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#ifdef CONFIG_PCIE1
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static struct pci_controller pcie1_hose;
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#endif
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void pci_init_board(void)
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{
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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struct fsl_pci_info pci_info[3];
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u32 devdisr, pordevsr, io_sel;
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u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
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int first_free_busno = 0;
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int num = 0;
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int pcie_ep, pcie_configured;
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devdisr = in_be32(&gur->devdisr);
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pordevsr = in_be32(&gur->pordevsr);
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porpllsr = in_be32(&gur->porpllsr);
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io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
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debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
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/* explicitly set 'Clock out select register' to echo SYSCLK input to our CPLD */
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setbits_be32(&gur->clkocr, MPC85xx_ATUM_CLKOCR);
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if (io_sel & 1) {
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if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
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printf("eTSEC1 is in sgmii mode.\n");
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if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
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printf("eTSEC2 is in sgmii mode.\n");
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if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
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printf("eTSEC3 is in sgmii mode.\n");
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if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS))
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printf("eTSEC4 is in sgmii mode.\n");
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}
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#ifdef CONFIG_PCIE1
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pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
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if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
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SET_STD_PCIE_INFO(pci_info[num], 1);
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pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
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#ifdef CONFIG_SYS_PCIE1_MEM_BUS2
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/* outbound memory */
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pci_set_region(&pcie1_hose.regions[0],
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CONFIG_SYS_PCIE1_MEM_BUS2,
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CONFIG_SYS_PCIE1_MEM_PHYS2,
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CONFIG_SYS_PCIE1_MEM_SIZE2,
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PCI_REGION_MEM);
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pcie1_hose.region_count = 1;
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#endif
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printf ("PCIE1: connected to Slot as %s (base addr %lx)\n",
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pcie_ep ? "Endpoint" : "Root Complex",
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pci_info[num].regs);
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first_free_busno = fsl_pci_init_port(&pci_info[num++],
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&pcie1_hose, first_free_busno);
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} else {
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printf("PCIE1: disabled\n");
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}
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puts("\n");
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#else
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setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
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#endif
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#ifdef CONFIG_PCI1
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pci_speed = 33333000; /*get_clock_freq (); PCI PSPEED in [4:5] */
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pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */
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pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
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pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
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if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
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SET_STD_PCI_INFO(pci_info[num], 1);
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pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
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printf("PCI1: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
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(pci_32) ? 32 : 64,
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(pci_speed == 33333000) ? "33" :
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(pci_speed == 66666000) ? "66" : "unknown",
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pci_clk_sel ? "sync" : "async",
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pci_agent ? "agent" : "host",
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pci_arb ? "arbiter" : "external-arbiter",
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pci_info[num].regs);
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first_free_busno = fsl_pci_init_port(&pci_info[num++],
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&pci1_hose, first_free_busno);
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} else {
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printf("PCI1: disabled\n");
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}
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puts("\n");
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#else
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setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
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#endif
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#ifdef CONFIG_PCI2
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if (!(devdisr & MPC85xx_DEVDISR_PCI2)) {
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SET_STD_PCI_INFO(pci_info[num], 2);
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pci_agent = fsl_setup_hose(&pci2_hose, pci_info[num].regs);
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puts("PCI2\n");
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first_free_busno = fsl_pci_init_port(&pci_info[num++],
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&pci1_hose, first_free_busno);
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} else {
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printf("PCI2: disabled\n");
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}
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puts("\n");
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#else
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setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable */
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#endif
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}
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int last_stage_init(void)
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{
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int ic = icache_status ();
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printf ("icache_status: %d\n", ic);
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return 0;
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}
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#if defined(CONFIG_OF_BOARD_SETUP)
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void ft_board_setup(void *blob, bd_t *bd)
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{
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ft_cpu_setup(blob, bd);
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FT_FSL_PCI_SETUP;
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}
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#endif
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@ -1,83 +0,0 @@
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/*
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* Copyright 2008 Freescale Semiconductor, Inc.
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*
|
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* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* Version 2 as published by the Free Software Foundation.
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*/
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#include <common.h>
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#include <i2c.h>
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#include <asm/fsl_ddr_sdram.h>
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#include <asm/fsl_ddr_dimm_params.h>
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static void
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get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
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{
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i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t));
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}
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unsigned int fsl_ddr_get_mem_data_rate(void)
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{
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return get_ddr_freq(0);
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}
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void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
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unsigned int ctrl_num)
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{
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unsigned int i;
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if (ctrl_num) {
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printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
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return;
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}
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for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
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get_spd(&(ctrl_dimms_spd[i]), SPD_EEPROM_ADDRESS);
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}
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}
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void fsl_ddr_board_options(memctl_options_t *popts,
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dimm_params_t *pdimm,
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unsigned int ctrl_num)
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{
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/*
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* Factors to consider for clock adjust:
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* - number of chips on bus
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* - position of slot
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* - DDR1 vs. DDR2?
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* - ???
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*
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* This needs to be determined on a board-by-board basis.
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* 0110 3/4 cycle late
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* 0111 7/8 cycle late
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*/
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popts->clk_adjust = 7;
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|
||||
/*
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||||
* Factors to consider for CPO:
|
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* - frequency
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||||
* - ddr1 vs. ddr2
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||||
*/
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||||
popts->cpo_override = 10;
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||||
/*
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* Factors to consider for write data delay:
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||||
* - number of DIMMs
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||||
*
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||||
* 1 = 1/4 clock delay
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||||
* 2 = 1/2 clock delay
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* 3 = 3/4 clock delay
|
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* 4 = 1 clock delay
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||||
* 5 = 5/4 clock delay
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||||
* 6 = 3/2 clock delay
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||||
*/
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||||
popts->write_data_delay = 3;
|
||||
|
||||
/*
|
||||
* Factors to consider for half-strength driver enable:
|
||||
* - number of DIMMs installed
|
||||
*/
|
||||
popts->half_strength_driver_enable = 0;
|
||||
}
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|
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@ -1,61 +0,0 @@
|
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/*
|
||||
* Copyright 2008 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* (C) Copyright 2000
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/fsl_law.h>
|
||||
#include <asm/mmu.h>
|
||||
|
||||
/*
|
||||
* LAW(Local Access Window) configuration:
|
||||
*
|
||||
* 0x0000_0000 0x7fff_ffff DDR 2G
|
||||
* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
|
||||
* 0xa000_0000 0xbfff_ffff PCIe MEM 512M
|
||||
* 0xc000_0000 0xdfff_ffff PCI2 MEM 512M
|
||||
* 0xe000_0000 0xe000_ffff CCSR 1M
|
||||
* 0xe200_0000 0xe10f_ffff PCI1 IO 1M
|
||||
* 0xe280_0000 0xe20f_ffff PCI2 IO 1M
|
||||
* 0xe300_0000 0xe30f_ffff PCIe IO 1M
|
||||
* 0xf800_0000 0xffff_ffff FLASH (boot bank) 128M
|
||||
*
|
||||
* Notes:
|
||||
* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
|
||||
* If flash is 8M at default position (last 8M), no LAW needed.
|
||||
*
|
||||
* LAW 0 is reserved for boot mapping
|
||||
*/
|
||||
|
||||
struct law_entry law_table[] = {
|
||||
SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
|
||||
SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_1),
|
||||
SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
|
||||
SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2),
|
||||
SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1),
|
||||
SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_1),
|
||||
/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
|
||||
SET_LAW(CONFIG_SYS_LBC_CACHE_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
|
||||
};
|
||||
|
||||
int num_law_entries = ARRAY_SIZE(law_table);
|
||||
|
|
@ -1,90 +0,0 @@
|
|||
/*
|
||||
* Copyright 2008 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* (C) Copyright 2000
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/mmu.h>
|
||||
|
||||
struct fsl_e_tlb_entry tlb_table[] = {
|
||||
/* TLB 0 - for temp stack in cache */
|
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
|
||||
/* TLB 1 Initializations */
|
||||
/*
|
||||
* TLB 0, 1: 128M Non-cacheable, guarded
|
||||
* 0xf8000000 128M FLASH
|
||||
* Out of reset this entry is only 4K.
|
||||
*/
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x4000000, CONFIG_SYS_FLASH_BASE + 0x4000000,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 0, BOOKE_PAGESZ_64M, 1),
|
||||
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 1, BOOKE_PAGESZ_64M, 1),
|
||||
|
||||
/*
|
||||
* TLB 2: 1G Non-cacheable, guarded
|
||||
* 0x80000000 1G PCI1/PCIE 8,9,a,b
|
||||
*/
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCI_PHYS, CONFIG_SYS_PCI_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 2, BOOKE_PAGESZ_1G, 1),
|
||||
|
||||
/*
|
||||
* TLB 3, 4: 512M Non-cacheable, guarded
|
||||
* 0xc0000000 1G PCI2
|
||||
*/
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS, CONFIG_SYS_PCI2_MEM_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 3, BOOKE_PAGESZ_256M, 1),
|
||||
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 4, BOOKE_PAGESZ_256M, 1),
|
||||
|
||||
/*
|
||||
* TLB 5: 64M Non-cacheable, guarded
|
||||
* 0xe000_0000 1M CCSRBAR
|
||||
* 0xe200_0000 1M PCI1 IO
|
||||
* 0xe210_0000 1M PCI2 IO
|
||||
* 0xe300_0000 1M PCIe IO
|
||||
*/
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 5, BOOKE_PAGESZ_64M, 1),
|
||||
};
|
||||
|
||||
int num_tlb_entries = ARRAY_SIZE(tlb_table);
|
||||
|
|
@ -441,7 +441,6 @@ MVBLM7 powerpc mpc83xx mvblm7 matrix_
|
|||
SIMPC8313_LP powerpc mpc83xx simpc8313 sheldon - SIMPC8313:NAND_LP
|
||||
SIMPC8313_SP powerpc mpc83xx simpc8313 sheldon - SIMPC8313:NAND_SP
|
||||
TQM834x powerpc mpc83xx tqm834x tqc
|
||||
ATUM8548 powerpc mpc85xx atum8548
|
||||
MPC8540EVAL powerpc mpc85xx mpc8540eval - - MPC8540EVAL:SYSCLK_66M
|
||||
MPC8540EVAL_33 powerpc mpc85xx mpc8540eval - - MPC8540EVAL
|
||||
MPC8540EVAL_33_slave powerpc mpc85xx mpc8540eval - - MPC8540EVAL:PCI_SLAVE
|
||||
|
|
|
|||
|
|
@ -1,29 +0,0 @@
|
|||
Building U-Boot
|
||||
---------------
|
||||
|
||||
The ATUM8548 code is known to build using ELDK 4.1.
|
||||
|
||||
$ make ATUM8548_config
|
||||
Configuring for ATUM8548 board...
|
||||
$ make
|
||||
|
||||
Using Flash
|
||||
-----------
|
||||
|
||||
The ATUM8548 board has one flash bank, of 128MB in size (2^23 = 0x08000000).
|
||||
|
||||
The BDI2000 commands for copying u-boot into flash are
|
||||
as follows:
|
||||
|
||||
erase 0xFFF80000 0x4000 0x20
|
||||
prog 0xfff80000 uboot.bin bin
|
||||
|
||||
Booting Linux
|
||||
-------------
|
||||
|
||||
U-boot/kermit commands for booting linux via NFS - assumming the proper
|
||||
bootargs are set - are as follows:
|
||||
|
||||
tftp 1000000 uImage.atum
|
||||
tftp c00000 mpc8548atum.dtb
|
||||
bootm 1000000 - c00000
|
||||
|
|
@ -1,443 +0,0 @@
|
|||
/*
|
||||
* Copyright 2007
|
||||
* Robert Lazarski, Instituto Atlantico, robertlazarski@gmail.com
|
||||
*
|
||||
* Copyright 2004, 2007 Freescale Semiconductor.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* atum8548 board configuration file
|
||||
*
|
||||
* Please refer to doc/README.atum8548 for more info.
|
||||
*
|
||||
*/
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/* Debug Options, Disable in production
|
||||
#define ET_DEBUG 1
|
||||
#define CONFIG_PANIC_HANG 1
|
||||
#define DEBUG 1
|
||||
*/
|
||||
|
||||
/* CPLD Configuration Options */
|
||||
#define MPC85xx_ATUM_CLKOCR 0x80000002
|
||||
|
||||
/* High Level Configuration Options */
|
||||
#define CONFIG_BOOKE 1 /* BOOKE */
|
||||
#define CONFIG_E500 1 /* BOOKE e500 family */
|
||||
#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
|
||||
#define CONFIG_MPC8548 1 /* MPC8548 specific */
|
||||
|
||||
#ifndef CONFIG_SYS_TEXT_BASE
|
||||
#define CONFIG_SYS_TEXT_BASE 0xfff80000
|
||||
#endif
|
||||
|
||||
#define CONFIG_PCI 1 /* enable any pci type devices */
|
||||
#define CONFIG_PCI1 1 /* PCI controller 1 */
|
||||
#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
|
||||
#define CONFIG_PCI2 1 /* PCI controller 2 */
|
||||
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
|
||||
|
||||
#define CONFIG_TSEC_ENET 1 /* tsec ethernet support */
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
|
||||
|
||||
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
|
||||
|
||||
#define CONFIG_SYS_CLK_FREQ 33000000
|
||||
|
||||
/*
|
||||
* These can be toggled for performance analysis, otherwise use default.
|
||||
*/
|
||||
#define CONFIG_L2_CACHE /* toggle L2 cache */
|
||||
#define CONFIG_BTB /* toggle branch predition */
|
||||
|
||||
/*
|
||||
* Only possible on E500 Version 2 or newer cores.
|
||||
*/
|
||||
#define CONFIG_ENABLE_36BIT_PHYS 1
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
|
||||
|
||||
#define CONFIG_CMD_SDRAM 1 /* SDRAM DIMM SPD info printout */
|
||||
#define CONFIG_ENABLE_36BIT_PHYS 1
|
||||
#undef CONFIG_SYS_DRAM_TEST
|
||||
#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
|
||||
#define CONFIG_SYS_MEMTEST_END 0x00400000
|
||||
|
||||
/*
|
||||
* Base addresses -- Note these are effective addresses where the
|
||||
* actual resources get mapped (not physical addresses)
|
||||
*/
|
||||
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
|
||||
#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
|
||||
#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
|
||||
#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
|
||||
|
||||
#define PCI_SPEED 33333000 /* CPLD currenlty does not have PCI setup info */
|
||||
|
||||
/* DDR Setup */
|
||||
#define CONFIG_FSL_DDR2
|
||||
#undef CONFIG_FSL_DDR_INTERACTIVE
|
||||
#define CONFIG_DDR_ECC /* only for ECC DDR module */
|
||||
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
|
||||
#define CONFIG_DDR_SPD
|
||||
|
||||
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
|
||||
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
|
||||
|
||||
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
|
||||
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
|
||||
#define CONFIG_VERY_BIG_RAM
|
||||
|
||||
#define CONFIG_NUM_DDR_CONTROLLERS 1
|
||||
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
|
||||
#define CONFIG_CHIP_SELECTS_PER_CTRL 2
|
||||
|
||||
/* I2C addresses of SPD EEPROMs */
|
||||
#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
|
||||
|
||||
/* Manually set up DDR parameters */
|
||||
#define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1024MB */
|
||||
#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f /* 0-1024 */
|
||||
#define CONFIG_SYS_DDR_CS0_CONFIG 0x80000102
|
||||
#define CONFIG_SYS_DDR_TIMING_0 0x00260802
|
||||
#define CONFIG_SYS_DDR_TIMING_1 0x38355322
|
||||
#define CONFIG_SYS_DDR_TIMING_2 0x039048c7
|
||||
#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
|
||||
#define CONFIG_SYS_DDR_MODE 0x00000432
|
||||
#define CONFIG_SYS_DDR_INTERVAL 0x05150100
|
||||
#define DDR_SDRAM_CFG 0x43000000
|
||||
|
||||
#undef CONFIG_CLOCKS_IN_MHZ
|
||||
|
||||
/*
|
||||
* Local Bus Definitions
|
||||
*/
|
||||
|
||||
/*
|
||||
* FLASH on the Local Bus
|
||||
* based on flash chip S29GL01GP
|
||||
* One bank, 128M, using the CFI driver.
|
||||
* Boot from BR0 bank at 0xf800_0000
|
||||
*
|
||||
* BR0:
|
||||
* Base address 0 = 0xF8000000 = BR0[0:16] = 1111 1000 0000 0000 0
|
||||
* Port Size = 16 bits = BRx[19:20] = 10
|
||||
* Use GPCM = BRx[24:26] = 000
|
||||
* Valid = BRx[31] = 1
|
||||
*
|
||||
* 0 4 8 12 16 20 24 28
|
||||
* 1111 1000 0000 0000 0001 0000 0000 0001 = f8001001 BR0
|
||||
*
|
||||
* OR0:
|
||||
* Addr Mask = 128M = ORx[0:16] = 1111 1000 0000 0000 0
|
||||
* Reserved ORx[17:18] = 00
|
||||
* CSNT = ORx[20] = 1
|
||||
* ACS = half cycle delay = ORx[21:22] = 11
|
||||
* SCY = 6 = ORx[24:27] = 0110
|
||||
* TRLX = use relaxed timing = ORx[29] = 1
|
||||
* EAD = use external address latch delay = OR[31] = 1
|
||||
*
|
||||
* 0 4 8 12 16 20 24 28
|
||||
* 1111 1000 0000 0000 0000 1110 0110 0101 = f8000E65 ORx
|
||||
*/
|
||||
|
||||
#define CONFIG_SYS_BOOT_BLOCK 0xf8000000 /* boot TLB block */
|
||||
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK /* start of FLASH 128M */
|
||||
|
||||
#define CONFIG_SYS_BR0_PRELIM 0xf8001001
|
||||
|
||||
#define CONFIG_SYS_OR0_PRELIM 0xf8000E65
|
||||
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
|
||||
#undef CONFIG_SYS_FLASH_CHECKSUM
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 512000 /* Flash Erase Timeout (ms) */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 8000 /* Flash Write Timeout (ms) */
|
||||
|
||||
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
|
||||
|
||||
#define CONFIG_FLASH_CFI_DRIVER 1
|
||||
#define CONFIG_SYS_FLASH_CFI 1
|
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO
|
||||
|
||||
/*
|
||||
* Flash on the LocalBus
|
||||
*/
|
||||
#define CONFIG_SYS_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */
|
||||
|
||||
/* Memory */
|
||||
#define CONFIG_SYS_INIT_RAM_LOCK 1
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
|
||||
|
||||
#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */
|
||||
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
|
||||
#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
|
||||
|
||||
/* Serial Port */
|
||||
#define CONFIG_CONS_INDEX 1
|
||||
#define CONFIG_SYS_NS16550
|
||||
#define CONFIG_SYS_NS16550_SERIAL
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE 1
|
||||
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
|
||||
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE \
|
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
|
||||
|
||||
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
|
||||
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
|
||||
|
||||
/* Use the HUSH parser */
|
||||
#define CONFIG_SYS_HUSH_PARSER
|
||||
#ifdef CONFIG_SYS_HUSH_PARSER
|
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
|
||||
#endif
|
||||
|
||||
/* pass open firmware flat tree */
|
||||
#define CONFIG_OF_LIBFDT 1
|
||||
#define CONFIG_OF_BOARD_SETUP 1
|
||||
|
||||
/*
|
||||
* I2C
|
||||
*/
|
||||
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support*/
|
||||
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
|
||||
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x3000
|
||||
|
||||
/*
|
||||
* General PCI
|
||||
* Memory space is mapped 1-1, but I/O space must start from 0.
|
||||
*/
|
||||
#define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */
|
||||
|
||||
#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
|
||||
#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS
|
||||
#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
|
||||
#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
|
||||
#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
|
||||
#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
|
||||
|
||||
#ifdef CONFIG_PCI2
|
||||
#define CONFIG_SYS_PCI2_MEM_BUS 0xC0000000
|
||||
#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BUS
|
||||
#define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */
|
||||
#define CONFIG_SYS_PCI2_IO_BUS 0x00000000
|
||||
#define CONFIG_SYS_PCI2_IO_PHYS 0xe2800000
|
||||
#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PCIE1
|
||||
#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
|
||||
#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
|
||||
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
|
||||
#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
|
||||
#define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000
|
||||
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */
|
||||
#endif
|
||||
|
||||
|
||||
#if !defined(CONFIG_PCI_PNP)
|
||||
#define PCI_ENET0_IOADDR 0xe0000000
|
||||
#define PCI_ENET0_MEMADDR 0xe0000000
|
||||
#define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_PCI)
|
||||
|
||||
#define CONFIG_NET_MULTI
|
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */
|
||||
|
||||
#undef CONFIG_EEPRO100
|
||||
#undef CONFIG_TULIP
|
||||
|
||||
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
||||
|
||||
#endif /* CONFIG_PCI */
|
||||
|
||||
#if defined(CONFIG_TSEC_ENET)
|
||||
|
||||
#ifndef CONFIG_NET_MULTI
|
||||
#define CONFIG_NET_MULTI 1
|
||||
#endif
|
||||
|
||||
#define CONFIG_MII 1 /* MII PHY management */
|
||||
#define CONFIG_TSEC1 1
|
||||
#define CONFIG_TSEC1_NAME "eTSEC0"
|
||||
#define CONFIG_TSEC2 1
|
||||
#define CONFIG_TSEC2_NAME "eTSEC1"
|
||||
#define CONFIG_TSEC3 1
|
||||
#define CONFIG_TSEC3_NAME "eTSEC2"
|
||||
#define CONFIG_TSEC4 1
|
||||
#define CONFIG_TSEC4_NAME "eTSEC3"
|
||||
#undef CONFIG_MPC85XX_FEC
|
||||
|
||||
#define TSEC1_PHY_ADDR 0
|
||||
#define TSEC2_PHY_ADDR 1
|
||||
#define TSEC3_PHY_ADDR 2
|
||||
#define TSEC4_PHY_ADDR 3
|
||||
|
||||
#define TSEC1_PHYIDX 0
|
||||
#define TSEC2_PHYIDX 0
|
||||
#define TSEC3_PHYIDX 0
|
||||
#define TSEC4_PHYIDX 0
|
||||
#define TSEC1_FLAGS TSEC_GIGABIT
|
||||
#define TSEC2_FLAGS TSEC_GIGABIT
|
||||
#define TSEC3_FLAGS TSEC_GIGABIT
|
||||
#define TSEC4_FLAGS TSEC_GIGABIT
|
||||
|
||||
/* Options are: eTSEC[0-3] */
|
||||
#define CONFIG_ETHPRIME "eTSEC2"
|
||||
#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
|
||||
#endif /* CONFIG_TSEC_ENET */
|
||||
|
||||
/*
|
||||
* Environment
|
||||
*/
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
|
||||
#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
|
||||
#define CONFIG_ENV_SIZE 0x2000
|
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
|
||||
|
||||
/*
|
||||
* BOOTP options
|
||||
*/
|
||||
#define CONFIG_BOOTP_BOOTFILESIZE
|
||||
#define CONFIG_BOOTP_BOOTPATH
|
||||
#define CONFIG_BOOTP_GATEWAY
|
||||
#define CONFIG_BOOTP_HOSTNAME
|
||||
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_CMD_MII
|
||||
|
||||
#if defined(CONFIG_PCI)
|
||||
#define CONFIG_CMD_PCI
|
||||
#endif
|
||||
|
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
|
||||
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
|
||||
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
|
||||
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
|
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Environment Configuration
|
||||
*/
|
||||
|
||||
/* The mac addresses for all ethernet interface */
|
||||
#if defined(CONFIG_TSEC_ENET)
|
||||
#define CONFIG_HAS_ETH0
|
||||
#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
|
||||
#define CONFIG_HAS_ETH1
|
||||
#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
|
||||
#define CONFIG_HAS_ETH2
|
||||
#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
|
||||
#define CONFIG_HAS_ETH3
|
||||
#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD
|
||||
#endif
|
||||
|
||||
#define CONFIG_IPADDR 10.101.43.142
|
||||
|
||||
#define CONFIG_HOSTNAME atum
|
||||
#define CONFIG_ROOTPATH /nfsroot
|
||||
#define CONFIG_BOOTFILE /tftpboot/uImage.atum
|
||||
#define CONFIG_UBOOTPATH /tftpboot/uboot.bin /* TFTP server */
|
||||
|
||||
#define CONFIG_SERVERIP 10.101.43.10
|
||||
#define CONFIG_GATEWAYIP 10.101.45.1
|
||||
#define CONFIG_NETMASK 255.255.248.0
|
||||
|
||||
#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
|
||||
|
||||
#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
|
||||
#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
|
||||
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
#define CONFIG_NFSBOOTCOMMAND \
|
||||
"setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=$serverip:$rootpath " \
|
||||
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $dtbaddr $dtbfile;" \
|
||||
"bootm $loadaddr - $dtbaddr"
|
||||
|
||||
|
||||
#define CONFIG_RAMBOOTCOMMAND \
|
||||
"setenv bootargs root=/dev/ram rw " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $ramdiskaddr $ramdiskfile;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $dtbaddr $dtbfile;" \
|
||||
"bootm $loadaddr $ramdiskaddr $dtbaddr"
|
||||
|
||||
#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in New Issue