Wolfgang Denk
12 years ago
commit
d628866474
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/*
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* dma.h - Blackfin DMA defines/structures/etc... |
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* |
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* Copyright 2004-2008 Analog Devices Inc. |
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* Licensed under the GPL-2 or later. |
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*/ |
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#ifndef _BLACKFIN_DMA_H_ |
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#define _BLACKFIN_DMA_H_ |
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#include <asm/mach-common/bits/dma.h> |
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struct dmasg_large { |
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void *next_desc_addr; |
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unsigned long start_addr; |
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unsigned short cfg; |
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unsigned short x_count; |
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short x_modify; |
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unsigned short y_count; |
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short y_modify; |
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} __attribute__((packed)); |
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struct dmasg { |
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unsigned long start_addr; |
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unsigned short cfg; |
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unsigned short x_count; |
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short x_modify; |
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unsigned short y_count; |
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short y_modify; |
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} __attribute__((packed)); |
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struct dma_register { |
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void *next_desc_ptr; /* DMA Next Descriptor Pointer register */ |
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unsigned long start_addr; /* DMA Start address register */ |
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unsigned short cfg; /* DMA Configuration register */ |
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unsigned short dummy1; /* DMA Configuration register */ |
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unsigned long reserved; |
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unsigned short x_count; /* DMA x_count register */ |
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unsigned short dummy2; |
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short x_modify; /* DMA x_modify register */ |
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unsigned short dummy3; |
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unsigned short y_count; /* DMA y_count register */ |
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unsigned short dummy4; |
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short y_modify; /* DMA y_modify register */ |
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unsigned short dummy5; |
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void *curr_desc_ptr; /* DMA Current Descriptor Pointer
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register */ |
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unsigned long curr_addr_ptr; /* DMA Current Address Pointer
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register */ |
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unsigned short irq_status; /* DMA irq status register */ |
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unsigned short dummy6; |
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unsigned short peripheral_map; /* DMA peripheral map register */ |
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unsigned short dummy7; |
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unsigned short curr_x_count; /* DMA Current x-count register */ |
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unsigned short dummy8; |
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unsigned long reserved2; |
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unsigned short curr_y_count; /* DMA Current y-count register */ |
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unsigned short dummy9; |
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unsigned long reserved3; |
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}; |
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#endif |
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File diff suppressed because it is too large
Load Diff
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/* DO NOT EDIT THIS FILE
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* Automatically generated by generate-def-headers.xsl |
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* DO NOT EDIT THIS FILE |
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*/ |
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#ifndef __BFIN_DEF_ADSP_BF512_proc__ |
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#define __BFIN_DEF_ADSP_BF512_proc__ |
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#include "../mach-common/ADSP-EDN-core_def.h" |
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#define PLL_CTL 0xFFC00000 /* PLL Control Register */ |
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#define PLL_DIV 0xFFC00004 /* PLL Divide Register */ |
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#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */ |
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#define PLL_STAT 0xFFC0000C /* PLL Status Register */ |
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#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */ |
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#define CHIPID 0xFFC00014 |
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#define SWRST 0xFFC00100 /* Software Reset Register */ |
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#define SYSCR 0xFFC00104 /* System Configuration register */ |
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#define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register */ |
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#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */ |
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#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */ |
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#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */ |
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#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */ |
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#define SIC_ISR0 0xFFC00120 /* Interrupt Status Register */ |
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#define SIC_IWR0 0xFFC00124 /* Interrupt Wakeup Register */ |
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#define SIC_IMASK1 0xFFC0014C /* Interrupt Mask register of SIC2 */ |
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#define SIC_IAR4 0xFFC00150 /* Interrupt Assignment register4 */ |
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#define SIC_IAR5 0xFFC00154 /* Interrupt Assignment register5 */ |
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#define SIC_IAR6 0xFFC00158 /* Interrupt Assignment register6 */ |
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#define SIC_IAR7 0xFFC0015C /* Interrupt Assignment register7 */ |
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#define SIC_ISR1 0xFFC00160 /* Interrupt Status register */ |
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#define SIC_IWR1 0xFFC00164 /* Interrupt Wakeup register */ |
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#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */ |
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#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */ |
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#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */ |
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#define RTC_STAT 0xFFC00300 /* RTC Status Register */ |
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#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */ |
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#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */ |
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#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */ |
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#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */ |
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#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Register */ |
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#define UART0_THR 0xFFC00400 /* Transmit Holding register */ |
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#define UART0_RBR 0xFFC00400 /* Receive Buffer register */ |
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#define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */ |
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#define UART0_IER 0xFFC00404 /* Interrupt Enable Register */ |
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#define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */ |
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#define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */ |
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#define UART0_LCR 0xFFC0040C /* Line Control Register */ |
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#define UART0_MCR 0xFFC00410 /* Modem Control Register */ |
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#define UART0_LSR 0xFFC00414 /* Line Status Register */ |
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#define UART0_MSR 0xFFC00418 /* Modem Status Register */ |
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#define UART0_SCR 0xFFC0041C /* SCR Scratch Register */ |
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#define UART0_GCTL 0xFFC00424 /* Global Control Register */ |
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#define SPI0_CTL 0xFFC00500 /* SPI0 Control Register */ |
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#define SPI0_FLG 0xFFC00504 /* SPI0 Flag register */ |
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#define SPI0_STAT 0xFFC00508 /* SPI0 Status register */ |
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#define SPI0_TDBR 0xFFC0050C /* SPI0 Transmit Data Buffer Register */ |
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#define SPI0_RDBR 0xFFC00510 /* SPI0 Receive Data Buffer Register */ |
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#define SPI0_BAUD 0xFFC00514 /* SPI0 Baud rate Register */ |
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#define SPI0_SHADOW 0xFFC00518 /* SPI0_RDBR Shadow Register */ |
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#define SPI1_CTL 0xFFC03400 /* SPI1 Control */ |
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#define SPI1_FLG 0xFFC03404 /* SPI1 Flag Register */ |
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#define SPI1_STAT 0xFFC03408 /* SPI1 Status Register */ |
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#define SPI1_TDBR 0xFFC0340C /* SPI1 Transmit Data Buffer */ |
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#define SPI1_RDBR 0xFFC03410 /* SPI1 Receive Data Buffer */ |
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#define SPI1_BAUD 0xFFC03414 /* SPI1 Baud Rate */ |
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#define SPI1_SHADOW 0xFFC03418 /* SPI1_RDBR Shadow Register */ |
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#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */ |
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#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */ |
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#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */ |
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#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */ |
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#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */ |
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#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */ |
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#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */ |
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#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */ |
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#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */ |
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#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */ |
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#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */ |
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#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */ |
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#define TIMER3_CONFIG 0xFFC00630 /* Timer 3 Configuration Register */ |
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#define TIMER3_COUNTER 0xFFC00634 /* Timer 3 Counter Register */ |
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#define TIMER3_PERIOD 0xFFC00638 /* Timer 3 Period Register */ |
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#define TIMER3_WIDTH 0xFFC0063C /* Timer 3 Width Register */ |
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#define TIMER4_CONFIG 0xFFC00640 /* Timer 4 Configuration Register */ |
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#define TIMER4_COUNTER 0xFFC00644 /* Timer 4 Counter Register */ |
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#define TIMER4_PERIOD 0xFFC00648 /* Timer 4 Period Register */ |
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#define TIMER4_WIDTH 0xFFC0064C /* Timer 4 Width Register */ |
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#define TIMER5_CONFIG 0xFFC00650 /* Timer 5 Configuration Register */ |
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#define TIMER5_COUNTER 0xFFC00654 /* Timer 5 Counter Register */ |
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#define TIMER5_PERIOD 0xFFC00658 /* Timer 5 Period Register */ |
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#define TIMER5_WIDTH 0xFFC0065C /* Timer 5 Width Register */ |
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#define TIMER6_CONFIG 0xFFC00660 /* Timer 6 Configuration Register */ |
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#define TIMER6_COUNTER 0xFFC00664 /* Timer 6 Counter Register */ |
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#define TIMER6_PERIOD 0xFFC00668 /* Timer 6 Period Register */ |
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#define TIMER6_WIDTH 0xFFC0066C /* Timer 6 Width Register\n */ |
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#define TIMER7_CONFIG 0xFFC00670 /* Timer 7 Configuration Register */ |
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#define TIMER7_COUNTER 0xFFC00674 /* Timer 7 Counter Register */ |
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#define TIMER7_PERIOD 0xFFC00678 /* Timer 7 Period Register */ |
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#define TIMER7_WIDTH 0xFFC0067C /* Timer 7 Width Register */ |
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#define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */ |
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#define TIMER_DISABLE 0xFFC00684 /* Timer Disable Register */ |
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#define TIMER_STATUS 0xFFC00688 /* Timer Status Register */ |
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#define PORTFIO 0xFFC00700 /* Port F I/O Pin State Specify Register */ |
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#define PORTFIO_CLEAR 0xFFC00704 /* Port F I/O Peripheral Interrupt Clear Register */ |
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#define PORTFIO_SET 0xFFC00708 /* Port F I/O Peripheral Interrupt Set Register */ |
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#define PORTFIO_TOGGLE 0xFFC0070C /* Port F I/O Pin State Toggle Register */ |
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#define PORTFIO_MASKA 0xFFC00710 /* Port F I/O Mask State Specify Interrupt A Register */ |
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#define PORTFIO_MASKA_CLEAR 0xFFC00714 /* Port F I/O Mask Disable Interrupt A Register */ |
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#define PORTFIO_MASKA_SET 0xFFC00718 /* Port F I/O Mask Enable Interrupt A Register */ |
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#define PORTFIO_MASKA_TOGGLE 0xFFC0071C /* Port F I/O Mask Toggle Enable Interrupt A Register */ |
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#define PORTFIO_MASKB 0xFFC00720 /* Port F I/O Mask State Specify Interrupt B Register */ |
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#define PORTFIO_MASKB_CLEAR 0xFFC00724 /* Port F I/O Mask Disable Interrupt B Register */ |
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#define PORTFIO_MASKB_SET 0xFFC00728 /* Port F I/O Mask Enable Interrupt B Register */ |
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#define PORTFIO_MASKB_TOGGLE 0xFFC0072C /* Port F I/O Mask Toggle Enable Interrupt B Register */ |
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#define PORTFIO_DIR 0xFFC00730 /* Port F I/O Direction Register */ |
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#define PORTFIO_POLAR 0xFFC00734 /* Port F I/O Source Polarity Register */ |
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#define PORTFIO_EDGE 0xFFC00738 /* Port F I/O Source Sensitivity Register */ |
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#define PORTFIO_BOTH 0xFFC0073C /* Port F I/O Set on BOTH Edges Register */ |
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#define PORTFIO_INEN 0xFFC00740 /* Port F I/O Input Enable Register */ |
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#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */ |
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#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ |
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#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */ |
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#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */ |
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#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */ |
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#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */ |
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#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */ |
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#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */ |
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#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */ |
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#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */ |
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#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */ |
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#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */ |
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#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */ |
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#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */ |
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#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */ |
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#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */ |
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#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */ |
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#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */ |
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#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */ |
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#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */ |
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#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */ |
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#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */ |
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#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */ |
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#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */ |
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#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */ |
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#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */ |
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#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */ |
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#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */ |
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#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */ |
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#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */ |
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#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */ |
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#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */ |
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#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */ |
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#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */ |
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#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */ |
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#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */ |
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#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */ |
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#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */ |
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#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */ |
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#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */ |
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#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */ |
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#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */ |
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#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */ |
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#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */ |
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#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */ |
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#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */ |
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#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */ |
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#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */ |
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#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */ |
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#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */ |
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#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */ |
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#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */ |
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#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */ |
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#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */ |
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#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */ |
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#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */ |
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#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */ |
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#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */ |
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#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */ |
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#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */ |
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#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */ |
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#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */ |
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#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */ |
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#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */ |
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#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */ |
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#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */ |
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#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */ |
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#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */ |
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#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */ |
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#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */ |
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#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */ |
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#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */ |
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#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */ |
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#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */ |
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#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */ |
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#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */ |
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#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */ |
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#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */ |
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#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */ |
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#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */ |
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#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */ |
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#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */ |
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#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */ |
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#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */ |
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#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */ |
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#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */ |
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#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */ |
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#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */ |
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#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */ |
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#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */ |
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#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */ |
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#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */ |
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#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */ |
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#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */ |
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#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */ |
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#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */ |
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#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */ |
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#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */ |
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#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */ |
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#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */ |
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#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */ |
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#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */ |
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#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */ |
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#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */ |
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#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */ |
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#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */ |
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#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */ |
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#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */ |
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#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */ |
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#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */ |
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#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */ |
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#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */ |
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#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */ |
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#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */ |
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#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */ |
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#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */ |
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#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */ |
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#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */ |
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#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */ |
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#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */ |
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#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */ |
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#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */ |
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#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */ |
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#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */ |
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#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */ |
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#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */ |
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#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */ |
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#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */ |
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#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */ |
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#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */ |
||||
#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */ |
||||
#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */ |
||||
#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */ |
||||
#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */ |
||||
#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */ |
||||
#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */ |
||||
#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */ |
||||
#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */ |
||||
#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */ |
||||
#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */ |
||||
#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */ |
||||
#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */ |
||||
#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */ |
||||
#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */ |
||||
#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */ |
||||
#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */ |
||||
#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */ |
||||
#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */ |
||||
#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */ |
||||
#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */ |
||||
#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */ |
||||
#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */ |
||||
#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */ |
||||
#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */ |
||||
#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */ |
||||
#define DMA8_NEXT_DESC_PTR 0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */ |
||||
#define DMA8_START_ADDR 0xFFC00E04 /* DMA Channel 8 Start Address Register */ |
||||
#define DMA8_CONFIG 0xFFC00E08 /* DMA Channel 8 Configuration Register */ |
||||
#define DMA8_X_COUNT 0xFFC00E10 /* DMA Channel 8 X Count Register */ |
||||
#define DMA8_X_MODIFY 0xFFC00E14 /* DMA Channel 8 X Modify Register */ |
||||
#define DMA8_Y_COUNT 0xFFC00E18 /* DMA Channel 8 Y Count Register */ |
||||
#define DMA8_Y_MODIFY 0xFFC00E1C /* DMA Channel 8 Y Modify Register */ |
||||
#define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */ |
||||
#define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */ |
||||
#define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */ |
||||
#define DMA8_PERIPHERAL_MAP 0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */ |
||||
#define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */ |
||||
#define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */ |
||||
#define DMA9_NEXT_DESC_PTR 0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */ |
||||
#define DMA9_START_ADDR 0xFFC00E44 /* DMA Channel 9 Start Address Register */ |
||||
#define DMA9_CONFIG 0xFFC00E48 /* DMA Channel 9 Configuration Register */ |
||||
#define DMA9_X_COUNT 0xFFC00E50 /* DMA Channel 9 X Count Register */ |
||||
#define DMA9_X_MODIFY 0xFFC00E54 /* DMA Channel 9 X Modify Register */ |
||||
#define DMA9_Y_COUNT 0xFFC00E58 /* DMA Channel 9 Y Count Register */ |
||||
#define DMA9_Y_MODIFY 0xFFC00E5C /* DMA Channel 9 Y Modify Register */ |
||||
#define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */ |
||||
#define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */ |
||||
#define DMA9_IRQ_STATUS 0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */ |
||||
#define DMA9_PERIPHERAL_MAP 0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */ |
||||
#define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */ |
||||
#define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */ |
||||
#define DMA10_NEXT_DESC_PTR 0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */ |
||||
#define DMA10_START_ADDR 0xFFC00E84 /* DMA Channel 10 Start Address Register */ |
||||
#define DMA10_CONFIG 0xFFC00E88 /* DMA Channel 10 Configuration Register */ |
||||
#define DMA10_X_COUNT 0xFFC00E90 /* DMA Channel 10 X Count Register */ |
||||
#define DMA10_X_MODIFY 0xFFC00E94 /* DMA Channel 10 X Modify Register */ |
||||
#define DMA10_Y_COUNT 0xFFC00E98 /* DMA Channel 10 Y Count Register */ |
||||
#define DMA10_Y_MODIFY 0xFFC00E9C /* DMA Channel 10 Y Modify Register */ |
||||
#define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */ |
||||
#define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */ |
||||
#define DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */ |
||||
#define DMA10_PERIPHERAL_MAP 0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */ |
||||
#define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */ |
||||
#define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */ |
||||
#define DMA11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */ |
||||
#define DMA11_START_ADDR 0xFFC00EC4 /* DMA Channel 11 Start Address Register */ |
||||
#define DMA11_CONFIG 0xFFC00EC8 /* DMA Channel 11 Configuration Register */ |
||||
#define DMA11_X_COUNT 0xFFC00ED0 /* DMA Channel 11 X Count Register */ |
||||
#define DMA11_X_MODIFY 0xFFC00ED4 /* DMA Channel 11 X Modify Register */ |
||||
#define DMA11_Y_COUNT 0xFFC00ED8 /* DMA Channel 11 Y Count Register */ |
||||
#define DMA11_Y_MODIFY 0xFFC00EDC /* DMA Channel 11 Y Modify Register */ |
||||
#define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */ |
||||
#define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */ |
||||
#define DMA11_IRQ_STATUS 0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */ |
||||
#define DMA11_PERIPHERAL_MAP 0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */ |
||||
#define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */ |
||||
#define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */ |
||||
#define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */ |
||||
#define MDMA_S0_START_ADDR 0xFFC00F44 /* MemDMA Stream 0 Source Start Address Register */ |
||||
#define MDMA_S0_CONFIG 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */ |
||||
#define MDMA_S0_X_COUNT 0xFFC00F50 /* MemDMA Stream 0 Source X Count Register */ |
||||
#define MDMA_S0_X_MODIFY 0xFFC00F54 /* MemDMA Stream 0 Source X Modify Register */ |
||||
#define MDMA_S0_Y_COUNT 0xFFC00F58 /* MemDMA Stream 0 Source Y Count Register */ |
||||
#define MDMA_S0_Y_MODIFY 0xFFC00F5C /* MemDMA Stream 0 Source Y Modify Register */ |
||||
#define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */ |
||||
#define MDMA_S0_CURR_ADDR 0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */ |
||||
#define MDMA_S0_IRQ_STATUS 0xFFC00F68 /* MemDMA Stream 0 Source Interrupt/Status Register */ |
||||
#define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /* MemDMA Stream 0 Source Peripheral Map Register */ |
||||
#define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */ |
||||
#define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */ |
||||
#define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */ |
||||
#define MDMA_D0_START_ADDR 0xFFC00F04 /* MemDMA Stream 0 Destination Start Address Register */ |
||||
#define MDMA_D0_CONFIG 0xFFC00F08 /* MemDMA Stream 0 Destination Configuration Register */ |
||||
#define MDMA_D0_X_COUNT 0xFFC00F10 /* MemDMA Stream 0 Destination X Count Register */ |
||||
#define MDMA_D0_X_MODIFY 0xFFC00F14 /* MemDMA Stream 0 Destination X Modify Register */ |
||||
#define MDMA_D0_Y_COUNT 0xFFC00F18 /* MemDMA Stream 0 Destination Y Count Register */ |
||||
#define MDMA_D0_Y_MODIFY 0xFFC00F1C /* MemDMA Stream 0 Destination Y Modify Register */ |
||||
#define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */ |
||||
#define MDMA_D0_CURR_ADDR 0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */ |
||||
#define MDMA_D0_IRQ_STATUS 0xFFC00F28 /* MemDMA Stream 0 Destination Interrupt/Status Register */ |
||||
#define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /* MemDMA Stream 0 Destination Peripheral Map Register */ |
||||
#define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */ |
||||
#define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */ |
||||
#define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */ |
||||
#define MDMA_S1_START_ADDR 0xFFC00FC4 /* MemDMA Stream 1 Source Start Address Register */ |
||||
#define MDMA_S1_CONFIG 0xFFC00FC8 /* MemDMA Stream 1 Source Configuration Register */ |
||||
#define MDMA_S1_X_COUNT 0xFFC00FD0 /* MemDMA Stream 1 Source X Count Register */ |
||||
#define MDMA_S1_X_MODIFY 0xFFC00FD4 /* MemDMA Stream 1 Source X Modify Register */ |
||||
#define MDMA_S1_Y_COUNT 0xFFC00FD8 /* MemDMA Stream 1 Source Y Count Register */ |
||||
#define MDMA_S1_Y_MODIFY 0xFFC00FDC /* MemDMA Stream 1 Source Y Modify Register */ |
||||
#define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */ |
||||
#define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */ |
||||
#define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /* MemDMA Stream 1 Source Interrupt/Status Register */ |
||||
#define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /* MemDMA Stream 1 Source Peripheral Map Register */ |
||||
#define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */ |
||||
#define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */ |
||||
#define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */ |
||||
#define MDMA_D1_START_ADDR 0xFFC00F84 /* MemDMA Stream 1 Destination Start Address Register */ |
||||
#define MDMA_D1_CONFIG 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */ |
||||
#define MDMA_D1_X_COUNT 0xFFC00F90 /* MemDMA Stream 1 Destination X Count Register */ |
||||
#define MDMA_D1_X_MODIFY 0xFFC00F94 /* MemDMA Stream 1 Destination X Modify Register */ |
||||
#define MDMA_D1_Y_COUNT 0xFFC00F98 /* MemDMA Stream 1 Destination Y Count Register */ |
||||
#define MDMA_D1_Y_MODIFY 0xFFC00F9C /* MemDMA Stream 1 Destination Y Modify Register */ |
||||
#define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */ |
||||
#define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */ |
||||
#define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */ |
||||
#define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /* MemDMA Stream 1 Destination Peripheral Map Register */ |
||||
#define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */ |
||||
#define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */ |
||||
#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */ |
||||
#define PPI_STATUS 0xFFC01004 /* PPI Status Register */ |
||||
#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */ |
||||
#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */ |
||||
#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */ |
||||
#define TWI_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */ |
||||
#define TWI_CONTROL 0xFFC01404 /* TWI Control Register */ |
||||
#define TWI_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */ |
||||
#define TWI_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */ |
||||
#define TWI_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */ |
||||
#define TWI_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */ |
||||
#define TWI_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */ |
||||
#define TWI_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */ |
||||
#define TWI_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */ |
||||
#define TWI_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */ |
||||
#define TWI_FIFO_CTL 0xFFC01428 /* FIFO Control Register */ |
||||
#define TWI_FIFO_STAT 0xFFC0142C /* FIFO Status Register */ |
||||
#define TWI_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */ |
||||
#define TWI_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */ |
||||
#define TWI_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */ |
||||
#define TWI_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */ |
||||
#define PORTGIO 0xFFC01500 /* Port G I/O Pin State Specify Register */ |
||||
#define PORTGIO_CLEAR 0xFFC01504 /* Port G I/O Peripheral Interrupt Clear Register */ |
||||
#define PORTGIO_SET 0xFFC01508 /* Port G I/O Peripheral Interrupt Set Register */ |
||||
#define PORTGIO_TOGGLE 0xFFC0150C /* Port G I/O Pin State Toggle Register */ |
||||
#define PORTGIO_MASKA 0xFFC01510 /* Port G I/O Mask State Specify Interrupt A Register */ |
||||
#define PORTGIO_MASKA_CLEAR 0xFFC01514 /* Port G I/O Mask Disable Interrupt A Register */ |
||||
#define PORTGIO_MASKA_SET 0xFFC01518 /* Port G I/O Mask Enable Interrupt A Register */ |
||||
#define PORTGIO_MASKA_TOGGLE 0xFFC0151C /* Port G I/O Mask Toggle Enable Interrupt A Register */ |
||||
#define PORTGIO_MASKB 0xFFC01520 /* Port G I/O Mask State Specify Interrupt B Register */ |
||||
#define PORTGIO_MASKB_CLEAR 0xFFC01524 /* Port G I/O Mask Disable Interrupt B Register */ |
||||
#define PORTGIO_MASKB_SET 0xFFC01528 /* Port G I/O Mask Enable Interrupt B Register */ |
||||
#define PORTGIO_MASKB_TOGGLE 0xFFC0152C /* Port G I/O Mask Toggle Enable Interrupt B Register */ |
||||
#define PORTGIO_DIR 0xFFC01530 /* Port G I/O Direction Register */ |
||||
#define PORTGIO_POLAR 0xFFC01534 /* Port G I/O Source Polarity Register */ |
||||
#define PORTGIO_EDGE 0xFFC01538 /* Port G I/O Source Sensitivity Register */ |
||||
#define PORTGIO_BOTH 0xFFC0153C /* Port G I/O Set on BOTH Edges Register */ |
||||
#define PORTGIO_INEN 0xFFC01540 /* Port G I/O Input Enable Register */ |
||||
#define PORTHIO 0xFFC01700 /* Port H I/O Pin State Specify Register */ |
||||
#define PORTHIO_CLEAR 0xFFC01704 /* Port H I/O Peripheral Interrupt Clear Register */ |
||||
#define PORTHIO_SET 0xFFC01708 /* Port H I/O Peripheral Interrupt Set Register */ |
||||
#define PORTHIO_TOGGLE 0xFFC0170C /* Port H I/O Pin State Toggle Register */ |
||||
#define PORTHIO_MASKA 0xFFC01710 /* Port H I/O Mask State Specify Interrupt A Register */ |
||||
#define PORTHIO_MASKA_CLEAR 0xFFC01714 /* Port H I/O Mask Disable Interrupt A Register */ |
||||
#define PORTHIO_MASKA_SET 0xFFC01718 /* Port H I/O Mask Enable Interrupt A Register */ |
||||
#define PORTHIO_MASKA_TOGGLE 0xFFC0171C /* Port H I/O Mask Toggle Enable Interrupt A Register */ |
||||
#define PORTHIO_MASKB 0xFFC01720 /* Port H I/O Mask State Specify Interrupt B Register */ |
||||
#define PORTHIO_MASKB_CLEAR 0xFFC01724 /* Port H I/O Mask Disable Interrupt B Register */ |
||||
#define PORTHIO_MASKB_SET 0xFFC01728 /* Port H I/O Mask Enable Interrupt B Register */ |
||||
#define PORTHIO_MASKB_TOGGLE 0xFFC0172C /* Port H I/O Mask Toggle Enable Interrupt B Register */ |
||||
#define PORTHIO_DIR 0xFFC01730 /* Port H I/O Direction Register */ |
||||
#define PORTHIO_POLAR 0xFFC01734 /* Port H I/O Source Polarity Register */ |
||||
#define PORTHIO_EDGE 0xFFC01738 /* Port H I/O Source Sensitivity Register */ |
||||
#define PORTHIO_BOTH 0xFFC0173C /* Port H I/O Set on BOTH Edges Register */ |
||||
#define PORTHIO_INEN 0xFFC01740 /* Port H I/O Input Enable Register */ |
||||
#define UART1_THR 0xFFC02000 /* Transmit Holding register */ |
||||
#define UART1_RBR 0xFFC02000 /* Receive Buffer register */ |
||||
#define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */ |
||||
#define UART1_IER 0xFFC02004 /* Interrupt Enable Register */ |
||||
#define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */ |
||||
#define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */ |
||||
#define UART1_LCR 0xFFC0200C /* Line Control Register */ |
||||
#define UART1_MCR 0xFFC02010 /* Modem Control Register */ |
||||
#define UART1_LSR 0xFFC02014 /* Line Status Register */ |
||||
#define UART1_MSR 0xFFC02018 /* Modem Status Register */ |
||||
#define UART1_SCR 0xFFC0201C /* SCR Scratch Register */ |
||||
#define UART1_GCTL 0xFFC02024 /* Global Control Register */ |
||||
#define PORTF_FER 0xFFC03200 /* Port F Function Enable Register (Alternate/Flag*) */ |
||||
#define PORTG_FER 0xFFC03204 /* Port G Function Enable Register (Alternate/Flag*) */ |
||||
#define PORTH_FER 0xFFC03208 /* Port H Function Enable Register (Alternate/Flag*) */ |
||||
#define HMDMA0_CONTROL 0xFFC03300 /* Handshake MDMA0 Control Register */ |
||||
#define HMDMA0_ECINIT 0xFFC03304 /* HMDMA0 Initial Edge Count Register */ |
||||
#define HMDMA0_BCINIT 0xFFC03308 /* HMDMA0 Initial Block Count Register */ |
||||
#define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshhold Register */ |
||||
#define HMDMA0_ECOVERFLOW 0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */ |
||||
#define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */ |
||||
#define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */ |
||||
#define HMDMA1_CONTROL 0xFFC03340 /* Handshake MDMA1 Control Register */ |
||||
#define HMDMA1_ECINIT 0xFFC03344 /* HMDMA1 Initial Edge Count Register */ |
||||
#define HMDMA1_BCINIT 0xFFC03348 /* HMDMA1 Initial Block Count Register */ |
||||
#define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshhold Register */ |
||||
#define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */ |
||||
#define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */ |
||||
#define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */ |
||||
#define PORTF_MUX 0xFFC03210 /* Port F mux control */ |
||||
#define PORTG_MUX 0xFFC03214 /* Port G mux control */ |
||||
#define PORTH_MUX 0xFFC03218 /* Port H mux control */ |
||||
#define PORTF_DRIVE 0xFFC03220 /* Port F drive strength control */ |
||||
#define PORTG_DRIVE 0xFFC03224 /* Port G drive strength control */ |
||||
#define PORTH_DRIVE 0xFFC03228 /* Port H drive strength control */ |
||||
#define PORTF_HYSTERESIS 0xFFC03240 /* Port F Schmitt trigger control */ |
||||
#define PORTG_HYSTERESIS 0xFFC03244 /* Port G Schmitt trigger control */ |
||||
#define PORTH_HYSTERESIS 0xFFC03248 /* Port H Schmitt trigger control */ |
||||
#define NONGPIO_DRIVE 0xFFC03280 /* Non-GPIO Port drive strength control */ |
||||
#define NONGPIO_HYSTERESIS 0xFFC03288 /* Non-GPIO Port Schmitt trigger control */ |
||||
#define CNT_CONFIG 0xFFC03500 /* Configuration/Control Register */ |
||||
#define CNT_IMASK 0xFFC03504 /* Interrupt Mask Register */ |
||||
#define CNT_STATUS 0xFFC03508 /* Status Register */ |
||||
#define CNT_COMMAND 0xFFC0350C /* Command Register */ |
||||
#define CNT_DEBOUNCE 0xFFC03510 /* Debounce Prescaler Register */ |
||||
#define CNT_COUNTER 0xFFC03514 /* Counter Register */ |
||||
#define CNT_MAX 0xFFC03518 /* Maximal Count Boundary Value Register */ |
||||
#define CNT_MIN 0xFFC0351C /* Minimal Count Boundary Value Register */ |
||||
#define SECURE_SYSSWT 0xFFC03620 /* Secure System Switches */ |
||||
#define SECURE_CONTROL 0xFFC03624 /* Secure Control */ |
||||
#define SECURE_STATUS 0xFFC03628 /* Secure Status */ |
||||
#define OTP_DATA0 0xFFC03680 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ |
||||
#define OTP_DATA1 0xFFC03684 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ |
||||
#define OTP_DATA2 0xFFC03688 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ |
||||
#define OTP_DATA3 0xFFC0368C /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ |
||||
#define PWM_CTRL 0xFFC03700 /* PWM Control Register */ |
||||
#define PWM_STAT 0xFFC03704 /* PWM Status Register */ |
||||
#define PWM_TM 0xFFC03708 /* PWM Period Register */ |
||||
#define PWM_DT 0xFFC0370C /* PWM Dead Time Register */ |
||||
#define PWM_GATE 0xFFC03710 /* PWM Chopping Control */ |
||||
#define PWM_CHA 0xFFC03714 /* PWM Channel A Duty Control */ |
||||
#define PWM_CHB 0xFFC03718 /* PWM Channel B Duty Control */ |
||||
#define PWM_CHC 0xFFC0371C /* PWM Channel C Duty Control */ |
||||
#define PWM_SEG 0xFFC03720 /* PWM Crossover and Output Enable */ |
||||
#define PWM_SYNCWT 0xFFC03724 /* PWM Sync pulse width control */ |
||||
#define PWM_CHAL 0xFFC03728 /* PWM Channel AL Duty Control (SR mode only) */ |
||||
#define PWM_CHBL 0xFFC0372C /* PWM Channel BL Duty Control (SR mode only) */ |
||||
#define PWM_CHCL 0xFFC03730 /* PWM Channel CL Duty Control (SR mode only) */ |
||||
#define PWM_LSI 0xFFC03734 /* Low Side Invert (SR mode only) */ |
||||
#define PWM_STAT2 0xFFC03738 /* PWM Status Register */ |
||||
#define DMA_TC_CNT 0xFFC00B0C |
||||
#define DMA_TC_PER 0xFFC00B10 |
||||
|
||||
#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */ |
||||
#define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1) |
||||
#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE) |
||||
#define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000 -> 0xFF903FFF Data Bank B SRAM */ |
||||
#define L1_DATA_B_SRAM_SIZE (0xFF903FFF - 0xFF900000 + 1) |
||||
#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE) |
||||
#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */ |
||||
#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1) |
||||
#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) |
||||
#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */ |
||||
#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1) |
||||
#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE) |
||||
#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */ |
||||
#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1) |
||||
#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE) |
||||
|
||||
#endif /* __BFIN_DEF_ADSP_BF512_proc__ */ |
||||
@ -0,0 +1,68 @@ |
||||
/* DO NOT EDIT THIS FILE
|
||||
* Automatically generated by generate-cdef-headers.xsl |
||||
* DO NOT EDIT THIS FILE |
||||
*/ |
||||
|
||||
#ifndef __BFIN_CDEF_ADSP_BF514_proc__ |
||||
#define __BFIN_CDEF_ADSP_BF514_proc__ |
||||
|
||||
#include "BF512_cdef.h" |
||||
|
||||
#define bfin_read_RSI_PWR_CONTROL() bfin_read16(RSI_PWR_CONTROL) |
||||
#define bfin_write_RSI_PWR_CONTROL(val) bfin_write16(RSI_PWR_CONTROL, val) |
||||
#define bfin_read_RSI_CLK_CONTROL() bfin_read16(RSI_CLK_CONTROL) |
||||
#define bfin_write_RSI_CLK_CONTROL(val) bfin_write16(RSI_CLK_CONTROL, val) |
||||
#define bfin_read_RSI_ARGUMENT() bfin_read32(RSI_ARGUMENT) |
||||
#define bfin_write_RSI_ARGUMENT(val) bfin_write32(RSI_ARGUMENT, val) |
||||
#define bfin_read_RSI_COMMAND() bfin_read16(RSI_COMMAND) |
||||
#define bfin_write_RSI_COMMAND(val) bfin_write16(RSI_COMMAND, val) |
||||
#define bfin_read_RSI_RESP_CMD() bfin_read16(RSI_RESP_CMD) |
||||
#define bfin_write_RSI_RESP_CMD(val) bfin_write16(RSI_RESP_CMD, val) |
||||
#define bfin_read_RSI_RESPONSE0() bfin_read32(RSI_RESPONSE0) |
||||
#define bfin_write_RSI_RESPONSE0(val) bfin_write32(RSI_RESPONSE0, val) |
||||
#define bfin_read_RSI_RESPONSE1() bfin_read32(RSI_RESPONSE1) |
||||
#define bfin_write_RSI_RESPONSE1(val) bfin_write32(RSI_RESPONSE1, val) |
||||
#define bfin_read_RSI_RESPONSE2() bfin_read32(RSI_RESPONSE2) |
||||
#define bfin_write_RSI_RESPONSE2(val) bfin_write32(RSI_RESPONSE2, val) |
||||
#define bfin_read_RSI_RESPONSE3() bfin_read32(RSI_RESPONSE3) |
||||
#define bfin_write_RSI_RESPONSE3(val) bfin_write32(RSI_RESPONSE3, val) |
||||
#define bfin_read_RSI_DATA_TIMER() bfin_read32(RSI_DATA_TIMER) |
||||
#define bfin_write_RSI_DATA_TIMER(val) bfin_write32(RSI_DATA_TIMER, val) |
||||
#define bfin_read_RSI_DATA_LGTH() bfin_read16(RSI_DATA_LGTH) |
||||
#define bfin_write_RSI_DATA_LGTH(val) bfin_write16(RSI_DATA_LGTH, val) |
||||
#define bfin_read_RSI_DATA_CONTROL() bfin_read16(RSI_DATA_CONTROL) |
||||
#define bfin_write_RSI_DATA_CONTROL(val) bfin_write16(RSI_DATA_CONTROL, val) |
||||
#define bfin_read_RSI_DATA_CNT() bfin_read16(RSI_DATA_CNT) |
||||
#define bfin_write_RSI_DATA_CNT(val) bfin_write16(RSI_DATA_CNT, val) |
||||
#define bfin_read_RSI_STATUS() bfin_read32(RSI_STATUS) |
||||
#define bfin_write_RSI_STATUS(val) bfin_write32(RSI_STATUS, val) |
||||
#define bfin_read_RSI_STATUSCL() bfin_read16(RSI_STATUSCL) |
||||
#define bfin_write_RSI_STATUSCL(val) bfin_write16(RSI_STATUSCL, val) |
||||
#define bfin_read_RSI_MASK0() bfin_read32(RSI_MASK0) |
||||
#define bfin_write_RSI_MASK0(val) bfin_write32(RSI_MASK0, val) |
||||
#define bfin_read_RSI_MASK1() bfin_read32(RSI_MASK1) |
||||
#define bfin_write_RSI_MASK1(val) bfin_write32(RSI_MASK1, val) |
||||
#define bfin_read_RSI_FIFO_CNT() bfin_read16(RSI_FIFO_CNT) |
||||
#define bfin_write_RSI_FIFO_CNT(val) bfin_write16(RSI_FIFO_CNT, val) |
||||
#define bfin_read_RSI_CEATA_CONTROL() bfin_read16(RSI_CEATA_CONTROL) |
||||
#define bfin_write_RSI_CEATA_CONTROL(val) bfin_write16(RSI_CEATA_CONTROL, val) |
||||
#define bfin_read_RSI_FIFO() bfin_read32(RSI_FIFO) |
||||
#define bfin_write_RSI_FIFO(val) bfin_write32(RSI_FIFO, val) |
||||
#define bfin_read_RSI_ESTAT() bfin_read16(RSI_ESTAT) |
||||
#define bfin_write_RSI_ESTAT(val) bfin_write16(RSI_ESTAT, val) |
||||
#define bfin_read_RSI_EMASK() bfin_read16(RSI_EMASK) |
||||
#define bfin_write_RSI_EMASK(val) bfin_write16(RSI_EMASK, val) |
||||
#define bfin_read_RSI_CONFIG() bfin_read16(RSI_CONFIG) |
||||
#define bfin_write_RSI_CONFIG(val) bfin_write16(RSI_CONFIG, val) |
||||
#define bfin_read_RSI_RD_WAIT_EN() bfin_read16(RSI_RD_WAIT_EN) |
||||
#define bfin_write_RSI_RD_WAIT_EN(val) bfin_write16(RSI_RD_WAIT_EN, val) |
||||
#define bfin_read_RSI_PID0() bfin_read16(RSI_PID0) |
||||
#define bfin_write_RSI_PID0(val) bfin_write16(RSI_PID0, val) |
||||
#define bfin_read_RSI_PID1() bfin_read16(RSI_PID1) |
||||
#define bfin_write_RSI_PID1(val) bfin_write16(RSI_PID1, val) |
||||
#define bfin_read_RSI_PID2() bfin_read16(RSI_PID2) |
||||
#define bfin_write_RSI_PID2(val) bfin_write16(RSI_PID2, val) |
||||
#define bfin_read_RSI_PID3() bfin_read16(RSI_PID3) |
||||
#define bfin_write_RSI_PID3(val) bfin_write16(RSI_PID3, val) |
||||
|
||||
#endif /* __BFIN_CDEF_ADSP_BF514_proc__ */ |
||||
@ -0,0 +1,40 @@ |
||||
/* DO NOT EDIT THIS FILE
|
||||
* Automatically generated by generate-def-headers.xsl |
||||
* DO NOT EDIT THIS FILE |
||||
*/ |
||||
|
||||
#ifndef __BFIN_DEF_ADSP_BF514_proc__ |
||||
#define __BFIN_DEF_ADSP_BF514_proc__ |
||||
|
||||
#include "BF512_def.h" |
||||
|
||||
#define RSI_PWR_CONTROL 0xFFC03800 /* RSI Power Control Register */ |
||||
#define RSI_CLK_CONTROL 0xFFC03804 /* RSI Clock Control Register */ |
||||
#define RSI_ARGUMENT 0xFFC03808 /* RSI Argument Register */ |
||||
#define RSI_COMMAND 0xFFC0380C /* RSI Command Register */ |
||||
#define RSI_RESP_CMD 0xFFC03810 /* RSI Response Command Register */ |
||||
#define RSI_RESPONSE0 0xFFC03814 /* RSI Response Register */ |
||||
#define RSI_RESPONSE1 0xFFC03818 /* RSI Response Register */ |
||||
#define RSI_RESPONSE2 0xFFC0381C /* RSI Response Register */ |
||||
#define RSI_RESPONSE3 0xFFC03820 /* RSI Response Register */ |
||||
#define RSI_DATA_TIMER 0xFFC03824 /* RSI Data Timer Register */ |
||||
#define RSI_DATA_LGTH 0xFFC03828 /* RSI Data Length Register */ |
||||
#define RSI_DATA_CONTROL 0xFFC0382C /* RSI Data Control Register */ |
||||
#define RSI_DATA_CNT 0xFFC03830 /* RSI Data Counter Register */ |
||||
#define RSI_STATUS 0xFFC03834 /* RSI Status Register */ |
||||
#define RSI_STATUSCL 0xFFC03838 /* RSI Status Clear Register */ |
||||
#define RSI_MASK0 0xFFC0383C /* RSI Interrupt 0 Mask Register */ |
||||
#define RSI_MASK1 0xFFC03840 /* RSI Interrupt 1 Mask Register */ |
||||
#define RSI_FIFO_CNT 0xFFC03848 /* RSI FIFO Counter Register */ |
||||
#define RSI_CEATA_CONTROL 0xFFC0384C /* RSI CEATA Register */ |
||||
#define RSI_FIFO 0xFFC03880 /* RSI Data FIFO Register */ |
||||
#define RSI_ESTAT 0xFFC038C0 /* RSI Exception Status Register */ |
||||
#define RSI_EMASK 0xFFC038C4 /* RSI Exception Mask Register */ |
||||
#define RSI_CONFIG 0xFFC038C8 /* RSI Configuration Register */ |
||||
#define RSI_RD_WAIT_EN 0xFFC038CC /* RSI Read Wait Enable Register */ |
||||
#define RSI_PID0 0xFFC038D0 /* RSI Peripheral ID Register 0 */ |
||||
#define RSI_PID1 0xFFC038D4 /* RSI Peripheral ID Register 1 */ |
||||
#define RSI_PID2 0xFFC038D8 /* RSI Peripheral ID Register 2 */ |
||||
#define RSI_PID3 0xFFC038DC /* RSI Peripheral ID Register 3 */ |
||||
|
||||
#endif /* __BFIN_DEF_ADSP_BF514_proc__ */ |
||||
@ -0,0 +1,170 @@ |
||||
/* DO NOT EDIT THIS FILE
|
||||
* Automatically generated by generate-cdef-headers.xsl |
||||
* DO NOT EDIT THIS FILE |
||||
*/ |
||||
|
||||
#ifndef __BFIN_CDEF_ADSP_BF516_proc__ |
||||
#define __BFIN_CDEF_ADSP_BF516_proc__ |
||||
|
||||
#include "BF514_cdef.h" |
||||
|
||||
#define bfin_read_EMAC_OPMODE() bfin_read32(EMAC_OPMODE) |
||||
#define bfin_write_EMAC_OPMODE(val) bfin_write32(EMAC_OPMODE, val) |
||||
#define bfin_read_EMAC_ADDRLO() bfin_read32(EMAC_ADDRLO) |
||||
#define bfin_write_EMAC_ADDRLO(val) bfin_write32(EMAC_ADDRLO, val) |
||||
#define bfin_read_EMAC_ADDRHI() bfin_read32(EMAC_ADDRHI) |
||||
#define bfin_write_EMAC_ADDRHI(val) bfin_write32(EMAC_ADDRHI, val) |
||||
#define bfin_read_EMAC_HASHLO() bfin_read32(EMAC_HASHLO) |
||||
#define bfin_write_EMAC_HASHLO(val) bfin_write32(EMAC_HASHLO, val) |
||||
#define bfin_read_EMAC_HASHHI() bfin_read32(EMAC_HASHHI) |
||||
#define bfin_write_EMAC_HASHHI(val) bfin_write32(EMAC_HASHHI, val) |
||||
#define bfin_read_EMAC_STAADD() bfin_read32(EMAC_STAADD) |
||||
#define bfin_write_EMAC_STAADD(val) bfin_write32(EMAC_STAADD, val) |
||||
#define bfin_read_EMAC_STADAT() bfin_read32(EMAC_STADAT) |
||||
#define bfin_write_EMAC_STADAT(val) bfin_write32(EMAC_STADAT, val) |
||||
#define bfin_read_EMAC_FLC() bfin_read32(EMAC_FLC) |
||||
#define bfin_write_EMAC_FLC(val) bfin_write32(EMAC_FLC, val) |
||||
#define bfin_read_EMAC_VLAN1() bfin_read32(EMAC_VLAN1) |
||||
#define bfin_write_EMAC_VLAN1(val) bfin_write32(EMAC_VLAN1, val) |
||||
#define bfin_read_EMAC_VLAN2() bfin_read32(EMAC_VLAN2) |
||||
#define bfin_write_EMAC_VLAN2(val) bfin_write32(EMAC_VLAN2, val) |
||||
#define bfin_read_EMAC_WKUP_CTL() bfin_read32(EMAC_WKUP_CTL) |
||||
#define bfin_write_EMAC_WKUP_CTL(val) bfin_write32(EMAC_WKUP_CTL, val) |
||||
#define bfin_read_EMAC_WKUP_FFMSK0() bfin_read32(EMAC_WKUP_FFMSK0) |
||||
#define bfin_write_EMAC_WKUP_FFMSK0(val) bfin_write32(EMAC_WKUP_FFMSK0, val) |
||||
#define bfin_read_EMAC_WKUP_FFMSK1() bfin_read32(EMAC_WKUP_FFMSK1) |
||||
#define bfin_write_EMAC_WKUP_FFMSK1(val) bfin_write32(EMAC_WKUP_FFMSK1, val) |
||||
#define bfin_read_EMAC_WKUP_FFMSK2() bfin_read32(EMAC_WKUP_FFMSK2) |
||||
#define bfin_write_EMAC_WKUP_FFMSK2(val) bfin_write32(EMAC_WKUP_FFMSK2, val) |
||||
#define bfin_read_EMAC_WKUP_FFMSK3() bfin_read32(EMAC_WKUP_FFMSK3) |
||||
#define bfin_write_EMAC_WKUP_FFMSK3(val) bfin_write32(EMAC_WKUP_FFMSK3, val) |
||||
#define bfin_read_EMAC_WKUP_FFCMD() bfin_read32(EMAC_WKUP_FFCMD) |
||||
#define bfin_write_EMAC_WKUP_FFCMD(val) bfin_write32(EMAC_WKUP_FFCMD, val) |
||||
#define bfin_read_EMAC_WKUP_FFOFF() bfin_read32(EMAC_WKUP_FFOFF) |
||||
#define bfin_write_EMAC_WKUP_FFOFF(val) bfin_write32(EMAC_WKUP_FFOFF, val) |
||||
#define bfin_read_EMAC_WKUP_FFCRC0() bfin_read32(EMAC_WKUP_FFCRC0) |
||||
#define bfin_write_EMAC_WKUP_FFCRC0(val) bfin_write32(EMAC_WKUP_FFCRC0, val) |
||||
#define bfin_read_EMAC_WKUP_FFCRC1() bfin_read32(EMAC_WKUP_FFCRC1) |
||||
#define bfin_write_EMAC_WKUP_FFCRC1(val) bfin_write32(EMAC_WKUP_FFCRC1, val) |
||||
#define bfin_read_EMAC_SYSCTL() bfin_read32(EMAC_SYSCTL) |
||||
#define bfin_write_EMAC_SYSCTL(val) bfin_write32(EMAC_SYSCTL, val) |
||||
#define bfin_read_EMAC_SYSTAT() bfin_read32(EMAC_SYSTAT) |
||||
#define bfin_write_EMAC_SYSTAT(val) bfin_write32(EMAC_SYSTAT, val) |
||||
#define bfin_read_EMAC_RX_STAT() bfin_read32(EMAC_RX_STAT) |
||||
#define bfin_write_EMAC_RX_STAT(val) bfin_write32(EMAC_RX_STAT, val) |
||||
#define bfin_read_EMAC_RX_STKY() bfin_read32(EMAC_RX_STKY) |
||||
#define bfin_write_EMAC_RX_STKY(val) bfin_write32(EMAC_RX_STKY, val) |
||||
#define bfin_read_EMAC_RX_IRQE() bfin_read32(EMAC_RX_IRQE) |
||||
#define bfin_write_EMAC_RX_IRQE(val) bfin_write32(EMAC_RX_IRQE, val) |
||||
#define bfin_read_EMAC_TX_STAT() bfin_read32(EMAC_TX_STAT) |
||||
#define bfin_write_EMAC_TX_STAT(val) bfin_write32(EMAC_TX_STAT, val) |
||||
#define bfin_read_EMAC_TX_STKY() bfin_read32(EMAC_TX_STKY) |
||||
#define bfin_write_EMAC_TX_STKY(val) bfin_write32(EMAC_TX_STKY, val) |
||||
#define bfin_read_EMAC_TX_IRQE() bfin_read32(EMAC_TX_IRQE) |
||||
#define bfin_write_EMAC_TX_IRQE(val) bfin_write32(EMAC_TX_IRQE, val) |
||||
#define bfin_read_EMAC_MMC_CTL() bfin_read32(EMAC_MMC_CTL) |
||||
#define bfin_write_EMAC_MMC_CTL(val) bfin_write32(EMAC_MMC_CTL, val) |
||||
#define bfin_read_EMAC_MMC_RIRQS() bfin_read32(EMAC_MMC_RIRQS) |
||||
#define bfin_write_EMAC_MMC_RIRQS(val) bfin_write32(EMAC_MMC_RIRQS, val) |
||||
#define bfin_read_EMAC_MMC_RIRQE() bfin_read32(EMAC_MMC_RIRQE) |
||||
#define bfin_write_EMAC_MMC_RIRQE(val) bfin_write32(EMAC_MMC_RIRQE, val) |
||||
#define bfin_read_EMAC_MMC_TIRQS() bfin_read32(EMAC_MMC_TIRQS) |
||||
#define bfin_write_EMAC_MMC_TIRQS(val) bfin_write32(EMAC_MMC_TIRQS, val) |
||||
#define bfin_read_EMAC_MMC_TIRQE() bfin_read32(EMAC_MMC_TIRQE) |
||||
#define bfin_write_EMAC_MMC_TIRQE(val) bfin_write32(EMAC_MMC_TIRQE, val) |
||||
#define bfin_read_EMAC_RXC_OK() bfin_read32(EMAC_RXC_OK) |
||||
#define bfin_write_EMAC_RXC_OK(val) bfin_write32(EMAC_RXC_OK, val) |
||||
#define bfin_read_EMAC_RXC_FCS() bfin_read32(EMAC_RXC_FCS) |
||||
#define bfin_write_EMAC_RXC_FCS(val) bfin_write32(EMAC_RXC_FCS, val) |
||||
#define bfin_read_EMAC_RXC_ALIGN() bfin_read32(EMAC_RXC_ALIGN) |
||||
#define bfin_write_EMAC_RXC_ALIGN(val) bfin_write32(EMAC_RXC_ALIGN, val) |
||||
#define bfin_read_EMAC_RXC_OCTET() bfin_read32(EMAC_RXC_OCTET) |
||||
#define bfin_write_EMAC_RXC_OCTET(val) bfin_write32(EMAC_RXC_OCTET, val) |
||||
#define bfin_read_EMAC_RXC_DMAOVF() bfin_read32(EMAC_RXC_DMAOVF) |
||||
#define bfin_write_EMAC_RXC_DMAOVF(val) bfin_write32(EMAC_RXC_DMAOVF, val) |
||||
#define bfin_read_EMAC_RXC_UNICST() bfin_read32(EMAC_RXC_UNICST) |
||||
#define bfin_write_EMAC_RXC_UNICST(val) bfin_write32(EMAC_RXC_UNICST, val) |
||||
#define bfin_read_EMAC_RXC_MULTI() bfin_read32(EMAC_RXC_MULTI) |
||||
#define bfin_write_EMAC_RXC_MULTI(val) bfin_write32(EMAC_RXC_MULTI, val) |
||||
#define bfin_read_EMAC_RXC_BROAD() bfin_read32(EMAC_RXC_BROAD) |
||||
#define bfin_write_EMAC_RXC_BROAD(val) bfin_write32(EMAC_RXC_BROAD, val) |
||||
#define bfin_read_EMAC_RXC_LNERRI() bfin_read32(EMAC_RXC_LNERRI) |
||||
#define bfin_write_EMAC_RXC_LNERRI(val) bfin_write32(EMAC_RXC_LNERRI, val) |
||||
#define bfin_read_EMAC_RXC_LNERRO() bfin_read32(EMAC_RXC_LNERRO) |
||||
#define bfin_write_EMAC_RXC_LNERRO(val) bfin_write32(EMAC_RXC_LNERRO, val) |
||||
#define bfin_read_EMAC_RXC_LONG() bfin_read32(EMAC_RXC_LONG) |
||||
#define bfin_write_EMAC_RXC_LONG(val) bfin_write32(EMAC_RXC_LONG, val) |
||||
#define bfin_read_EMAC_RXC_MACCTL() bfin_read32(EMAC_RXC_MACCTL) |
||||
#define bfin_write_EMAC_RXC_MACCTL(val) bfin_write32(EMAC_RXC_MACCTL, val) |
||||
#define bfin_read_EMAC_RXC_OPCODE() bfin_read32(EMAC_RXC_OPCODE) |
||||
#define bfin_write_EMAC_RXC_OPCODE(val) bfin_write32(EMAC_RXC_OPCODE, val) |
||||
#define bfin_read_EMAC_RXC_PAUSE() bfin_read32(EMAC_RXC_PAUSE) |
||||
#define bfin_write_EMAC_RXC_PAUSE(val) bfin_write32(EMAC_RXC_PAUSE, val) |
||||
#define bfin_read_EMAC_RXC_ALLFRM() bfin_read32(EMAC_RXC_ALLFRM) |
||||
#define bfin_write_EMAC_RXC_ALLFRM(val) bfin_write32(EMAC_RXC_ALLFRM, val) |
||||
#define bfin_read_EMAC_RXC_ALLOCT() bfin_read32(EMAC_RXC_ALLOCT) |
||||
#define bfin_write_EMAC_RXC_ALLOCT(val) bfin_write32(EMAC_RXC_ALLOCT, val) |
||||
#define bfin_read_EMAC_RXC_TYPED() bfin_read32(EMAC_RXC_TYPED) |
||||
#define bfin_write_EMAC_RXC_TYPED(val) bfin_write32(EMAC_RXC_TYPED, val) |
||||
#define bfin_read_EMAC_RXC_SHORT() bfin_read32(EMAC_RXC_SHORT) |
||||
#define bfin_write_EMAC_RXC_SHORT(val) bfin_write32(EMAC_RXC_SHORT, val) |
||||
#define bfin_read_EMAC_RXC_EQ64() bfin_read32(EMAC_RXC_EQ64) |
||||
#define bfin_write_EMAC_RXC_EQ64(val) bfin_write32(EMAC_RXC_EQ64, val) |
||||
#define bfin_read_EMAC_RXC_LT128() bfin_read32(EMAC_RXC_LT128) |
||||
#define bfin_write_EMAC_RXC_LT128(val) bfin_write32(EMAC_RXC_LT128, val) |
||||
#define bfin_read_EMAC_RXC_LT256() bfin_read32(EMAC_RXC_LT256) |
||||
#define bfin_write_EMAC_RXC_LT256(val) bfin_write32(EMAC_RXC_LT256, val) |
||||
#define bfin_read_EMAC_RXC_LT512() bfin_read32(EMAC_RXC_LT512) |
||||
#define bfin_write_EMAC_RXC_LT512(val) bfin_write32(EMAC_RXC_LT512, val) |
||||
#define bfin_read_EMAC_RXC_LT1024() bfin_read32(EMAC_RXC_LT1024) |
||||
#define bfin_write_EMAC_RXC_LT1024(val) bfin_write32(EMAC_RXC_LT1024, val) |
||||
#define bfin_read_EMAC_RXC_GE1024() bfin_read32(EMAC_RXC_GE1024) |
||||
#define bfin_write_EMAC_RXC_GE1024(val) bfin_write32(EMAC_RXC_GE1024, val) |
||||
#define bfin_read_EMAC_TXC_OK() bfin_read32(EMAC_TXC_OK) |
||||
#define bfin_write_EMAC_TXC_OK(val) bfin_write32(EMAC_TXC_OK, val) |
||||
#define bfin_read_EMAC_TXC_1COL() bfin_read32(EMAC_TXC_1COL) |
||||
#define bfin_write_EMAC_TXC_1COL(val) bfin_write32(EMAC_TXC_1COL, val) |
||||
#define bfin_read_EMAC_TXC_GT1COL() bfin_read32(EMAC_TXC_GT1COL) |
||||
#define bfin_write_EMAC_TXC_GT1COL(val) bfin_write32(EMAC_TXC_GT1COL, val) |
||||
#define bfin_read_EMAC_TXC_OCTET() bfin_read32(EMAC_TXC_OCTET) |
||||
#define bfin_write_EMAC_TXC_OCTET(val) bfin_write32(EMAC_TXC_OCTET, val) |
||||
#define bfin_read_EMAC_TXC_DEFER() bfin_read32(EMAC_TXC_DEFER) |
||||
#define bfin_write_EMAC_TXC_DEFER(val) bfin_write32(EMAC_TXC_DEFER, val) |
||||
#define bfin_read_EMAC_TXC_LATECL() bfin_read32(EMAC_TXC_LATECL) |
||||
#define bfin_write_EMAC_TXC_LATECL(val) bfin_write32(EMAC_TXC_LATECL, val) |
||||
#define bfin_read_EMAC_TXC_XS_COL() bfin_read32(EMAC_TXC_XS_COL) |
||||
#define bfin_write_EMAC_TXC_XS_COL(val) bfin_write32(EMAC_TXC_XS_COL, val) |
||||
#define bfin_read_EMAC_TXC_DMAUND() bfin_read32(EMAC_TXC_DMAUND) |
||||
#define bfin_write_EMAC_TXC_DMAUND(val) bfin_write32(EMAC_TXC_DMAUND, val) |
||||
#define bfin_read_EMAC_TXC_CRSERR() bfin_read32(EMAC_TXC_CRSERR) |
||||
#define bfin_write_EMAC_TXC_CRSERR(val) bfin_write32(EMAC_TXC_CRSERR, val) |
||||
#define bfin_read_EMAC_TXC_UNICST() bfin_read32(EMAC_TXC_UNICST) |
||||
#define bfin_write_EMAC_TXC_UNICST(val) bfin_write32(EMAC_TXC_UNICST, val) |
||||
#define bfin_read_EMAC_TXC_MULTI() bfin_read32(EMAC_TXC_MULTI) |
||||
#define bfin_write_EMAC_TXC_MULTI(val) bfin_write32(EMAC_TXC_MULTI, val) |
||||
#define bfin_read_EMAC_TXC_BROAD() bfin_read32(EMAC_TXC_BROAD) |
||||
#define bfin_write_EMAC_TXC_BROAD(val) bfin_write32(EMAC_TXC_BROAD, val) |
||||
#define bfin_read_EMAC_TXC_XS_DFR() bfin_read32(EMAC_TXC_XS_DFR) |
||||
#define bfin_write_EMAC_TXC_XS_DFR(val) bfin_write32(EMAC_TXC_XS_DFR, val) |
||||
#define bfin_read_EMAC_TXC_MACCTL() bfin_read32(EMAC_TXC_MACCTL) |
||||
#define bfin_write_EMAC_TXC_MACCTL(val) bfin_write32(EMAC_TXC_MACCTL, val) |
||||
#define bfin_read_EMAC_TXC_ALLFRM() bfin_read32(EMAC_TXC_ALLFRM) |
||||
#define bfin_write_EMAC_TXC_ALLFRM(val) bfin_write32(EMAC_TXC_ALLFRM, val) |
||||
#define bfin_read_EMAC_TXC_ALLOCT() bfin_read32(EMAC_TXC_ALLOCT) |
||||
#define bfin_write_EMAC_TXC_ALLOCT(val) bfin_write32(EMAC_TXC_ALLOCT, val) |
||||
#define bfin_read_EMAC_TXC_EQ64() bfin_read32(EMAC_TXC_EQ64) |
||||
#define bfin_write_EMAC_TXC_EQ64(val) bfin_write32(EMAC_TXC_EQ64, val) |
||||
#define bfin_read_EMAC_TXC_LT128() bfin_read32(EMAC_TXC_LT128) |
||||
#define bfin_write_EMAC_TXC_LT128(val) bfin_write32(EMAC_TXC_LT128, val) |
||||
#define bfin_read_EMAC_TXC_LT256() bfin_read32(EMAC_TXC_LT256) |
||||
#define bfin_write_EMAC_TXC_LT256(val) bfin_write32(EMAC_TXC_LT256, val) |
||||
#define bfin_read_EMAC_TXC_LT512() bfin_read32(EMAC_TXC_LT512) |
||||
#define bfin_write_EMAC_TXC_LT512(val) bfin_write32(EMAC_TXC_LT512, val) |
||||
#define bfin_read_EMAC_TXC_LT1024() bfin_read32(EMAC_TXC_LT1024) |
||||
#define bfin_write_EMAC_TXC_LT1024(val) bfin_write32(EMAC_TXC_LT1024, val) |
||||
#define bfin_read_EMAC_TXC_GE1024() bfin_read32(EMAC_TXC_GE1024) |
||||
#define bfin_write_EMAC_TXC_GE1024(val) bfin_write32(EMAC_TXC_GE1024, val) |
||||
#define bfin_read_EMAC_TXC_ABORT() bfin_read32(EMAC_TXC_ABORT) |
||||
#define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT, val) |
||||
|
||||
#endif /* __BFIN_CDEF_ADSP_BF516_proc__ */ |
||||
@ -0,0 +1,91 @@ |
||||
/* DO NOT EDIT THIS FILE
|
||||
* Automatically generated by generate-def-headers.xsl |
||||
* DO NOT EDIT THIS FILE |
||||
*/ |
||||
|
||||
#ifndef __BFIN_DEF_ADSP_BF516_proc__ |
||||
#define __BFIN_DEF_ADSP_BF516_proc__ |
||||
|
||||
#include "BF514_def.h" |
||||
|
||||
#define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */ |
||||
#define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */ |
||||
#define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */ |
||||
#define EMAC_HASHLO 0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */ |
||||
#define EMAC_HASHHI 0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */ |
||||
#define EMAC_STAADD 0xFFC03014 /* Station Management Address Register */ |
||||
#define EMAC_STADAT 0xFFC03018 /* Station Management Data Register */ |
||||
#define EMAC_FLC 0xFFC0301C /* Flow Control Register */ |
||||
#define EMAC_VLAN1 0xFFC03020 /* VLAN1 Tag Register */ |
||||
#define EMAC_VLAN2 0xFFC03024 /* VLAN2 Tag Register */ |
||||
#define EMAC_WKUP_CTL 0xFFC0302C /* Wake-Up Control/Status Register */ |
||||
#define EMAC_WKUP_FFMSK0 0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */ |
||||
#define EMAC_WKUP_FFMSK1 0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */ |
||||
#define EMAC_WKUP_FFMSK2 0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */ |
||||
#define EMAC_WKUP_FFMSK3 0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */ |
||||
#define EMAC_WKUP_FFCMD 0xFFC03040 /* Wake-Up Frame Filter Commands Register */ |
||||
#define EMAC_WKUP_FFOFF 0xFFC03044 /* Wake-Up Frame Filter Offsets Register */ |
||||
#define EMAC_WKUP_FFCRC0 0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */ |
||||
#define EMAC_WKUP_FFCRC1 0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */ |
||||
#define EMAC_SYSCTL 0xFFC03060 /* EMAC System Control Register */ |
||||
#define EMAC_SYSTAT 0xFFC03064 /* EMAC System Status Register */ |
||||
#define EMAC_RX_STAT 0xFFC03068 /* RX Current Frame Status Register */ |
||||
#define EMAC_RX_STKY 0xFFC0306C /* RX Sticky Frame Status Register */ |
||||
#define EMAC_RX_IRQE 0xFFC03070 /* RX Frame Status Interrupt Enables Register */ |
||||
#define EMAC_TX_STAT 0xFFC03074 /* TX Current Frame Status Register */ |
||||
#define EMAC_TX_STKY 0xFFC03078 /* TX Sticky Frame Status Register */ |
||||
#define EMAC_TX_IRQE 0xFFC0307C /* TX Frame Status Interrupt Enables Register */ |
||||
#define EMAC_MMC_CTL 0xFFC03080 /* MMC Counter Control Register */ |
||||
#define EMAC_MMC_RIRQS 0xFFC03084 /* MMC RX Interrupt Status Register */ |
||||
#define EMAC_MMC_RIRQE 0xFFC03088 /* MMC RX Interrupt Enables Register */ |
||||
#define EMAC_MMC_TIRQS 0xFFC0308C /* MMC TX Interrupt Status Register */ |
||||
#define EMAC_MMC_TIRQE 0xFFC03090 /* MMC TX Interrupt Enables Register */ |
||||
#define EMAC_RXC_OK 0xFFC03100 /* RX Frame Successful Count */ |
||||
#define EMAC_RXC_FCS 0xFFC03104 /* RX Frame FCS Failure Count */ |
||||
#define EMAC_RXC_ALIGN 0xFFC03108 /* RX Alignment Error Count */ |
||||
#define EMAC_RXC_OCTET 0xFFC0310C /* RX Octets Successfully Received Count */ |
||||
#define EMAC_RXC_DMAOVF 0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */ |
||||
#define EMAC_RXC_UNICST 0xFFC03114 /* Unicast RX Frame Count */ |
||||
#define EMAC_RXC_MULTI 0xFFC03118 /* Multicast RX Frame Count */ |
||||
#define EMAC_RXC_BROAD 0xFFC0311C /* Broadcast RX Frame Count */ |
||||
#define EMAC_RXC_LNERRI 0xFFC03120 /* RX Frame In Range Error Count */ |
||||
#define EMAC_RXC_LNERRO 0xFFC03124 /* RX Frame Out Of Range Error Count */ |
||||
#define EMAC_RXC_LONG 0xFFC03128 /* RX Frame Too Long Count */ |
||||
#define EMAC_RXC_MACCTL 0xFFC0312C /* MAC Control RX Frame Count */ |
||||
#define EMAC_RXC_OPCODE 0xFFC03130 /* Unsupported Op-Code RX Frame Count */ |
||||
#define EMAC_RXC_PAUSE 0xFFC03134 /* MAC Control Pause RX Frame Count */ |
||||
#define EMAC_RXC_ALLFRM 0xFFC03138 /* Overall RX Frame Count */ |
||||
#define EMAC_RXC_ALLOCT 0xFFC0313C /* Overall RX Octet Count */ |
||||
#define EMAC_RXC_TYPED 0xFFC03140 /* Type/Length Consistent RX Frame Count */ |
||||
#define EMAC_RXC_SHORT 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */ |
||||
#define EMAC_RXC_EQ64 0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */ |
||||
#define EMAC_RXC_LT128 0xFFC0314C /* Good RX Frame Count - Byte Count 64 <= x < 128 */ |
||||
#define EMAC_RXC_LT256 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */ |
||||
#define EMAC_RXC_LT512 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */ |
||||
#define EMAC_RXC_LT1024 0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */ |
||||
#define EMAC_RXC_GE1024 0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */ |
||||
#define EMAC_TXC_OK 0xFFC03180 /* TX Frame Successful Count */ |
||||
#define EMAC_TXC_1COL 0xFFC03184 /* TX Frames Successful After Single Collision Count */ |
||||
#define EMAC_TXC_GT1COL 0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */ |
||||
#define EMAC_TXC_OCTET 0xFFC0318C /* TX Octets Successfully Received Count */ |
||||
#define EMAC_TXC_DEFER 0xFFC03190 /* TX Frame Delayed Due To Busy Count */ |
||||
#define EMAC_TXC_LATECL 0xFFC03194 /* Late TX Collisions Count */ |
||||
#define EMAC_TXC_XS_COL 0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */ |
||||
#define EMAC_TXC_DMAUND 0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */ |
||||
#define EMAC_TXC_CRSERR 0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */ |
||||
#define EMAC_TXC_UNICST 0xFFC031A4 /* Unicast TX Frame Count */ |
||||
#define EMAC_TXC_MULTI 0xFFC031A8 /* Multicast TX Frame Count */ |
||||
#define EMAC_TXC_BROAD 0xFFC031AC /* Broadcast TX Frame Count */ |
||||
#define EMAC_TXC_XS_DFR 0xFFC031B0 /* TX Frames With Excessive Deferral Count */ |
||||
#define EMAC_TXC_MACCTL 0xFFC031B4 /* MAC Control TX Frame Count */ |
||||
#define EMAC_TXC_ALLFRM 0xFFC031B8 /* Overall TX Frame Count */ |
||||
#define EMAC_TXC_ALLOCT 0xFFC031BC /* Overall TX Octet Count */ |
||||
#define EMAC_TXC_EQ64 0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */ |
||||
#define EMAC_TXC_LT128 0xFFC031C4 /* Good TX Frame Count - Byte Count 64 <= x < 128 */ |
||||
#define EMAC_TXC_LT256 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */ |
||||
#define EMAC_TXC_LT512 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */ |
||||
#define EMAC_TXC_LT1024 0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */ |
||||
#define EMAC_TXC_GE1024 0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */ |
||||
#define EMAC_TXC_ABORT 0xFFC031D8 /* Total TX Frames Aborted Count */ |
||||
|
||||
#endif /* __BFIN_DEF_ADSP_BF516_proc__ */ |
||||
@ -0,0 +1,58 @@ |
||||
/* DO NOT EDIT THIS FILE
|
||||
* Automatically generated by generate-cdef-headers.xsl |
||||
* DO NOT EDIT THIS FILE |
||||
*/ |
||||
|
||||
#ifndef __BFIN_CDEF_ADSP_BF518_proc__ |
||||
#define __BFIN_CDEF_ADSP_BF518_proc__ |
||||
|
||||
#include "BF516_cdef.h" |
||||
|
||||
#define bfin_read_EMAC_PTP_CTL() bfin_read16(EMAC_PTP_CTL) |
||||
#define bfin_write_EMAC_PTP_CTL(val) bfin_write16(EMAC_PTP_CTL, val) |
||||
#define bfin_read_EMAC_PTP_IE() bfin_read16(EMAC_PTP_IE) |
||||
#define bfin_write_EMAC_PTP_IE(val) bfin_write16(EMAC_PTP_IE, val) |
||||
#define bfin_read_EMAC_PTP_ISTAT() bfin_read16(EMAC_PTP_ISTAT) |
||||
#define bfin_write_EMAC_PTP_ISTAT(val) bfin_write16(EMAC_PTP_ISTAT, val) |
||||
#define bfin_read_EMAC_PTP_FOFF() bfin_read32(EMAC_PTP_FOFF) |
||||
#define bfin_write_EMAC_PTP_FOFF(val) bfin_write32(EMAC_PTP_FOFF, val) |
||||
#define bfin_read_EMAC_PTP_FV1() bfin_read32(EMAC_PTP_FV1) |
||||
#define bfin_write_EMAC_PTP_FV1(val) bfin_write32(EMAC_PTP_FV1, val) |
||||
#define bfin_read_EMAC_PTP_FV2() bfin_read32(EMAC_PTP_FV2) |
||||
#define bfin_write_EMAC_PTP_FV2(val) bfin_write32(EMAC_PTP_FV2, val) |
||||
#define bfin_read_EMAC_PTP_FV3() bfin_read32(EMAC_PTP_FV3) |
||||
#define bfin_write_EMAC_PTP_FV3(val) bfin_write32(EMAC_PTP_FV3, val) |
||||
#define bfin_read_EMAC_PTP_ADDEND() bfin_read32(EMAC_PTP_ADDEND) |
||||
#define bfin_write_EMAC_PTP_ADDEND(val) bfin_write32(EMAC_PTP_ADDEND, val) |
||||
#define bfin_read_EMAC_PTP_ACCR() bfin_read32(EMAC_PTP_ACCR) |
||||
#define bfin_write_EMAC_PTP_ACCR(val) bfin_write32(EMAC_PTP_ACCR, val) |
||||
#define bfin_read_EMAC_PTP_OFFSET() bfin_read32(EMAC_PTP_OFFSET) |
||||
#define bfin_write_EMAC_PTP_OFFSET(val) bfin_write32(EMAC_PTP_OFFSET, val) |
||||
#define bfin_read_EMAC_PTP_TIMELO() bfin_read32(EMAC_PTP_TIMELO) |
||||
#define bfin_write_EMAC_PTP_TIMELO(val) bfin_write32(EMAC_PTP_TIMELO, val) |
||||
#define bfin_read_EMAC_PTP_TIMEHI() bfin_read32(EMAC_PTP_TIMEHI) |
||||
#define bfin_write_EMAC_PTP_TIMEHI(val) bfin_write32(EMAC_PTP_TIMEHI, val) |
||||
#define bfin_read_EMAC_PTP_RXSNAPLO() bfin_read32(EMAC_PTP_RXSNAPLO) |
||||
#define bfin_write_EMAC_PTP_RXSNAPLO(val) bfin_write32(EMAC_PTP_RXSNAPLO, val) |
||||
#define bfin_read_EMAC_PTP_RXSNAPHI() bfin_read32(EMAC_PTP_RXSNAPHI) |
||||
#define bfin_write_EMAC_PTP_RXSNAPHI(val) bfin_write32(EMAC_PTP_RXSNAPHI, val) |
||||
#define bfin_read_EMAC_PTP_TXSNAPLO() bfin_read32(EMAC_PTP_TXSNAPLO) |
||||
#define bfin_write_EMAC_PTP_TXSNAPLO(val) bfin_write32(EMAC_PTP_TXSNAPLO, val) |
||||
#define bfin_read_EMAC_PTP_TXSNAPHI() bfin_read32(EMAC_PTP_TXSNAPHI) |
||||
#define bfin_write_EMAC_PTP_TXSNAPHI(val) bfin_write32(EMAC_PTP_TXSNAPHI, val) |
||||
#define bfin_read_EMAC_PTP_ALARMLO() bfin_read32(EMAC_PTP_ALARMLO) |
||||
#define bfin_write_EMAC_PTP_ALARMLO(val) bfin_write32(EMAC_PTP_ALARMLO, val) |
||||
#define bfin_read_EMAC_PTP_ALARMHI() bfin_read32(EMAC_PTP_ALARMHI) |
||||
#define bfin_write_EMAC_PTP_ALARMHI(val) bfin_write32(EMAC_PTP_ALARMHI, val) |
||||
#define bfin_read_EMAC_PTP_ID_OFF() bfin_read16(EMAC_PTP_ID_OFF) |
||||
#define bfin_write_EMAC_PTP_ID_OFF(val) bfin_write16(EMAC_PTP_ID_OFF, val) |
||||
#define bfin_read_EMAC_PTP_ID_SNAP() bfin_read32(EMAC_PTP_ID_SNAP) |
||||
#define bfin_write_EMAC_PTP_ID_SNAP(val) bfin_write32(EMAC_PTP_ID_SNAP, val) |
||||
#define bfin_read_EMAC_PTP_PPS_STARTLO() bfin_read32(EMAC_PTP_PPS_STARTLO) |
||||
#define bfin_write_EMAC_PTP_PPS_STARTLO(val) bfin_write32(EMAC_PTP_PPS_STARTLO, val) |
||||
#define bfin_read_EMAC_PTP_PPS_STARTHI() bfin_read32(EMAC_PTP_PPS_STARTHI) |
||||
#define bfin_write_EMAC_PTP_PPS_STARTHI(val) bfin_write32(EMAC_PTP_PPS_STARTHI, val) |
||||
#define bfin_read_EMAC_PTP_PPS_PERIOD() bfin_read32(EMAC_PTP_PPS_PERIOD) |
||||
#define bfin_write_EMAC_PTP_PPS_PERIOD(val) bfin_write32(EMAC_PTP_PPS_PERIOD, val) |
||||
|
||||
#endif /* __BFIN_CDEF_ADSP_BF518_proc__ */ |
||||
@ -0,0 +1,35 @@ |
||||
/* DO NOT EDIT THIS FILE
|
||||
* Automatically generated by generate-def-headers.xsl |
||||
* DO NOT EDIT THIS FILE |
||||
*/ |
||||
|
||||
#ifndef __BFIN_DEF_ADSP_BF518_proc__ |
||||
#define __BFIN_DEF_ADSP_BF518_proc__ |
||||
|
||||
#include "BF516_def.h" |
||||
|
||||
#define EMAC_PTP_CTL 0xFFC030A0 /* PTP Block Control */ |
||||
#define EMAC_PTP_IE 0xFFC030A4 /* PTP Block Interrupt Enable */ |
||||
#define EMAC_PTP_ISTAT 0xFFC030A8 /* PTP Block Interrupt Status */ |
||||
#define EMAC_PTP_FOFF 0xFFC030AC /* PTP Filter offset Register */ |
||||
#define EMAC_PTP_FV1 0xFFC030B0 /* PTP Filter Value Register 1 */ |
||||
#define EMAC_PTP_FV2 0xFFC030B4 /* PTP Filter Value Register 2 */ |
||||
#define EMAC_PTP_FV3 0xFFC030B8 /* PTP Filter Value Register 3 */ |
||||
#define EMAC_PTP_ADDEND 0xFFC030BC /* PTP Addend for Frequency Compensation */ |
||||
#define EMAC_PTP_ACCR 0xFFC030C0 /* PTP Accumulator for Frequency Compensation */ |
||||
#define EMAC_PTP_OFFSET 0xFFC030C4 /* PTP Time Offset Register */ |
||||
#define EMAC_PTP_TIMELO 0xFFC030C8 /* PTP Precision Clock Time Low */ |
||||
#define EMAC_PTP_TIMEHI 0xFFC030CC /* PTP Precision Clock Time High */ |
||||
#define EMAC_PTP_RXSNAPLO 0xFFC030D0 /* PTP Receive Snapshot Register Low */ |
||||
#define EMAC_PTP_RXSNAPHI 0xFFC030D4 /* PTP Receive Snapshot Register High */ |
||||
#define EMAC_PTP_TXSNAPLO 0xFFC030D8 /* PTP Transmit Snapshot Register Low */ |
||||
#define EMAC_PTP_TXSNAPHI 0xFFC030DC /* PTP Transmit Snapshot Register High */ |
||||
#define EMAC_PTP_ALARMLO 0xFFC030E0 /* PTP Alarm time Low */ |
||||
#define EMAC_PTP_ALARMHI 0xFFC030E4 /* PTP Alarm time High */ |
||||
#define EMAC_PTP_ID_OFF 0xFFC030E8 /* PTP Capture ID offset register */ |
||||
#define EMAC_PTP_ID_SNAP 0xFFC030EC /* PTP Capture ID register */ |
||||
#define EMAC_PTP_PPS_STARTLO 0xFFC030F0 /* PPS Start Time Low */ |
||||
#define EMAC_PTP_PPS_STARTHI 0xFFC030F4 /* PPS Start Time High */ |
||||
#define EMAC_PTP_PPS_PERIOD 0xFFC030F8 /* PPS Count Register */ |
||||
|
||||
#endif /* __BFIN_DEF_ADSP_BF518_proc__ */ |
||||
@ -0,0 +1,158 @@ |
||||
/*
|
||||
* DO NOT EDIT THIS FILE |
||||
* This file is under version control at |
||||
* svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
|
||||
* and can be replaced with that version at any time |
||||
* DO NOT EDIT THIS FILE |
||||
* |
||||
* Copyright 2004-2010 Analog Devices Inc. |
||||
* Licensed under the ADI BSD license. |
||||
* https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
|
||||
*/ |
||||
|
||||
/* This file should be up to date with:
|
||||
* - Revision E, 01/26/2010; ADSP-BF512/BF514/BF516/BF518 Blackfin Processor Anomaly List |
||||
*/ |
||||
|
||||
/* We plan on not supporting 0.0 silicon, but 0.1 isn't out yet - sorry */ |
||||
#if __SILICON_REVISION__ < 0 |
||||
# error will not work on BF518 silicon version |
||||
#endif |
||||
|
||||
#ifndef _MACH_ANOMALY_H_ |
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#define _MACH_ANOMALY_H_ |
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|
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/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ |
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#define ANOMALY_05000074 (1) |
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