iMX5: EfikaMX: Preliminary board support
Supported: MMC IDE PMIC SPI flash LEDs I can boot the kernel supplied by freescale/genesi with this from MMC card and/or PATA disk. Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
This commit is contained in:
Marek Vasut
Albert Aribaud
parent
8a1edd7d54
commit
d59140170a
|
|
@ -833,6 +833,7 @@ Marek Vasut <marek.vasut@gmail.com>
|
|||
palmtc xscale
|
||||
vpac270 xscale
|
||||
zipitz2 xscale
|
||||
efikamx i.MX51
|
||||
|
||||
Hugo Villeneuve <hugo.villeneuve@lyrtech.com>
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,52 @@
|
|||
#
|
||||
# Copyright (C) 2010, Marek Vasut <marek.vasut@gmail.com>
|
||||
#
|
||||
# BASED ON: imx51evk
|
||||
#
|
||||
# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
|
||||
#
|
||||
# (C) Copyright 2009 Freescale Semiconductor, Inc.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(BOARD).o
|
||||
|
||||
COBJS := efikamx.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
|
||||
$(call cmd_link_o_target, $(OBJS) $(SOBJS))
|
||||
|
||||
clean:
|
||||
rm -f $(SOBJS) $(OBJS)
|
||||
|
||||
distclean: clean
|
||||
rm -f $(LIB) core *.bak .depend
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
|
|
@ -0,0 +1,25 @@
|
|||
#
|
||||
# Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
CONFIG_SYS_TEXT_BASE = 0x97800000
|
||||
IMX_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/imximage.cfg
|
||||
ALL += $(obj)u-boot.imx
|
||||
|
|
@ -0,0 +1,689 @@
|
|||
/*
|
||||
* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
|
||||
*
|
||||
* (C) Copyright 2009 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/arch/mx5x_pins.h>
|
||||
#include <asm/arch/iomux.h>
|
||||
#include <mxc_gpio.h>
|
||||
#include <asm/errno.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/arch/crm_regs.h>
|
||||
#include <i2c.h>
|
||||
#include <mmc.h>
|
||||
#include <fsl_esdhc.h>
|
||||
#include <fsl_pmic.h>
|
||||
#include <mc13892.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
/*
|
||||
* Compile-time error checking
|
||||
*/
|
||||
#ifndef CONFIG_MXC_SPI
|
||||
#error "CONFIG_MXC_SPI not set, this is essential for board's operation!"
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Shared variables / local defines
|
||||
*/
|
||||
/* LED */
|
||||
#define EFIKAMX_LED_BLUE 0x1
|
||||
#define EFIKAMX_LED_GREEN 0x2
|
||||
#define EFIKAMX_LED_RED 0x4
|
||||
|
||||
void efikamx_toggle_led(uint32_t mask);
|
||||
|
||||
/* Board revisions */
|
||||
#define EFIKAMX_BOARD_REV_11 0x1
|
||||
#define EFIKAMX_BOARD_REV_12 0x2
|
||||
#define EFIKAMX_BOARD_REV_13 0x3
|
||||
#define EFIKAMX_BOARD_REV_14 0x4
|
||||
|
||||
/*
|
||||
* Board identification
|
||||
*/
|
||||
u32 get_efika_rev(void)
|
||||
{
|
||||
u32 rev = 0;
|
||||
/*
|
||||
* Retrieve board ID:
|
||||
* rev1.1: 1,1,1
|
||||
* rev1.2: 1,1,0
|
||||
* rev1.3: 1,0,1
|
||||
* rev1.4: 1,0,0
|
||||
*/
|
||||
mxc_request_iomux(MX51_PIN_NANDF_CS0, IOMUX_CONFIG_GPIO);
|
||||
mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0),
|
||||
MXC_GPIO_DIRECTION_OUT);
|
||||
/* set to 1 in order to get correct value on board rev1.1 */
|
||||
mxc_gpio_set(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0), 1);
|
||||
|
||||
mxc_request_iomux(MX51_PIN_NANDF_CS0, IOMUX_CONFIG_GPIO);
|
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_CS0, PAD_CTL_100K_PU);
|
||||
mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0),
|
||||
MXC_GPIO_DIRECTION_IN);
|
||||
rev |= (!!mxc_gpio_get(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0))) << 0;
|
||||
|
||||
mxc_request_iomux(MX51_PIN_NANDF_CS1, IOMUX_CONFIG_GPIO);
|
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_CS1, PAD_CTL_100K_PU);
|
||||
mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS1),
|
||||
MXC_GPIO_DIRECTION_IN);
|
||||
rev |= (!!mxc_gpio_get(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS1))) << 1;
|
||||
|
||||
mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_GPIO);
|
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, PAD_CTL_100K_PU);
|
||||
mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_NANDF_RB3),
|
||||
MXC_GPIO_DIRECTION_IN);
|
||||
rev |= (!!mxc_gpio_get(IOMUX_TO_GPIO(MX51_PIN_NANDF_RB3))) << 2;
|
||||
|
||||
return (~rev & 0x7) + 1;
|
||||
}
|
||||
|
||||
u32 get_board_rev(void)
|
||||
{
|
||||
return get_cpu_rev() | (get_efika_rev() << 8);
|
||||
}
|
||||
|
||||
/*
|
||||
* DRAM initialization
|
||||
*/
|
||||
int dram_init(void)
|
||||
{
|
||||
/* dram_init must store complete ramsize in gd->ram_size */
|
||||
gd->ram_size = get_ram_size((volatile void *)CONFIG_SYS_SDRAM_BASE,
|
||||
PHYS_SDRAM_1_SIZE);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* UART configuration
|
||||
*/
|
||||
static void setup_iomux_uart(void)
|
||||
{
|
||||
unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
|
||||
PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH;
|
||||
|
||||
mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0);
|
||||
mxc_iomux_set_pad(MX51_PIN_UART1_RXD, pad | PAD_CTL_SRE_FAST);
|
||||
mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0);
|
||||
mxc_iomux_set_pad(MX51_PIN_UART1_TXD, pad | PAD_CTL_SRE_FAST);
|
||||
mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0);
|
||||
mxc_iomux_set_pad(MX51_PIN_UART1_RTS, pad);
|
||||
mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0);
|
||||
mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad);
|
||||
}
|
||||
|
||||
/*
|
||||
* SPI configuration
|
||||
*/
|
||||
#ifdef CONFIG_MXC_SPI
|
||||
static void setup_iomux_spi(void)
|
||||
{
|
||||
/* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */
|
||||
mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0);
|
||||
mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI,
|
||||
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
|
||||
|
||||
/* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1. */
|
||||
mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0);
|
||||
mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO,
|
||||
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
|
||||
|
||||
/* Configure SS0 as a GPIO */
|
||||
mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_GPIO);
|
||||
mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS0),
|
||||
MXC_GPIO_DIRECTION_OUT);
|
||||
mxc_gpio_set(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS0), 0);
|
||||
|
||||
/* Configure SS1 as a GPIO */
|
||||
mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_GPIO);
|
||||
mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS1),
|
||||
MXC_GPIO_DIRECTION_OUT);
|
||||
mxc_gpio_set(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS1), 1);
|
||||
|
||||
/* 000: Select mux mode: ALT0 mux port: SS2 of instance: ecspi1. */
|
||||
mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT0);
|
||||
mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY,
|
||||
PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
|
||||
|
||||
/* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */
|
||||
mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0);
|
||||
mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK,
|
||||
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
|
||||
}
|
||||
#else
|
||||
static inline void setup_iomux_spi(void) { }
|
||||
#endif
|
||||
|
||||
/*
|
||||
* PMIC configuration
|
||||
*/
|
||||
#ifdef CONFIG_MXC_SPI
|
||||
static void power_init(void)
|
||||
{
|
||||
unsigned int val;
|
||||
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
|
||||
|
||||
/* Write needed to Power Gate 2 register */
|
||||
val = pmic_reg_read(REG_POWER_MISC);
|
||||
val &= ~PWGT2SPIEN;
|
||||
pmic_reg_write(REG_POWER_MISC, val);
|
||||
|
||||
/* Externally powered */
|
||||
val = pmic_reg_read(REG_CHARGE);
|
||||
val |= ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | CHGAUTOB;
|
||||
pmic_reg_write(REG_CHARGE, val);
|
||||
|
||||
/* power up the system first */
|
||||
pmic_reg_write(REG_POWER_MISC, PWUP);
|
||||
|
||||
/* Set core voltage to 1.1V */
|
||||
val = pmic_reg_read(REG_SW_0);
|
||||
val = (val & ~SWx_VOLT_MASK) | SWx_1_100V;
|
||||
pmic_reg_write(REG_SW_0, val);
|
||||
|
||||
/* Setup VCC (SW2) to 1.25 */
|
||||
val = pmic_reg_read(REG_SW_1);
|
||||
val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
|
||||
pmic_reg_write(REG_SW_1, val);
|
||||
|
||||
/* Setup 1V2_DIG1 (SW3) to 1.25 */
|
||||
val = pmic_reg_read(REG_SW_2);
|
||||
val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
|
||||
pmic_reg_write(REG_SW_2, val);
|
||||
udelay(50);
|
||||
|
||||
/* Raise the core frequency to 800MHz */
|
||||
writel(0x0, &mxc_ccm->cacrr);
|
||||
|
||||
/* Set switchers in Auto in NORMAL mode & STANDBY mode */
|
||||
/* Setup the switcher mode for SW1 & SW2*/
|
||||
val = pmic_reg_read(REG_SW_4);
|
||||
val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
|
||||
(SWMODE_MASK << SWMODE2_SHIFT)));
|
||||
val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
|
||||
(SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
|
||||
pmic_reg_write(REG_SW_4, val);
|
||||
|
||||
/* Setup the switcher mode for SW3 & SW4 */
|
||||
val = pmic_reg_read(REG_SW_5);
|
||||
val = (val & ~((SWMODE_MASK << SWMODE3_SHIFT) |
|
||||
(SWMODE_MASK << SWMODE4_SHIFT)));
|
||||
val |= (SWMODE_AUTO_AUTO << SWMODE3_SHIFT) |
|
||||
(SWMODE_AUTO_AUTO << SWMODE4_SHIFT);
|
||||
pmic_reg_write(REG_SW_5, val);
|
||||
|
||||
/* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.6V */
|
||||
val = pmic_reg_read(REG_SETTING_0);
|
||||
val &= ~(VCAM_MASK | VGEN3_MASK | VDIG_MASK);
|
||||
val |= VDIG_1_65 | VGEN3_1_8 | VCAM_2_6;
|
||||
pmic_reg_write(REG_SETTING_0, val);
|
||||
|
||||
/* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */
|
||||
val = pmic_reg_read(REG_SETTING_1);
|
||||
val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
|
||||
val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775;
|
||||
pmic_reg_write(REG_SETTING_1, val);
|
||||
|
||||
/* Configure VGEN3 and VCAM regulators to use external PNP */
|
||||
val = VGEN3CONFIG | VCAMCONFIG;
|
||||
pmic_reg_write(REG_MODE_1, val);
|
||||
udelay(200);
|
||||
|
||||
/* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
|
||||
val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
|
||||
VVIDEOEN | VAUDIOEN | VSDEN;
|
||||
pmic_reg_write(REG_MODE_1, val);
|
||||
|
||||
val = pmic_reg_read(REG_POWER_CTL2);
|
||||
val |= WDIRESET;
|
||||
pmic_reg_write(REG_POWER_CTL2, val);
|
||||
|
||||
udelay(2500);
|
||||
}
|
||||
#else
|
||||
static inline void power_init(void) { }
|
||||
#endif
|
||||
|
||||
/*
|
||||
* MMC configuration
|
||||
*/
|
||||
#ifdef CONFIG_FSL_ESDHC
|
||||
struct fsl_esdhc_cfg esdhc_cfg[2] = {
|
||||
{MMC_SDHC1_BASE_ADDR, 1},
|
||||
{MMC_SDHC2_BASE_ADDR, 1},
|
||||
};
|
||||
|
||||
int board_mmc_getcd(u8 *absent, struct mmc *mmc)
|
||||
{
|
||||
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
|
||||
|
||||
if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
|
||||
*absent = mxc_gpio_get(IOMUX_TO_GPIO(MX51_PIN_GPIO1_0));
|
||||
else
|
||||
*absent = mxc_gpio_get(IOMUX_TO_GPIO(MX51_PIN_GPIO1_8));
|
||||
|
||||
return 0;
|
||||
}
|
||||
int board_mmc_init(bd_t *bis)
|
||||
{
|
||||
int ret;
|
||||
|
||||
/* SDHC1 is used on all revisions, setup control pins first */
|
||||
mxc_request_iomux(MX51_PIN_GPIO1_0,
|
||||
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
|
||||
mxc_iomux_set_pad(MX51_PIN_GPIO1_0,
|
||||
PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE |
|
||||
PAD_CTL_PUE_KEEPER | PAD_CTL_100K_PU |
|
||||
PAD_CTL_ODE_OPENDRAIN_NONE |
|
||||
PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
|
||||
mxc_request_iomux(MX51_PIN_GPIO1_1,
|
||||
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
|
||||
mxc_iomux_set_pad(MX51_PIN_GPIO1_1,
|
||||
PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE |
|
||||
PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE |
|
||||
PAD_CTL_SRE_FAST);
|
||||
|
||||
mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_GPIO1_0),
|
||||
MXC_GPIO_DIRECTION_IN);
|
||||
mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_GPIO1_1),
|
||||
MXC_GPIO_DIRECTION_IN);
|
||||
|
||||
/* Internal SDHC1 IOMUX + SDHC2 IOMUX on old boards */
|
||||
if (get_efika_rev() < EFIKAMX_BOARD_REV_12) {
|
||||
/* SDHC1 IOMUX */
|
||||
mxc_request_iomux(MX51_PIN_SD1_CMD,
|
||||
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
|
||||
mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
|
||||
PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
|
||||
PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
|
||||
|
||||
mxc_request_iomux(MX51_PIN_SD1_CLK,
|
||||
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
|
||||
mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
|
||||
PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
|
||||
PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
|
||||
|
||||
mxc_request_iomux(MX51_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0);
|
||||
mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
|
||||
PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
|
||||
PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
|
||||
|
||||
mxc_request_iomux(MX51_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0);
|
||||
mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
|
||||
PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
|
||||
PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
|
||||
|
||||
mxc_request_iomux(MX51_PIN_SD1_DATA2, IOMUX_CONFIG_ALT0);
|
||||
mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
|
||||
PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
|
||||
PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
|
||||
|
||||
mxc_request_iomux(MX51_PIN_SD1_DATA3, IOMUX_CONFIG_ALT0);
|
||||
mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
|
||||
PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
|
||||
PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
|
||||
|
||||
/* SDHC2 IOMUX */
|
||||
mxc_request_iomux(MX51_PIN_SD2_CMD,
|
||||
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
|
||||
mxc_iomux_set_pad(MX51_PIN_SD2_CMD,
|
||||
PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
|
||||
|
||||
mxc_request_iomux(MX51_PIN_SD2_CLK,
|
||||
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
|
||||
mxc_iomux_set_pad(MX51_PIN_SD2_CLK,
|
||||
PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
|
||||
|
||||
mxc_request_iomux(MX51_PIN_SD2_DATA0, IOMUX_CONFIG_ALT0);
|
||||
mxc_iomux_set_pad(MX51_PIN_SD2_DATA0,
|
||||
PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
|
||||
|
||||
mxc_request_iomux(MX51_PIN_SD2_DATA1, IOMUX_CONFIG_ALT0);
|
||||
mxc_iomux_set_pad(MX51_PIN_SD2_DATA1,
|
||||
PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
|
||||
|
||||
mxc_request_iomux(MX51_PIN_SD2_DATA2, IOMUX_CONFIG_ALT0);
|
||||
mxc_iomux_set_pad(MX51_PIN_SD2_DATA2,
|
||||
PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
|
||||
|
||||
mxc_request_iomux(MX51_PIN_SD2_DATA3, IOMUX_CONFIG_ALT0);
|
||||
mxc_iomux_set_pad(MX51_PIN_SD2_DATA3,
|
||||
PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
|
||||
|
||||
/* SDHC2 Control lines IOMUX */
|
||||
mxc_request_iomux(MX51_PIN_GPIO1_7,
|
||||
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
|
||||
mxc_iomux_set_pad(MX51_PIN_GPIO1_7,
|
||||
PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE |
|
||||
PAD_CTL_PUE_KEEPER | PAD_CTL_100K_PU |
|
||||
PAD_CTL_ODE_OPENDRAIN_NONE |
|
||||
PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
|
||||
mxc_request_iomux(MX51_PIN_GPIO1_8,
|
||||
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
|
||||
mxc_iomux_set_pad(MX51_PIN_GPIO1_8,
|
||||
PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE |
|
||||
PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE |
|
||||
PAD_CTL_SRE_FAST);
|
||||
|
||||
mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_GPIO1_8),
|
||||
MXC_GPIO_DIRECTION_IN);
|
||||
mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_GPIO1_7),
|
||||
MXC_GPIO_DIRECTION_IN);
|
||||
|
||||
ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
|
||||
if (!ret)
|
||||
ret = fsl_esdhc_initialize(bis, &esdhc_cfg[1]);
|
||||
} else { /* New boards use only SDHC1 */
|
||||
/* SDHC1 IOMUX */
|
||||
mxc_request_iomux(MX51_PIN_SD1_CMD,
|
||||
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
|
||||
mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
|
||||
PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
|
||||
|
||||
mxc_request_iomux(MX51_PIN_SD1_CLK,
|
||||
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
|
||||
mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
|
||||
PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
|
||||
|
||||
mxc_request_iomux(MX51_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0);
|
||||
mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
|
||||
PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
|
||||
|
||||
mxc_request_iomux(MX51_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0);
|
||||
mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
|
||||
PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
|
||||
|
||||
mxc_request_iomux(MX51_PIN_SD1_DATA2, IOMUX_CONFIG_ALT0);
|
||||
mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
|
||||
PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
|
||||
|
||||
mxc_request_iomux(MX51_PIN_SD1_DATA3, IOMUX_CONFIG_ALT0);
|
||||
mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
|
||||
PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
|
||||
|
||||
ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* ATA
|
||||
*/
|
||||
#ifdef CONFIG_MX51_PATA
|
||||
#define ATA_PAD_CONFIG (PAD_CTL_DRV_HIGH | PAD_CTL_DRV_VOT_HIGH)
|
||||
void setup_iomux_ata(void)
|
||||
{
|
||||
mxc_request_iomux(MX51_PIN_NANDF_ALE, IOMUX_CONFIG_ALT1);
|
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_ALE, ATA_PAD_CONFIG);
|
||||
mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT1);
|
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_CS2, ATA_PAD_CONFIG);
|
||||
mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT1);
|
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_CS3, ATA_PAD_CONFIG);
|
||||
mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT1);
|
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_CS4, ATA_PAD_CONFIG);
|
||||
mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT1);
|
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_CS5, ATA_PAD_CONFIG);
|
||||
mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT1);
|
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_CS6, ATA_PAD_CONFIG);
|
||||
mxc_request_iomux(MX51_PIN_NANDF_RE_B, IOMUX_CONFIG_ALT1);
|
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_RE_B, ATA_PAD_CONFIG);
|
||||
mxc_request_iomux(MX51_PIN_NANDF_WE_B, IOMUX_CONFIG_ALT1);
|
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_WE_B, ATA_PAD_CONFIG);
|
||||
mxc_request_iomux(MX51_PIN_NANDF_CLE, IOMUX_CONFIG_ALT1);
|
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_CLE, ATA_PAD_CONFIG);
|
||||
mxc_request_iomux(MX51_PIN_NANDF_RB0, IOMUX_CONFIG_ALT1);
|
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_RB0, ATA_PAD_CONFIG);
|
||||
mxc_request_iomux(MX51_PIN_NANDF_WP_B, IOMUX_CONFIG_ALT1);
|
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_WP_B, ATA_PAD_CONFIG);
|
||||
mxc_request_iomux(MX51_PIN_GPIO_NAND, IOMUX_CONFIG_ALT1);
|
||||
mxc_iomux_set_pad(MX51_PIN_GPIO_NAND, ATA_PAD_CONFIG);
|
||||
mxc_request_iomux(MX51_PIN_NANDF_RB1, IOMUX_CONFIG_ALT1);
|
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_RB1, ATA_PAD_CONFIG);
|
||||
mxc_request_iomux(MX51_PIN_NANDF_D0, IOMUX_CONFIG_ALT1);
|
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_D0, ATA_PAD_CONFIG);
|
||||
mxc_request_iomux(MX51_PIN_NANDF_D1, IOMUX_CONFIG_ALT1);
|
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_D1, ATA_PAD_CONFIG);
|
||||
mxc_request_iomux(MX51_PIN_NANDF_D2, IOMUX_CONFIG_ALT1);
|
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_D2, ATA_PAD_CONFIG);
|
||||
mxc_request_iomux(MX51_PIN_NANDF_D3, IOMUX_CONFIG_ALT1);
|
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_D3, ATA_PAD_CONFIG);
|
||||
mxc_request_iomux(MX51_PIN_NANDF_D4, IOMUX_CONFIG_ALT1);
|
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_D4, ATA_PAD_CONFIG);
|
||||
mxc_request_iomux(MX51_PIN_NANDF_D5, IOMUX_CONFIG_ALT1);
|
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_D5, ATA_PAD_CONFIG);
|
||||
mxc_request_iomux(MX51_PIN_NANDF_D6, IOMUX_CONFIG_ALT1);
|
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_D6, ATA_PAD_CONFIG);
|
||||
mxc_request_iomux(MX51_PIN_NANDF_D7, IOMUX_CONFIG_ALT1);
|
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_D7, ATA_PAD_CONFIG);
|
||||
mxc_request_iomux(MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT1);
|
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_D8, ATA_PAD_CONFIG);
|
||||
mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT1);
|
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_D9, ATA_PAD_CONFIG);
|
||||
mxc_request_iomux(MX51_PIN_NANDF_D10, IOMUX_CONFIG_ALT1);
|
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_D10, ATA_PAD_CONFIG);
|
||||
mxc_request_iomux(MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT1);
|
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_D11, ATA_PAD_CONFIG);
|
||||
mxc_request_iomux(MX51_PIN_NANDF_D12, IOMUX_CONFIG_ALT1);
|
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_D12, ATA_PAD_CONFIG);
|
||||
mxc_request_iomux(MX51_PIN_NANDF_D13, IOMUX_CONFIG_ALT1);
|
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_D13, ATA_PAD_CONFIG);
|
||||
mxc_request_iomux(MX51_PIN_NANDF_D14, IOMUX_CONFIG_ALT1);
|
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_D14, ATA_PAD_CONFIG);
|
||||
mxc_request_iomux(MX51_PIN_NANDF_D15, IOMUX_CONFIG_ALT1);
|
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_D15, ATA_PAD_CONFIG);
|
||||
}
|
||||
#else
|
||||
static inline void setup_iomux_ata(void) { }
|
||||
#endif
|
||||
|
||||
/*
|
||||
* LED configuration
|
||||
*/
|
||||
void setup_iomux_led(void)
|
||||
{
|
||||
/* Blue LED */
|
||||
mxc_request_iomux(MX51_PIN_CSI1_D9, IOMUX_CONFIG_ALT3);
|
||||
mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_CSI1_D9),
|
||||
MXC_GPIO_DIRECTION_OUT);
|
||||
/* Green LED */
|
||||
mxc_request_iomux(MX51_PIN_CSI1_VSYNC, IOMUX_CONFIG_ALT3);
|
||||
mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_CSI1_VSYNC),
|
||||
MXC_GPIO_DIRECTION_OUT);
|
||||
/* Red LED */
|
||||
mxc_request_iomux(MX51_PIN_CSI1_HSYNC, IOMUX_CONFIG_ALT3);
|
||||
mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_CSI1_HSYNC),
|
||||
MXC_GPIO_DIRECTION_OUT);
|
||||
}
|
||||
|
||||
void efikamx_toggle_led(uint32_t mask)
|
||||
{
|
||||
mxc_gpio_set(IOMUX_TO_GPIO(MX51_PIN_CSI1_D9),
|
||||
mask & EFIKAMX_LED_BLUE);
|
||||
mxc_gpio_set(IOMUX_TO_GPIO(MX51_PIN_CSI1_VSYNC),
|
||||
mask & EFIKAMX_LED_GREEN);
|
||||
mxc_gpio_set(IOMUX_TO_GPIO(MX51_PIN_CSI1_HSYNC),
|
||||
mask & EFIKAMX_LED_RED);
|
||||
}
|
||||
|
||||
/*
|
||||
* Board initialization
|
||||
*/
|
||||
static void init_drive_strength(void)
|
||||
{
|
||||
mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEDDR, PAD_CTL_DDR_INPUT_CMOS);
|
||||
mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEADDR, PAD_CTL_PKE_ENABLE);
|
||||
mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRAPKS, PAD_CTL_PUE_KEEPER);
|
||||
mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRAPUS, PAD_CTL_100K_PU);
|
||||
mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_A1, PAD_CTL_SRE_FAST);
|
||||
mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_A0, PAD_CTL_DRV_HIGH);
|
||||
mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_A1, PAD_CTL_DRV_HIGH);
|
||||
mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_RAS,
|
||||
PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
|
||||
mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CAS,
|
||||
PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
|
||||
mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEDDR, PAD_CTL_PKE_ENABLE);
|
||||
mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRPKS, PAD_CTL_PUE_KEEPER);
|
||||
mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR0, PAD_CTL_HYS_NONE);
|
||||
mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR1, PAD_CTL_HYS_NONE);
|
||||
mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR2, PAD_CTL_HYS_NONE);
|
||||
mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR3, PAD_CTL_HYS_NONE);
|
||||
mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B0, PAD_CTL_SRE_FAST);
|
||||
mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B1, PAD_CTL_SRE_FAST);
|
||||
mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B2, PAD_CTL_SRE_FAST);
|
||||
mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B4, PAD_CTL_SRE_FAST);
|
||||
mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRPUS, PAD_CTL_100K_PU);
|
||||
mxc_iomux_set_pad(MX51_PIN_CTL_GRP_INMODE1, PAD_CTL_DDR_INPUT_CMOS);
|
||||
mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B0, PAD_CTL_DRV_MEDIUM);
|
||||
mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B1, PAD_CTL_DRV_MEDIUM);
|
||||
mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B2, PAD_CTL_DRV_MEDIUM);
|
||||
mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B4, PAD_CTL_DRV_MEDIUM);
|
||||
|
||||
/* Setting pad options */
|
||||
mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDWE,
|
||||
PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
|
||||
PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
|
||||
mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCKE0,
|
||||
PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
|
||||
PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
|
||||
mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCKE1,
|
||||
PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
|
||||
PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
|
||||
mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCLK,
|
||||
PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
|
||||
PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
|
||||
mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS0,
|
||||
PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
|
||||
PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
|
||||
mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS1,
|
||||
PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
|
||||
PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
|
||||
mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS2,
|
||||
PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
|
||||
PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
|
||||
mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS3,
|
||||
PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
|
||||
PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
|
||||
mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CS0,
|
||||
PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
|
||||
PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
|
||||
mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CS1,
|
||||
PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
|
||||
PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
|
||||
mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM0,
|
||||
PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
|
||||
PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
|
||||
mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM1,
|
||||
PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
|
||||
PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
|
||||
mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM2,
|
||||
PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
|
||||
PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
|
||||
mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM3,
|
||||
PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
|
||||
PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
|
||||
}
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
init_drive_strength();
|
||||
|
||||
setup_iomux_uart();
|
||||
setup_iomux_spi();
|
||||
setup_iomux_led();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
gd->bd->bi_arch_number = MACH_TYPE_MX51_LANGE51;
|
||||
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_late_init(void)
|
||||
{
|
||||
setup_iomux_spi();
|
||||
|
||||
power_init();
|
||||
|
||||
setup_iomux_led();
|
||||
setup_iomux_ata();
|
||||
|
||||
efikamx_toggle_led(EFIKAMX_LED_BLUE);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
u32 system_rev = get_cpu_rev();
|
||||
u32 cause;
|
||||
struct src *src_regs = (struct src *)SRC_BASE_ADDR;
|
||||
|
||||
puts("Board: Efika MX ");
|
||||
|
||||
switch (system_rev & 0xff) {
|
||||
case CHIP_REV_3_0:
|
||||
puts("3.0 [");
|
||||
break;
|
||||
case CHIP_REV_2_5:
|
||||
puts("2.5 [");
|
||||
break;
|
||||
case CHIP_REV_2_0:
|
||||
puts("2.0 [");
|
||||
break;
|
||||
case CHIP_REV_1_1:
|
||||
puts("1.1 [");
|
||||
break;
|
||||
case CHIP_REV_1_0:
|
||||
default:
|
||||
puts("1.0 [");
|
||||
break;
|
||||
}
|
||||
|
||||
cause = src_regs->srsr;
|
||||
switch (cause) {
|
||||
case 0x0001:
|
||||
puts("POR");
|
||||
break;
|
||||
case 0x0009:
|
||||
puts("RST");
|
||||
break;
|
||||
case 0x0010:
|
||||
case 0x0011:
|
||||
puts("WDOG");
|
||||
break;
|
||||
default:
|
||||
printf("unknown 0x%x", cause);
|
||||
}
|
||||
puts("]\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,122 @@
|
|||
#
|
||||
# Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
|
||||
#
|
||||
# BASED ON: imx51evk
|
||||
#
|
||||
# (C) Copyright 2009
|
||||
# Stefano Babic DENX Software Engineering sbabic@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not write to the Free Software
|
||||
# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
|
||||
# MA 02110-1301 USA
|
||||
#
|
||||
# Refer docs/README.imxmage for more details about how-to configure
|
||||
# and create imximage boot image
|
||||
#
|
||||
# The syntax is taken as close as possible with the kwbimage
|
||||
|
||||
# Boot Device : one of
|
||||
# spi, sd (the board has no nand neither onenand)
|
||||
BOOT_FROM spi
|
||||
|
||||
# Device Configuration Data (DCD)
|
||||
#
|
||||
# Each entry must have the format:
|
||||
# Addr-type Address Value
|
||||
#
|
||||
# where:
|
||||
# Addr-type register length (1,2 or 4 bytes)
|
||||
# Address absolute address of the register
|
||||
# value value to be stored in the register
|
||||
|
||||
# Setting IOMUXC
|
||||
DATA 4 0x73fa88a0 0x000
|
||||
DATA 4 0x73fa850c 0x20c5
|
||||
DATA 4 0x73fa8510 0x20c5
|
||||
DATA 4 0x73fa883c 0x5
|
||||
DATA 4 0x73fa8848 0x5
|
||||
DATA 4 0x73fa84b8 0xe7
|
||||
DATA 4 0x73fa84bc 0x45
|
||||
DATA 4 0x73fa84c0 0x45
|
||||
DATA 4 0x73fa84c4 0x45
|
||||
DATA 4 0x73fa84c8 0x45
|
||||
DATA 4 0x73fa8820 0x0
|
||||
DATA 4 0x73fa84a4 0x5
|
||||
DATA 4 0x73fa84a8 0x5
|
||||
DATA 4 0x73fa84ac 0xe5
|
||||
DATA 4 0x73fa84b0 0xe5
|
||||
DATA 4 0x73fa84b4 0xe5
|
||||
DATA 4 0x73fa84cc 0xe5
|
||||
DATA 4 0x73fa84d0 0xe4
|
||||
|
||||
DATA 4 0x73fa882c 0x4
|
||||
DATA 4 0x73fa88a4 0x4
|
||||
DATA 4 0x73fa88ac 0x4
|
||||
DATA 4 0x73fa88b8 0x4
|
||||
|
||||
# Setting DDR for micron
|
||||
# 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model
|
||||
# CAS=3 BL=4
|
||||
# ESDCTL_ESDCTL0
|
||||
DATA 4 0x83fd9000 0x82a20000
|
||||
# ESDCTL_ESDCTL1
|
||||
DATA 4 0x83fd9008 0x82a20000
|
||||
# ESDCTL_ESDMISC
|
||||
DATA 4 0x83fd9010 0xcaaaf6d0
|
||||
# ESDCTL_ESDCFG0
|
||||
DATA 4 0x83fd9004 0x3f3574aa
|
||||
# ESDCTL_ESDCFG1
|
||||
DATA 4 0x83fd900c 0x3f3574aa
|
||||
|
||||
# Init DRAM on CS0
|
||||
# ESDCTL_ESDSCR
|
||||
DATA 4 0x83fd9014 0x04008008
|
||||
DATA 4 0x83fd9014 0x0000801a
|
||||
DATA 4 0x83fd9014 0x0000801b
|
||||
DATA 4 0x83fd9014 0x00448019
|
||||
DATA 4 0x83fd9014 0x07328018
|
||||
DATA 4 0x83fd9014 0x04008008
|
||||
DATA 4 0x83fd9014 0x00008010
|
||||
DATA 4 0x83fd9014 0x00008010
|
||||
DATA 4 0x83fd9014 0x06328018
|
||||
DATA 4 0x83fd9014 0x03808019
|
||||
DATA 4 0x83fd9014 0x00408019
|
||||
DATA 4 0x83fd9014 0x00008000
|
||||
|
||||
# Init DRAM on CS1
|
||||
DATA 4 0x83fd9014 0x0400800c
|
||||
DATA 4 0x83fd9014 0x0000801e
|
||||
DATA 4 0x83fd9014 0x0000801f
|
||||
DATA 4 0x83fd9014 0x0000801d
|
||||
DATA 4 0x83fd9014 0x0732801c
|
||||
DATA 4 0x83fd9014 0x0400800c
|
||||
DATA 4 0x83fd9014 0x00008014
|
||||
DATA 4 0x83fd9014 0x00008014
|
||||
DATA 4 0x83fd9014 0x0632801c
|
||||
DATA 4 0x83fd9014 0x0380801d
|
||||
DATA 4 0x83fd9014 0x0040801d
|
||||
DATA 4 0x83fd9014 0x00008004
|
||||
|
||||
# Write to CTL0
|
||||
DATA 4 0x83fd9000 0xb2a20000
|
||||
# Write to CTL1
|
||||
DATA 4 0x83fd9008 0xb2a20000
|
||||
# ESDMISC
|
||||
DATA 4 0x83fd9010 0x000ad6d0
|
||||
#ESDCTL_ESDCDLYGD
|
||||
DATA 4 0x83fd9034 0x90000000
|
||||
DATA 4 0x83fd9014 0x00000000
|
||||
|
|
@ -105,6 +105,7 @@ magnesium arm arm926ejs imx27lite logicpd
|
|||
omap5912osk arm arm926ejs - ti omap
|
||||
edminiv2 arm arm926ejs - LaCie orion5x
|
||||
ca9x4_ct_vxp arm armv7 vexpress armltd
|
||||
efikamx arm armv7 efikamx - mx5
|
||||
mx51evk arm armv7 mx51evk freescale mx5
|
||||
mx53evk arm armv7 mx53evk freescale mx5
|
||||
vision2 arm armv7 vision2 ttcontrol mx5
|
||||
|
|
|
|||
|
|
@ -0,0 +1,232 @@
|
|||
/*
|
||||
* Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
|
||||
*
|
||||
* (C) Copyright 2009 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Configuration settings for the MX51EVK Board
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
/*
|
||||
* High Level Board Configuration Options
|
||||
*/
|
||||
/* An i.MX51 CPU */
|
||||
#define CONFIG_MX51
|
||||
#include <asm/arch/imx-regs.h>
|
||||
|
||||
#define CONFIG_SYS_MX5_HCLK 24000000
|
||||
#define CONFIG_SYS_MX5_CLK32 32768
|
||||
#define CONFIG_DISPLAY_CPUINFO
|
||||
#define CONFIG_DISPLAY_BOARDINFO
|
||||
|
||||
#define CONFIG_L2_OFF
|
||||
|
||||
/*
|
||||
* Bootloader Components Configuration
|
||||
*/
|
||||
#define CONFIG_CMD_SPI
|
||||
#define CONFIG_CMD_SF
|
||||
#define CONFIG_CMD_MMC
|
||||
#define CONFIG_CMD_FAT
|
||||
#define CONFIG_CMD_IDE
|
||||
#undef CONFIG_CMD_IMLS
|
||||
|
||||
/*
|
||||
* Environmental settings
|
||||
*/
|
||||
|
||||
#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
|
||||
#define CONFIG_ENV_SECT_SIZE (1 * 64 * 1024)
|
||||
#define CONFIG_ENV_SIZE (4 * 1024)
|
||||
|
||||
/*
|
||||
* ATAG setup
|
||||
*/
|
||||
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
|
||||
#define CONFIG_REVISION_TAG
|
||||
#define CONFIG_SETUP_MEMORY_TAGS
|
||||
#define CONFIG_INITRD_TAG
|
||||
|
||||
/*
|
||||
* Size of malloc() pool
|
||||
*/
|
||||
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F
|
||||
#define BOARD_LATE_INIT
|
||||
|
||||
/*
|
||||
* Hardware drivers
|
||||
*/
|
||||
#define CONFIG_MXC_UART
|
||||
#define CONFIG_SYS_MX51_UART1
|
||||
#define CONFIG_CONS_INDEX 1
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
|
||||
|
||||
#define CONFIG_MXC_GPIO
|
||||
|
||||
/*
|
||||
* SPI Interface
|
||||
*/
|
||||
#ifdef CONFIG_CMD_SPI
|
||||
|
||||
#define CONFIG_HARD_SPI
|
||||
#define CONFIG_MXC_SPI
|
||||
#define CONFIG_DEFAULT_SPI_BUS 1
|
||||
#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH)
|
||||
|
||||
/* SPI FLASH */
|
||||
#ifdef CONFIG_CMD_SF
|
||||
|
||||
#define CONFIG_SPI_FLASH
|
||||
#define CONFIG_SPI_FLASH_SST
|
||||
#define CONFIG_SPI_FLASH_CS (1 | 121 << 8)
|
||||
#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
|
||||
#define CONFIG_SF_DEFAULT_SPEED 25000000
|
||||
|
||||
#define CONFIG_ENV_SPI_CS (1 | 121 << 8)
|
||||
#define CONFIG_ENV_SPI_BUS 0
|
||||
#define CONFIG_ENV_SPI_MAX_HZ 25000000
|
||||
#define CONFIG_ENV_SPI_MODE (SPI_MODE_0)
|
||||
#define CONFIG_FSL_ENV_IN_SF
|
||||
#define CONFIG_ENV_IS_IN_SPI_FLASH
|
||||
#define CONFIG_SYS_NO_FLASH
|
||||
|
||||
#else
|
||||
#define CONFIG_ENV_IS_NOWHERE
|
||||
#endif
|
||||
|
||||
/* SPI PMIC */
|
||||
#define CONFIG_FSL_PMIC
|
||||
#define CONFIG_FSL_PMIC_BUS 0
|
||||
#define CONFIG_FSL_PMIC_CS (0 | 120 << 8)
|
||||
#define CONFIG_FSL_PMIC_CLK 25000000
|
||||
#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
|
||||
#define CONFIG_RTC_MC13783
|
||||
#endif
|
||||
|
||||
/*
|
||||
* MMC Configs
|
||||
*/
|
||||
#ifdef CONFIG_CMD_MMC
|
||||
#define CONFIG_MMC
|
||||
#define CONFIG_GENERIC_MMC
|
||||
#define CONFIG_FSL_ESDHC
|
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
|
||||
#define CONFIG_SYS_FSL_ESDHC_NUM 2
|
||||
#endif
|
||||
|
||||
/*
|
||||
* ATA/IDE
|
||||
*/
|
||||
#ifdef CONFIG_CMD_IDE
|
||||
#define CONFIG_LBA48
|
||||
#undef CONFIG_IDE_LED
|
||||
#undef CONFIG_IDE_RESET
|
||||
|
||||
#define CONFIG_MX51_PATA
|
||||
|
||||
#define __io
|
||||
|
||||
#define CONFIG_SYS_IDE_MAXBUS 1
|
||||
#define CONFIG_SYS_IDE_MAXDEVICE 1
|
||||
|
||||
#define CONFIG_SYS_ATA_BASE_ADDR 0x83fe0000
|
||||
#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0
|
||||
|
||||
#define CONFIG_SYS_ATA_DATA_OFFSET 0xa0
|
||||
#define CONFIG_SYS_ATA_REG_OFFSET 0xa0
|
||||
#define CONFIG_SYS_ATA_ALT_OFFSET 0xd8
|
||||
|
||||
#define CONFIG_SYS_ATA_STRIDE 4
|
||||
|
||||
#define CONFIG_IDE_PREINIT
|
||||
#define CONFIG_MXC_ATA_PIO_MODE 4
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Filesystems
|
||||
*/
|
||||
#ifdef CONFIG_CMD_FAT
|
||||
#define CONFIG_DOS_PARTITION
|
||||
#endif
|
||||
|
||||
#undef CONFIG_CMD_PING
|
||||
#undef CONFIG_CMD_DHCP
|
||||
#undef CONFIG_CMD_NET
|
||||
#undef CONFIG_CMD_NFS
|
||||
#define CONFIG_CMD_DATE
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
#define CONFIG_BOOTDELAY 3
|
||||
#define CONFIG_LOADADDR 0x90800000
|
||||
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
|
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
|
||||
#define CONFIG_SYS_PROMPT "Efika> "
|
||||
#define CONFIG_AUTO_COMPLETE
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
/* Print Buffer Size */
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x90000000
|
||||
#define CONFIG_SYS_MEMTEST_END 0x10000
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
|
||||
|
||||
#define CONFIG_SYS_HZ 1000
|
||||
#define CONFIG_CMDLINE_EDITING
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Stack sizes
|
||||
*
|
||||
* The stack sizes are set up in start.S using the settings below
|
||||
*/
|
||||
#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Physical Memory Map
|
||||
*/
|
||||
#define CONFIG_NR_DRAM_BANKS 1
|
||||
#define PHYS_SDRAM_1 CSD0_BASE_ADDR
|
||||
#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024)
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
|
||||
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET \
|
||||
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_ADDR \
|
||||
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
|
||||
|
||||
#define CONFIG_SYS_DDR_CLKSEL 0
|
||||
#define CONFIG_SYS_CLKTL_CBCDR 0x59E35100
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue