FSL DDR: Convert PM854 to new DDR code.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Kumar Gala
parent
33b9079ba2
commit
d53bd3e17b
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@ -25,10 +25,13 @@ include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).a
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COBJS := $(BOARD).o law.o tlb.o
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COBJS-y += $(BOARD).o
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COBJS-y += law.o
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COBJS-y += tlb.o
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COBJS-$(CONFIG_FSL_DDR1) += ddr.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS-y))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS)
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@ -0,0 +1,70 @@
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/*
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* Copyright 2008 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* Version 2 as published by the Free Software Foundation.
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*/
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#include <common.h>
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#include <i2c.h>
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#include <asm/fsl_ddr_sdram.h>
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static void
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get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address)
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{
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i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t));
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}
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unsigned int
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fsl_ddr_get_mem_data_rate(void)
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{
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return get_ddr_freq(0);
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}
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void
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fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd,
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unsigned int ctrl_num)
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{
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unsigned int i;
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unsigned int i2c_address = 0;
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for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
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if (ctrl_num == 0 && i == 0) {
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i2c_address = SPD_EEPROM_ADDRESS;
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}
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get_spd(&(ctrl_dimms_spd[i]), i2c_address);
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}
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}
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void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num)
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{
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/*
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* Factors to consider for CPO:
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* - frequency
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* - ddr1 vs. ddr2
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*/
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popts->cpo_override = 0;
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/*
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* Factors to consider for write data delay:
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* - number of DIMMs
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*
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* 1 = 1/4 clock delay
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* 2 = 1/2 clock delay
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* 3 = 3/4 clock delay
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* 4 = 1 clock delay
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* 5 = 5/4 clock delay
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* 6 = 3/2 clock delay
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*/
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popts->write_data_delay = 3;
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/*
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* Factors to consider for half-strength driver enable:
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* - number of DIMMs installed
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*/
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popts->half_strength_driver_enable = 0;
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}
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@ -28,7 +28,9 @@
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#include <common.h>
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#include <pci.h>
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#include <asm/processor.h>
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#include <asm/mmu.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_ddr_sdram.h>
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#include <spd_sdram.h>
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#if defined(CONFIG_DDR_ECC)
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@ -105,7 +107,9 @@ initdram(int board_type)
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#endif
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#if defined(CONFIG_SPD_EEPROM)
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dram_size = spd_sdram ();
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dram_size = fsl_ddr_sdram();
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dram_size = setup_ddr_tlbs(dram_size / 0x100000);
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dram_size *= 0x100000;
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#else
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dram_size = fixed_sdram ();
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#endif
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@ -44,12 +44,6 @@
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#define CONFIG_PCI
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#define CONFIG_TSEC_ENET /* tsec ethernet support */
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#define CONFIG_ENV_OVERWRITE
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#undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup*/
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#define CONFIG_DDR_DLL /* possible DLL fix needed */
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#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
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#define CONFIG_DDR_ECC /* only for ECC DDR module */
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#define CONFIG_MEM_INIT_VALUE 0xDEADBEEF
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#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
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@ -96,32 +90,36 @@
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#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
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/*
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* DDR Setup
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*/
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#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
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/* DDR Setup */
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#define CONFIG_FSL_DDR1
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#undef CONFIG_FSL_DDR_INTERACTIVE
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#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
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#undef CONFIG_DDR_SPD
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#define CONFIG_DDR_DLL /* possible DLL fix needed */
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#define CONFIG_DDR_ECC /* only for ECC DDR module */
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#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
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#define CFG_DDR_SDRAM_BASE 0x00000000
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#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
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#define CONFIG_VERY_BIG_RAM
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#if defined(CONFIG_SPD_EEPROM)
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/*
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* Determine DDR configuration from I2C interface.
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*/
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#define SPD_EEPROM_ADDRESS 0x58 /* DDR DIMM */
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#define CONFIG_NUM_DDR_CONTROLLERS 1
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#define CONFIG_DIMM_SLOTS_PER_CTLR 1
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#define CONFIG_CHIP_SELECTS_PER_CTRL 2
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#else
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/*
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* Manually set up DDR parameters
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*/
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#define CFG_SDRAM_SIZE 256 /* DDR is 256 MB */
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#define CFG_DDR_CS0_BNDS 0x0000000f /* 0-256MB */
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#define CFG_DDR_CS0_CONFIG 0x80000102
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#define CFG_DDR_TIMING_1 0x47444321
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#define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
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#define CFG_DDR_CONTROL 0xc2008000 /* unbuffered,no DYN_PWR */
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#define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */
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#define CFG_DDR_INTERVAL 0x045b0100 /* autocharge,no open page */
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#endif
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/* I2C addresses of SPD EEPROMs */
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#define SPD_EEPROM_ADDRESS 0x58 /* CTLR 0 DIMM 0 */
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/* Manually set up DDR parameters */
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#define CFG_SDRAM_SIZE 256 /* DDR is 256 MB */
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#define CFG_DDR_CS0_BNDS 0x0000000f /* 0-256MB */
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#define CFG_DDR_CS0_CONFIG 0x80000102
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#define CFG_DDR_TIMING_1 0x47444321
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#define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
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#define CFG_DDR_CONTROL 0xc2008000 /* unbuffered,no DYN_PWR */
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#define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */
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#define CFG_DDR_INTERVAL 0x045b0100 /* autocharge,no open page */
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/*
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* SDRAM on the Local Bus
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