at91: Update meesc board to new SoC access
* convert meesc board to use c stucture SoC access * change gpio access to at91_gpio syntax * moved CONFIG_SYS_HZ below board and cpu defines (purely cosmetic) Signed-off-by: Daniel Gorsulowski <Daniel.Gorsulowski@esd.eu> Signed-off-by: Reinhard Meyer <u-boot@emk-elektronik.de>
This commit is contained in:
Daniel Gorsulowski
Reinhard Meyer
parent
9f07dedeb0
commit
d4562e0940
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@ -3,7 +3,7 @@
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* Stelian Pop <stelian.pop@leadtechdesign.com>
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* Lead Tech Design <www.leadtechdesign.com>
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*
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* (C) Copyright 2009
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* (C) Copyright 2009-2010
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* Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
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* esd electronic system design gmbh <www.esd.eu>
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*
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@ -28,13 +28,13 @@
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#include <common.h>
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#include <asm/arch/at91sam9263.h>
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#include <asm/arch/at91sam9_matrix.h>
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#include <asm/arch/at91sam9_smc.h>
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#include <asm/arch/at91_common.h>
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#include <asm/arch/at91_pmc.h>
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#include <asm/arch/at91_rstc.h>
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#include <asm/arch/at91_matrix.h>
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#include <asm/arch/at91_pio.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/io.h>
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#include <netdev.h>
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@ -52,10 +52,10 @@ int get_hw_rev(void)
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if (hw_rev >= 0)
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return hw_rev;
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hw_rev = at91_get_gpio_value(AT91_PIN_PB19);
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hw_rev |= at91_get_gpio_value(AT91_PIN_PB20) << 1;
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hw_rev |= at91_get_gpio_value(AT91_PIN_PB21) << 2;
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hw_rev |= at91_get_gpio_value(AT91_PIN_PB22) << 3;
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hw_rev = at91_get_pio_value(AT91_PIO_PORTB, 19);
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hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 20) << 1;
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hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 21) << 2;
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hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 22) << 3;
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if (hw_rev == 15)
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hw_rev = 0;
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@ -67,44 +67,44 @@ int get_hw_rev(void)
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static void meesc_nand_hw_init(void)
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{
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unsigned long csa;
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at91_smc_t *smc = (at91_smc_t *) AT91_SMC0_BASE;
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at91_matrix_t *matrix = (at91_matrix_t *) AT91_MATRIX_BASE;
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/* Enable CS3 */
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csa = at91_sys_read(AT91_MATRIX_EBI0CSA);
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at91_sys_write(AT91_MATRIX_EBI0CSA,
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csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA);
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csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
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writel(csa, &matrix->csa[0]);
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/* Configure SMC CS3 for NAND/SmartMedia */
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at91_sys_write(AT91_SMC_SETUP(3),
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AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
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AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
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at91_sys_write(AT91_SMC_PULSE(3),
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AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
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AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
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at91_sys_write(AT91_SMC_CYCLE(3),
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AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
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at91_sys_write(AT91_SMC_MODE(3),
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AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
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AT91_SMC_EXNWMODE_DISABLE |
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#ifdef CONFIG_SYS_NAND_DBW_16
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AT91_SMC_DBW_16 |
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#else /* CONFIG_SYS_NAND_DBW_8 */
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AT91_SMC_DBW_8 |
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#endif
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AT91_SMC_TDF_(2));
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writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
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AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
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&smc->cs[3].setup);
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writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
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AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
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&smc->cs[3].pulse);
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writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
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&smc->cs[3].cycle);
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writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
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AT91_SMC_MODE_EXNW_DISABLE |
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AT91_SMC_MODE_DBW_8 |
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AT91_SMC_MODE_TDF_CYCLE(2),
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&smc->cs[3].mode);
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/* Configure RDY/BSY */
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at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
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at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
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/* Enable NandFlash */
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at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
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at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
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}
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#endif /* CONFIG_CMD_NAND */
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#ifdef CONFIG_MACB
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static void meesc_macb_hw_init(void)
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{
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at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
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/* Enable clock */
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at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_EMAC);
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writel(1 << AT91SAM9263_ID_EMAC, &pmc->pcer);
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at91_macb_hw_init();
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}
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#endif
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@ -117,26 +117,27 @@ static void meesc_macb_hw_init(void)
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*/
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static void meesc_ethercat_hw_init(void)
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{
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at91_smc_t *smc1 = (at91_smc_t *) AT91_SMC1_BASE;
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/* Configure SMC EBI1_CS0 for EtherCAT */
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at91_sys_write(AT91_SMC1_SETUP(0),
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AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) |
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AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
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at91_sys_write(AT91_SMC1_PULSE(0),
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AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(9) |
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AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(9));
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at91_sys_write(AT91_SMC1_CYCLE(0),
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AT91_SMC_NWECYCLE_(10) | AT91_SMC_NRDCYCLE_(5));
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writel(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) |
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AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0),
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&smc1->cs[0].setup);
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writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(9) |
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AT91_SMC_PULSE_NRD(5) | AT91_SMC_PULSE_NCS_RD(9),
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&smc1->cs[0].pulse);
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writel(AT91_SMC_CYCLE_NWE(10) | AT91_SMC_CYCLE_NRD(6),
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&smc1->cs[0].cycle);
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/*
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* Configure behavior at external wait signal, byte-select mode, 16 bit
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* data bus width, none data float wait states and TDF optimization
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*/
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at91_sys_write(AT91_SMC1_MODE(0),
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AT91_SMC_READMODE | AT91_SMC_EXNWMODE_READY |
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AT91_SMC_BAT_SELECT | AT91_SMC_DBW_16 | AT91_SMC_TDF_(0) |
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AT91_SMC_TDFMODE);
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writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_EXNW_READY |
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AT91_SMC_MODE_DBW_16 | AT91_SMC_MODE_TDF_CYCLE(0) |
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AT91_SMC_MODE_TDF, &smc1->cs[0].mode);
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/* Configure RDY/BSY */
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at91_set_B_periph(AT91_PIN_PE20, 0); /* EBI1_NWAIT */
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at91_set_b_periph(AT91_PIO_PORTE, 20, 0); /* EBI1_NWAIT */
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}
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int dram_init(void)
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@ -150,7 +151,7 @@ int board_eth_init(bd_t *bis)
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{
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int rc = 0;
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#ifdef CONFIG_MACB
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rc = macb_eth_initialize(0, (void *)AT91SAM9263_BASE_EMAC, 0x00);
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rc = macb_eth_initialize(0, (void *)AT91_EMAC_BASE, 0x00);
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#endif
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return rc;
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}
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@ -175,7 +176,7 @@ int checkboard(void)
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gd->bd->bi_arch_number = MACH_TYPE_ETHERCAN2;
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puts("Board: EtherCAN/2 Gateway");
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/* switch on LED1D */
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at91_set_gpio_output(AT91_PIN_PB12, 1);
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at91_set_pio_output(AT91_PIO_PORTB, 12, 1);
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break;
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default:
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/* assume, no ET1100 present, arch number of EtherCAN/2-Board */
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@ -222,8 +223,9 @@ u32 get_board_rev(void)
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#ifdef CONFIG_MISC_INIT_R
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int misc_init_r(void)
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{
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char *str;
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char buf[32];
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char *str;
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char buf[32];
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at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
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/*
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* Normally the processor clock has a divisor of 2.
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@ -231,10 +233,9 @@ int misc_init_r(void)
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* Check the user has set environment mdiv to 4 to change the divisor.
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*/
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if ((str = getenv("mdiv")) && (strcmp(str, "4") == 0)) {
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at91_sys_write(AT91_PMC_MCKR,
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(at91_sys_read(AT91_PMC_MCKR) & ~AT91_PMC_MDIV) |
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AT91SAM9_PMC_MDIV_4);
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at91_clock_init(0);
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writel((readl(&pmc->mckr) & ~AT91_PMC_MDIV) |
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AT91SAM9_PMC_MDIV_4, &pmc->mckr);
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at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
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serial_setbrg();
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/* Notify the user that the clock is not default */
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printf("Setting master clock to %s MHz\n",
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@ -247,10 +248,13 @@ int misc_init_r(void)
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int board_init(void)
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{
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at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
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/* Peripheral Clock Enable Register */
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at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_PIOA |
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1 << AT91SAM9263_ID_PIOB |
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1 << AT91SAM9263_ID_PIOCDE);
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writel(1 << AT91SAM9263_ID_PIOA |
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1 << AT91SAM9263_ID_PIOB |
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1 << AT91SAM9263_ID_PIOCDE,
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&pmc->pcer);
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/* initialize ET1100 Controller */
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meesc_ethercat_hw_init();
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@ -31,14 +31,12 @@
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_AT91_LEGACY
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/* Common stuff */
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#define CONFIG_SYS_HZ 1000 /* decrementer freq */
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#define CONFIG_MEESC 1 /* Board is esd MEESC */
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#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
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#define CONFIG_AT91SAM9263 1 /* It's an AT91SAM9263 SoC */
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#define CONFIG_SYS_AT91_MAIN_CLOCK 16000000/* 16.0 MHz crystal */
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#define CONFIG_SYS_HZ 1000 /* decrementer freq */
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#define CONFIG_DISPLAY_BOARDINFO 1
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#define CONFIG_DISPLAY_CPUINFO 1 /* display cpu info and speed */
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#define CONFIG_PREBOOT /* enable preboot variable */
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@ -122,9 +120,9 @@
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#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
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/* our CLE is AD22 */
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#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
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#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15
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#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA22
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#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTD, 15
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#define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTA, 22
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#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
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#endif
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/* Ethernet */
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