From 3fee334c85fd16904f8d23487247508cceab0228 Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Wed, 9 Feb 2011 13:40:51 -0600 Subject: [PATCH 1/4] fsl: update CRC after setting EEPROM identifier The "mac id" command is used to initialize the EEPROM data to a specific format, but it was not updating the CRC. This didn't cause any real problems, because writing the data to the EEPROM will always update the CRC anyway, but it did result in a bogus CRC warning. Signed-off-by: Timur Tabi Signed-off-by: Kumar Gala --- board/freescale/common/sys_eeprom.c | 1 + 1 file changed, 1 insertion(+) diff --git a/board/freescale/common/sys_eeprom.c b/board/freescale/common/sys_eeprom.c index 11dfd84fe..3ecfb06cc 100644 --- a/board/freescale/common/sys_eeprom.c +++ b/board/freescale/common/sys_eeprom.c @@ -361,6 +361,7 @@ int do_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #else memcpy(e.id, "CCID", sizeof(e.id)); #endif + update_crc(); return 0; } From a34af3cc9f1fdda04d446e65ceab3a28d9dc2bb1 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 9 Feb 2011 23:36:24 -0600 Subject: [PATCH 2/4] powerpc/85xx: Fix p1_p2_rdb boards.cfg We should have been defining the actual board name in the options, not the processor. Fix this for P1011RDB, P1020RDB, P2010RDB, and P2020RDB. Signed-off-by: Kumar Gala --- boards.cfg | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/boards.cfg b/boards.cfg index 59d4a41f2..9b3428788 100644 --- a/boards.cfg +++ b/boards.cfg @@ -480,26 +480,26 @@ MPC8569MDS_NAND powerpc mpc85xx mpc8569mds freesca MPC8572DS powerpc mpc85xx mpc8572ds freescale - MPC8572DS MPC8572DS_36BIT powerpc mpc85xx mpc8572ds freescale - MPC8572DS:36BIT MPC8572DS_NAND powerpc mpc85xx mpc8572ds freescale - MPC8572DS:NAND -P1011RDB powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011 -P1011RDB_NAND powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011,NAND -P1011RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011,SDCARD -P1011RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011,SPIFLASH +P1011RDB powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011RDB +P1011RDB_NAND powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011RDB,NAND +P1011RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011RDB,SDCARD +P1011RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011RDB,SPIFLASH P1020RDB powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB P1020RDB_NAND powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB,NAND P1020RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB,SDCARD -P1020RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020,SPIFLASH +P1020RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB,SPIFLASH P1022DS powerpc mpc85xx p1022ds freescale -P2010RDB powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010 -P2010RDB_NAND powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010,NAND -P2010RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010,SDCARD -P2010RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010,SPIFLASH +P2010RDB powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010RDB +P2010RDB_NAND powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010RDB,NAND +P2010RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010RDB,SDCARD +P2010RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010RDB,SPIFLASH P2020DS powerpc mpc85xx p2020ds freescale P2020DS_36BIT powerpc mpc85xx p2020ds freescale - P2020DS:36BIT P2020DS_DDR2 powerpc mpc85xx p2020ds freescale - P2020DS:DDR2 -P2020RDB powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020 -P2020RDB_NAND powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020,NAND -P2020RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020,SDCARD -P2020RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020,SPIFLASH +P2020RDB powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB +P2020RDB_NAND powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,NAND +P2020RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,SDCARD +P2020RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,SPIFLASH P4080DS powerpc mpc85xx corenet_ds freescale mpq101 powerpc mpc85xx mpq101 mercury - mpq101 stxgp3 powerpc mpc85xx stxgp3 stx From b1d67857af0f66f3def3d0461c141d9b4eccc15e Mon Sep 17 00:00:00 2001 From: Priyanka Jain Date: Tue, 8 Feb 2011 13:17:56 +0530 Subject: [PATCH 3/4] powerpc/85xx: corrected p1_p2_rdb EEPROM address Board EEPROM is used to read/save Ethernet MAC addresses. Signed-off-by: Priyanka Jain Signed-off-by: Kumar Gala --- include/configs/P1_P2_RDB.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index bf3474004..982cdd501 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -344,7 +344,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_I2C_MULTI_BUS #define CONFIG_I2C_CMD_TREE #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address*/ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 #define CONFIG_SYS_I2C_SLAVE 0x7F #define CONFIG_SYS_I2C_NOPROBES {{0,0x29}} /* Don't probe these addrs */ #define CONFIG_SYS_I2C_OFFSET 0x3000 @@ -357,7 +356,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #ifdef CONFIG_ID_EEPROM #define CONFIG_SYS_I2C_EEPROM_NXID #endif -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_EEPROM_BUS_NUM 1 From 856e4b0d7fa366b300bae4f5b9512d7baac6bff1 Mon Sep 17 00:00:00 2001 From: York Sun Date: Thu, 10 Feb 2011 10:13:10 -0800 Subject: [PATCH 4/4] powerpc/8xxx: Add additional cycle to write-to-read turnaound for DDR3 When DDR data rate is higher than 1200MT/s or controller interleaving is enabled, additional cycle for write-to-read turnaround is needed to satisfy dynamic ODT timing. Signed-off-by: York Sun Signed-off-by: Kumar Gala --- arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c | 3 +++ arch/powerpc/cpu/mpc8xxx/ddr/ddr.h | 2 +- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c index c3e1d7664..936c1951f 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -236,9 +236,12 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr, * tAXPD=1, need design to confirm. */ int tXP = max((get_memory_clk_period_ps() * 3), 7500); /* unit=ps */ + unsigned int data_rate = fsl_ddr_get_mem_data_rate(); tmrd_mclk = 4; /* set the turnaround time */ trwt_mclk = 1; + if ((data_rate/1000000 > 1150) || (popts->memctl_interleaving)) + twrt_mclk = 1; if (popts->dynamic_power == 0) { /* powerdown is not used */ act_pd_exit_mclk = 1; diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h b/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h index 35b60a041..c7c12c1c2 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h @@ -80,5 +80,5 @@ extern void check_interleaving_options(fsl_ddr_info_t *pinfo); extern unsigned int mclk_to_picos(unsigned int mclk); extern unsigned int get_memory_clk_period_ps(void); extern unsigned int picos_to_mclk(unsigned int picos); - +extern unsigned int fsl_ddr_get_mem_data_rate(void); #endif