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Minor Coding Style Cleanup. 

Signed-off-by: Wolfgang Denk <wd@denx.de>
This commit is contained in:
Wolfgang Denk 2011-02-02 22:36:10 +01:00
parent be9db564de
commit d1a24f0618
8 changed files with 68 additions and 69 deletions
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4
arch/powerpc/include/asm/config_mpc85xx.h
View File

@ -35,11 +35,11 @@
#define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_FSL_SEC_COMPAT 2
#elif defined(CONFIG_MPC8540) #elif defined(CONFIG_MPC8540)
#define CONFIG_MAX_CPUS 1 #define CONFIG_MAX_CPUS 1
#define CONFIG_SYS_FSL_NUM_LAWS 8 #define CONFIG_SYS_FSL_NUM_LAWS 8
#elif defined(CONFIG_MPC8541) #elif defined(CONFIG_MPC8541)
#define CONFIG_MAX_CPUS 1 #define CONFIG_MAX_CPUS 1
#define CONFIG_SYS_FSL_NUM_LAWS 8 #define CONFIG_SYS_FSL_NUM_LAWS 8
#define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_FSL_SEC_COMPAT 2

2
arch/powerpc/include/asm/config_mpc86xx.h
View File

@ -27,7 +27,7 @@
#define CONFIG_MAX_CPUS 1 #define CONFIG_MAX_CPUS 1
#define CONFIG_SYS_FSL_NUM_LAWS 10 #define CONFIG_SYS_FSL_NUM_LAWS 10
#elif defined(CONFIG_MPC8641) #elif defined(CONFIG_MPC8641)
#define CONFIG_MAX_CPUS 2 #define CONFIG_MAX_CPUS 2
#define CONFIG_SYS_FSL_NUM_LAWS 10 #define CONFIG_SYS_FSL_NUM_LAWS 10

4
common/hwconfig.c
View File

@ -81,8 +81,8 @@ static const char *__hwconfig(const char *opt, size_t *arglen,
if (!env_hwconfig) { if (!env_hwconfig) {
if (!(gd->flags & GD_FLG_ENV_READY)) { if (!(gd->flags & GD_FLG_ENV_READY)) {
printf("WARNING: Calling __hwconfig without a buffer " printf("WARNING: Calling __hwconfig without a buffer "
"and before environment is ready\n"); "and before environment is ready\n");
return NULL; return NULL;
} }
env_hwconfig = getenv("hwconfig"); env_hwconfig = getenv("hwconfig");
} }

84
doc/README.fsl-ddr
View File

@ -2,25 +2,25 @@
Table of interleaving modes supported in cpu/8xxx/ddr/ Table of interleaving modes supported in cpu/8xxx/ddr/
====================================================== ======================================================
+-------------+---------------------------------------------------------+ +-------------+---------------------------------------------------------+
| | Rank Interleaving | | | Rank Interleaving |
| +--------+-----------+-----------+------------+-----------+ | +--------+-----------+-----------+------------+-----------+
|Memory | | | | 2x2 | 4x1 | |Memory | | | | 2x2 | 4x1 |
|Controller | None | 2x1 lower | 2x1 upper | {CS0+CS1}, | {CS0+CS1+ | |Controller | None | 2x1 lower | 2x1 upper | {CS0+CS1}, | {CS0+CS1+ |
|Interleaving | | {CS0+CS1} | {CS2+CS3} | {CS2+CS3} | CS2+CS3} | |Interleaving | | {CS0+CS1} | {CS2+CS3} | {CS2+CS3} | CS2+CS3} |
+-------------+--------+-----------+-----------+------------+-----------+ +-------------+--------+-----------+-----------+------------+-----------+
|None | Yes | Yes | Yes | Yes | Yes | |None | Yes | Yes | Yes | Yes | Yes |
+-------------+--------+-----------+-----------+------------+-----------+ +-------------+--------+-----------+-----------+------------+-----------+
|Cacheline | Yes | Yes | No | No, Only(*)| Yes | |Cacheline | Yes | Yes | No | No, Only(*)| Yes |
| |CS0 Only| | | {CS0+CS1} | | | |CS0 Only| | | {CS0+CS1} | |
+-------------+--------+-----------+-----------+------------+-----------+ +-------------+--------+-----------+-----------+------------+-----------+
|Page | Yes | Yes | No | No, Only(*)| Yes | |Page | Yes | Yes | No | No, Only(*)| Yes |
| |CS0 Only| | | {CS0+CS1} | | | |CS0 Only| | | {CS0+CS1} | |
+-------------+--------+-----------+-----------+------------+-----------+ +-------------+--------+-----------+-----------+------------+-----------+
|Bank | Yes | Yes | No | No, Only(*)| Yes | |Bank | Yes | Yes | No | No, Only(*)| Yes |
| |CS0 Only| | | {CS0+CS1} | | | |CS0 Only| | | {CS0+CS1} | |
+-------------+--------+-----------+-----------+------------+-----------+ +-------------+--------+-----------+-----------+------------+-----------+
|Superbank | No | Yes | No | No, Only(*)| Yes | |Superbank | No | Yes | No | No, Only(*)| Yes |
| | | | | {CS0+CS1} | | | | | | | {CS0+CS1} | |
+-------------+--------+-----------+-----------+------------+-----------+ +-------------+--------+-----------+-----------+------------+-----------+
(*) Although the hardware can be configured with memory controller (*) Although the hardware can be configured with memory controller
interleaving using "2x2" rank interleaving, it only interleaves {CS0+CS1} interleaving using "2x2" rank interleaving, it only interleaves {CS0+CS1}
@ -116,57 +116,57 @@ in Ohms.
Two slots system Two slots system
+-----------------------+----------+---------------+-----------------------------+-----------------------------+ +-----------------------+----------+---------------+-----------------------------+-----------------------------+
| Configuration | |DRAM controller| Slot 1 | Slot 2 | | Configuration | |DRAM controller| Slot 1 | Slot 2 |
+-----------+-----------+----------+-------+-------+--------------+--------------+--------------+--------------+ +-----------+-----------+----------+-------+-------+--------------+--------------+--------------+--------------+
| | | | | | Rank 1 | Rank 2 | Rank 1 | Rank 2 | | | | | | | Rank 1 | Rank 2 | Rank 1 | Rank 2 |
+ Slot 1 | Slot 2 |Write/Read| Write | Read |-------+------+-------+------+-------+------+-------+------+ + Slot 1 | Slot 2 |Write/Read| Write | Read |-------+------+-------+------+-------+------+-------+------+
| | | | | | Write | Read | Write | Read | Write | Read | Write | Read | | | | | | | Write | Read | Write | Read | Write | Read | Write | Read |
+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
| | | Slot 1 | off | 75 | 120 | off | off | off | off | off | 30 | 30 | | | | Slot 1 | off | 75 | 120 | off | off | off | off | off | 30 | 30 |
| Dual Rank | Dual Rank |----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ | Dual Rank | Dual Rank |----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
| | | Slot 2 | off | 75 | off | off | 30 | 30 | 120 | off | off | off | | | | Slot 2 | off | 75 | off | off | 30 | 30 | 120 | off | off | off |
+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
| | | Slot 1 | off | 75 | 120 | off | off | off | 20 | 20 | | | | | | Slot 1 | off | 75 | 120 | off | off | off | 20 | 20 | | |
| Dual Rank |Single Rank|----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ | Dual Rank |Single Rank|----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
| | | Slot 2 | off | 75 | off | off | 20 | 20 | 120 *| off | | | | | | Slot 2 | off | 75 | off | off | 20 | 20 | 120 *| off | | |
+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
| | | Slot 1 | off | 75 | 120 *| off | | | off | off | 20 | 20 | | | | Slot 1 | off | 75 | 120 *| off | | | off | off | 20 | 20 |
|Single Rank| Dual Rank |----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ |Single Rank| Dual Rank |----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
| | | Slot 2 | off | 75 | 20 | 20 | | | 120 | off | off | off | | | | Slot 2 | off | 75 | 20 | 20 | | | 120 | off | off | off |
+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
| | | Slot 1 | off | 75 | 120 *| off | | | 30 | 30 | | | | | | Slot 1 | off | 75 | 120 *| off | | | 30 | 30 | | |
|Single Rank|Single Rank|----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ |Single Rank|Single Rank|----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
| | | Slot 2 | off | 75 | 30 | 30 | | | 120 *| off | | | | | | Slot 2 | off | 75 | 30 | 30 | | | 120 *| off | | |
+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
| Dual Rank | Empty | Slot 1 | off | 75 | 40 | off | off | off | | | | | | Dual Rank | Empty | Slot 1 | off | 75 | 40 | off | off | off | | | | |
+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
| Empty | Dual Rank | Slot 2 | off | 75 | | | | | 40 | off | off | off | | Empty | Dual Rank | Slot 2 | off | 75 | | | | | 40 | off | off | off |
+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
|Single Rank| Empty | Slot 1 | off | 75 | 40 | off | | | | | | | |Single Rank| Empty | Slot 1 | off | 75 | 40 | off | | | | | | |
+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
| Empty |Single Rank| Slot 2 | off | 75 | | | | | 40 | off | | | | Empty |Single Rank| Slot 2 | off | 75 | | | | | 40 | off | | |
+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
Single slot system Single slot system
+-------------+------------+---------------+-----------------------------+-----------------------------+ +-------------+------------+---------------+-----------------------------+-----------------------------+
| | |DRAM controller| Rank 1 | Rank 2 | Rank 3 | Rank 4 | | | |DRAM controller| Rank 1 | Rank 2 | Rank 3 | Rank 4 |
|Configuration| Write/Read |-------+-------+-------+------+-------+------+-------+------+-------+------+ |Configuration| Write/Read |-------+-------+-------+------+-------+------+-------+------+-------+------+
| | | Write | Read | Write | Read | Write | Read | Write | Read | Write | Read | | | | Write | Read | Write | Read | Write | Read | Write | Read | Write | Read |
+-------------+------------+-------+-------+-------+------+-------+------+-------+------+-------+------+ +-------------+------------+-------+-------+-------+------+-------+------+-------+------+-------+------+
| | R1 | off | 75 | 120 *| off | off | off | 20 | 20 | off | off | | | R1 | off | 75 | 120 *| off | off | off | 20 | 20 | off | off |
| |------------+-------+-------+-------+------+-------+------+-------+------+-------+------+ | |------------+-------+-------+-------+------+-------+------+-------+------+-------+------+
| | R2 | off | 75 | off | 20 | 120 | off | 20 | 20 | off | off | | | R2 | off | 75 | off | 20 | 120 | off | 20 | 20 | off | off |
| Quad Rank |------------+-------+-------+-------+------+-------+------+-------+------+-------+------+ | Quad Rank |------------+-------+-------+-------+------+-------+------+-------+------+-------+------+
| | R3 | off | 75 | 20 | 20 | off | off | 120 *| off | off | off | | | R3 | off | 75 | 20 | 20 | off | off | 120 *| off | off | off |
| |------------+-------+-------+-------+------+-------+------+-------+------+-------+------+ | |------------+-------+-------+-------+------+-------+------+-------+------+-------+------+
| | R4 | off | 75 | 20 | 20 | off | off | off | 20 | 120 | off | | | R4 | off | 75 | 20 | 20 | off | off | off | 20 | 120 | off |
+-------------+------------+-------+-------+-------+------+-------+------+-------+------+-------+------+ +-------------+------------+-------+-------+-------+------+-------+------+-------+------+-------+------+
| | R1 | off | 75 | 40 | off | off | off | | | R1 | off | 75 | 40 | off | off | off |
| Dual Rank |------------+-------+-------+-------+------+-------+------+ | Dual Rank |------------+-------+-------+-------+------+-------+------+
| | R2 | off | 75 | 40 | off | off | off | | | R2 | off | 75 | 40 | off | off | off |
+-------------+------------+-------+-------+-------+------+-------+------+ +-------------+------------+-------+-------+-------+------+-------+------+
| Single Rank | R1 | off | 75 | 40 | off | | Single Rank | R1 | off | 75 | 40 | off |
+-------------+------------+-------+-------+-------+------+ +-------------+------------+-------+-------+-------+------+
Reference http://www.xrosstalkmag.com/mag_issues/xrosstalk_oct08_final.pdf Reference http://www.xrosstalkmag.com/mag_issues/xrosstalk_oct08_final.pdf
http://download.micron.com/pdf/technotes/ddr3/tn4108_ddr3_design_guide.pdf http://download.micron.com/pdf/technotes/ddr3/tn4108_ddr3_design_guide.pdf

1
drivers/mmc/davinci_mmc.c
View File

@ -401,4 +401,3 @@ int davinci_mmc_init(bd_t *bis, struct davinci_mmc *host)
return 0; return 0;
} }

38
drivers/mtd/nand/nand_base.c
View File

@ -95,8 +95,8 @@ static struct nand_ecclayout nand_oob_64 = {
static struct nand_ecclayout nand_oob_128 = { static struct nand_ecclayout nand_oob_128 = {
.eccbytes = 48, .eccbytes = 48,
.eccpos = { .eccpos = {
80, 81, 82, 83, 84, 85, 86, 87, 80, 81, 82, 83, 84, 85, 86, 87,
88, 89, 90, 91, 92, 93, 94, 95, 88, 89, 90, 91, 92, 93, 94, 95,
96, 97, 98, 99, 100, 101, 102, 103, 96, 97, 98, 99, 100, 101, 102, 103,
104, 105, 106, 107, 108, 109, 110, 111, 104, 105, 106, 107, 108, 109, 110, 111,
112, 113, 114, 115, 116, 117, 118, 119, 112, 113, 114, 115, 116, 117, 118, 119,
@ -1257,7 +1257,7 @@ static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
if (mtd->ecc_stats.failed - stats.failed) if (mtd->ecc_stats.failed - stats.failed)
return -EBADMSG; return -EBADMSG;
return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0; return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
} }
/** /**
@ -1455,7 +1455,7 @@ static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
uint8_t *buf = ops->oobbuf; uint8_t *buf = ops->oobbuf;
MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_read_oob: from = 0x%08Lx, len = %i\n", MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_read_oob: from = 0x%08Lx, len = %i\n",
(unsigned long long)from, readlen); (unsigned long long)from, readlen);
if (ops->mode == MTD_OOB_AUTO) if (ops->mode == MTD_OOB_AUTO)
len = chip->ecc.layout->oobavail; len = chip->ecc.layout->oobavail;
@ -1464,7 +1464,7 @@ static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
if (unlikely(ops->ooboffs >= len)) { if (unlikely(ops->ooboffs >= len)) {
MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: " MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
"Attempt to start read outside oob\n"); "Attempt to start read outside oob\n");
return -EINVAL; return -EINVAL;
} }
@ -1473,7 +1473,7 @@ static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) - ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
(from >> chip->page_shift)) * len)) { (from >> chip->page_shift)) * len)) {
MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: " MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
"Attempt read beyond end of device\n"); "Attempt read beyond end of device\n");
return -EINVAL; return -EINVAL;
} }
@ -1548,7 +1548,7 @@ static int nand_read_oob(struct mtd_info *mtd, loff_t from,
/* Do not allow reads past end of device */ /* Do not allow reads past end of device */
if (ops->datbuf && (from + ops->len) > mtd->size) { if (ops->datbuf && (from + ops->len) > mtd->size) {
MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: " MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
"Attempt read beyond end of device\n"); "Attempt read beyond end of device\n");
return -EINVAL; return -EINVAL;
} }
@ -1981,7 +1981,7 @@ static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
struct nand_chip *chip = mtd->priv; struct nand_chip *chip = mtd->priv;
MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_write_oob: to = 0x%08x, len = %i\n", MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_write_oob: to = 0x%08x, len = %i\n",
(unsigned int)to, (int)ops->ooblen); (unsigned int)to, (int)ops->ooblen);
if (ops->mode == MTD_OOB_AUTO) if (ops->mode == MTD_OOB_AUTO)
len = chip->ecc.layout->oobavail; len = chip->ecc.layout->oobavail;
@ -1991,13 +1991,13 @@ static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
/* Do not allow write past end of page */ /* Do not allow write past end of page */
if ((ops->ooboffs + ops->ooblen) > len) { if ((ops->ooboffs + ops->ooblen) > len) {
MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_write_oob: " MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_write_oob: "
"Attempt to write past end of page\n"); "Attempt to write past end of page\n");
return -EINVAL; return -EINVAL;
} }
if (unlikely(ops->ooboffs >= len)) { if (unlikely(ops->ooboffs >= len)) {
MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: " MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
"Attempt to start write outside oob\n"); "Attempt to start write outside oob\n");
return -EINVAL; return -EINVAL;
} }
@ -2007,7 +2007,7 @@ static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
((mtd->size >> chip->page_shift) - ((mtd->size >> chip->page_shift) -
(to >> chip->page_shift)) * len)) { (to >> chip->page_shift)) * len)) {
MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: " MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
"Attempt write beyond end of device\n"); "Attempt write beyond end of device\n");
return -EINVAL; return -EINVAL;
} }
@ -2063,7 +2063,7 @@ static int nand_write_oob(struct mtd_info *mtd, loff_t to,
/* Do not allow writes past end of device */ /* Do not allow writes past end of device */
if (ops->datbuf && (to + ops->len) > mtd->size) { if (ops->datbuf && (to + ops->len) > mtd->size) {
MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: " MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
"Attempt read beyond end of device\n"); "Attempt read beyond end of device\n");
return -EINVAL; return -EINVAL;
} }
@ -2166,14 +2166,14 @@ int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
/* Length must align on block boundary */ /* Length must align on block boundary */
if (instr->len & ((1 << chip->phys_erase_shift) - 1)) { if (instr->len & ((1 << chip->phys_erase_shift) - 1)) {
MTDDEBUG (MTD_DEBUG_LEVEL0, MTDDEBUG (MTD_DEBUG_LEVEL0,
"nand_erase: Length not block aligned\n"); "nand_erase: Length not block aligned\n");
return -EINVAL; return -EINVAL;
} }
/* Do not allow erase past end of device */ /* Do not allow erase past end of device */
if ((instr->len + instr->addr) > mtd->size) { if ((instr->len + instr->addr) > mtd->size) {
MTDDEBUG (MTD_DEBUG_LEVEL0, MTDDEBUG (MTD_DEBUG_LEVEL0,
"nand_erase: Erase past end of device\n"); "nand_erase: Erase past end of device\n");
return -EINVAL; return -EINVAL;
} }
@ -2195,7 +2195,7 @@ int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
/* Check, if it is write protected */ /* Check, if it is write protected */
if (nand_check_wp(mtd)) { if (nand_check_wp(mtd)) {
MTDDEBUG (MTD_DEBUG_LEVEL0, MTDDEBUG (MTD_DEBUG_LEVEL0,
"nand_erase: Device is write protected!!!\n"); "nand_erase: Device is write protected!!!\n");
instr->state = MTD_ERASE_FAILED; instr->state = MTD_ERASE_FAILED;
goto erase_exit; goto erase_exit;
} }
@ -2249,7 +2249,7 @@ int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
/* See if block erase succeeded */ /* See if block erase succeeded */
if (status & NAND_STATUS_FAIL) { if (status & NAND_STATUS_FAIL) {
MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_erase: " MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_erase: "
"Failed erase, page 0x%08x\n", page); "Failed erase, page 0x%08x\n", page);
instr->state = MTD_ERASE_FAILED; instr->state = MTD_ERASE_FAILED;
instr->fail_addr = ((loff_t)page << chip->page_shift); instr->fail_addr = ((loff_t)page << chip->page_shift);
goto erase_exit; goto erase_exit;
@ -2461,7 +2461,7 @@ static const struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
for (; type->name != NULL; type++) for (; type->name != NULL; type++)
if (dev_id == type->id) if (dev_id == type->id)
break; break;
if (!type->name) { if (!type->name) {
/* supress warning if there is no nand */ /* supress warning if there is no nand */
@ -2569,8 +2569,8 @@ static const struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
chip->cmdfunc = nand_command_lp; chip->cmdfunc = nand_command_lp;
MTDDEBUG (MTD_DEBUG_LEVEL0, "NAND device: Manufacturer ID:" MTDDEBUG (MTD_DEBUG_LEVEL0, "NAND device: Manufacturer ID:"
" 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, dev_id, " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, dev_id,
nand_manuf_ids[maf_idx].name, type->name); nand_manuf_ids[maf_idx].name, type->name);
return type; return type;
} }

2
drivers/pci/fsl_pci_init.c
View File

@ -514,7 +514,7 @@ void fsl_pci_config_unlock(struct pci_controller *hose)
} }
#if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || \ #if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || \
defined(CONFIG_PCIE3) || defined(CONFIG_PCIE4) defined(CONFIG_PCIE3) || defined(CONFIG_PCIE4)
int fsl_configure_pcie(struct fsl_pci_info *info, int fsl_configure_pcie(struct fsl_pci_info *info,
struct pci_controller *hose, struct pci_controller *hose,
const char *connected, int busno) const char *connected, int busno)

2
include/configs/shmin.h
View File

@ -45,7 +45,7 @@
#define CONFIG_BAUDRATE 115200 #define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTARGS "console=ttySC0,115200" #define CONFIG_BOOTARGS "console=ttySC0,115200"
/* /*
* This board has original boot loader. If you write u-boot to 0x0, * This board has original boot loader. If you write u-boot to 0x0,
* you should set undef. * you should set undef.
*/ */