ppc4xx: Add NAND booting support for AMCC Bamboo (440EP) eval board
This patch adds NAND booting support for the AMCC Bamboo eval board. Since the NAND-SPL boot image is limited to 4kbytes, this version only supports the onboard 64MBytes of DDR. The DIMM modules can't be supported, since the setup code for I2C DIMM autodetection and configuration is too big for this NAND bootloader. Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Roese
parent
42be56f53c
commit
cf959c7d66
30
MAKEALL
30
MAKEALL
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@ -76,21 +76,21 @@ LIST_8xx=" \
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LIST_4xx=" \
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acadia ADCIOP alpr AP1000 \
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AR405 ASH405 bamboo bubinga \
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CANBT CMS700 CPCI2DP CPCI405 \
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CPCI4052 CPCI405AB CPCI405DT CPCI440 \
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CPCIISER4 CRAYL1 csb272 csb472 \
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DASA_SIM DP405 DU405 ebony \
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ERIC EXBITGEN G2000 HH405 \
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HUB405 JSE KAREF katmai \
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luan METROBOX MIP405 MIP405T \
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ML2 ml300 ocotea OCRTC \
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ORSG p3p440 PCI405 pcs440ep \
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PIP405 PLU405 PMC405 PPChameleonEVB \
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sbc405 sc3 sequoia sequoia_nand \
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taishan VOH405 VOM405 W7OLMC \
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W7OLMG walnut WUH405 XPEDITE1K \
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yellowstone yosemite yucca \
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AR405 ASH405 bamboo bamboo_nand \
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bubinga CANBT CMS700 CPCI2DP \
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CPCI405 CPCI4052 CPCI405AB CPCI405DT \
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CPCI440 CPCIISER4 CRAYL1 csb272 \
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csb472 DASA_SIM DP405 DU405 \
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ebony ERIC EXBITGEN G2000 \
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HH405 HUB405 JSE KAREF \
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katmai luan METROBOX MIP405 \
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MIP405T ML2 ml300 ocotea \
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OCRTC ORSG p3p440 PCI405 \
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pcs440ep PIP405 PLU405 PMC405 \
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PPChameleonEVB sbc405 sc3 sequoia \
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sequoia_nand taishan VOH405 VOM405 \
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W7OLMC W7OLMG walnut WUH405 \
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XPEDITE1K yellowstone yosemite yucca \
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"
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#########################################################################
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10
Makefile
10
Makefile
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@ -1035,6 +1035,16 @@ ASH405_config: unconfig
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bamboo_config: unconfig
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@$(MKCONFIG) $(@:_config=) ppc ppc4xx bamboo amcc
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bamboo_nand_config: unconfig
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@mkdir -p $(obj)include
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@mkdir -p $(obj)nand_spl
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@mkdir -p $(obj)board/amcc/bamboo
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@echo "#define CONFIG_NAND_U_BOOT" > $(obj)include/config.h
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@echo "Compile NAND boot image for bamboo"
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@$(MKCONFIG) -a bamboo ppc ppc4xx bamboo amcc
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@echo "TEXT_BASE = 0x01000000" > $(obj)board/amcc/bamboo/config.tmp
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@echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
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bubinga_config: unconfig
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@$(MKCONFIG) $(@:_config=) ppc ppc4xx bubinga amcc
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@ -110,6 +110,13 @@
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# endif
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#endif /* CFG_INIT_DCACHE_CS */
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#define function_prolog(func_name) .text; \
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.align 2; \
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.globl func_name; \
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func_name:
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#define function_epilog(func_name) .type func_name,@function; \
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.size func_name,.-func_name
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/* We don't want the MMU yet.
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*/
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#undef MSR_KERNEL
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@ -388,8 +395,9 @@ rsttlb: tlbwe r0,r1,0x0000 /* Invalidate all entries (V=0)*/
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2:
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#if defined(CONFIG_NAND_SPL)
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#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
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/*
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* Enable internal SRAM
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* Enable internal SRAM (only on 440EPx/GRx, 440EP/GR have no OCM)
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*/
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lis r2,0x7fff
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ori r2,r2,0xffff
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@ -399,6 +407,45 @@ rsttlb: tlbwe r0,r1,0x0000 /* Invalidate all entries (V=0)*/
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mfdcr r1,isram0_pmeg
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and r1,r1,r2 /* Disable pwr mgmt */
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mtdcr isram0_pmeg,r1
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#endif
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#if defined(CONFIG_440EP)
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/*
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* On 440EP with no internal SRAM, we setup SDRAM very early
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* and copy the NAND_SPL to SDRAM and jump to it
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*/
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/* Clear Dcache to use as RAM */
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addis r3,r0,CFG_INIT_RAM_ADDR@h
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ori r3,r3,CFG_INIT_RAM_ADDR@l
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addis r4,r0,CFG_INIT_RAM_END@h
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ori r4,r4,CFG_INIT_RAM_END@l
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rlwinm. r5,r4,0,27,31
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rlwinm r5,r4,27,5,31
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beq ..d_ran3
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addi r5,r5,0x0001
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..d_ran3:
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mtctr r5
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..d_ag3:
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dcbz r0,r3
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addi r3,r3,32
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bdnz ..d_ag3
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/*----------------------------------------------------------------*/
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/* Setup the stack in internal SRAM */
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/*----------------------------------------------------------------*/
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lis r1,CFG_INIT_RAM_ADDR@h
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ori r1,r1,CFG_INIT_SP_OFFSET@l
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li r0,0
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stwu r0,-4(r1)
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stwu r0,-4(r1) /* Terminate call chain */
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stwu r1,-8(r1) /* Save back chain and move SP */
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lis r0,RESET_VECTOR@h /* Address of reset vector */
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ori r0,r0, RESET_VECTOR@l
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stwu r1,-8(r1) /* Save back chain and move SP */
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stw r0,+12(r1) /* Save return addr (underflow vect) */
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sync
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bl early_sdram_init
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sync
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#endif /* CONFIG_440EP */
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/*
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* Copy SPL from cache into internal SRAM
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@ -429,7 +476,7 @@ spl_loop:
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start_ram:
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sync
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isync
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#endif
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#endif /* CONFIG_NAND_SPL */
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bl 3f
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b _start
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@ -1137,7 +1184,6 @@ crit_return:
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lwz r1,GPR1(r1)
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SYNC
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rfci
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#endif /* CONFIG_NAND_SPL */
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/* Cache functions.
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*/
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@ -1254,24 +1300,6 @@ wr_tcr:
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mtspr tcr, r3
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blr
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/*------------------------------------------------------------------------------- */
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/* Function: in8 */
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/* Description: Input 8 bits */
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/*------------------------------------------------------------------------------- */
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.globl in8
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in8:
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lbz r3,0x0000(r3)
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blr
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/*------------------------------------------------------------------------------- */
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/* Function: out8 */
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/* Description: Output 8 bits */
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/*------------------------------------------------------------------------------- */
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.globl out8
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out8:
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stb r4,0x0000(r3)
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blr
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/*------------------------------------------------------------------------------- */
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/* Function: out16 */
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/* Description: Output 16 bits */
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@ -1290,15 +1318,6 @@ out16r:
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sthbrx r4,r0,r3
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blr
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/*------------------------------------------------------------------------------- */
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/* Function: out32 */
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/* Description: Output 32 bits */
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/*------------------------------------------------------------------------------- */
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.globl out32
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out32:
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stw r4,0x0000(r3)
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blr
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/*------------------------------------------------------------------------------- */
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/* Function: out32r */
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/* Description: Byte reverse and output 32 bits */
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@ -1326,15 +1345,6 @@ in16r:
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lhbrx r3,r0,r3
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blr
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/*------------------------------------------------------------------------------- */
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/* Function: in32 */
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/* Description: Input 32 bits */
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/*------------------------------------------------------------------------------- */
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.globl in32
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in32:
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lwz 3,0x0000(3)
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blr
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/*------------------------------------------------------------------------------- */
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/* Function: in32r */
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/* Description: Input 32 bits and byte reverse */
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@ -1377,9 +1387,6 @@ ppcSync:
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sync
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blr
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/*------------------------------------------------------------------------------*/
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#ifndef CONFIG_NAND_SPL
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/*
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* void relocate_code (addr_sp, gd, addr_moni)
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*
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@ -1644,8 +1651,88 @@ trap_reloc:
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stw r0, 4(r7)
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blr
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#if defined(CONFIG_440)
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/*----------------------------------------------------------------------------+
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| dcbz_area.
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+----------------------------------------------------------------------------*/
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function_prolog(dcbz_area)
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rlwinm. r5,r4,0,27,31
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rlwinm r5,r4,27,5,31
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beq ..d_ra2
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addi r5,r5,0x0001
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..d_ra2:mtctr r5
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..d_ag2:dcbz r0,r3
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addi r3,r3,32
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bdnz ..d_ag2
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sync
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blr
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function_epilog(dcbz_area)
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/*----------------------------------------------------------------------------+
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| dflush. Assume 32K at vector address is cachable.
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+----------------------------------------------------------------------------*/
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function_prolog(dflush)
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mfmsr r9
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rlwinm r8,r9,0,15,13
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rlwinm r8,r8,0,17,15
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mtmsr r8
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addi r3,r0,0x0000
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mtspr dvlim,r3
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mfspr r3,ivpr
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addi r4,r0,1024
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mtctr r4
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..dflush_loop:
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lwz r6,0x0(r3)
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addi r3,r3,32
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bdnz ..dflush_loop
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addi r3,r3,-32
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mtctr r4
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..ag: dcbf r0,r3
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addi r3,r3,-32
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bdnz ..ag
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sync
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mtmsr r9
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blr
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function_epilog(dflush)
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#endif /* CONFIG_440 */
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#endif /* CONFIG_NAND_SPL */
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/*------------------------------------------------------------------------------- */
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/* Function: in8 */
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/* Description: Input 8 bits */
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/*------------------------------------------------------------------------------- */
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.globl in8
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in8:
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lbz r3,0x0000(r3)
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blr
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/*------------------------------------------------------------------------------- */
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/* Function: out8 */
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/* Description: Output 8 bits */
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/*------------------------------------------------------------------------------- */
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.globl out8
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out8:
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stb r4,0x0000(r3)
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blr
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/*------------------------------------------------------------------------------- */
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/* Function: out32 */
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/* Description: Output 32 bits */
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/*------------------------------------------------------------------------------- */
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.globl out32
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out32:
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stw r4,0x0000(r3)
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blr
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/*------------------------------------------------------------------------------- */
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/* Function: in32 */
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/* Description: Input 32 bits */
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/*------------------------------------------------------------------------------- */
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.globl in32
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in32:
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lwz 3,0x0000(3)
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blr
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/**************************************************************************/
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/* PPC405EP specific stuff */
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@ -1892,13 +1979,6 @@ pll_wait:
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#endif /* CONFIG_405EP */
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#if defined(CONFIG_440)
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#define function_prolog(func_name) .text; \
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.align 2; \
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.globl func_name; \
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func_name:
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#define function_epilog(func_name) .type func_name,@function; \
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.size func_name,.-func_name
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/*----------------------------------------------------------------------------+
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| mttlb3.
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+----------------------------------------------------------------------------*/
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@ -1946,47 +2026,4 @@ pll_wait:
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TLBRE(3,3,0)
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blr
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function_epilog(mftlb1)
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/*----------------------------------------------------------------------------+
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| dcbz_area.
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+----------------------------------------------------------------------------*/
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function_prolog(dcbz_area)
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rlwinm. r5,r4,0,27,31
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rlwinm r5,r4,27,5,31
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beq ..d_ra2
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addi r5,r5,0x0001
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..d_ra2:mtctr r5
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..d_ag2:dcbz r0,r3
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addi r3,r3,32
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bdnz ..d_ag2
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sync
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blr
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function_epilog(dcbz_area)
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/*----------------------------------------------------------------------------+
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| dflush. Assume 32K at vector address is cachable.
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+----------------------------------------------------------------------------*/
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function_prolog(dflush)
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mfmsr r9
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rlwinm r8,r9,0,15,13
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rlwinm r8,r8,0,17,15
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mtmsr r8
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addi r3,r0,0x0000
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mtspr dvlim,r3
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mfspr r3,ivpr
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addi r4,r0,1024
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mtctr r4
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..dflush_loop:
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lwz r6,0x0(r3)
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addi r3,r3,32
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bdnz ..dflush_loop
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addi r3,r3,-32
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mtctr r4
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..ag: dcbf r0,r3
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addi r3,r3,-32
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bdnz ..ag
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sync
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mtmsr r9
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blr
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function_epilog(dflush)
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#endif /* CONFIG_440 */
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@ -50,7 +50,7 @@
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*----------------------------------------------------------------------*/
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#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
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#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
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#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN)
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#define CFG_MONITOR_BASE TEXT_BASE
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#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
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#define CFG_FLASH_BASE 0xfff00000 /* start of FLASH */
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#define CFG_PCI_MEMBASE 0xa0000000 /* mapped pci memory*/
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@ -104,14 +104,11 @@
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/*-----------------------------------------------------------------------
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* Environment
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*----------------------------------------------------------------------*/
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/*
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* Define here the location of the environment variables (FLASH or EEPROM).
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* Note: DENX encourages to use redundant environment in FLASH.
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*/
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#if 1
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#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
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#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
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#else
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#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
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#define CFG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */
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#define CFG_ENV_IS_EMBEDDED 1 /* use embedded environment */
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#endif
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/*-----------------------------------------------------------------------
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@ -133,7 +130,7 @@
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#ifdef CFG_ENV_IS_IN_FLASH
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#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
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#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
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#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
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#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
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/* Address and size of Redundant Environment Sector */
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@ -141,22 +138,89 @@
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#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
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#endif /* CFG_ENV_IS_IN_FLASH */
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/*
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* IPL (Initial Program Loader, integrated inside CPU)
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* Will load first 4k from NAND (SPL) into cache and execute it from there.
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*
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* SPL (Secondary Program Loader)
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* Will load special U-Boot version (NUB) from NAND and execute it. This SPL
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* has to fit into 4kByte. It sets up the CPU and configures the SDRAM
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* controller and the NAND controller so that the special U-Boot image can be
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* loaded from NAND to SDRAM.
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*
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* NUB (NAND U-Boot)
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* This NAND U-Boot (NUB) is a special U-Boot version which can be started
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* from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
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*
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* On 440EPx the SPL is copied to SDRAM before the NAND controller is
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* set up. While still running from cache, I experienced problems accessing
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* the NAND controller. sr - 2006-08-25
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*/
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#define CFG_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */
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#define CFG_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */
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#define CFG_NAND_BOOT_SPL_DST 0x00800000 /* Copy SPL here */
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#define CFG_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */
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#define CFG_NAND_U_BOOT_START CFG_NAND_U_BOOT_DST /* Start NUB from this addr */
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#define CFG_NAND_BOOT_SPL_DELTA (CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)
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/*
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* Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
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*/
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#define CFG_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */
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#define CFG_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */
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/*
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* Now the NAND chip has to be defined (no autodetection used!)
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*/
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#define CFG_NAND_PAGE_SIZE 512 /* NAND chip page size */
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#define CFG_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */
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#define CFG_NAND_PAGE_COUNT 32 /* NAND chip page count */
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#define CFG_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */
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#define CFG_NAND_4_ADDR_CYCLE 1 /* Fourth addr used (>32MB) */
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#define CFG_NAND_ECCSIZE 256
|
||||
#define CFG_NAND_ECCBYTES 3
|
||||
#define CFG_NAND_ECCSTEPS (CFG_NAND_PAGE_SIZE / CFG_NAND_ECCSIZE)
|
||||
#define CFG_NAND_OOBSIZE 16
|
||||
#define CFG_NAND_ECCTOTAL (CFG_NAND_ECCBYTES * CFG_NAND_ECCSTEPS)
|
||||
#define CFG_NAND_ECCPOS {0, 1, 2, 3, 6, 7}
|
||||
|
||||
#ifdef CFG_ENV_IS_IN_NAND
|
||||
/*
|
||||
* For NAND booting the environment is embedded in the U-Boot image. Please take
|
||||
* look at the file board/amcc/sequoia/u-boot-nand.lds for details.
|
||||
*/
|
||||
#define CFG_ENV_SIZE CFG_NAND_BLOCK_SIZE
|
||||
#define CFG_ENV_OFFSET (CFG_NAND_U_BOOT_OFFS + CFG_ENV_SIZE)
|
||||
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET + CFG_ENV_SIZE)
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* NAND FLASH
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CFG_MAX_NAND_DEVICE 1
|
||||
#define NAND_MAX_CHIPS 1
|
||||
#define CFG_NAND_CS 1
|
||||
#define CFG_MAX_NAND_DEVICE 2
|
||||
#define NAND_MAX_CHIPS CFG_MAX_NAND_DEVICE
|
||||
#define CFG_NAND_BASE (CFG_NAND_ADDR + CFG_NAND_CS)
|
||||
#define CFG_NAND_BASE_LIST { CFG_NAND_BASE, CFG_NAND_ADDR + 2 }
|
||||
#define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
|
||||
|
||||
#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
|
||||
#define CFG_NAND_CS 1
|
||||
#else
|
||||
#define CFG_NAND_CS 0 /* NAND chip connected to CSx */
|
||||
/* Memory Bank 0 (NAND-FLASH) initialization */
|
||||
#define CFG_EBC_PB0AP 0x018003c0
|
||||
#define CFG_EBC_PB0CR (CFG_NAND_ADDR | 0x1c000)
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* DDR SDRAM
|
||||
*----------------------------------------------------------------------------- */
|
||||
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
|
||||
#undef CONFIG_DDR_ECC /* don't use ECC */
|
||||
#define CFG_SIMULATE_SPD_EEPROM 0xff /* simulate spd eeprom on this address */
|
||||
#define SPD_EEPROM_ADDRESS {CFG_SIMULATE_SPD_EEPROM, 0x50, 0x51}
|
||||
#define SPD_EEPROM_ADDRESS {CFG_SIMULATE_SPD_EEPROM, 0x50, 0x51}
|
||||
#define CFG_MBYTES_SDRAM (64) /* 64MB fixed size for early-sdram-init */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* I2C
|
||||
|
|
|
|||
|
|
@ -0,0 +1,100 @@
|
|||
#
|
||||
# (C) Copyright 2007
|
||||
# Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk
|
||||
|
||||
LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
|
||||
LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS)
|
||||
AFLAGS += -DCONFIG_NAND_SPL
|
||||
CFLAGS += -DCONFIG_NAND_SPL
|
||||
|
||||
SOBJS = start.o init.o resetvec.o
|
||||
COBJS = nand_boot.o nand_ecc.o ndfc.o sdram.o
|
||||
|
||||
SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
|
||||
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
|
||||
__OBJS := $(SOBJS) $(COBJS)
|
||||
LNDIR := $(OBJTREE)/nand_spl/board/$(BOARDDIR)
|
||||
|
||||
nandobj := $(OBJTREE)/nand_spl/
|
||||
|
||||
ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
|
||||
|
||||
all: $(obj).depend $(ALL)
|
||||
|
||||
$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
|
||||
$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
|
||||
|
||||
$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
|
||||
$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
|
||||
|
||||
$(nandobj)u-boot-spl: $(OBJS)
|
||||
cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \
|
||||
-Map $(nandobj)u-boot-spl.map \
|
||||
-o $(nandobj)u-boot-spl
|
||||
|
||||
# create symbolic links for common files
|
||||
|
||||
# from cpu directory
|
||||
$(obj)ndfc.c:
|
||||
@rm -f $(obj)ndfc.c
|
||||
ln -s $(SRCTREE)/cpu/ppc4xx/ndfc.c $(obj)ndfc.c
|
||||
|
||||
$(obj)resetvec.S:
|
||||
@rm -f $(obj)resetvec.S
|
||||
ln -s $(SRCTREE)/cpu/ppc4xx/resetvec.S $(obj)resetvec.S
|
||||
|
||||
$(obj)start.S:
|
||||
@rm -f $(obj)start.S
|
||||
ln -s $(SRCTREE)/cpu/ppc4xx/start.S $(obj)start.S
|
||||
|
||||
# from board directory
|
||||
$(obj)init.S:
|
||||
@rm -f $(obj)init.S
|
||||
ln -s $(SRCTREE)/board/amcc/bamboo/init.S $(obj)init.S
|
||||
|
||||
# from nand_spl directory
|
||||
$(obj)nand_boot.c:
|
||||
@rm -f $(obj)nand_boot.c
|
||||
ln -s $(SRCTREE)/nand_spl/nand_boot.c $(obj)nand_boot.c
|
||||
|
||||
# from drivers/nand directory
|
||||
$(obj)nand_ecc.c:
|
||||
@rm -f $(obj)nand_ecc.c
|
||||
ln -s $(SRCTREE)/drivers/nand/nand_ecc.c $(obj)nand_ecc.c
|
||||
|
||||
#########################################################################
|
||||
|
||||
$(obj)%.o: $(obj)%.S
|
||||
$(CC) $(AFLAGS) -c -o $@ $<
|
||||
|
||||
$(obj)%.o: $(obj)%.c
|
||||
$(CC) $(CFLAGS) -c -o $@ $<
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
|
|
@ -0,0 +1,49 @@
|
|||
#
|
||||
# (C) Copyright 2007
|
||||
# Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
#
|
||||
# AMCC 440EP Reference Platform (Bamboo) board
|
||||
#
|
||||
|
||||
#
|
||||
# TEXT_BASE for SPL:
|
||||
#
|
||||
# On 440EP(x) platforms the SPL is located at 0xfffff000...0xffffffff,
|
||||
# in the last 4kBytes of memory space in cache.
|
||||
# We will copy this SPL into instruction-cache in start.S. So we set
|
||||
# TEXT_BASE to starting address in i-cache here.
|
||||
#
|
||||
TEXT_BASE = 0x00800000
|
||||
|
||||
# PAD_TO used to generate a 16kByte binary needed for the combined image
|
||||
# -> PAD_TO = TEXT_BASE + 0x4000
|
||||
PAD_TO = 0x00804000
|
||||
|
||||
PLATFORM_CPPFLAGS += -DCONFIG_440=1
|
||||
|
||||
ifeq ($(debug),1)
|
||||
PLATFORM_CPPFLAGS += -DDEBUG
|
||||
endif
|
||||
|
||||
ifeq ($(dbcr),1)
|
||||
PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
|
||||
endif
|
||||
|
|
@ -0,0 +1,92 @@
|
|||
/*
|
||||
* (C) Copyright 2007
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <ppc4xx.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
static void wait_init_complete(void)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
do {
|
||||
mfsdram(mem_mcsts, val);
|
||||
} while (!(val & 0x80000000));
|
||||
}
|
||||
|
||||
/*
|
||||
* early_sdram_init()
|
||||
*
|
||||
* As the name already indicates, this function is called very early
|
||||
* from start.S and configures the SDRAM with fixed values. This is needed,
|
||||
* since the 440EP has no internal SRAM and the 4kB NAND_SPL loader has
|
||||
* not enough free space to implement the complete I2C SPD DDR autodetection
|
||||
* routines. Therefore the Bamboo only supports the onboard 64MBytes of SDRAM
|
||||
* when booting from NAND flash.
|
||||
*/
|
||||
void early_sdram_init(void)
|
||||
{
|
||||
/*
|
||||
* Soft-reset SDRAM controller.
|
||||
*/
|
||||
mtsdr(sdr_srst, SDR0_SRST_DMC);
|
||||
mtsdr(sdr_srst, 0x00000000);
|
||||
|
||||
/*
|
||||
* Disable memory controller.
|
||||
*/
|
||||
mtsdram(mem_cfg0, 0x00000000);
|
||||
|
||||
/*
|
||||
* Setup some default
|
||||
*/
|
||||
mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default) */
|
||||
mtsdram(mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
|
||||
mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
|
||||
mtsdram(mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */
|
||||
mtsdram(mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
|
||||
|
||||
/*
|
||||
* Following for CAS Latency = 2.5 @ 133 MHz PLB
|
||||
*/
|
||||
mtsdram(mem_b0cr, 0x00082001);
|
||||
mtsdram(mem_tr0, 0x41094012);
|
||||
mtsdram(mem_tr1, 0x8080083d); /* SS=T2 SL=STAGE 3 CD=1 CT=0x00*/
|
||||
mtsdram(mem_rtr, 0x04100000); /* Interval 7.8µs @ 133MHz PLB */
|
||||
mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM*/
|
||||
|
||||
/*
|
||||
* Enable the controller, then wait for DCEN to complete
|
||||
*/
|
||||
mtsdram(mem_cfg0, 0x80000000); /* DCEN=1, PMUD=0*/
|
||||
wait_init_complete();
|
||||
}
|
||||
|
||||
long int initdram(int board_type)
|
||||
{
|
||||
/*
|
||||
* Nothing to do here, just return size of fixed SDRAM setup
|
||||
*/
|
||||
return CFG_MBYTES_SDRAM << 20;
|
||||
}
|
||||
|
|
@ -0,0 +1,65 @@
|
|||
/*
|
||||
* (C) Copyright 2007
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(powerpc:common)
|
||||
SECTIONS
|
||||
{
|
||||
.resetvec 0x00800FFC :
|
||||
{
|
||||
*(.resetvec)
|
||||
} = 0xffff
|
||||
|
||||
.text :
|
||||
{
|
||||
start.o (.text)
|
||||
init.o (.text)
|
||||
nand_boot.o (.text)
|
||||
sdram.o (.text)
|
||||
ndfc.o (.text)
|
||||
|
||||
*(.text)
|
||||
*(.fixup)
|
||||
}
|
||||
_etext = .;
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.rodata*)
|
||||
*(.data*)
|
||||
*(.sdata*)
|
||||
__got2_start = .;
|
||||
*(.got2)
|
||||
__got2_end = .;
|
||||
}
|
||||
|
||||
_edata = .;
|
||||
|
||||
__bss_start = .;
|
||||
.bss :
|
||||
{
|
||||
*(.sbss)
|
||||
*(.bss)
|
||||
}
|
||||
|
||||
_end = . ;
|
||||
}
|
||||
Loading…
Reference in New Issue