* Patch by Jon Loeliger, 24 Aug 2004:
- Fix PCI window on MPC85xx; remove unneeded PCI initialization
from board_early_init_f()
- Provide SW workaround for PCI initialization on 85xx CDS
- Convert MPC85xxADS to use common CFI flash driver
* Cleanup: avoid compiler warnings
* Add CMC PU2 board to MAKEALL script
This commit is contained in:
wdenk
parent
08b6aa6154
commit
cf33678e51
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@ -2,6 +2,12 @@
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Changes since U-Boot 1.1.1:
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======================================================================
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* Patch by Jon Loeliger, 24 Aug 2004:
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- Fix PCI window on MPC85xx; remove unneeded PCI initialization
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from board_early_init_f()
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- Provide SW workaround for PCI initialization on 85xx CDS
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- Convert MPC85xxADS to use common CFI flash driver
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* Patches by George G. Davis, 24 Aug 2004:
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- Enable ramdisk/initrd tagged param support for omap1610h2_config
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- Remove static network setup defaults from mx1ads_config
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9
MAKEALL
9
MAKEALL
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@ -140,10 +140,11 @@ LIST_ARM7="B2 ep7312 evb4510 impa7 modnet50"
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#########################################################################
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LIST_ARM9=" \
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at91rm9200dk integratorcp integratorap lpd7a400 \
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mx1ads mx1fs2 omap1510inn omap1610h2 \
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omap1610inn omap730p2 scb9328 smdk2400 \
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smdk2410 trab VCMA9 versatile \
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at91rm9200dk cmc_pu2 integratorcp integratorap \
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lpd7a400 mx1ads mx1fs2 omap1510inn \
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omap1610h2 omap1610inn omap730p2 scb9328 \
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smdk2400 smdk2410 trab VCMA9 \
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versatile \
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"
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#########################################################################
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@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
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LIB = lib$(BOARD).a
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OBJS := $(BOARD).o flash.o
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OBJS := $(BOARD).o
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SOBJS := init.o
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#SOBJS :=
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@ -44,13 +44,6 @@ long int fixed_sdram(void);
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int board_early_init_f (void)
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{
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#if defined(CONFIG_PCI)
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volatile immap_t *immr = (immap_t *)CFG_IMMR;
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volatile ccsr_pcix_t *pci = &immr->im_pcix;
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pci->peer &= 0xffffffdf; /* disable master abort */
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#endif
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return 0;
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}
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@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
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LIB = lib$(BOARD).a
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OBJS := $(BOARD).o flash.o
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OBJS := $(BOARD).o
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SOBJS := init.o
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#SOBJS :=
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@ -214,13 +214,6 @@ typedef struct bcsr_ {
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int board_early_init_f (void)
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{
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#if defined(CONFIG_PCI)
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volatile immap_t *immr = (immap_t *)CFG_IMMR;
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volatile ccsr_pcix_t *pci = &immr->im_pcix;
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pci->peer &= 0xffffffdf; /* disable master abort */
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#endif
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return 0;
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}
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@ -121,7 +121,7 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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reset_cpu(0);
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#else
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#ifdef CONFIG_DBGU
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AT91PS_USART us = AT91C_BASE_DBGU;
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AT91PS_USART us = (AT91PS_USART) AT91C_BASE_DBGU;
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#endif
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#ifdef CONFIG_USART0
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AT91PS_USART us = AT91C_BASE_US0;
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@ -77,7 +77,7 @@ pci_mpc85xx_init(struct pci_controller *hose)
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pcix->powbear1 = 0x00000000;
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pcix->powar1 = 0x8004401c; /* 512M MEM space */
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pcix->potar2 = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff;
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pcix->potar2 = 0x00000000;
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pcix->potear2 = 0x00000000;
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pcix->powbar2 = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff;
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pcix->powbear2 = 0x00000000;
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@ -85,12 +85,38 @@ pci_mpc85xx_init(struct pci_controller *hose)
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pcix->pitar1 = 0x00000000;
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pcix->piwbar1 = 0x00000000;
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pcix->piwar1 = 0xa0F5501f;
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pcix->piwar1 = 0xa0f5501e; /* Enable, Prefetch, Local Mem,
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* Snoop R/W, 2G */
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/*
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* Hose scan.
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*/
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pci_register_hose(hose);
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#if defined(CONFIG_MPC8555CDS) || defined(CONFIG_MPC8541CDS)
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/*
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* This is a SW workaround for an apparent HW problem
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* in the PCI controller on the MPC85555/41 CDS boards.
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* The first config cycle must be to a valid, known
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* device on the PCI bus in order to trick the PCI
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* controller state machine into a known valid state.
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* Without this, the first config cycle has the chance
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* of hanging the controller permanently, just leaving
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* it in a semi-working state, or leaving it working.
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*
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* Pick on the Tundra, Device 17, to get it right.
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*/
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{
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u8 header_type;
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pci_hose_read_config_byte(hose,
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PCI_BDF(0,17,0),
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PCI_HEADER_TYPE,
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&header_type);
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}
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#endif
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hose->last_busno = pci_hose_scan(hose);
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}
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@ -137,13 +137,15 @@
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#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
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#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
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#define CFG_RAMBOOT
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#else
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#undef CFG_RAMBOOT
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#endif
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#define CFG_FLASH_CFI_DRIVER
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#define CFG_FLASH_CFI
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#define CFG_FLASH_EMPTY_INFO
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#undef CONFIG_CLOCKS_IN_MHZ
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@ -262,7 +264,7 @@
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
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#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 256 kB for Mon */
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#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
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/* Serial Port */
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@ -140,13 +140,15 @@
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#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
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#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
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#define CFG_RAMBOOT
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#else
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#undef CFG_RAMBOOT
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#endif
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#define CFG_FLASH_CFI_DRIVER
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#define CFG_FLASH_CFI
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#define CFG_FLASH_EMPTY_INFO
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#undef CONFIG_CLOCKS_IN_MHZ
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
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#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 256 kB for Mon */
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#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
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/* Serial Port */
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