MPC85xx: TQM8548: workaround for erratum DDR 19 and 20
This patch adds the workaround for erratum DDR20 according to MPC8548 Device Errata document, Rev. 1: "CKE signal may not function correctly after assertion of HRESET". Furthermore, the bug DDR19 is fixed in processor version 2.1 and the work-around must be removed. Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
This commit is contained in:
Wolfgang Grandegger
Andy Fleming
parent
080408fdc7
commit
cf07a5baec
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@ -1,3 +1,4 @@
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/*
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* (C) Copyright 2005
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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@ -78,6 +79,7 @@ long int sdram_setup (int casl)
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volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
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#ifdef CONFIG_TQM8548
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
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#else /* !CONFIG_TQM8548 */
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unsigned long cfg_ddr_timing1;
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unsigned long cfg_ddr_mode;
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@ -147,13 +149,12 @@ long int sdram_setup (int casl)
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ddr->sdram_interval = (1040 << 16) | 0x100;
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/*
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* workaround for erratum DD10 of MPC8458 family below rev. 2.0:
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* DDR IO receiver must be set to an acceptable bias point by modifying
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* a hidden register.
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* Workaround for erratum DDR19 according to MPC8548 Device Errata
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* document, Rev. 1: DDR IO receiver must be set to an acceptable
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* bias point by modifying a hidden register.
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*/
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if (SVR_REV (get_svr ()) < 0x20) {
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if (SVR_REV (get_svr ()) < 0x21)
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gur->ddrioovcr = 0x90000000; /* enable, VSEL 1.8V */
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}
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/* DDR SDRAM CFG 2
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* FRC_SR: normal mode
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@ -181,7 +182,104 @@ long int sdram_setup (int casl)
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/* wait for clock stabilization */
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asm ("sync;isync;msync");
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udelay(1000);
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udelay (1000);
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#if defined(CONFIG_TQM8548_AG) || defined(CONFIG_TQM8548_BE)
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/*
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* Workaround for erratum DDR20 according to MPC8548 Device Errata
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* document, Rev. 1: "CKE signal may not function correctly after
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* assertion of HRESET"
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*/
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/* 1. Configure DDR register as is done in normal DDR configuration.
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* Do not set DDR_SDRAM_CFG[MEM_EN].
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*
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* 2. Set reserved bit EEBACR[3] at offset 0x1000
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*/
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ecm->eebacr |= 0x10000000;
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/*
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* 3. Before DDR_SDRAM_CFG[MEM_EN] is set, write DDR_SDRAM_CFG_2[D_INIT]
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*
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* DDR_SDRAM_CFG_2:
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* FRC_SR: normal mode
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* SR_IE: no self-refresh interrupt
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* DLL_RST_DIS: don't care, leave at reset value
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* DQS_CFG: differential DQS signals
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* ODT_CFG: assert ODT to internal IOs only during reads to DRAM
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* LVWx_CFG: don't care, leave at reset value
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* NUM_PR: 1 refresh will be issued at a time
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* DM_CFG: don't care, leave at reset value
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* D_INIT: enable data initialization
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*/
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ddr->sdram_cfg_2 |= 0x00000010;
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/*
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* 4. Before DDR_SDRAM_CFG[MEM_EN] set, write D3[21] to disable data
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* training
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*/
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ddr->debug_3 |= 0x00000400;
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/*
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* 5. Wait 200 micro-seconds
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*/
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udelay (200);
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/*
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* 6. Set DDR_SDRAM_CFG[MEM_EN]
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*
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* BTW, initialize DDR_SDRAM_CFG:
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* MEM_EN: enabled
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* SREN: don't care, leave at reset value
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* ECC_EN: no error report
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* RD_EN: no registered DIMMs
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* SDRAM_TYPE: DDR2
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* DYN_PWR: no power management
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* 32_BE: don't care, leave at reset value
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* 8_BE: 4 beat burst
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* NCAP: don't care, leave at reset value
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* 2T_EN: 1T Timing
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* BA_INTLV_CTL: no interleaving
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* x32_EN: x16 organization
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* PCHB8: MA[10] for auto-precharge
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* HSE: half strength for single and 2-layer stacks
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* (full strength for 3- and 4-layer stacks not
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* yet considered)
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* MEM_HALT: no halt
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* BI: automatic initialization
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*/
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ddr->sdram_cfg = 0x83000008;
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/*
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* 7. Poll DDR_SDRAM_CFG_2[D_INIT] until it is cleared by hardware
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*/
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asm ("sync;isync;msync");
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while (ddr->sdram_cfg_2 & 0x00000010)
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asm ("eieio");
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/*
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* 8. Clear D3[21] to re-enable data training
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*/
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ddr->debug_3 &= ~0x00000400;
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/*
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* 9. Set D2(21) to force data training to run
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*/
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ddr->debug_2 |= 0x00000400;
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/*
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* 10. Poll on D2[21] until it is cleared by hardware
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*/
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asm ("sync;isync;msync");
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while (ddr->debug_2 & 0x00000400)
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asm ("eieio");
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/*
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* 11. Clear reserved bit EEBACR[3] at offset 0x1000
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*/
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ecm->eebacr &= ~0x10000000;
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#else /* !(CONFIG_TQM8548_AG || CONFIG_TQM8548_BE) */
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/* DDR SDRAM CLK CNTL
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* MEM_EN: enabled
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@ -203,9 +301,11 @@ long int sdram_setup (int casl)
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* BI: automatic initialization
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*/
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ddr->sdram_cfg = 0x83000008;
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asm ("sync; isync; msync");
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udelay(1000);
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#endif /* CONFIG_TQM8548_AG || CONFIG_TQM8548_BE */
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asm ("sync; isync; msync");
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udelay (1000);
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#else /* !CONFIG_TQM8548 */
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switch (casl) {
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case 20:
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