Merge branch 'next' of ../next

This commit is contained in:
Wolfgang Denk 2010-12-22 21:16:17 +01:00
commit cdc51c294a
232 changed files with 4745 additions and 2032 deletions

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@ -415,6 +415,7 @@ Georg Schardt <schardt@team-ctech.de>
Heiko Schocher <hs@denx.de>
charon MPC5200
ids8247 MPC8247
jupiter MPC5200
kmeter1 MPC8360
@ -550,6 +551,7 @@ Rowel Atienza <rowel@diwalabs.com>
Stefano Babic <sbabic@denx.de>
ea20 davinci
polaris xscale
trizepsiv xscale
mx51evk i.MX51
@ -664,10 +666,6 @@ Matthias Kaehlcke <matthias@kaehlcke.net>
Konstantin Kletschke <kletschke@synertronixx.de>
scb9328 ARM920T
Simon Kagstrom <simon.kagstrom@netinsight.net>
openrd_base ARM926EJS (Kirkwood SoC)
Nishant Kamat <nskamat@ti.com>
omap1610h2 ARM926EJS
@ -837,7 +835,9 @@ Matt Waddel <matt.waddel@linaro.org>
Prafulla Wadaskar <prafulla@marvell.com>
aspenite ARM926EJS (ARMADA100 88AP168 SoC)
mv88f6281gtw_ge ARM926EJS (Kirkwood SoC)
openrd_base ARM926EJS (Kirkwood SoC)
rd6281a ARM926EJS (Kirkwood SoC)
sheevaplug ARM926EJS (Kirkwood SoC)
@ -854,6 +854,11 @@ Alex Z
lart SA1100
dnp1110 SA1110
Syed Mohammed Khasim <sm.khasim@gmail.com>
Sughosh Ganu <urwithsughosh@gmail.com>
hawkboard ARM926EJS (OMAP-L138)
-------------------------------------------------------------------------
Unknown / orphaned boards:

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@ -327,6 +327,7 @@ LIST_ARM9=" \
ap926ejs \
ap946es \
ap966 \
aspenite \
cp920t \
cp922_XA10 \
cp926ejs \

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@ -36,9 +36,6 @@
#define DEBUG
#undef DEBUG
/* U-Boot routines needed */
extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
/*****************************************************************************
*
* This is the API core.

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@ -0,0 +1,46 @@
#
# (C) Copyright 2010
# Marvell Semiconductor <www.marvell.com>
# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
# MA 02110-1301 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(SOC).o
COBJS-y = cpu.o timer.o dram.o
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y))
all: $(obj).depend $(LIB)
$(LIB): $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

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@ -0,0 +1,92 @@
/*
* (C) Copyright 2010
* Marvell Semiconductor <www.marvell.com>
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
* Contributor: Mahavir Jain <mjain@marvell.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#include <common.h>
#include <asm/arch/armada100.h>
#include <asm/io.h>
#define UARTCLK14745KHZ (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1))
#define SET_MRVL_ID (1<<8)
#define L2C_RAM_SEL (1<<4)
int arch_cpu_init(void)
{
u32 val;
struct armd1cpu_registers *cpuregs =
(struct armd1cpu_registers *) ARMD1_CPU_BASE;
struct armd1apb1_registers *apb1clkres =
(struct armd1apb1_registers *) ARMD1_APBC1_BASE;
struct armd1mpmu_registers *mpmu =
(struct armd1mpmu_registers *) ARMD1_MPMU_BASE;
/* set SEL_MRVL_ID bit in ARMADA100_CPU_CONF register */
val = readl(&cpuregs->cpu_conf);
val = val | SET_MRVL_ID;
writel(val, &cpuregs->cpu_conf);
/* Enable Clocks for all hardware units */
writel(0xFFFFFFFF, &mpmu->acgr);
/* Turn on AIB and AIB-APB Functional clock */
writel(APBC_APBCLK | APBC_FNCLK, &apb1clkres->aib);
/* ensure L2 cache is not mapped as SRAM */
val = readl(&cpuregs->cpu_conf);
val = val & ~(L2C_RAM_SEL);
writel(val, &cpuregs->cpu_conf);
/* Enable GPIO clock */
writel(APBC_APBCLK, &apb1clkres->gpio);
/*
* Enable Functional and APB clock at 14.7456MHz
* for configured UART console
*/
#if (CONFIG_SYS_NS16550_COM1 == ARMD1_UART3_BASE)
writel(UARTCLK14745KHZ, &apb1clkres->uart3);
#elif (CONFIG_SYS_NS16550_COM1 == ARMD1_UART2_BASE)
writel(UARTCLK14745KHZ, &apb1clkres->uart2);
#else
writel(UARTCLK14745KHZ, &apb1clkres->uart1);
#endif
icache_enable();
return 0;
}
#if defined(CONFIG_DISPLAY_CPUINFO)
int print_cpuinfo(void)
{
u32 id;
struct armd1cpu_registers *cpuregs =
(struct armd1cpu_registers *) ARMD1_CPU_BASE;
id = readl(&cpuregs->chip_id);
printf("SoC: Armada 88AP%X-%X\n", (id & 0xFFF), (id >> 0x10));
return 0;
}
#endif

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@ -0,0 +1,131 @@
/*
* (C) Copyright 2010
* Marvell Semiconductor <www.marvell.com>
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>,
* Contributor: Mahavir Jain <mjain@marvell.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#include <common.h>
#include <asm/arch/armada100.h>
DECLARE_GLOBAL_DATA_PTR;
/*
* ARMADA100 DRAM controller supports upto 8 banks
* for chip select 0 and 1
*/
/*
* DDR Memory Control Registers
* Refer Datasheet Appendix A.17
*/
struct armd1ddr_map_registers {
u32 cs; /* Memory Address Map Register -CS */
u32 pad[3];
};
struct armd1ddr_registers {
u8 pad[0x100 - 0x000];
struct armd1ddr_map_registers mmap[2];
};
/*
* armd1_sdram_base - reads SDRAM Base Address Register
*/
u32 armd1_sdram_base(int chip_sel)
{
struct armd1ddr_registers *ddr_regs =
(struct armd1ddr_registers *)ARMD1_DRAM_BASE;
u32 result = 0;
u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs);
if (!CS_valid)
return 0;
result = readl(&ddr_regs->mmap[chip_sel].cs) & 0xFF800000;
return result;
}
/*
* armd1_sdram_size - reads SDRAM size
*/
u32 armd1_sdram_size(int chip_sel)
{
struct armd1ddr_registers *ddr_regs =
(struct armd1ddr_registers *)ARMD1_DRAM_BASE;
u32 result = 0;
u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs);
if (!CS_valid)
return 0;
result = readl(&ddr_regs->mmap[chip_sel].cs);
result = (result >> 16) & 0xF;
if (result < 0x7) {
printf("Unknown DRAM Size\n");
return -1;
} else {
return ((0x8 << (result - 0x7)) * 1024 * 1024);
}
}
#ifndef CONFIG_SYS_BOARD_DRAM_INIT
int dram_init(void)
{
int i;
gd->ram_size = 0;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
gd->bd->bi_dram[i].start = armd1_sdram_base(i);
gd->bd->bi_dram[i].size = armd1_sdram_size(i);
/*
* It is assumed that all memory banks are consecutive
* and without gaps.
* If the gap is found, ram_size will be reported for
* consecutive memory only
*/
if (gd->bd->bi_dram[i].start != gd->ram_size)
break;
gd->ram_size += gd->bd->bi_dram[i].size;
}
for (; i < CONFIG_NR_DRAM_BANKS; i++) {
/* If above loop terminated prematurely, we need to set
* remaining banks' start address & size as 0. Otherwise other
* u-boot functions and Linux kernel gets wrong values which
* could result in crash */
gd->bd->bi_dram[i].start = 0;
gd->bd->bi_dram[i].size = 0;
}
return 0;
}
/*
* If this function is not defined here,
* board.c alters dram bank zero configuration defined above.
*/
void dram_init_banksize(void)
{
dram_init();
}
#endif /* CONFIG_SYS_BOARD_DRAM_INIT */

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@ -0,0 +1,207 @@
/*
* (C) Copyright 2010
* Marvell Semiconductor <www.marvell.com>
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
* Contributor: Mahavir Jain <mjain@marvell.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#include <common.h>
#include <asm/arch/armada100.h>
/*
* Timer registers
* Refer Section A.6 in Datasheet
*/
struct armd1tmr_registers {
u32 clk_ctrl; /* Timer clk control reg */
u32 match[9]; /* Timer match registers */
u32 count[3]; /* Timer count registers */
u32 status[3];
u32 ie[3];
u32 preload[3]; /* Timer preload value */
u32 preload_ctrl[3];
u32 wdt_match_en;
u32 wdt_match_r;
u32 wdt_val;
u32 wdt_sts;
u32 icr[3];
u32 wdt_icr;
u32 cer; /* Timer count enable reg */
u32 cmr;
u32 ilr[3];
u32 wcr;
u32 wfar;
u32 wsar;
u32 cvwr;
};
#define TIMER 0 /* Use TIMER 0 */
/* Each timer has 3 match registers */
#define MATCH_CMP(x) ((3 * TIMER) + x)
#define TIMER_LOAD_VAL 0xffffffff
#define COUNT_RD_REQ 0x1
DECLARE_GLOBAL_DATA_PTR;
/* Using gd->tbu from timestamp and gd->tbl for lastdec */
/* For preventing risk of instability in reading counter value,
* first set read request to register cvwr and then read same
* register after it captures counter value.
*/
ulong read_timer(void)
{
struct armd1tmr_registers *armd1timers =
(struct armd1tmr_registers *) ARMD1_TIMER_BASE;
volatile int loop=100;
writel(COUNT_RD_REQ, &armd1timers->cvwr);
while (loop--);
return(readl(&armd1timers->cvwr));
}
void reset_timer_masked(void)
{
/* reset time */
gd->tbl = read_timer();
gd->tbu = 0;
}
ulong get_timer_masked(void)
{
ulong now = read_timer();
if (now >= gd->tbl) {
/* normal mode */
gd->tbu += now - gd->tbl;
} else {
/* we have an overflow ... */
gd->tbu += now + TIMER_LOAD_VAL - gd->tbl;
}
gd->tbl = now;
return gd->tbu;
}
void reset_timer(void)
{
reset_timer_masked();
}
ulong get_timer(ulong base)
{
return ((get_timer_masked() / (CONFIG_SYS_HZ_CLOCK / 1000)) -
base);
}
void set_timer(ulong t)
{
gd->tbu = t;
}
void __udelay(unsigned long usec)
{
ulong delayticks;
ulong endtime;
delayticks = (usec * (CONFIG_SYS_HZ_CLOCK / 1000000));
endtime = get_timer_masked() + delayticks;
while (get_timer_masked() < endtime);
}
/*
* init the Timer
*/
int timer_init(void)
{
struct armd1apb1_registers *apb1clkres =
(struct armd1apb1_registers *) ARMD1_APBC1_BASE;
struct armd1tmr_registers *armd1timers =
(struct armd1tmr_registers *) ARMD1_TIMER_BASE;
/* Enable Timer clock at 3.25 MHZ */
writel(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3), &apb1clkres->timers);
/* load value into timer */
writel(0x0, &armd1timers->clk_ctrl);
/* Use Timer 0 Match Resiger 0 */
writel(TIMER_LOAD_VAL, &armd1timers->match[MATCH_CMP(0)]);
/* Preload value is 0 */
writel(0x0, &armd1timers->preload[TIMER]);
/* Enable match comparator 0 for Timer 0 */
writel(0x1, &armd1timers->preload_ctrl[TIMER]);
/* Enable timer 0 */
writel(0x1, &armd1timers->cer);
/* init the gd->tbu and gd->tbl value */
reset_timer_masked();
return 0;
}
#define MPMU_APRR_WDTR (1<<4)
#define TMR_WFAR 0xbaba /* WDT Register First key */
#define TMP_WSAR 0xeb10 /* WDT Register Second key */
/*
* This function uses internal Watchdog Timer
* based reset mechanism.
* Steps to write watchdog registers (protected access)
* 1. Write key value to TMR_WFAR reg.
* 2. Write key value to TMP_WSAR reg.
* 3. Perform write operation.
*/
void reset_cpu (unsigned long ignored)
{
struct armd1mpmu_registers *mpmu =
(struct armd1mpmu_registers *) ARMD1_MPMU_BASE;
struct armd1tmr_registers *armd1timers =
(struct armd1tmr_registers *) ARMD1_TIMER_BASE;
u32 val;
/* negate hardware reset to the WDT after system reset */
val = readl(&mpmu->aprr);
val = val | MPMU_APRR_WDTR;
writel(val, &mpmu->aprr);
/* reset/enable WDT clock */
writel(APBC_APBCLK | APBC_FNCLK | APBC_RST, &mpmu->wdtpcr);
readl(&mpmu->wdtpcr);
writel(APBC_APBCLK | APBC_FNCLK, &mpmu->wdtpcr);
readl(&mpmu->wdtpcr);
/* clear previous WDT status */
writel(TMR_WFAR, &armd1timers->wfar);
writel(TMP_WSAR, &armd1timers->wsar);
writel(0, &armd1timers->wdt_sts);
/* set match counter */
writel(TMR_WFAR, &armd1timers->wfar);
writel(TMP_WSAR, &armd1timers->wsar);
writel(0xf, &armd1timers->wdt_match_r);
/* enable WDT reset */
writel(TMR_WFAR, &armd1timers->wfar);
writel(TMP_WSAR, &armd1timers->wsar);
writel(0x3, &armd1timers->wdt_match_en);
while(1);
}

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@ -0,0 +1,121 @@
/*
* (C) Copyright 2010
* Marvell Semiconductor <www.marvell.com>
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
* Contributor: Mahavir Jain <mjain@marvell.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#ifndef _ASM_ARCH_ARMADA100_H
#define _ASM_ARCH_ARMADA100_H
#ifndef __ASSEMBLY__
#include <asm/types.h>
#include <asm/io.h>
#endif /* __ASSEMBLY__ */
#if defined (CONFIG_ARMADA100)
#include <asm/arch/cpu.h>
/* Common APB clock register bit definitions */
#define APBC_APBCLK (1<<0) /* APB Bus Clock Enable */
#define APBC_FNCLK (1<<1) /* Functional Clock Enable */
#define APBC_RST (1<<2) /* Reset Generation */
/* Functional Clock Selection Mask */
#define APBC_FNCLKSEL(x) (((x) & 0xf) << 4)
/* Register Base Addresses */
#define ARMD1_DRAM_BASE 0xB0000000
#define ARMD1_TIMER_BASE 0xD4014000
#define ARMD1_APBC1_BASE 0xD4015000
#define ARMD1_APBC2_BASE 0xD4015800
#define ARMD1_UART1_BASE 0xD4017000
#define ARMD1_UART2_BASE 0xD4018000
#define ARMD1_GPIO_BASE 0xD4019000
#define ARMD1_SSP1_BASE 0xD401B000
#define ARMD1_SSP2_BASE 0xD401C000
#define ARMD1_MFPR_BASE 0xD401E000
#define ARMD1_SSP3_BASE 0xD401F000
#define ARMD1_SSP4_BASE 0xD4020000
#define ARMD1_SSP5_BASE 0xD4021000
#define ARMD1_UART3_BASE 0xD4026000
#define ARMD1_MPMU_BASE 0xD4050000
#define ARMD1_APMU_BASE 0xD4282800
#define ARMD1_CPU_BASE 0xD4282C00
/*
* Main Power Management (MPMU) Registers
* Refer Datasheet Appendix A.8
*/
struct armd1mpmu_registers {
u8 pad0[0x08 - 0x00];
u32 fccr; /*0x0008*/
u32 pocr; /*0x000c*/
u32 posr; /*0x0010*/
u32 succr; /*0x0014*/
u8 pad1[0x030 - 0x014 - 4];
u32 gpcr; /*0x0030*/
u8 pad2[0x200 - 0x030 - 4];
u32 wdtpcr; /*0x0200*/
u8 pad3[0x1000 - 0x200 - 4];
u32 apcr; /*0x1000*/
u32 apsr; /*0x1004*/
u8 pad4[0x1020 - 0x1004 - 4];
u32 aprr; /*0x1020*/
u32 acgr; /*0x1024*/
u32 arsr; /*0x1028*/
};
/*
* APB1 Clock Reset/Control Registers
* Refer Datasheet Appendix A.10
*/
struct armd1apb1_registers {
u32 uart1; /*0x000*/
u32 uart2; /*0x004*/
u32 gpio; /*0x008*/
u32 pwm1; /*0x00c*/
u32 pwm2; /*0x010*/
u32 pwm3; /*0x014*/
u32 pwm4; /*0x018*/
u8 pad0[0x028 - 0x018 - 4];
u32 rtc; /*0x028*/
u32 twsi0; /*0x02c*/
u32 kpc; /*0x030*/
u32 timers; /*0x034*/
u8 pad1[0x03c - 0x034 - 4];
u32 aib; /*0x03c*/
u32 sw_jtag; /*0x040*/
u32 timer1; /*0x044*/
u32 onewire; /*0x048*/
u8 pad2[0x050 - 0x048 - 4];
u32 asfar; /*0x050 AIB Secure First Access Reg*/
u32 assar; /*0x054 AIB Secure Second Access Reg*/
u8 pad3[0x06c - 0x054 - 4];
u32 twsi1; /*0x06c*/
u32 uart3; /*0x070*/
u8 pad4[0x07c - 0x070 - 4];
u32 timer2; /*0x07C*/
u8 pad5[0x084 - 0x07c - 4];
u32 ac97; /*0x084*/
};
#endif /* CONFIG_ARMADA100 */
#endif /* _ASM_ARCH_ARMADA100_H */

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@ -0,0 +1,53 @@
/*
* (C) Copyright 2010
* Marvell Semiconductor <www.marvell.com>
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>, Contributor: Mahavir Jain <mjain@marvell.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#ifndef _ARMADA100CPU_H
#define _ARMADA100CPU_H
#include <asm/io.h>
#include <asm/system.h>
/*
* CPU Interface Registers
* Refer Datasheet Appendix A.2
*/
struct armd1cpu_registers {
u32 chip_id; /* Chip Id Reg */
u32 pad;
u32 cpu_conf; /* CPU Conf Reg */
u32 pad1;
u32 cpu_sram_spd; /* CPU SRAM Speed Reg */
u32 pad2;
u32 cpu_l2c_spd; /* CPU L2cache Speed Conf */
u32 mcb_conf; /* MCB Conf Reg */
u32 sys_boot_ctl; /* Sytem Boot Control */
};
/*
* Functions
*/
u32 armd1_sdram_base(int);
u32 armd1_sdram_size(int);
#endif /* _ARMADA100CPU_H */

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@ -0,0 +1,67 @@
/*
* Based on linux/arch/arm/mach-mpp/include/mfp-pxa168.h
* (C) Copyright 2007
* Marvell Semiconductor <www.marvell.com>
* 2007-08-21: eric miao <eric.miao@marvell.com>
*
* (C) Copyright 2010
* Marvell Semiconductor <www.marvell.com>
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
* Contributor: Mahavir Jain <mjain@marvell.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#ifndef __ARMADA100_MFP_H
#define __ARMADA100_MFP_H
/*
* Frequently used MFP Configuration macros for all ARMADA100 family of SoCs
*
* offset, pull,pF, drv,dF, edge,eF ,afn,aF
*/
/* UART1 */
#define MFP107_UART1_TXD MFP_REG(0x01ac) | MFP_AF1 | MFP_DRIVE_FAST
#define MFP107_UART1_RXD MFP_REG(0x01ac) | MFP_AF2 | MFP_DRIVE_FAST
#define MFP108_UART1_RXD MFP_REG(0x01b0) | MFP_AF1 | MFP_DRIVE_FAST
#define MFP108_UART1_TXD MFP_REG(0x01b0) | MFP_AF2 | MFP_DRIVE_FAST
#define MFP109_UART1_CTS MFP_REG(0x01b4) | MFP_AF1 | MFP_DRIVE_MEDIUM
#define MFP109_UART1_RTS MFP_REG(0x01b4) | MFP_AF2 | MFP_DRIVE_MEDIUM
#define MFP110_UART1_RTS MFP_REG(0x01b8) | MFP_AF1 | MFP_DRIVE_MEDIUM
#define MFP110_UART1_CTS MFP_REG(0x01b8) | MFP_AF2 | MFP_DRIVE_MEDIUM
#define MFP111_UART1_RI MFP_REG(0x01bc) | MFP_AF1 | MFP_DRIVE_MEDIUM
#define MFP111_UART1_DSR MFP_REG(0x01bc) | MFP_AF2 | MFP_DRIVE_MEDIUM
#define MFP112_UART1_DTR MFP_REG(0x01c0) | MFP_AF1 | MFP_DRIVE_MEDIUM
#define MFP112_UART1_DCD MFP_REG(0x01c0) | MFP_AF2 | MFP_DRIVE_MEDIUM
/* UART2 */
#define MFP47_UART2_RXD MFP_REG(0x0028) | MFP_AF6 | MFP_DRIVE_MEDIUM
#define MFP48_UART2_TXD MFP_REG(0x002c) | MFP_AF6 | MFP_DRIVE_MEDIUM
#define MFP88_UART2_RXD MFP_REG(0x0160) | MFP_AF2 | MFP_DRIVE_MEDIUM
#define MFP89_UART2_TXD MFP_REG(0x0164) | MFP_AF2 | MFP_DRIVE_MEDIUM
/* UART3 */
#define MFPO8_UART3_RXD MFP_REG(0x06c) | MFP_AF2 | MFP_DRIVE_MEDIUM
#define MFPO9_UART3_TXD MFP_REG(0x070) | MFP_AF2 | MFP_DRIVE_MEDIUM
/* More macros can be defined here... */
#define MFP_PIN_MAX 117
#endif /* __ARMADA100_MFP_H */

View File

@ -45,10 +45,25 @@ struct pinmux_resource {
.n_pins = ARRAY_SIZE(item) \
}
#define HAWKBOARD_KICK0_UNLOCK 0x83e70b13
#define HAWKBOARD_KICK1_UNLOCK 0x95a4f1e0
struct lpsc_resource {
const int lpsc_no;
};
int dvevm_read_mac_address(uint8_t *buf);
void davinci_sync_env_enetaddr(uint8_t *rom_enetaddr);
int davinci_configure_pin_mux(const struct pinmux_config *pins, int n_pins);
int davinci_configure_pin_mux_items(const struct pinmux_resource *item,
int n_items);
#if defined(CONFIG_DRIVER_TI_EMAC) && defined(CONFIG_MACH_DAVINCI_DA850_EVM)
void davinci_emac_mii_mode_sel(int mode_sel);
#endif
#if defined(CONFIG_SOC_DA8XX)
void irq_init(void);
int da8xx_configure_lpsc_items(const struct lpsc_resource *item,
const int n_items);
#endif
#endif /* __MISC_H */

View File

@ -133,7 +133,8 @@ typedef volatile unsigned int * dv_reg_p;
#define DAVINCI_PSC1_BASE 0x01e27000
#define DAVINCI_SPI0_BASE 0x01c41000
#define DAVINCI_USB_OTG_BASE 0x01e00000
#define DAVINCI_SPI1_BASE 0x01e12000
#define DAVINCI_SPI1_BASE (cpu_is_da830() ? \
0x01e12000 : 0x01f0e000)
#define DAVINCI_GPIO_BASE 0x01e26000
#define DAVINCI_EMAC_CNTRL_REGS_BASE 0x01e23000
#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE 0x01e22000
@ -149,7 +150,12 @@ typedef volatile unsigned int * dv_reg_p;
#define DAVINCI_DDR_EMIF_DATA_BASE 0xc0000000
#define DAVINCI_INTC_BASE 0xfffee000
#define DAVINCI_BOOTCFG_BASE 0x01c14000
#define JTAG_ID_REG (DAVINCI_BOOTCFG_BASE + 0x18)
#define GPIO_BANK2_REG_DIR_ADDR (DAVINCI_GPIO_BASE + 0x38)
#define GPIO_BANK2_REG_OPDATA_ADDR (DAVINCI_GPIO_BASE + 0x3c)
#define GPIO_BANK2_REG_SET_ADDR (DAVINCI_GPIO_BASE + 0x40)
#define GPIO_BANK2_REG_CLR_ADDR (DAVINCI_GPIO_BASE + 0x44)
#endif /* CONFIG_SOC_DA8XX */
/* Power and Sleep Controller (PSC) Domains */
@ -363,6 +369,9 @@ struct davinci_pllc_regs {
#define davinci_pllc_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL0_BASE)
#define DAVINCI_PLLC_DIV_MASK 0x1f
#define ASYNC3 get_async3_src()
#define PLL1_SYSCLK2 ((1 << 16) | 0x2)
#define DAVINCI_SPI1_CLKID (cpu_is_da830() ? 2 : ASYNC3)
/* Clock IDs */
enum davinci_clk_ids {
DAVINCI_SPI0_CLKID = 2,
@ -379,7 +388,10 @@ int clk_get(enum davinci_clk_ids id);
/* Boot config */
struct davinci_syscfg_regs {
dv_reg revid;
dv_reg rsvd[71];
dv_reg rsvd[13];
dv_reg kick0;
dv_reg kick1;
dv_reg rsvd1[56];
dv_reg pinmux[20];
dv_reg suspsrc;
dv_reg chipsig;
@ -442,6 +454,27 @@ struct davinci_uart_ctrl_regs {
#define DAVINCI_UART_PWREMU_MGMT_URRST (1 << 13)
#define DAVINCI_UART_PWREMU_MGMT_UTRST (1 << 14)
static inline int cpu_is_da830(void)
{
unsigned int jtag_id = REG(JTAG_ID_REG);
unsigned short part_no = (jtag_id >> 12) & 0xffff;
return ((part_no == 0xb7df) ? 1 : 0);
}
static inline int cpu_is_da850(void)
{
unsigned int jtag_id = REG(JTAG_ID_REG);
unsigned short part_no = (jtag_id >> 12) & 0xffff;
return ((part_no == 0xb7d1) ? 1 : 0);
}
static inline int get_async3_src(void)
{
return (REG(&davinci_syscfg_regs->cfgchip3) & 0x10) ?
PLL1_SYSCLK2 : 2;
}
#endif /* CONFIG_SOC_DA8XX */
#endif /* __ASM_ARCH_HARDWARE_H */

View File

@ -33,7 +33,7 @@
DECLARE_GLOBAL_DATA_PTR;
int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char * const argv[])
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
volatile rcm_t *rcm = (rcm_t *) (MMAP_RCM);
udelay(1000);

View File

@ -34,7 +34,7 @@
DECLARE_GLOBAL_DATA_PTR;
int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char * const argv[])
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
volatile ccm_t *ccm = (ccm_t *) MMAP_CCM;

View File

@ -38,7 +38,7 @@
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_M5208
int do_reset(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char * const argv[])
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
volatile rcm_t *rcm = (rcm_t *)(MMAP_RCM);
@ -141,7 +141,7 @@ int checkcpu(void)
return 0;
}
int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char * const argv[])
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
/* Call the board specific reset actions first. */
if(board_reset) {
@ -176,7 +176,7 @@ int watchdog_init(void)
#endif
#ifdef CONFIG_M5272
int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char * const argv[])
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
@ -256,7 +256,7 @@ int watchdog_init(void)
#endif /* #ifdef CONFIG_M5272 */
#ifdef CONFIG_M5275
int do_reset(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char * const argv[])
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
volatile rcm_t *rcm = (rcm_t *)(MMAP_RCM);
@ -336,7 +336,7 @@ int checkcpu(void)
return 0;
}
int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char * const argv[])
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
MCFRESET_RCR = MCFRESET_RCR_SOFTRST;
return 0;
@ -353,7 +353,7 @@ int checkcpu(void)
return 0;
}
int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char * const argv[])
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
/* enable watchdog, set timeout to 0 and wait */
mbar_writeByte(MCFSIM_SYPCR, 0xc0);
@ -383,7 +383,7 @@ int checkcpu(void)
return 0;
}
int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char * const argv[])
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
/* enable watchdog, set timeout to 0 and wait */
mbar_writeByte(SIM_SYPCR, 0xc0);

View File

@ -34,7 +34,7 @@
DECLARE_GLOBAL_DATA_PTR;
int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char * const argv[])
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
volatile rcm_t *rcm = (rcm_t *) (MMAP_RCM);

View File

@ -34,7 +34,7 @@
DECLARE_GLOBAL_DATA_PTR;
int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char * const argv[])
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
volatile rcm_t *rcm = (rcm_t *) (MMAP_RCM);
udelay(1000);

View File

@ -34,7 +34,7 @@
DECLARE_GLOBAL_DATA_PTR;
int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char * const argv[])
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
volatile gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);

View File

@ -1,24 +0,0 @@
#
# (C) Copyright 2000
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
PLATFORM_RELFLAGS +=

View File

@ -40,7 +40,7 @@ int checkcpu (void)
return (0);
}
int do_reset(void)
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
disable_interrupts();
/* indirect call to go beyond 256MB limitation of toolchain */

View File

@ -234,8 +234,7 @@ soft_restart(unsigned long addr)
!defined(CONFIG_ELPPC) && \
!defined(CONFIG_PPMC7XX)
/* no generic way to do board reset. simply call soft_reset. */
void
do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
ulong addr;
/* flush and disable I/D cache */
@ -263,7 +262,12 @@ do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
addr = CONFIG_SYS_MONITOR_BASE - sizeof (ulong);
#endif
soft_restart(addr);
while(1); /* not reached */
/* not reached */
while(1)
;
return 1;
}
#endif

View File

@ -43,13 +43,14 @@ SECTIONS
PROVIDE (erotext = .);
.reloc :
{
KEEP(*(.got))
_GOT2_TABLE_ = .;
KEEP(*(.got2))
KEEP(*(.got))
PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
_FIXUP_TABLE_ = .;
KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :

View File

@ -37,14 +37,15 @@ SECTIONS
PROVIDE (erotext = .);
.reloc :
{
KEEP(*(.got))
_GOT2_TABLE_ = .;
KEEP(*(.got2))
KEEP(*(.got))
PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
_FIXUP_TABLE_ = .;
KEEP(*(.fixup))
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
__got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
.data :

View File

@ -46,13 +46,14 @@ SECTIONS
PROVIDE (erotext = .);
.reloc :
{
KEEP(*(.got))
_GOT2_TABLE_ = .;
KEEP(*(.got2))
KEEP(*(.got))
PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
_FIXUP_TABLE_ = .;
KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :

View File

@ -41,13 +41,14 @@ SECTIONS
PROVIDE (erotext = .);
.reloc :
{
KEEP(*(.got))
_GOT2_TABLE_ = .;
KEEP(*(.got2))
KEEP(*(.got))
PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
_FIXUP_TABLE_ = .;
KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
__got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
.data :

View File

@ -40,13 +40,14 @@ SECTIONS
PROVIDE (erotext = .);
.reloc :
{
KEEP(*(.got))
_GOT2_TABLE_ = .;
KEEP(*(.got2))
KEEP(*(.got))
PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
_FIXUP_TABLE_ = .;
KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
__got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
.data :

View File

@ -41,13 +41,14 @@ SECTIONS
PROVIDE (erotext = .);
.reloc :
{
KEEP(*(.got))
_GOT2_TABLE_ = .;
KEEP(*(.got2))
KEEP(*(.got))
PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
_FIXUP_TABLE_ = .;
KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
__got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
.data :

View File

@ -40,13 +40,14 @@ SECTIONS
PROVIDE (erotext = .);
.reloc :
{
KEEP(*(.got))
_GOT2_TABLE_ = .;
KEEP(*(.got2))
KEEP(*(.got))
PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
_FIXUP_TABLE_ = .;
KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
__got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
.data :

View File

@ -39,13 +39,14 @@ SECTIONS
PROVIDE (erotext = .);
.reloc :
{
KEEP(*(.got))
_GOT2_TABLE_ = .;
KEEP(*(.got2))
KEEP(*(.got))
PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
_FIXUP_TABLE_ = .;
KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
__got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
.data :

View File

@ -199,7 +199,7 @@ int checkcpu (void)
/* ------------------------------------------------------------------------- */
int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char * const argv[])
int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
/* Everything after the first generation of PQ3 parts has RSTCR */
#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \

View File

@ -54,13 +54,14 @@ SECTIONS
PROVIDE (erotext = .);
.reloc :
{
KEEP(*(.got))
_GOT2_TABLE_ = .;
KEEP(*(.got2))
KEEP(*(.got))
PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
_FIXUP_TABLE_ = .;
KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
__got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
.data :

View File

@ -123,8 +123,7 @@ checkcpu(void)
}
void
do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile ccsr_gur_t *gur = &immap->im_gur;
@ -137,6 +136,8 @@ do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
while (1)
;
return 1;
}

View File

@ -45,13 +45,14 @@ SECTIONS
PROVIDE (erotext = .);
.reloc :
{
KEEP(*(.got))
_GOT2_TABLE_ = .;
KEEP(*(.got2))
KEEP(*(.got))
PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
_FIXUP_TABLE_ = .;
KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
__got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
.data :

View File

@ -416,7 +416,6 @@ static void test(void);
static void DQS_calibration_process(void);
#endif
#endif
int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
static unsigned char spd_read(uchar chip, uint addr)
{

View File

@ -48,21 +48,23 @@
*-------------------------------------------------------------------------------
*/
/* U-Boot - Startup Code for AMCC 4xx PowerPC based Embedded Boards
/*
* Startup code for IBM/AMCC PowerPC 4xx (PPC4xx) based boards
*
* The following description only applies to the NOR flash style booting.
* NAND booting is different. For more details about NAND booting on 4xx
* take a look at doc/README.nand-boot-ppc440.
*
* The processor starts at 0xfffffffc and the code is executed
* from flash/rom.
* in memory, but as long we don't jump around before relocating.
* board_init lies at a quite high address and when the cpu has
* jumped there, everything is ok.
* This works because the cpu gives the FLASH (CS0) the whole
* address space at startup, and board_init lies as a echo of
* the flash somewhere up there in the memorymap.
*
* board_init will change CS0 to be positioned at the correct
* address and (s)dram will be positioned at address 0
* The CPU starts at address 0xfffffffc (last word in the address space).
* The U-Boot image therefore has to be located in the "upper" area of the
* flash (e.g. 512MiB - 0xfff80000 ... 0xffffffff). The default value for
* the boot chip-select (CS0) is quite big and covers this area. On the
* 405EX this is for example 0xffe00000 ... 0xffffffff. U-Boot will
* reconfigure this CS0 (and other chip-selects as well when configured
* this way) in the boot process to the "correct" values matching the
* board layout.
*/
#include <asm-offsets.h>
#include <config.h>
#include <asm/ppc4xx.h>
@ -265,7 +267,7 @@
/* NOTREACHED - board_init_f() does not return */
#endif
#if defined(CONFIG_SYS_RAMBOOT)
#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_BOOT_FROM_XMD)
/*
* 4xx RAM-booting U-Boot image is started from offset 0
*/

View File

@ -23,8 +23,12 @@
#include "config.h" /* CONFIG_BOARDDIR */
#ifndef RESET_VECTOR_ADDRESS
#ifdef CONFIG_RESET_VECTOR_ADDRESS
#define RESET_VECTOR_ADDRESS CONFIG_RESET_VECTOR_ADDRESS
#else
#define RESET_VECTOR_ADDRESS 0xfffffffc
#endif
#endif
OUTPUT_ARCH(powerpc)
@ -55,13 +59,14 @@ SECTIONS
PROVIDE (erotext = .);
.reloc :
{
KEEP(*(.got))
_GOT2_TABLE_ = .;
KEEP(*(.got2))
KEEP(*(.got))
PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
_FIXUP_TABLE_ = .;
KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
__got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
.data :
@ -100,7 +105,11 @@ SECTIONS
* start.o, since the first shadow TLB only covers 4k
* of address space.
*/
#ifdef CONFIG_INIT_TLB
CONFIG_INIT_TLB (.bootpg)
#else
CONFIG_BOARDDIR/init.o (.bootpg)
#endif
} :text = 0xffff
#endif

View File

@ -47,7 +47,6 @@
DECLARE_GLOBAL_DATA_PTR;
extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
extern ulong get_effective_memsize(void);
static ulong get_sp (void);
static void set_clocks_in_mhz (bd_t *kbd);

View File

@ -12,11 +12,13 @@ void breakinst(void);
int
kgdb_setjmp(long *buf)
{
asm ("mflr 0; stw 0,0(%0);"
"stw 1,4(%0); stw 2,8(%0);"
"mfcr 0; stw 0,12(%0);"
"stmw 13,16(%0)"
: : "r" (buf));
unsigned long temp;
asm volatile("mflr %0; stw %0,0(%1);"
"stw %%r1,4(%1); stw %%r2,8(%1);"
"mfcr %0; stw %0,12(%1);"
"stmw %%r13,16(%1)"
: "=&r"(temp) : "r" (buf));
/* XXX should save fp regs as well */
return 0;
}
@ -24,13 +26,16 @@ kgdb_setjmp(long *buf)
void
kgdb_longjmp(long *buf, int val)
{
unsigned long temp;
if (val == 0)
val = 1;
asm ("lmw 13,16(%0);"
"lwz 0,12(%0); mtcrf 0x38,0;"
"lwz 0,0(%0); lwz 1,4(%0); lwz 2,8(%0);"
"mtlr 0; mr 3,%1"
: : "r" (buf), "r" (val));
asm volatile("lmw %%r13,16(%1);"
"lwz %0,12(%1); mtcrf 0x38,%0;"
"lwz %0,0(%1); lwz %%r1,4(%1); lwz %%r2,8(%1);"
"mtlr %0; mr %%r3,%2"
: "=&r"(temp) : "r" (buf), "r" (val));
}
static inline unsigned long

View File

@ -78,6 +78,8 @@ unsigned long ticks2usec(unsigned long ticks)
int init_timebase (void)
{
unsigned long temp;
#if defined(CONFIG_5xx) || defined(CONFIG_8xx)
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
@ -86,7 +88,8 @@ int init_timebase (void)
#endif
/* reset */
asm ("li 3,0 ; mttbu 3 ; mttbl 3 ;");
asm volatile("li %0,0 ; mttbu %0 ; mttbl %0;"
: "=&r"(temp) );
#if defined(CONFIG_5xx) || defined(CONFIG_8xx)
/* enable */

View File

@ -0,0 +1,52 @@
#
# (C) Copyright 2010
# Marvell Semiconductor <www.marvell.com>
# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
# Contributor: Mahavir Jain <mjain@marvell.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
# MA 02110-1301 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
COBJS := aspenite.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

View File

@ -0,0 +1,53 @@
/*
* (C) Copyright 2010
* Marvell Semiconductor <www.marvell.com>
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
* Contributor: Mahavir Jain <mjain@marvell.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#include <common.h>
#include <mvmfp.h>
#include <asm/arch/mfp.h>
#include <asm/arch/armada100.h>
DECLARE_GLOBAL_DATA_PTR;
int board_early_init_f(void)
{
u32 mfp_cfg[] = {
/* Enable Console on UART1 */
MFP107_UART1_RXD,
MFP108_UART1_TXD,
MFP_EOC /*End of configureation*/
};
/* configure MFP's */
mfp_config(mfp_cfg);
return 0;
}
int board_init(void)
{
/* arch number of Board */
gd->bd->bi_arch_number = MACH_TYPE_ASPENITE;
/* adress of boot parameters */
gd->bd->bi_boot_params = armd1_sdram_base(0) + 0x100;
return 0;
}

View File

@ -1,25 +0,0 @@
#
# (C) Copyright 2000
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
# Use board specific linker script
LDSCRIPT := $(SRCTREE)/board/amirix/ap1000/u-boot.lds

View File

@ -1,25 +0,0 @@
#
# (C) Copyright 2000-2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
PLATFORM_CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE)

View File

@ -1,28 +0,0 @@
#
# (C) Copyright 2001
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
# ATC boards
#
PLATFORM_CPPFLAGS += -I$(TOPDIR)

View File

@ -35,7 +35,6 @@
#include "fwupdate.h"
extern int do_bootm(cmd_tbl_t *, int, int, char * const []);
extern long do_fat_read(const char *, void *, unsigned long, int);
extern int do_fat_fsload(cmd_tbl_t *, int, int, char * const []);

View File

@ -1,28 +0,0 @@
#
# (C) Copyright 2003
# Martin Winistoerfer, martinwinistoerfer@gmx.ch.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
# CMI Board Configuration
#
PLATFORM_CPPFLAGS += -I$(TOPDIR)

View File

@ -1,28 +0,0 @@
#
# (C) Copyright 2001-2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
# CPC45 board
#
PLATFORM_CPPFLAGS += -I$(TOPDIR)

View File

@ -1,28 +0,0 @@
#
# (C) Copyright 2001
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
# CPU86 boards
#
PLATFORM_CPPFLAGS += -I$(TOPDIR)

View File

@ -1,28 +0,0 @@
#
# (C) Copyright 2001-2005
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
# CPU87 board
#
PLATFORM_CPPFLAGS += -I$(TOPDIR)

View File

@ -1,31 +0,0 @@
#
# (C) Copyright 2000-2004
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2004
# Tolunay Orkun, NextIO Inc., torkun@nextio.com.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
# Cogent CSB272 board
#
LDFLAGS += $(LINKER_UNDEFS)

View File

@ -1,31 +0,0 @@
#
# (C) Copyright 2000-2004
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2004
# Tolunay Orkun, NextIO Inc., torkun@nextio.com.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
# Cogent CSB472 board
#
LDFLAGS += $(LINKER_UNDEFS)

View File

@ -29,7 +29,7 @@ endif
LIB = $(obj)lib$(VENDOR).o
COBJS := misc.o
COBJS := misc.o davinci_pinmux.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))

View File

@ -0,0 +1,105 @@
/*
* DaVinci pinmux functions.
*
* Copyright (C) 2009 Nick Thompson, GE Fanuc Ltd, <nick.thompson@gefanuc.com>
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
* Copyright (C) 2008 Lyrtech <www.lyrtech.com>
* Copyright (C) 2004 Texas Instruments.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <common.h>
#include <asm/arch/hardware.h>
#include <asm/io.h>
#include <asm/arch/davinci_misc.h>
/*
* Change the setting of a pin multiplexer field.
*
* Takes an array of pinmux settings similar to:
*
* struct pinmux_config uart_pins[] = {
* { &davinci_syscfg_regs->pinmux[8], 2, 7 },
* { &davinci_syscfg_regs->pinmux[9], 2, 0 }
* };
*
* Stepping through the array, each pinmux[n] register has the given value
* set in the pin mux field specified.
*
* The number of pins in the array must be passed (ARRAY_SIZE can provide
* this value conveniently).
*
* Returns 0 if all field numbers and values are in the correct range,
* else returns -1.
*/
int davinci_configure_pin_mux(const struct pinmux_config *pins,
const int n_pins)
{
int i;
/* check for invalid pinmux values */
for (i = 0; i < n_pins; i++) {
if (pins[i].field >= PIN_MUX_NUM_FIELDS ||
(pins[i].value & ~PIN_MUX_FIELD_MASK) != 0)
return -1;
}
/* configure the pinmuxes */
for (i = 0; i < n_pins; i++) {
const int offset = pins[i].field * PIN_MUX_FIELD_SIZE;
const unsigned int value = pins[i].value << offset;
const unsigned int mask = PIN_MUX_FIELD_MASK << offset;
const dv_reg *mux = pins[i].mux;
writel(value | (readl(mux) & (~mask)), mux);
}
return 0;
}
/*
* Configure multiple pinmux resources.
*
* Takes an pinmux_resource array of pinmux_config and pin counts:
*
* const struct pinmux_resource pinmuxes[] = {
* PINMUX_ITEM(uart_pins),
* PINMUX_ITEM(i2c_pins),
* };
*
* The number of items in the array must be passed (ARRAY_SIZE can provide
* this value conveniently).
*
* Each item entry is configured in the defined order. If configuration
* of any item fails, -1 is returned and none of the following items are
* configured. On success, 0 is returned.
*/
int davinci_configure_pin_mux_items(const struct pinmux_resource *item,
const int n_items)
{
int i;
for (i = 0; i < n_items; i++) {
if (davinci_configure_pin_mux(item[i].pins,
item[i].n_pins) != 0)
return -1;
}
return 0;
}

View File

@ -29,10 +29,11 @@
#include <net.h>
#include <asm/arch/hardware.h>
#include <asm/io.h>
#include "misc.h"
#include <asm/arch/davinci_misc.h>
DECLARE_GLOBAL_DATA_PTR;
#ifndef CONFIG_PRELOADER
int dram_init(void)
{
/* dram_init must store complete ramsize in gd->ram_size */
@ -47,6 +48,7 @@ void dram_init_banksize(void)
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = gd->ram_size;
}
#endif
#ifdef CONFIG_DRIVER_TI_EMAC
@ -75,6 +77,22 @@ err:
return 0;
}
/*
* Set the mii mode as MII or RMII
*/
#if defined(CONFIG_DRIVER_TI_EMAC)
void davinci_emac_mii_mode_sel(int mode_sel)
{
int val;
val = readl(&davinci_syscfg_regs->cfgchip3);
if (mode_sel == 0)
val &= ~(1 << 8);
else
val |= (1 << 8);
writel(val, &davinci_syscfg_regs->cfgchip3);
}
#endif
/*
* If there is no MAC address in the environment, then it will be initialized
* (silently) from the value in the EEPROM.
@ -94,79 +112,38 @@ void davinci_sync_env_enetaddr(uint8_t *rom_enetaddr)
}
}
#endif /* DAVINCI_EMAC */
#endif /* CONFIG_DRIVER_TI_EMAC */
/*
* Change the setting of a pin multiplexer field.
*
* Takes an array of pinmux settings similar to:
*
* struct pinmux_config uart_pins[] = {
* { &davinci_syscfg_regs->pinmux[8], 2, 7 },
* { &davinci_syscfg_regs->pinmux[9], 2, 0 }
* };
*
* Stepping through the array, each pinmux[n] register has the given value
* set in the pin mux field specified.
*
* The number of pins in the array must be passed (ARRAY_SIZE can provide
* this value conveniently).
*
* Returns 0 if all field numbers and values are in the correct range,
* else returns -1.
*/
int davinci_configure_pin_mux(const struct pinmux_config *pins,
const int n_pins)
#if defined(CONFIG_SOC_DA8XX)
#ifndef CONFIG_USE_IRQ
void irq_init(void)
{
int i;
/*
* Mask all IRQs by clearing the global enable and setting
* the enable clear for all the 90 interrupts.
*/
/* check for invalid pinmux values */
for (i = 0; i < n_pins; i++) {
if (pins[i].field >= PIN_MUX_NUM_FIELDS ||
(pins[i].value & ~PIN_MUX_FIELD_MASK) != 0)
return -1;
}
writel(0, &davinci_aintc_regs->ger);
/* configure the pinmuxes */
for (i = 0; i < n_pins; i++) {
const int offset = pins[i].field * PIN_MUX_FIELD_SIZE;
const unsigned int value = pins[i].value << offset;
const unsigned int mask = PIN_MUX_FIELD_MASK << offset;
const dv_reg *mux = pins[i].mux;
writel(0, &davinci_aintc_regs->hier);
writel(value | (readl(mux) & (~mask)), mux);
}
return 0;
writel(0xffffffff, &davinci_aintc_regs->ecr1);
writel(0xffffffff, &davinci_aintc_regs->ecr2);
writel(0xffffffff, &davinci_aintc_regs->ecr3);
}
#endif
/*
* Configure multiple pinmux resources.
*
* Takes an pinmux_resource array of pinmux_config and pin counts:
*
* const struct pinmux_resource pinmuxes[] = {
* PINMUX_ITEM(uart_pins),
* PINMUX_ITEM(i2c_pins),
* };
*
* The number of items in the array must be passed (ARRAY_SIZE can provide
* this value conveniently).
*
* Each item entry is configured in the defined order. If configuration
* of any item fails, -1 is returned and none of the following items are
* configured. On success, 0 is returned.
* Enable PSC for various peripherals.
*/
int davinci_configure_pin_mux_items(const struct pinmux_resource *item,
int da8xx_configure_lpsc_items(const struct lpsc_resource *item,
const int n_items)
{
int i;
for (i = 0; i < n_items; i++) {
if (davinci_configure_pin_mux(item[i].pins,
item[i].n_pins) != 0)
return -1;
}
for (i = 0; i < n_items; i++)
lpsc_on(item[i].lpsc_no);
return 0;
}
#endif

View File

@ -27,9 +27,9 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
COBJS-y += common.o
COBJS-$(CONFIG_MACH_DAVINCI_DA830_EVM) += da830evm.o
COBJS-$(CONFIG_MACH_DAVINCI_DA850_EVM) += da850evm.o
COBJS-$(CONFIG_MACH_DAVINCI_HAWK) += hawkboard.o
COBJS := $(COBJS-y)

View File

@ -1,55 +0,0 @@
/*
* Miscellaneous DA8XX functions.
*
* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include "common.h"
#ifndef CONFIG_USE_IRQ
void irq_init(void)
{
/*
* Mask all IRQs by clearing the global enable and setting
* the enable clear for all the 90 interrupts.
*/
writel(0, &davinci_aintc_regs->ger);
writel(0, &davinci_aintc_regs->hier);
writel(0xffffffff, &davinci_aintc_regs->ecr1);
writel(0xffffffff, &davinci_aintc_regs->ecr2);
writel(0xffffffff, &davinci_aintc_regs->ecr3);
}
#endif
/*
* Enable PSC for various peripherals.
*/
int da8xx_configure_lpsc_items(const struct lpsc_resource *item,
const int n_items)
{
int i;
for (i = 0; i < n_items; i++)
lpsc_on(item[i].lpsc_no);
return 0;
}

View File

@ -1,30 +0,0 @@
/*
* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __COMMON_H
#define __COMMON_H
struct lpsc_resource {
const int lpsc_no;
};
void irq_init(void);
int da8xx_configure_lpsc_items(const struct lpsc_resource *item,
int n_items);
#endif /* __COMMON_H */

View File

@ -40,8 +40,7 @@
#include <asm/arch/emif_defs.h>
#include <asm/arch/emac_defs.h>
#include <asm/io.h>
#include "../common/misc.h"
#include "common.h"
#include <asm/arch/davinci_misc.h>
DECLARE_GLOBAL_DATA_PTR;

View File

@ -29,8 +29,7 @@
#include <asm/arch/emif_defs.h>
#include <asm/arch/emac_defs.h>
#include <asm/io.h>
#include "../common/misc.h"
#include "common.h"
#include <asm/arch/davinci_misc.h>
DECLARE_GLOBAL_DATA_PTR;
@ -54,6 +53,15 @@ static const struct pinmux_config uart_pins[] = {
#ifdef CONFIG_DRIVER_TI_EMAC
static const struct pinmux_config emac_pins[] = {
#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
{ pinmux(14), 8, 2 },
{ pinmux(14), 8, 3 },
{ pinmux(14), 8, 4 },
{ pinmux(14), 8, 5 },
{ pinmux(14), 8, 6 },
{ pinmux(14), 8, 7 },
{ pinmux(15), 8, 1 },
#else /* ! CONFIG_DRIVER_TI_EMAC_USE_RMII */
{ pinmux(2), 8, 1 },
{ pinmux(2), 8, 2 },
{ pinmux(2), 8, 3 },
@ -69,10 +77,10 @@ static const struct pinmux_config emac_pins[] = {
{ pinmux(3), 8, 5 },
{ pinmux(3), 8, 6 },
{ pinmux(3), 8, 7 },
#endif /* CONFIG_DRIVER_TI_EMAC_USE_RMII */
{ pinmux(4), 8, 0 },
{ pinmux(4), 8, 1 }
};
#endif /* CONFIG_DRIVER_TI_EMAC */
/* I2C pin muxer settings */
static const struct pinmux_config i2c_pins[] = {
@ -99,6 +107,13 @@ const struct pinmux_config nand_pins[] = {
};
#endif
#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
#define HAS_RMII 1
#else
#define HAS_RMII 0
#endif
#endif /* CONFIG_DRIVER_TI_EMAC */
static const struct pinmux_resource pinmuxes[] = {
#ifdef CONFIG_SPI_FLASH
PINMUX_ITEM(spi1_pins),
@ -203,9 +218,8 @@ int board_init(void)
#ifdef CONFIG_DRIVER_TI_EMAC
if (davinci_configure_pin_mux(emac_pins, ARRAY_SIZE(emac_pins)) != 0)
return 1;
/* set cfgchip3 to select MII */
writel(readl(&davinci_syscfg_regs->cfgchip3) & ~(1 << 8),
&davinci_syscfg_regs->cfgchip3);
davinci_emac_mii_mode_sel(HAS_RMII);
#endif /* CONFIG_DRIVER_TI_EMAC */
/* enable the console UART */
@ -218,11 +232,100 @@ int board_init(void)
#ifdef CONFIG_DRIVER_TI_EMAC
#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
/**
* rmii_hw_init
*
* DA850/OMAP-L138 EVM can interface to a daughter card for
* additional features. This card has an I2C GPIO Expander TCA6416
* to select the required functions like camera, RMII Ethernet,
* character LCD, video.
*
* Initialization of the expander involves configuring the
* polarity and direction of the ports. P07-P05 are used here.
* These ports are connected to a Mux chip which enables only one
* functionality at a time.
*
* For RMII phy to respond, the MII MDIO clock has to be disabled
* since both the PHY devices have address as zero. The MII MDIO
* clock is controlled via GPIO2[6].
*
* This code is valid for Beta version of the hardware
*/
int rmii_hw_init(void)
{
const struct pinmux_config gpio_pins[] = {
{ pinmux(6), 8, 1 }
};
u_int8_t buf[2];
unsigned int temp;
int ret;
/* PinMux for GPIO */
if (davinci_configure_pin_mux(gpio_pins, ARRAY_SIZE(gpio_pins)) != 0)
return 1;
/* I2C Exapnder configuration */
/* Set polarity to non-inverted */
buf[0] = 0x0;
buf[1] = 0x0;
ret = i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 4, 1, buf, 2);
if (ret) {
printf("\nExpander @ 0x%02x write FAILED!!!\n",
CONFIG_SYS_I2C_EXPANDER_ADDR);
return ret;
}
/* Configure P07-P05 as outputs */
buf[0] = 0x1f;
buf[1] = 0xff;
ret = i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 6, 1, buf, 2);
if (ret) {
printf("\nExpander @ 0x%02x write FAILED!!!\n",
CONFIG_SYS_I2C_EXPANDER_ADDR);
}
/* For Ethernet RMII selection
* P07(SelA)=0
* P06(SelB)=1
* P05(SelC)=1
*/
if (i2c_read(CONFIG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) {
printf("\nExpander @ 0x%02x read FAILED!!!\n",
CONFIG_SYS_I2C_EXPANDER_ADDR);
}
buf[0] &= 0x1f;
buf[0] |= (0 << 7) | (1 << 6) | (1 << 5);
if (i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) {
printf("\nExpander @ 0x%02x write FAILED!!!\n",
CONFIG_SYS_I2C_EXPANDER_ADDR);
}
/* Set the output as high */
temp = REG(GPIO_BANK2_REG_SET_ADDR);
temp |= (0x01 << 6);
REG(GPIO_BANK2_REG_SET_ADDR) = temp;
/* Set the GPIO direction as output */
temp = REG(GPIO_BANK2_REG_DIR_ADDR);
temp &= ~(0x01 << 6);
REG(GPIO_BANK2_REG_DIR_ADDR) = temp;
return 0;
}
#endif /* CONFIG_DRIVER_TI_EMAC_USE_RMII */
/*
* Initializes on-board ethernet controllers.
*/
int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
/* Select RMII fucntion through the expander */
if (rmii_hw_init())
printf("RMII hardware init failed!!!\n");
#endif
if (!davinci_emac_initialize()) {
printf("Error: Ethernet init failed!\n");
return -1;

View File

@ -0,0 +1,68 @@
/*
* Modified for Hawkboard - Syed Mohammed Khasim <khasim@beagleboard.org>
*
* Copyright (C) 2008 Sekhar Nori, Texas Instruments, Inc. <nsekhar@ti.com>
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
* Copyright (C) 2004 Texas Instruments.
*
* ----------------------------------------------------------------------------
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
* ----------------------------------------------------------------------------
*/
#include <common.h>
#include <asm/errno.h>
#include <asm/arch/hardware.h>
#include <asm/io.h>
#include <asm/arch/davinci_misc.h>
#include <ns16550.h>
DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
{
/* arch number of the board */
gd->bd->bi_arch_number = MACH_TYPE_OMAPL138_HAWKBOARD;
/* address of boot parameters */
gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
return 0;
}
int board_early_init_f(void)
{
/*
* Kick Registers need to be set to allow access to Pin Mux registers
*/
writel(HAWKBOARD_KICK0_UNLOCK, &davinci_syscfg_regs->kick0);
writel(HAWKBOARD_KICK1_UNLOCK, &davinci_syscfg_regs->kick1);
/* set cfgchip3 to select mii */
writel(readl(&davinci_syscfg_regs->cfgchip3) &
~(1 << 8), &davinci_syscfg_regs->cfgchip3);
return 0;
}
int misc_init_r(void)
{
char buf[32];
printf("ARM Clock : %s MHz\n",
strmhz(buf, clk_get(DAVINCI_ARM_CLKID)));
return 0;
}

View File

@ -0,0 +1,157 @@
/*
* Modified for Hawkboard - Syed Mohammed Khasim <khasim@beagleboard.org>
*
* Copyright (C) 2008 Sekhar Nori, Texas Instruments, Inc. <nsekhar@ti.com>
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
* Copyright (C) 2004 Texas Instruments.
*
* ----------------------------------------------------------------------------
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
* ----------------------------------------------------------------------------
*/
#include <common.h>
#include <asm/errno.h>
#include <asm/arch/hardware.h>
#include <asm/io.h>
#include <asm/arch/davinci_misc.h>
#include <ns16550.h>
DECLARE_GLOBAL_DATA_PTR;
#define pinmux(x) (&davinci_syscfg_regs->pinmux[x])
static const struct pinmux_config mii_pins[] = {
{ pinmux(2), 8, 1 },
{ pinmux(2), 8, 2 },
{ pinmux(2), 8, 3 },
{ pinmux(2), 8, 4 },
{ pinmux(2), 8, 5 },
{ pinmux(2), 8, 6 },
{ pinmux(2), 8, 7 }
};
static const struct pinmux_config mdio_pins[] = {
{ pinmux(4), 8, 0 },
{ pinmux(4), 8, 1 }
};
static const struct pinmux_config nand_pins[] = {
{ pinmux(7), 1, 1 },
{ pinmux(7), 1, 2 },
{ pinmux(7), 1, 4 },
{ pinmux(7), 1, 5 },
{ pinmux(9), 1, 0 },
{ pinmux(9), 1, 1 },
{ pinmux(9), 1, 2 },
{ pinmux(9), 1, 3 },
{ pinmux(9), 1, 4 },
{ pinmux(9), 1, 5 },
{ pinmux(9), 1, 6 },
{ pinmux(9), 1, 7 },
{ pinmux(12), 1, 5 },
{ pinmux(12), 1, 6 }
};
static const struct pinmux_config uart2_pins[] = {
{ pinmux(0), 4, 6 },
{ pinmux(0), 4, 7 },
{ pinmux(4), 2, 4 },
{ pinmux(4), 2, 5 }
};
static const struct pinmux_config i2c_pins[] = {
{ pinmux(4), 2, 4 },
{ pinmux(4), 2, 5 }
};
static const struct pinmux_resource pinmuxes[] = {
PINMUX_ITEM(mii_pins),
PINMUX_ITEM(mdio_pins),
PINMUX_ITEM(i2c_pins),
PINMUX_ITEM(nand_pins),
PINMUX_ITEM(uart2_pins),
};
static const struct lpsc_resource lpsc[] = {
{ DAVINCI_LPSC_AEMIF }, /* NAND, NOR */
{ DAVINCI_LPSC_SPI1 }, /* Serial Flash */
{ DAVINCI_LPSC_EMAC }, /* image download */
{ DAVINCI_LPSC_UART2 }, /* console */
{ DAVINCI_LPSC_GPIO },
};
void board_init_f(ulong bootflag)
{
/*
* Kick Registers need to be set to allow access to Pin Mux registers
*/
writel(HAWKBOARD_KICK0_UNLOCK, &davinci_syscfg_regs->kick0);
writel(HAWKBOARD_KICK1_UNLOCK, &davinci_syscfg_regs->kick1);
/* setup the SUSPSRC for ARM to control emulation suspend */
writel(readl(&davinci_syscfg_regs->suspsrc) &
~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
DAVINCI_SYSCFG_SUSPSRC_UART2), &davinci_syscfg_regs->suspsrc);
/* Power on required peripherals
* ARM does not have acess by default to PSC0 and PSC1
* assuming here that the DSP bootloader has set the IOPU
* such that PSC access is available to ARM
*/
da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc));
/* configure pinmux settings */
davinci_configure_pin_mux_items(pinmuxes,
ARRAY_SIZE(pinmuxes));
writel(readl(&davinci_uart2_ctrl_regs->pwremu_mgmt) |
(DAVINCI_UART_PWREMU_MGMT_FREE) |
(DAVINCI_UART_PWREMU_MGMT_URRST) |
(DAVINCI_UART_PWREMU_MGMT_UTRST),
&davinci_uart2_ctrl_regs->pwremu_mgmt);
NS16550_init((NS16550_t)(DAVINCI_UART2_BASE),
CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
puts("Nand boot...\n");
nand_boot();
}
void puts(const char *str)
{
while (*str)
putc(*str++);
}
void putc(char c)
{
if (gd->flags & GD_FLG_SILENT)
return;
if (c == '\n')
NS16550_putc((NS16550_t)(DAVINCI_UART2_BASE), '\r');
NS16550_putc((NS16550_t)(DAVINCI_UART2_BASE), c);
}
void hang(void)
{
puts("### ERROR ### Please RESET the board ###\n");
for (;;)
;
}

View File

@ -22,7 +22,7 @@
#include <asm/arch/hardware.h>
#include <asm/arch/emif_defs.h>
#include <asm/arch/nand_defs.h>
#include "../common/misc.h"
#include <asm/arch/davinci_misc.h>
#include <net.h>
#include <netdev.h>

View File

@ -22,7 +22,7 @@
#include <asm/arch/hardware.h>
#include <asm/arch/gpio_defs.h>
#include <asm/arch/nand_defs.h>
#include "../common/misc.h"
#include <asm/arch/davinci_misc.h>
#include <net.h>
#include <netdev.h>

View File

@ -24,7 +24,7 @@
#include <asm/arch/nand_defs.h>
#include <asm/arch/gpio_defs.h>
#include <netdev.h>
#include "../common/misc.h"
#include <asm/arch/davinci_misc.h>
DECLARE_GLOBAL_DATA_PTR;

View File

@ -27,7 +27,7 @@
#include <common.h>
#include <i2c.h>
#include <asm/arch/hardware.h>
#include "../common/misc.h"
#include <asm/arch/davinci_misc.h>
DECLARE_GLOBAL_DATA_PTR;

View File

@ -1,7 +1,9 @@
#
# (C) Copyright 2001
# (C) Copyright 2000, 2001, 2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
#
# See file CREDITS for list of people who contributed to this
# project.
#
@ -21,7 +23,31 @@
# MA 02111-1307 USA
#
#
# Siemens SCM boards
#
PLATFORM_CPPFLAGS += -I$(TOPDIR)
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS-y += ea20.o
COBJS := $(COBJS-y)
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak *~ .depend
#########################################################################
# This is for $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

196
board/davinci/ea20/ea20.c Normal file
View File

@ -0,0 +1,196 @@
/*
* (C) Copyright 2010
* Stefano Babic, DENX Software Engineering, sbabic@denx.de
*
* Based on da850evm.c, original Copyrights follow:
*
* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
*
* Based on da830evm.c. Original Copyrights follow:
*
* Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com>
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <common.h>
#include <i2c.h>
#include <net.h>
#include <netdev.h>
#include <asm/arch/hardware.h>
#include <asm/arch/emif_defs.h>
#include <asm/arch/emac_defs.h>
#include <asm/io.h>
#include <asm/arch/davinci_misc.h>
DECLARE_GLOBAL_DATA_PTR;
#define pinmux(x) (&davinci_syscfg_regs->pinmux[x])
/* SPI0 pin muxer settings */
static const struct pinmux_config spi1_pins[] = {
{ pinmux(5), 1, 1 },
{ pinmux(5), 1, 2 },
{ pinmux(5), 1, 4 },
{ pinmux(5), 1, 5 }
};
/* UART pin muxer settings */
static const struct pinmux_config uart_pins[] = {
{ pinmux(0), 4, 6 },
{ pinmux(0), 4, 7 },
{ pinmux(4), 2, 4 },
{ pinmux(4), 2, 5 }
};
#ifdef CONFIG_DRIVER_TI_EMAC
#define HAS_RMII 1
static const struct pinmux_config emac_pins[] = {
{ pinmux(14), 8, 2 },
{ pinmux(14), 8, 3 },
{ pinmux(14), 8, 4 },
{ pinmux(14), 8, 5 },
{ pinmux(14), 8, 6 },
{ pinmux(14), 8, 7 },
{ pinmux(15), 8, 1 },
{ pinmux(4), 8, 0 },
{ pinmux(4), 8, 1 }
};
#endif
#ifdef CONFIG_NAND_DAVINCI
const struct pinmux_config nand_pins[] = {
{ pinmux(7), 1, 1 },
{ pinmux(7), 1, 2 },
{ pinmux(7), 1, 4 },
{ pinmux(7), 1, 5 },
{ pinmux(9), 1, 0 },
{ pinmux(9), 1, 1 },
{ pinmux(9), 1, 2 },
{ pinmux(9), 1, 3 },
{ pinmux(9), 1, 4 },
{ pinmux(9), 1, 5 },
{ pinmux(9), 1, 6 },
{ pinmux(9), 1, 7 },
{ pinmux(12), 1, 5 },
{ pinmux(12), 1, 6 }
};
#endif
static const struct pinmux_resource pinmuxes[] = {
#ifdef CONFIG_SPI_FLASH
PINMUX_ITEM(spi1_pins),
#endif
PINMUX_ITEM(uart_pins),
#ifdef CONFIG_NAND_DAVINCI
PINMUX_ITEM(nand_pins),
#endif
};
static const struct lpsc_resource lpsc[] = {
{ DAVINCI_LPSC_AEMIF }, /* NAND, NOR */
{ DAVINCI_LPSC_SPI1 }, /* Serial Flash */
{ DAVINCI_LPSC_EMAC }, /* image download */
{ DAVINCI_LPSC_UART2 }, /* console */
{ DAVINCI_LPSC_GPIO },
};
int board_init(void)
{
#ifndef CONFIG_USE_IRQ
irq_init();
#endif
#ifdef CONFIG_NAND_DAVINCI
/*
* NAND CS setup - cycle counts based on da850evm NAND timings in the
* Linux kernel @ 25MHz EMIFA
*/
writel((DAVINCI_ABCR_WSETUP(0) |
DAVINCI_ABCR_WSTROBE(0) |
DAVINCI_ABCR_WHOLD(0) |
DAVINCI_ABCR_RSETUP(0) |
DAVINCI_ABCR_RSTROBE(1) |
DAVINCI_ABCR_RHOLD(0) |
DAVINCI_ABCR_TA(0) |
DAVINCI_ABCR_ASIZE_8BIT),
&davinci_emif_regs->ab2cr); /* CS3 */
#endif
/* arch number of the board */
gd->bd->bi_arch_number = MACH_TYPE_EA20;
/* address of boot parameters */
gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
/*
* Power on required peripherals
* ARM does not have access by default to PSC0 and PSC1
* assuming here that the DSP bootloader has set the IOPU
* such that PSC access is available to ARM
*/
if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc)))
return 1;
/* setup the SUSPSRC for ARM to control emulation suspend */
writel(readl(&davinci_syscfg_regs->suspsrc) &
~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
DAVINCI_SYSCFG_SUSPSRC_UART2),
&davinci_syscfg_regs->suspsrc);
/* configure pinmux settings */
if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes)))
return 1;
#ifdef CONFIG_DRIVER_TI_EMAC
if (davinci_configure_pin_mux(emac_pins, ARRAY_SIZE(emac_pins)) != 0)
return 1;
davinci_emac_mii_mode_sel(HAS_RMII);
#endif /* CONFIG_DRIVER_TI_EMAC */
/* enable the console UART */
writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
DAVINCI_UART_PWREMU_MGMT_UTRST),
&davinci_uart2_ctrl_regs->pwremu_mgmt);
return 0;
}
#ifdef CONFIG_DRIVER_TI_EMAC
/*
* Initializes on-board ethernet controllers.
*/
int board_eth_init(bd_t *bis)
{
if (!davinci_emac_initialize()) {
printf("Error: Ethernet init failed!\n");
return -1;
}
/*
* This board has a RMII PHY. However, the MDC line on the SOM
* must not be disabled (there is no MII PHY on the
* baseboard) via the GPIO2[6], because this pin
* disables at the same time the SPI flash.
*/
return 0;
}
#endif /* CONFIG_DRIVER_TI_EMAC */

View File

@ -27,7 +27,7 @@
#include <common.h>
#include <i2c.h>
#include <asm/arch/hardware.h>
#include "../common/misc.h"
#include <asm/arch/davinci_misc.h>
DECLARE_GLOBAL_DATA_PTR;

View File

@ -30,7 +30,7 @@
#include <common.h>
#include <i2c.h>
#include <asm/arch/hardware.h>
#include "../common/misc.h"
#include <asm/arch/davinci_misc.h>
#define DAVINCI_A3CR (0x01E00014) /* EMIF-A CS3 config register. */
#define DAVINCI_A3CR_VAL (0x3FFFFFFD) /* EMIF-A CS3 value for FPGA. */

View File

@ -28,7 +28,7 @@
#include <nand.h>
#include <asm/arch/nand_defs.h>
#include <asm/arch/hardware.h>
#include "../common/misc.h"
#include <asm/arch/davinci_misc.h>
DECLARE_GLOBAL_DATA_PTR;

View File

@ -184,7 +184,7 @@ void after_reloc (ulong dest_addr)
* do_reset is done here because in this case it is board specific, since the
* 7xx CPUs can only be reset by external HW (the RTC in this case).
*/
void do_reset (cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char * const argv[])
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
#if defined(CONFIG_RTC_MK48T59)
/* trigger watchdog immediately */
@ -192,6 +192,7 @@ void do_reset (cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char * const ar
#else
#error "You must define the macro CONFIG_RTC_MK48T59."
#endif
return 0;
}
/* ------------------------------------------------------------------------- */

View File

@ -1,28 +0,0 @@
#
# (C) Copyright 2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
# EP8260 boards
#
PLATFORM_CPPFLAGS += -I$(TOPDIR)

View File

@ -38,7 +38,6 @@ DECLARE_GLOBAL_DATA_PTR;
#undef FPGA_DEBUG
extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
extern void lxt971_no_sleep(void);
/* fpga configuration data - gzip compressed and generated by bin2c */

View File

@ -29,8 +29,6 @@
DECLARE_GLOBAL_DATA_PTR;
/*cmd_boot.c*/
extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
extern void lxt971_no_sleep(void);
/* ------------------------------------------------------------------------- */

View File

@ -33,7 +33,6 @@
#define FPGA_DEBUG
#endif
extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
extern void lxt971_no_sleep(void);
/* fpga configuration data - gzip compressed and generated by bin2c */

View File

@ -29,10 +29,6 @@
DECLARE_GLOBAL_DATA_PTR;
/*cmd_boot.c*/
extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
/* ------------------------------------------------------------------------- */
#if 0

View File

@ -29,7 +29,6 @@
#if defined(CONFIG_CMD_BSP)
extern int do_bootm (cmd_tbl_t *, int, int, char *[]);
extern int do_source (cmd_tbl_t *, int, int, char *[]);
#define ADDRMASK 0xfffff000

View File

@ -32,7 +32,6 @@
DECLARE_GLOBAL_DATA_PTR;
extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
extern void __ft_board_setup(void *blob, bd_t *bd);
#undef FPGA_DEBUG

View File

@ -122,7 +122,6 @@ static char show_config_tab[][15] = {{"PCI0DLL_2 "}, /* 31 */
extern flash_info_t flash_info[];
extern int do_bootm (cmd_tbl_t *, int, int, char *[]);
extern int do_bootvx (cmd_tbl_t *, int, int, char *[]);
/* ------------------------------------------------------------------------- */

View File

@ -28,9 +28,6 @@
DECLARE_GLOBAL_DATA_PTR;
/*cmd_boot.c*/
extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
extern void lxt971_no_sleep(void);

View File

@ -1,25 +0,0 @@
#
# (C) Copyright 2000
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
# Use board specific linker script
LDSCRIPT := $(SRCTREE)/board/esd/dasa_sim/u-boot.lds

View File

@ -30,9 +30,6 @@
DECLARE_GLOBAL_DATA_PTR;
/*cmd_boot.c*/
extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
extern void lxt971_no_sleep(void);

View File

@ -236,7 +236,6 @@ static const SMI_REGS init_regs_1024x768 [] =
#define FPGA_DEBUG
#endif
extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
extern void lxt971_no_sleep(void);
/* fpga configuration data - gzip compressed and generated by bin2c */

View File

@ -34,8 +34,6 @@
#if defined(CONFIG_CMD_BSP)
extern int do_bootm (cmd_tbl_t *, int, int, char *[]);
/*
* Command loadpci: wait for signal from host and boot image.
*/

View File

@ -34,7 +34,6 @@
DECLARE_GLOBAL_DATA_PTR;
/* Prototypes */
int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
unsigned long fpga_done_state(void);
unsigned long fpga_init_state(void);

View File

@ -32,7 +32,6 @@
DECLARE_GLOBAL_DATA_PTR;
extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
extern void lxt971_no_sleep(void);
/* fpga configuration data - gzip compressed and generated by bin2c */

View File

@ -29,7 +29,6 @@
/* Prototypes */
int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len);
int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len);

View File

@ -33,7 +33,6 @@
#define FPGA_DEBUG
#endif
extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
extern void lxt971_no_sleep(void);
/* fpga configuration data - gzip compressed and generated by bin2c */

View File

@ -32,8 +32,6 @@
#define FPGA_DEBUG
#endif
extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
/* fpga configuration data - gzip compressed and generated by bin2c */
const unsigned char fpgadata[] =
{

View File

@ -26,10 +26,6 @@
#include <malloc.h>
#include <asm/immap.h>
/* Prototypes */
int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
int checkboard (void) {
ulong val;
uchar val8;

View File

@ -306,7 +306,7 @@ int misc_init_r (void)
#if defined(CONFIG_HAVE_OWN_RESET)
int
do_reset (void *cmdtp, int flag, int argc, char * const argv[])
do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
volatile ioport_t *iop;

View File

@ -1,24 +0,0 @@
#
# (C) Copyright 2000
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
OBJCFLAGS = --set-section-flags=.ppcenv=contents,alloc,load,data

View File

@ -1,28 +0,0 @@
#
# (C) Copyright 2001
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
# ICU862 boards
#
OBJCFLAGS = --set-section-flags=.ppcenv=contents,alloc,load,data

View File

@ -1,27 +0,0 @@
#
# (C) Copyright 2005
# Heiko Schocher, DENX Software Engineering, <hs@denx.de>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
# IDS 8247 Board
#
PLATFORM_CPPFLAGS += -I$(TOPDIR)

View File

@ -1,27 +0,0 @@
#
# (C) Copyright 2004
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
# INKA 4X0 board:
#
LDSCRIPT := $(SRCTREE)/arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds

View File

@ -45,10 +45,10 @@
* memory.
*
* If at some time this restriction doesn't apply anymore, just define
* CONFIG_SYS_ENABLE_SDRAM_CACHE in the board config file and this code should setup
* CONFIG_4xx_DCACHE in the board config file and this code should setup
* everything correctly.
*/
#ifdef CONFIG_SYS_ENABLE_SDRAM_CACHE
#ifdef CONFIG_4xx_DCACHE
#define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */
#else
#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */
@ -220,18 +220,32 @@ phys_size_t initdram (int board_type)
program_tlb(0, CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20,
MY_TLB_WORD2_I_ENABLE);
#if defined(CONFIG_DDR_ECC)
#if defined(CONFIG_4xx_DCACHE)
/*
* If ECC is enabled, initialize the parity bits.
*/
program_ecc(0, CONFIG_SYS_MBYTES_SDRAM << 20, 0);
#else /* CONFIG_4xx_DCACHE */
/*
* Setup 2nd TLB with same physical address but different virtual address
* with cache enabled. This is done for fast ECC generation.
*/
program_tlb(0, CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20, 0);
#ifdef CONFIG_DDR_ECC
/*
* If ECC is enabled, initialize the parity bits.
*/
program_ecc(CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20, 0);
#endif
/*
* Now after initialization (auto-calibration and ECC generation)
* remove the TLB entries with caches enabled and program again with
* desired cache functionality
*/
remove_tlb(CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20);
#endif /* CONFIG_4xx_DCACHE */
#endif /* CONFIG_DDR_ECC */
/*
* Clear possible errors resulting from data-eye-search.

View File

@ -1,24 +0,0 @@
#
# (C) Copyright 2004
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
LDSCRIPT := $(SRCTREE)/arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds

View File

@ -1,24 +0,0 @@
#
# (C) Copyright 2003-2010
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
LDSCRIPT := $(SRCTREE)/board/matrix_vision/mvsmr/u-boot.lds

View File

@ -1,25 +0,0 @@
#
# (C) Copyright 2000
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
# Use board specific linker script
LDSCRIPT := $(SRCTREE)/board/ml2/u-boot.lds

View File

@ -1,27 +0,0 @@
#
# (C) Copyright 2001
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
# MOUSSE boards
#
LDSCRIPT := $(SRCTREE)/board/mousse/u-boot.lds

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