XPedite5370 board support
Initial support for Extreme Engineering Solutions XPedite5370 - a MPC8572-based 3U VPX single board computer with a PMC/XMC site. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
This commit is contained in:
Peter Tyser
Andrew Fleming-AFLEMING
parent
e92739d34e
commit
ccf0fdd02b
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@ -411,6 +411,9 @@ Rune Torgersen <runet@innovsys.com>
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MPC8266ADS MPC8266
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Peter Tyser <ptyser@xes-inc.com>
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XPEDITE5370 MPC8572
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David Updegraff <dave@cray.com>
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1
MAKEALL
1
MAKEALL
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@ -385,6 +385,7 @@ LIST_85xx=" \
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TQM8548 \
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TQM8555 \
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TQM8560 \
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XPEDITE5370 \
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"
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#########################################################################
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3
Makefile
3
Makefile
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@ -2463,6 +2463,9 @@ TQM8560_config: unconfig
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echo "#define CONFIG_BOARDNAME \"TQM$${CTYPE}\"">>$(obj)include/config.h;
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@$(MKCONFIG) -a TQM85xx ppc mpc85xx tqm85xx tqc
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XPEDITE5370_config: unconfig
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@$(MKCONFIG) $(@:_config=) ppc mpc85xx xpedite5370 xes
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#########################################################################
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## MPC86xx Systems
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#########################################################################
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@ -0,0 +1,56 @@
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#
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# (C) Copyright 2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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ifneq ($(OBJTREE),$(SRCTREE))
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$(shell mkdir -p $(obj)board/$(VENDOR)/common)
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endif
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LIB = $(obj)lib$(VENDOR).a
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COBJS-$(CONFIG_MPC8572) += fsl_8572_clk.o
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COBJS-$(CONFIG_MPC85xx) += fsl_85xx_ddr.o
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COBJS-$(CONFIG_FSL_PCI_INIT) += fsl_85xx_pci.o
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SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS-y))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS)
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$(AR) $(ARFLAGS) $@ $(OBJS)
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clean:
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rm -f $(SOBJS) $(OBJS)
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distclean: clean
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rm -f $(LIB) core *.bak $(obj).depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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@ -0,0 +1,51 @@
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/*
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* Copyright 2008 Extreme Engineering Solutions, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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/*
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* Return SYSCLK input frequency - 50 MHz or 66 MHz depending on POR config
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*/
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unsigned long get_board_sys_clk(ulong dummy)
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{
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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u32 gpporcr = gur->gpporcr;
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if (gpporcr & 0x10000)
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return 66666666;
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else
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return 50000000;
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}
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/*
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* Return DDR input clock - synchronous with SYSCLK or 66 MHz
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*/
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unsigned long get_board_ddr_clk(ulong dummy)
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{
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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u32 ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9;
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if (ddr_ratio == 0x7)
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return get_board_sys_clk(dummy);
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return 66666666;
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}
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@ -0,0 +1,93 @@
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/*
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* Copyright 2008 Extreme Engineering Solutions, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/fsl_ddr_sdram.h>
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#include <asm/mmu.h>
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
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extern void ddr_enable_ecc(unsigned int dram_size);
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#endif
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phys_size_t initdram(int board_type)
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{
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phys_size_t dram_size = fsl_ddr_sdram();
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dram_size = setup_ddr_tlbs(dram_size / 0x100000);
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dram_size *= 0x100000;
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
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/* Initialize and enable DDR ECC */
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ddr_enable_ecc(dram_size);
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#endif
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return dram_size;
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}
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#if defined(CONFIG_DDR_ECC) || (CONFIG_NUM_DDR_CONTROLLERS > 1)
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void board_add_ram_info(int use_default)
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{
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#if (CONFIG_NUM_DDR_CONTROLLERS > 1)
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volatile ccsr_ddr_t *ddr1 = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
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#endif
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puts(" (");
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#if (CONFIG_NUM_DDR_CONTROLLERS > 1)
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/* Print interleaving information */
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if (ddr1->cs0_config & 0x20000000) {
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switch ((ddr1->cs0_config >> 24) & 0xf) {
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case 0:
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puts("cache line");
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break;
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case 1:
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puts("page");
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break;
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case 2:
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puts("bank");
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break;
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case 3:
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puts("super-bank");
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break;
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default:
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puts("invalid");
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break;
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}
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} else {
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puts("no");
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}
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puts(" interleaving");
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#endif
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#if (CONFIG_NUM_DDR_CONTROLLERS > 1) && defined(CONFIG_DDR_ECC)
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puts(", ");
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#endif
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#if defined(CONFIG_DDR_ECC)
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puts("ECC enabled");
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#endif
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puts(")");
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}
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#endif /* CONFIG_DDR_ECC || CONFIG_NUM_DDR_CONTROLLERS > 1 */
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@ -0,0 +1,265 @@
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/*
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* Copyright 2008 Extreme Engineering Solutions, Inc.
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* Copyright 2007-2008 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <pci.h>
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#include <asm/immap_85xx.h>
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#include <asm/immap_fsl_pci.h>
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#include <libfdt.h>
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#include <fdt_support.h>
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extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
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extern void fsl_pci_init(struct pci_controller *hose);
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int first_free_busno = 0;
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#ifdef CONFIG_PCIE1
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static struct pci_controller pcie1_hose;
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#endif
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#ifdef CONFIG_PCIE2
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static struct pci_controller pcie2_hose;
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#endif
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#ifdef CONFIG_PCIE3
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static struct pci_controller pcie3_hose;
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#endif
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/* Correlate host/agent POR bits to usable info. Table 4-14 */
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struct host_agent_cfg_t {
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uchar pcie_root[3];
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uchar rio_host;
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} host_agent_cfg[8] = {
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{{0, 0, 0}, 0},
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{{0, 1, 1}, 1},
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{{1, 0, 1}, 0},
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{{1, 1, 0}, 1},
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{{0, 0, 1}, 0},
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{{0, 1, 0}, 1},
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{{1, 0, 0}, 0},
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{{1, 1, 1}, 1}
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};
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/* Correlate port width POR bits to usable info. Table 4-15 */
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struct io_port_cfg_t {
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uchar pcie_width[3];
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uchar rio_width;
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} io_port_cfg[16] = {
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{{0, 0, 0}, 0},
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{{0, 0, 0}, 0},
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{{4, 0, 0}, 0},
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{{4, 4, 0}, 0},
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{{0, 0, 0}, 0},
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{{0, 0, 0}, 0},
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{{0, 0, 0}, 4},
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{{4, 2, 2}, 0},
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{{0, 0, 0}, 0},
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{{0, 0, 0}, 0},
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{{0, 0, 0}, 0},
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{{4, 0, 0}, 4},
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{{4, 0, 0}, 4},
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{{0, 0, 0}, 4},
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{{0, 0, 0}, 4},
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{{8, 0, 0}, 0},
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};
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void pci_init_board(void)
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{
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struct pci_controller *hose;
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volatile ccsr_fsl_pci_t *pci;
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int width;
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int host;
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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uint devdisr = gur->devdisr;
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uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
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uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
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struct pci_region *r;
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debug(" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
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devdisr, io_sel, host_agent);
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#ifdef CONFIG_PCIE1
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pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
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hose = &pcie1_hose;
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host = host_agent_cfg[host_agent].pcie_root[0];
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width = io_port_cfg[io_sel].pcie_width[0];
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r = hose->regions;
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if (width && !(devdisr & MPC85xx_DEVDISR_PCIE)) {
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printf("\n PCIE1 connected as %s (x%d)",
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host ? "Root Complex" : "End Point", width);
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if (pci->pme_msg_det) {
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pci->pme_msg_det = 0xffffffff;
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debug(" with errors. Clearing. Now 0x%08x",
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pci->pme_msg_det);
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}
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printf("\n");
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/* inbound */
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r += fsl_pci_setup_inbound_windows(r);
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/* outbound memory */
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pci_set_region(r++,
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CONFIG_SYS_PCIE1_MEM_BASE,
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CONFIG_SYS_PCIE1_MEM_PHYS,
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CONFIG_SYS_PCIE1_MEM_SIZE,
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PCI_REGION_MEM);
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/* outbound io */
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pci_set_region(r++,
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CONFIG_SYS_PCIE1_IO_BASE,
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CONFIG_SYS_PCIE1_IO_PHYS,
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CONFIG_SYS_PCIE1_IO_SIZE,
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PCI_REGION_IO);
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hose->region_count = r - hose->regions;
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hose->first_busno = first_free_busno;
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pci_setup_indirect(hose, (int)&pci->cfg_addr,
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(int) &pci->cfg_data);
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fsl_pci_init(hose);
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first_free_busno = hose->last_busno+1;
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printf(" PCIE1 on bus %02x - %02x\n",
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hose->first_busno, hose->last_busno);
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}
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#else
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gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
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#endif /* CONFIG_PCIE1 */
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#ifdef CONFIG_PCIE2
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pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
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hose = &pcie2_hose;
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host = host_agent_cfg[host_agent].pcie_root[1];
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width = io_port_cfg[io_sel].pcie_width[1];
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r = hose->regions;
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|
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if (width && !(devdisr & MPC85xx_DEVDISR_PCIE2)) {
|
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printf("\n PCIE2 connected as %s (x%d)",
|
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host ? "Root Complex" : "End Point", width);
|
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if (pci->pme_msg_det) {
|
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pci->pme_msg_det = 0xffffffff;
|
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debug(" with errors. Clearing. Now 0x%08x",
|
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pci->pme_msg_det);
|
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}
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printf("\n");
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|
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/* inbound */
|
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r += fsl_pci_setup_inbound_windows(r);
|
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|
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/* outbound memory */
|
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pci_set_region(r++,
|
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CONFIG_SYS_PCIE2_MEM_BASE,
|
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CONFIG_SYS_PCIE2_MEM_PHYS,
|
||||
CONFIG_SYS_PCIE2_MEM_SIZE,
|
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PCI_REGION_MEM);
|
||||
|
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/* outbound io */
|
||||
pci_set_region(r++,
|
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CONFIG_SYS_PCIE2_IO_BASE,
|
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CONFIG_SYS_PCIE2_IO_PHYS,
|
||||
CONFIG_SYS_PCIE2_IO_SIZE,
|
||||
PCI_REGION_IO);
|
||||
|
||||
hose->region_count = r - hose->regions;
|
||||
|
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hose->first_busno = first_free_busno;
|
||||
pci_setup_indirect(hose, (int)&pci->cfg_addr,
|
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(int)&pci->cfg_data);
|
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|
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fsl_pci_init(hose);
|
||||
first_free_busno = hose->last_busno+1;
|
||||
printf(" PCIE2 on bus %02x - %02x\n",
|
||||
hose->first_busno, hose->last_busno);
|
||||
|
||||
}
|
||||
#else
|
||||
gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */
|
||||
#endif /* CONFIG_PCIE2 */
|
||||
|
||||
#ifdef CONFIG_PCIE3
|
||||
pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
|
||||
hose = &pcie3_hose;
|
||||
host = host_agent_cfg[host_agent].pcie_root[2];
|
||||
width = io_port_cfg[io_sel].pcie_width[2];
|
||||
r = hose->regions;
|
||||
|
||||
if (width && !(devdisr & MPC85xx_DEVDISR_PCIE3)) {
|
||||
printf("\n PCIE3 connected as %s (x%d)",
|
||||
host ? "Root Complex" : "End Point", width);
|
||||
if (pci->pme_msg_det) {
|
||||
pci->pme_msg_det = 0xffffffff;
|
||||
debug(" with errors. Clearing. Now 0x%08x",
|
||||
pci->pme_msg_det);
|
||||
}
|
||||
printf("\n");
|
||||
|
||||
/* inbound */
|
||||
r += fsl_pci_setup_inbound_windows(r);
|
||||
|
||||
/* outbound memory */
|
||||
pci_set_region(r++,
|
||||
CONFIG_SYS_PCIE3_MEM_BASE,
|
||||
CONFIG_SYS_PCIE3_MEM_PHYS,
|
||||
CONFIG_SYS_PCIE3_MEM_SIZE,
|
||||
PCI_REGION_MEM);
|
||||
|
||||
/* outbound io */
|
||||
pci_set_region(r++,
|
||||
CONFIG_SYS_PCIE3_IO_BASE,
|
||||
CONFIG_SYS_PCIE3_IO_PHYS,
|
||||
CONFIG_SYS_PCIE3_IO_SIZE,
|
||||
PCI_REGION_IO);
|
||||
|
||||
hose->region_count = r - hose->regions;
|
||||
|
||||
hose->first_busno = first_free_busno;
|
||||
pci_setup_indirect(hose, (int)&pci->cfg_addr,
|
||||
(int)&pci->cfg_data);
|
||||
|
||||
fsl_pci_init(hose);
|
||||
first_free_busno = hose->last_busno+1;
|
||||
printf(" PCIE3 on bus %02x - %02x\n",
|
||||
hose->first_busno, hose->last_busno);
|
||||
}
|
||||
#else
|
||||
gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */
|
||||
#endif /* CONFIG_PCIE3 */
|
||||
}
|
||||
|
||||
#if defined(CONFIG_OF_BOARD_SETUP)
|
||||
extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
|
||||
struct pci_controller *hose);
|
||||
|
||||
void ft_board_pci_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
#ifdef CONFIG_PCIE1
|
||||
ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
|
||||
#endif
|
||||
#ifdef CONFIG_PCIE2
|
||||
ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
|
||||
#endif
|
||||
#ifdef CONFIG_PCIE3
|
||||
ft_fsl_pci_setup(blob, "pci0", &pcie3_hose);
|
||||
#endif
|
||||
}
|
||||
#endif /* CONFIG_OF_BOARD_SETUP */
|
||||
|
|
@ -0,0 +1,45 @@
|
|||
#
|
||||
# Copyright 2008 Extreme Engineering Solutions, Inc.
|
||||
# Copyright 2007 Freescale Semiconductor, Inc.
|
||||
# (C) Copyright 2001-2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS-y += $(BOARD).o
|
||||
COBJS-y += ddr.o
|
||||
COBJS-y += law.o
|
||||
COBJS-y += tlb.o
|
||||
|
||||
SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS-y))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS-y))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
|
||||
$(AR) $(ARFLAGS) $@ $(OBJS)
|
||||
|
||||
clean:
|
||||
rm -f $(OBJS) $(SOBJS)
|
||||
|
||||
distclean: clean
|
||||
rm -f $(LIB) core *.bak .depend
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
|
|
@ -0,0 +1,35 @@
|
|||
#
|
||||
# Copyright 2008 Extreme Engineering Solutions, Inc.
|
||||
# Copyright 2007-2008 Freescale Semiconductor, Inc.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
#
|
||||
# xpedite5370 board
|
||||
#
|
||||
ifndef TEXT_BASE
|
||||
TEXT_BASE = 0xfff80000
|
||||
endif
|
||||
|
||||
PLATFORM_RELFLAGS += -mrelocatable
|
||||
|
||||
PLATFORM_CPPFLAGS += -DCONFIG_E500=1
|
||||
PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
|
||||
PLATFORM_CPPFLAGS += -DCONFIG_MPC8572=1
|
||||
|
|
@ -0,0 +1,270 @@
|
|||
/*
|
||||
* Copyright 2008 Extreme Engineering Solutions, Inc.
|
||||
* Copyright 2008 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <i2c.h>
|
||||
|
||||
#include <asm/fsl_ddr_sdram.h>
|
||||
#include <asm/fsl_ddr_dimm_params.h>
|
||||
|
||||
static void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
|
||||
{
|
||||
i2c_read(i2c_address, SPD_EEPROM_OFFSET, 2, (uchar *)spd,
|
||||
sizeof(ddr2_spd_eeprom_t));
|
||||
}
|
||||
|
||||
unsigned int fsl_ddr_get_mem_data_rate(void)
|
||||
{
|
||||
return get_ddr_freq(0);
|
||||
}
|
||||
|
||||
void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
|
||||
unsigned int ctrl_num)
|
||||
{
|
||||
unsigned int i;
|
||||
unsigned int i2c_address = 0;
|
||||
|
||||
for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
|
||||
if (ctrl_num == 0)
|
||||
i2c_address = SPD_EEPROM_ADDRESS1;
|
||||
if (ctrl_num == 1)
|
||||
i2c_address = SPD_EEPROM_ADDRESS2;
|
||||
get_spd(&(ctrl_dimms_spd[i]), i2c_address);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* There are four board-specific SDRAM timing parameters which must be
|
||||
* calculated based on the particular PCB artwork. These are:
|
||||
* 1.) CPO (Read Capture Delay)
|
||||
* - TIMING_CFG_2 register
|
||||
* Source: Calculation based on board trace lengths and
|
||||
* chip-specific internal delays.
|
||||
* 2.) WR_DATA_DELAY (Write Command to Data Strobe Delay)
|
||||
* - TIMING_CFG_2 register
|
||||
* Source: Calculation based on board trace lengths.
|
||||
* Unless clock and DQ lanes are very different
|
||||
* lengths (>2"), this should be set to the nominal value
|
||||
* of 1/2 clock delay.
|
||||
* 3.) CLK_ADJUST (Clock and Addr/Cmd alignment control)
|
||||
* - DDR_SDRAM_CLK_CNTL register
|
||||
* Source: Signal Integrity Simulations
|
||||
* 4.) 2T Timing on Addr/Ctl
|
||||
* - TIMING_CFG_2 register
|
||||
* Source: Signal Integrity Simulations
|
||||
* Usually only needed with heavy load/very high speed (>DDR2-800)
|
||||
*
|
||||
* ====== XPedite5370 DDR2-600 read delay calculations ======
|
||||
*
|
||||
* See Freescale's App Note AN2583 as refrence. This document also
|
||||
* contains the chip-specific delays for 8548E, 8572, etc.
|
||||
*
|
||||
* For MPC8572E
|
||||
* Minimum chip delay (Ch 0): 1.372ns
|
||||
* Maximum chip delay (Ch 0): 2.914ns
|
||||
* Minimum chip delay (Ch 1): 1.220ns
|
||||
* Maximum chip delay (Ch 1): 2.595ns
|
||||
*
|
||||
* CLK adjust = 5 (from simulations) = 5/8* 3.33ns = 2080ps
|
||||
*
|
||||
* Minimum delay calc (Ch 0):
|
||||
* clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
|
||||
* 2.3" * 180 - 400ps + 1.9" * 180 + 2080ps + 1372ps
|
||||
* = 3808ps
|
||||
* = 3.808ns
|
||||
*
|
||||
* Maximum delay calc (Ch 0):
|
||||
* clock prop + dram skew + max dqs prop delay + clk_adjust + max chip dly
|
||||
* 2.3" * 180 + 400ps + 2.4" * 180 + 2080ps + 2914ps
|
||||
* = 6240ps
|
||||
* = 6.240ns
|
||||
*
|
||||
* Minimum delay calc (Ch 1):
|
||||
* clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
|
||||
* 1.46" * 180- 400ps + 0.7" * 180 + 2080ps + 1220ps
|
||||
* = 3288ps
|
||||
* = 3.288ns
|
||||
*
|
||||
* Maximum delay calc (Ch 1):
|
||||
* clock prop + dram skew + max dqs prop delay + clk_adjust + min chip dly
|
||||
* 1.46" * 180+ 400ps + 1.1" * 180 + 2080ps + 2595ps
|
||||
* = 5536ps
|
||||
* = 5.536ns
|
||||
*
|
||||
* Ch.0: 3.808ns to 6.240ns additional delay needed (pick 5ns as target)
|
||||
* This is 1.5 clock cycles, pick CPO = READ_LAT + 3/2 (0x8)
|
||||
* Ch.1: 3.288ns to 5.536ns additional delay needed (pick 4.4ns as target)
|
||||
* This is 1.32 clock cycles, pick CPO = READ_LAT + 5/4 (0x7)
|
||||
*
|
||||
*
|
||||
* ====== XPedite5370 DDR2-800 read delay calculations ======
|
||||
*
|
||||
* See Freescale's App Note AN2583 as refrence. This document also
|
||||
* contains the chip-specific delays for 8548E, 8572, etc.
|
||||
*
|
||||
* For MPC8572E
|
||||
* Minimum chip delay (Ch 0): 1.372ns
|
||||
* Maximum chip delay (Ch 0): 2.914ns
|
||||
* Minimum chip delay (Ch 1): 1.220ns
|
||||
* Maximum chip delay (Ch 1): 2.595ns
|
||||
*
|
||||
* CLK adjust = 5 (from simulations) = 5/8* 2.5ns = 1563ps
|
||||
*
|
||||
* Minimum delay calc (Ch 0):
|
||||
* clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
|
||||
* 2.3" * 180 - 350ps + 1.9" * 180 + 1563ps + 1372ps
|
||||
* = 3341ps
|
||||
* = 3.341ns
|
||||
*
|
||||
* Maximum delay calc (Ch 0):
|
||||
* clock prop + dram skew + max dqs prop delay + clk_adjust + max chip dly
|
||||
* 2.3" * 180 + 350ps + 2.4" * 180 + 1563ps + 2914ps
|
||||
* = 5673ps
|
||||
* = 5.673ns
|
||||
*
|
||||
* Minimum delay calc (Ch 1):
|
||||
* clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
|
||||
* 1.46" * 180- 350ps + 0.7" * 180 + 1563ps + 1220ps
|
||||
* = 2822ps
|
||||
* = 2.822ns
|
||||
*
|
||||
* Maximum delay calc (Ch 1):
|
||||
* clock prop + dram skew + max dqs prop delay + clk_adjust + min chip dly
|
||||
* 1.46" * 180+ 350ps + 1.1" * 180 + 1563ps + 2595ps
|
||||
* = 4968ps
|
||||
* = 4.968ns
|
||||
*
|
||||
* Ch.0: 3.341ns to 5.673ns additional delay needed (pick 4.5ns as target)
|
||||
* This is 1.8 clock cycles, pick CPO = READ_LAT + 7/4 (0x9)
|
||||
* Ch.1: 2.822ns to 4.968ns additional delay needed (pick 3.9ns as target)
|
||||
* This is 1.56 clock cycles, pick CPO = READ_LAT + 3/2 (0x8)
|
||||
*
|
||||
* Write latency (WR_DATA_DELAY) is calculated by doing the following:
|
||||
*
|
||||
* The DDR SDRAM specification requires DQS be received no sooner than
|
||||
* 75% of an SDRAM clock period—and no later than 125% of a clock
|
||||
* period—from the capturing clock edge of the command/address at the
|
||||
* SDRAM.
|
||||
*
|
||||
* Based on the above tracelengths, the following are calculated:
|
||||
* Ch. 0 8572 to DRAM propagation (DQ lanes) : 1.9" * 180 = 0.342ns
|
||||
* Ch. 0 8572 to DRAM propagation (CLKs) : 2.3" * 180 = 0.414ns
|
||||
* Ch. 1 8572 to DRAM propagation (DQ lanes) : 0.7" * 180 = 0.126ns
|
||||
* Ch. 1 8572 to DRAM propagation (CLKs ) : 1.47" * 180 = 0.264ns
|
||||
*
|
||||
* Difference in arrival time CLK vs. DQS:
|
||||
* Ch. 0 0.072ns
|
||||
* Ch. 1 0.138ns
|
||||
*
|
||||
* Both of these values are much less than 25% of the clock
|
||||
* period at DDR2-600 or DDR2-800, so no additional delay is needed over
|
||||
* the 1/2 cycle which normally aligns the first DQS transition
|
||||
* exactly WL (CAS latency minus one cycle) after the CAS strobe.
|
||||
* See Figure 9-53 in MPC8572E manual: "1/2 delay" in Freescale's
|
||||
* terminology corresponds to exactly one clock period delay after
|
||||
* the CAS strobe. (due to the fact that the "delay" is referenced
|
||||
* from the *falling* edge of the CLK, just after the rising edge
|
||||
* which the CAS strobe is latched on.
|
||||
*/
|
||||
|
||||
typedef struct board_memctl_options {
|
||||
uint16_t datarate_mhz_low;
|
||||
uint16_t datarate_mhz_high;
|
||||
uint8_t clk_adjust;
|
||||
uint8_t cpo_override;
|
||||
uint8_t write_data_delay;
|
||||
} board_memctl_options_t;
|
||||
|
||||
static struct board_memctl_options bopts_ctrl[][2] = {
|
||||
{
|
||||
/* Controller 0 */
|
||||
{
|
||||
/* DDR2 600/667 */
|
||||
.datarate_mhz_low = 500,
|
||||
.datarate_mhz_high = 750,
|
||||
.clk_adjust = 5,
|
||||
.cpo_override = 8,
|
||||
.write_data_delay = 2,
|
||||
},
|
||||
{
|
||||
/* DDR2 800 */
|
||||
.datarate_mhz_low = 750,
|
||||
.datarate_mhz_high = 850,
|
||||
.clk_adjust = 5,
|
||||
.cpo_override = 9,
|
||||
.write_data_delay = 2,
|
||||
},
|
||||
},
|
||||
{
|
||||
/* Controller 1 */
|
||||
{
|
||||
/* DDR2 600/667 */
|
||||
.datarate_mhz_low = 500,
|
||||
.datarate_mhz_high = 750,
|
||||
.clk_adjust = 5,
|
||||
.cpo_override = 7,
|
||||
.write_data_delay = 2,
|
||||
},
|
||||
{
|
||||
/* DDR2 800 */
|
||||
.datarate_mhz_low = 750,
|
||||
.datarate_mhz_high = 850,
|
||||
.clk_adjust = 5,
|
||||
.cpo_override = 8,
|
||||
.write_data_delay = 2,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
void fsl_ddr_board_options(memctl_options_t *popts,
|
||||
dimm_params_t *pdimm,
|
||||
unsigned int ctrl_num)
|
||||
{
|
||||
struct board_memctl_options *bopts = bopts_ctrl[ctrl_num];
|
||||
sys_info_t sysinfo;
|
||||
int i;
|
||||
unsigned int datarate;
|
||||
|
||||
get_sys_info(&sysinfo);
|
||||
datarate = sysinfo.freqDDRBus / 1000 / 1000;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(bopts_ctrl[ctrl_num]); i++) {
|
||||
if ((bopts[i].datarate_mhz_low <= datarate) &&
|
||||
(bopts[i].datarate_mhz_high >= datarate)) {
|
||||
debug("controller %d:\n", ctrl_num);
|
||||
debug(" clk_adjust = %d\n", bopts[i].clk_adjust);
|
||||
debug(" cpo = %d\n", bopts[i].cpo_override);
|
||||
debug(" write_data_delay = %d\n",
|
||||
bopts[i].write_data_delay);
|
||||
popts->clk_adjust = bopts[i].clk_adjust;
|
||||
popts->cpo_override = bopts[i].cpo_override;
|
||||
popts->write_data_delay = bopts[i].write_data_delay;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Factors to consider for half-strength driver enable:
|
||||
* - number of DIMMs installed
|
||||
*/
|
||||
popts->half_strength_driver_enable = 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,54 @@
|
|||
/*
|
||||
* Copyright 2008 Extreme Engineering Solutions, Inc.
|
||||
* Copyright 2008 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* (C) Copyright 2000
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/fsl_law.h>
|
||||
#include <asm/mmu.h>
|
||||
|
||||
/*
|
||||
* Notes:
|
||||
* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
|
||||
* If flash is 8M at default position (last 8M), no LAW needed.
|
||||
*/
|
||||
|
||||
struct law_entry law_table[] = {
|
||||
SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
|
||||
SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
|
||||
#ifdef CONFIG_SYS_PCIE1_MEM_PHYS
|
||||
SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_1G, LAW_TRGT_IF_PCIE_1),
|
||||
SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1),
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_PCIE2_MEM_PHYS
|
||||
SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_2),
|
||||
SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_2),
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_PCIE3_MEM_PHYS
|
||||
SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_3),
|
||||
SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_3),
|
||||
#endif
|
||||
};
|
||||
|
||||
int num_law_entries = ARRAY_SIZE(law_table);
|
||||
|
|
@ -0,0 +1,94 @@
|
|||
/*
|
||||
* Copyright 2008 Extreme Engineering Solutions, Inc.
|
||||
* Copyright 2008 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* (C) Copyright 2000
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/mmu.h>
|
||||
|
||||
struct fsl_e_tlb_entry tlb_table[] = {
|
||||
/* TLB 0 - for temp stack in cache */
|
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
|
||||
CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
|
||||
CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
|
||||
CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
|
||||
/* W**G* - NOR flashes */
|
||||
/* This will be changed to *I*G* after relocation to RAM. */
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE2, CONFIG_SYS_FLASH_BASE2,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
|
||||
0, 0, BOOKE_PAGESZ_256M, 1),
|
||||
|
||||
/* *I*G* - CCSRBAR */
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 1, BOOKE_PAGESZ_1M, 1),
|
||||
|
||||
/* *I*G* - NAND flash */
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 2, BOOKE_PAGESZ_1M, 1),
|
||||
|
||||
#ifdef CONFIG_PCIE1
|
||||
/* *I*G* - PCIe */
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_PHYS, CONFIG_SYS_PCIE1_MEM_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 3, BOOKE_PAGESZ_1G, 1),
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PCIE2
|
||||
/* *I*G* - PCIe */
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_PHYS, CONFIG_SYS_PCIE2_MEM_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 4, BOOKE_PAGESZ_256M, 1),
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PCIE3
|
||||
/* *I*G* - PCIe */
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_PHYS, CONFIG_SYS_PCIE3_MEM_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 5, BOOKE_PAGESZ_256M, 1),
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || defined(CONFIG_PCIE3)
|
||||
/* *I*G* - PCIe */
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_PHYS, CONFIG_SYS_PCIE1_IO_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 6, BOOKE_PAGESZ_64M, 1),
|
||||
#endif
|
||||
|
||||
};
|
||||
|
||||
int num_tlb_entries = ARRAY_SIZE(tlb_table);
|
||||
|
|
@ -0,0 +1,145 @@
|
|||
/*
|
||||
* Copyright 2008 Extreme Engineering Solutions, Inc.
|
||||
* Copyright 2007-2008 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(powerpc)
|
||||
/* Do we need any of these for elf?
|
||||
__DYNAMIC = 0; */
|
||||
PHDRS
|
||||
{
|
||||
text PT_LOAD;
|
||||
bss PT_LOAD;
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
/* Read-only sections, merged into text segment: */
|
||||
. = + SIZEOF_HEADERS;
|
||||
.interp : { *(.interp) }
|
||||
.hash : { *(.hash) }
|
||||
.dynsym : { *(.dynsym) }
|
||||
.dynstr : { *(.dynstr) }
|
||||
.rel.text : { *(.rel.text) }
|
||||
.rela.text : { *(.rela.text) }
|
||||
.rel.data : { *(.rel.data) }
|
||||
.rela.data : { *(.rela.data) }
|
||||
.rel.rodata : { *(.rel.rodata) }
|
||||
.rela.rodata : { *(.rela.rodata) }
|
||||
.rel.got : { *(.rel.got) }
|
||||
.rela.got : { *(.rela.got) }
|
||||
.rel.ctors : { *(.rel.ctors) }
|
||||
.rela.ctors : { *(.rela.ctors) }
|
||||
.rel.dtors : { *(.rel.dtors) }
|
||||
.rela.dtors : { *(.rela.dtors) }
|
||||
.rel.bss : { *(.rel.bss) }
|
||||
.rela.bss : { *(.rela.bss) }
|
||||
.rel.plt : { *(.rel.plt) }
|
||||
.rela.plt : { *(.rela.plt) }
|
||||
.init : { *(.init) }
|
||||
.plt : { *(.plt) }
|
||||
.text :
|
||||
{
|
||||
*(.text)
|
||||
*(.got1)
|
||||
} :text
|
||||
_etext = .;
|
||||
PROVIDE (etext = .);
|
||||
.rodata :
|
||||
{
|
||||
*(.rodata)
|
||||
*(.rodata1)
|
||||
*(.rodata.str1.4)
|
||||
*(.eh_frame)
|
||||
} :text
|
||||
.fini : { *(.fini) } =0
|
||||
.ctors : { *(.ctors) }
|
||||
.dtors : { *(.dtors) }
|
||||
|
||||
/* Read-write section, merged into data segment: */
|
||||
. = (. + 0x00FF) & 0xFFFFFF00;
|
||||
_erotext = .;
|
||||
PROVIDE (erotext = .);
|
||||
.reloc :
|
||||
{
|
||||
*(.got)
|
||||
_GOT2_TABLE_ = .;
|
||||
*(.got2)
|
||||
_FIXUP_TABLE_ = .;
|
||||
*(.fixup)
|
||||
}
|
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
|
||||
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data)
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata2)
|
||||
*(.dynamic)
|
||||
CONSTRUCTORS
|
||||
}
|
||||
_edata = .;
|
||||
PROVIDE (edata = .);
|
||||
|
||||
. = .;
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
. = .;
|
||||
__start___ex_table = .;
|
||||
__ex_table : { *(__ex_table) }
|
||||
__stop___ex_table = .;
|
||||
|
||||
. = ALIGN(256);
|
||||
__init_begin = .;
|
||||
.text.init : { *(.text.init) }
|
||||
.data.init : { *(.data.init) }
|
||||
. = ALIGN(256);
|
||||
__init_end = .;
|
||||
|
||||
.bootpg ADDR(.text) + 0x7f000 :
|
||||
{
|
||||
cpu/mpc85xx/start.o (.bootpg)
|
||||
} :text = 0xffff
|
||||
|
||||
.resetvec ADDR(.text) + 0x7fffc :
|
||||
{
|
||||
*(.resetvec)
|
||||
} :text = 0xffff
|
||||
|
||||
. = ADDR(.text) + 0x80000;
|
||||
|
||||
__bss_start = .;
|
||||
.bss (NOLOAD) :
|
||||
{
|
||||
*(.sbss) *(.scommon)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(COMMON)
|
||||
} :bss
|
||||
|
||||
. = ALIGN(4);
|
||||
_end = . ;
|
||||
PROVIDE (end = .);
|
||||
}
|
||||
|
|
@ -0,0 +1,128 @@
|
|||
/*
|
||||
* Copyright 2008 Extreme Engineering Solutions, Inc.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/mmu.h>
|
||||
#include <asm/immap_85xx.h>
|
||||
#include <asm/immap_fsl_pci.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/cache.h>
|
||||
#include <libfdt.h>
|
||||
#include <fdt_support.h>
|
||||
#include <pca953x.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
extern void ft_board_pci_setup(void *blob, bd_t *bd);
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
char *s;
|
||||
|
||||
printf("Board: X-ES %s 3U VPX SBC\n", CONFIG_SYS_BOARD_NAME);
|
||||
printf(" ");
|
||||
s = getenv("board_rev");
|
||||
if (s)
|
||||
printf("Rev %s, ", s);
|
||||
s = getenv("serial#");
|
||||
if (s)
|
||||
printf("Serial# %s, ", s);
|
||||
s = getenv("board_cfg");
|
||||
if (s)
|
||||
printf("Cfg %s", s);
|
||||
printf("\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void flash_cs_fixup(void)
|
||||
{
|
||||
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
|
||||
int flash_sel;
|
||||
|
||||
/*
|
||||
* Print boot dev and swap flash flash chip selects if booted from 2nd
|
||||
* flash. Swapping chip selects presents user with a common memory
|
||||
* map regardless of which flash was booted from.
|
||||
*/
|
||||
flash_sel = !((pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) &
|
||||
CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS));
|
||||
printf("FLASH: Executed from FLASH%d\n", flash_sel ? 2 : 1);
|
||||
|
||||
if (flash_sel) {
|
||||
lbc->br0 = CONFIG_SYS_BR1_PRELIM;
|
||||
lbc->or0 = CONFIG_SYS_OR1_PRELIM;
|
||||
|
||||
lbc->br1 = CONFIG_SYS_BR0_PRELIM;
|
||||
lbc->or1 = CONFIG_SYS_OR0_PRELIM;
|
||||
}
|
||||
}
|
||||
|
||||
int board_early_init_r(void)
|
||||
{
|
||||
/* Initialize PCA9557 devices */
|
||||
pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0);
|
||||
pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR1, 0xff, 0);
|
||||
pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0);
|
||||
pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0);
|
||||
|
||||
/*
|
||||
* Remap NOR flash region to caching-inhibited
|
||||
* so that flash can be erased/programmed properly.
|
||||
*/
|
||||
|
||||
/* Flush d-cache and invalidate i-cache of any FLASH data */
|
||||
flush_dcache();
|
||||
invalidate_icache();
|
||||
|
||||
/* Invalidate existing TLB entry for NOR flash */
|
||||
disable_tlb(0);
|
||||
set_tlb(1, (CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
|
||||
(CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 0, BOOKE_PAGESZ_256M, 1);
|
||||
|
||||
flash_cs_fixup();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_OF_BOARD_SETUP)
|
||||
void ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
#ifdef CONFIG_PCI
|
||||
ft_board_pci_setup(blob, bd);
|
||||
#endif
|
||||
ft_cpu_setup(blob, bd);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MP
|
||||
extern void cpu_mp_lmb_reserve(struct lmb *lmb);
|
||||
|
||||
void board_lmb_reserve(struct lmb *lmb)
|
||||
{
|
||||
cpu_mp_lmb_reserve(lmb);
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,589 @@
|
|||
/*
|
||||
* Copyright 2008 Extreme Engineering Solutions, Inc.
|
||||
* Copyright 2007-2008 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* xpedite5370 board configuration file
|
||||
*/
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
*/
|
||||
#define CONFIG_BOOKE 1 /* BOOKE */
|
||||
#define CONFIG_E500 1 /* BOOKE e500 family */
|
||||
#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
|
||||
#define CONFIG_MPC8572 1
|
||||
#define CONFIG_XPEDITE5370 1
|
||||
#define CONFIG_SYS_BOARD_NAME "XPedite5370"
|
||||
#define CONFIG_NUM_CPUS 2 /* 2 Cores */
|
||||
#define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */
|
||||
#define CONFIG_RELOC_FIXUP_WORKS /* Fully relocate to SDRAM */
|
||||
|
||||
#define CONFIG_PCI 1 /* Enable PCI/PCIE */
|
||||
#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
|
||||
#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
|
||||
#define CONFIG_PCIE1 1 /* PCIE controler 1 */
|
||||
#define CONFIG_PCIE2 1 /* PCIE controler 2 */
|
||||
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
|
||||
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
|
||||
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
|
||||
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
|
||||
|
||||
/*
|
||||
* DDR config
|
||||
*/
|
||||
#define CONFIG_FSL_DDR2
|
||||
#undef CONFIG_FSL_DDR_INTERACTIVE
|
||||
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
|
||||
#define CONFIG_DDR_SPD
|
||||
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
|
||||
#define SPD_EEPROM_ADDRESS1 0x54 /* Both channels use the */
|
||||
#define SPD_EEPROM_ADDRESS2 0x54 /* same SPD data */
|
||||
#define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */
|
||||
#define CONFIG_NUM_DDR_CONTROLLERS 2
|
||||
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
|
||||
#define CONFIG_CHIP_SELECTS_PER_CTRL 1
|
||||
#define CONFIG_DDR_ECC
|
||||
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
|
||||
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
|
||||
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
|
||||
#define CONFIG_VERY_BIG_RAM
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
extern unsigned long get_board_sys_clk(unsigned long dummy);
|
||||
extern unsigned long get_board_ddr_clk(unsigned long dummy);
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */
|
||||
#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */
|
||||
|
||||
/*
|
||||
* These can be toggled for performance analysis, otherwise use default.
|
||||
*/
|
||||
#define CONFIG_L2_CACHE /* toggle L2 cache */
|
||||
#define CONFIG_BTB /* toggle branch predition */
|
||||
#define CONFIG_ENABLE_36BIT_PHYS 1
|
||||
|
||||
/*
|
||||
* Base addresses -- Note these are effective addresses where the
|
||||
* actual resources get mapped (not physical addresses)
|
||||
*/
|
||||
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
|
||||
#define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */
|
||||
#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
|
||||
#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
|
||||
#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR + 0xa000)
|
||||
#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR + 0x9000)
|
||||
|
||||
/*
|
||||
* Diagnostics
|
||||
*/
|
||||
#define CONFIG_SYS_ALT_MEMTEST
|
||||
#define CONFIG_SYS_MEMTEST_START 0x10000000
|
||||
#define CONFIG_SYS_MEMTEST_END 0x20000000
|
||||
|
||||
/*
|
||||
* Memory map
|
||||
* 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
|
||||
* 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable
|
||||
* 0xc000_0000 0xcfff_ffff PCIe2 Mem 256M non-cacheable
|
||||
* 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
|
||||
* 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable
|
||||
* 0xe880_0000 0xe8ff_ffff PCIe2 IO 8M non-cacheable
|
||||
* 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
|
||||
* 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
|
||||
* 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable
|
||||
* 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable
|
||||
*/
|
||||
|
||||
#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_4 | LCRR_EADC_3)
|
||||
|
||||
/*
|
||||
* NAND flash configuration
|
||||
*/
|
||||
#define CONFIG_SYS_NAND_BASE 0xef800000
|
||||
#define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */
|
||||
|
||||
/*
|
||||
* NOR flash configuration
|
||||
*/
|
||||
#define CONFIG_SYS_FLASH_BASE 0xf8000000
|
||||
#define CONFIG_SYS_FLASH_BASE2 0xf0000000
|
||||
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
|
||||
#define CONFIG_FLASH_CFI_DRIVER
|
||||
#define CONFIG_SYS_FLASH_CFI
|
||||
#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \
|
||||
{0xf7f40000, 0xc0000} }
|
||||
#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
|
||||
|
||||
/*
|
||||
* Chip select configuration
|
||||
*/
|
||||
/* NOR Flash 0 on CS0 */
|
||||
#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
|
||||
BR_PS_16 | \
|
||||
BR_V)
|
||||
#define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB | \
|
||||
OR_GPCM_CSNT | \
|
||||
OR_GPCM_XACS | \
|
||||
OR_GPCM_ACS_DIV2 | \
|
||||
OR_GPCM_SCY_8 | \
|
||||
OR_GPCM_TRLX | \
|
||||
OR_GPCM_EHTR | \
|
||||
OR_GPCM_EAD)
|
||||
|
||||
/* NOR Flash 1 on CS1 */
|
||||
#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \
|
||||
BR_PS_16 | \
|
||||
BR_V)
|
||||
#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
|
||||
|
||||
/* NAND flash on CS2 */
|
||||
#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \
|
||||
(2<<BR_DECC_SHIFT) | \
|
||||
BR_PS_8 | \
|
||||
BR_MS_FCM | \
|
||||
BR_V)
|
||||
|
||||
/* NAND flash on CS2 */
|
||||
#define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB | \
|
||||
OR_FCM_PGS | \
|
||||
OR_FCM_CSCT | \
|
||||
OR_FCM_CST | \
|
||||
OR_FCM_CHT | \
|
||||
OR_FCM_SCY_1 | \
|
||||
OR_FCM_TRLX | \
|
||||
OR_FCM_EHTR)
|
||||
|
||||
/* NAND flash on CS3 */
|
||||
#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 | \
|
||||
(2<<BR_DECC_SHIFT) | \
|
||||
BR_PS_8 | \
|
||||
BR_MS_FCM | \
|
||||
BR_V)
|
||||
#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
|
||||
|
||||
/*
|
||||
* Use L1 as initial stack
|
||||
*/
|
||||
#define CONFIG_SYS_INIT_RAM_LOCK 1
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
|
||||
#define CONFIG_SYS_INIT_RAM_END 0x00004000
|
||||
|
||||
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
|
||||
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
|
||||
|
||||
/*
|
||||
* Serial Port
|
||||
*/
|
||||
#define CONFIG_CONS_INDEX 1
|
||||
#define CONFIG_SYS_NS16550
|
||||
#define CONFIG_SYS_NS16550_SERIAL
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE 1
|
||||
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
|
||||
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
|
||||
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE \
|
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
|
||||
|
||||
/*
|
||||
* Use the HUSH parser
|
||||
*/
|
||||
#define CONFIG_SYS_HUSH_PARSER
|
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
|
||||
|
||||
/*
|
||||
* Pass open firmware flat tree
|
||||
*/
|
||||
#define CONFIG_OF_LIBFDT 1
|
||||
#define CONFIG_OF_BOARD_SETUP 1
|
||||
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
|
||||
|
||||
#define CONFIG_SYS_64BIT_VSPRINTF 1
|
||||
#define CONFIG_SYS_64BIT_STRTOUL 1
|
||||
|
||||
/*
|
||||
* I2C
|
||||
*/
|
||||
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support */
|
||||
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_I2C2_OFFSET 0x3100
|
||||
#define CONFIG_I2C_MULTI_BUS
|
||||
#define CONFIG_I2C_CMD_TREE
|
||||
|
||||
/* PEX8518 slave I2C interface */
|
||||
#define CONFIG_SYS_I2C_PEX8518_ADDR 0x70
|
||||
|
||||
/* I2C DS1631 temperature sensor */
|
||||
#define CONFIG_SYS_I2C_DS1621_ADDR 0x48
|
||||
#define CONFIG_DTT_DS1621
|
||||
#define CONFIG_DTT_SENSORS { 0 }
|
||||
|
||||
/* I2C EEPROM - AT24C128B */
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
|
||||
|
||||
/* I2C RTC */
|
||||
#define CONFIG_RTC_M41T11 1
|
||||
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
|
||||
#define CONFIG_SYS_M41T11_BASE_YEAR 2000
|
||||
|
||||
/* GPIO/EEPROM/SRAM */
|
||||
#define CONFIG_DS4510
|
||||
#define CONFIG_SYS_I2C_DS4510_ADDR 0x51
|
||||
|
||||
/* GPIO */
|
||||
#define CONFIG_PCA953X
|
||||
#define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
|
||||
#define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c
|
||||
#define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e
|
||||
#define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f
|
||||
#define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0
|
||||
|
||||
/*
|
||||
* PU = pulled high, PD = pulled low
|
||||
* I = input, O = output, IO = input/output
|
||||
*/
|
||||
/* PCA9557 @ 0x18*/
|
||||
#define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */
|
||||
#define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select */
|
||||
#define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */
|
||||
#define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select */
|
||||
#define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */
|
||||
#define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Set to 0 to enable NVM writing */
|
||||
#define CONFIG_SYS_PCA953X_C0_VCORE_VID2 0x40 /* VID2 of ISL6262 */
|
||||
#define CONFIG_SYS_PCA953X_C0_VCORE_VID3 0x80 /* VID3 of ISL6262 */
|
||||
|
||||
/* PCA9557 @ 0x1c*/
|
||||
#define CONFIG_SYS_PCA953X_XMC0_ROOT0 0x01 /* PU; Low if XMC is RC */
|
||||
#define CONFIG_SYS_PCA953X_XMC0_MVMR0 0x02 /* XMC EEPROM write protect */
|
||||
#define CONFIG_SYS_PCA953X_XMC0_WAKE 0x04 /* PU; XMC wake */
|
||||
#define CONFIG_SYS_PCA953X_XMC0_BIST 0x08 /* PU; XMC built in self test */
|
||||
#define CONFIG_SYS_PCA953X_XMC_PRESENT 0x10 /* PU; Low if XMC module installed */
|
||||
#define CONFIG_SYS_PCA953X_PMC_PRESENT 0x20 /* PU; Low if PMC module installed */
|
||||
#define CONFIG_SYS_PCA953X_PMC0_MONARCH 0x40 /* PMC monarch mode enable */
|
||||
#define CONFIG_SYS_PCA953X_PMC0_EREADY 0x80 /* PU; PMC PCI eready */
|
||||
|
||||
/* PCA9557 @ 0x1e*/
|
||||
#define CONFIG_SYS_PCA953X_P0_GA0 0x01 /* PU; VPX Geographical address */
|
||||
#define CONFIG_SYS_PCA953X_P0_GA1 0x02 /* PU; VPX Geographical address */
|
||||
#define CONFIG_SYS_PCA953X_P0_GA2 0x04 /* PU; VPX Geographical address */
|
||||
#define CONFIG_SYS_PCA953X_P0_GA3 0x08 /* PU; VPX Geographical address */
|
||||
#define CONFIG_SYS_PCA953X_P0_GA4 0x10 /* PU; VPX Geographical address */
|
||||
#define CONFIG_SYS_PCA953X_P0_GAP 0x20 /* PU; tied to VPX P0.GAP */
|
||||
#define CONFIG_SYS_PCA953X_P1_SYSEN 0x80 /* PU; Pulled high; tied to VPX P1.SYSCON */
|
||||
|
||||
/* PCA9557 @ 0x1f */
|
||||
#define CONFIG_SYS_PCA953X_GPIO_VPX0 0x01 /* PU */
|
||||
#define CONFIG_SYS_PCA953X_GPIO_VPX1 0x02 /* PU */
|
||||
#define CONFIG_SYS_PCA953X_GPIO_VPX2 0x04 /* PU */
|
||||
#define CONFIG_SYS_PCA953X_GPIO_VPX3 0x08 /* PU */
|
||||
#define CONFIG_SYS_PCA953X_VPX_FRU_WRCTL 0x10 /* PD; I2C master source for FRU SEEPROM */
|
||||
|
||||
/*
|
||||
* General PCI
|
||||
* Memory space is mapped 1-1, but I/O space must start from 0.
|
||||
*/
|
||||
/* PCIE1 - VPX P1 */
|
||||
#define CONFIG_SYS_PCIE1_MEM_BASE 0x80000000
|
||||
#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE
|
||||
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */
|
||||
#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
|
||||
#define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000
|
||||
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
|
||||
|
||||
/* PCIE2 - PEX8518 */
|
||||
#define CONFIG_SYS_PCIE2_MEM_BASE 0xc0000000
|
||||
#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BASE
|
||||
#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
|
||||
#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
|
||||
#define CONFIG_SYS_PCIE2_IO_PHYS 0xe8800000
|
||||
#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 /* 8M */
|
||||
|
||||
/*
|
||||
* Networking options
|
||||
*/
|
||||
#define CONFIG_TSEC_ENET /* tsec ethernet support */
|
||||
#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
|
||||
#define CONFIG_NET_MULTI 1
|
||||
#define CONFIG_TSEC_TBI
|
||||
#define CONFIG_MII 1 /* MII PHY management */
|
||||
#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
|
||||
#define CONFIG_ETHPRIME "eTSEC2"
|
||||
|
||||
#define CONFIG_TSEC1 1
|
||||
#define CONFIG_TSEC1_NAME "eTSEC1"
|
||||
#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
|
||||
#define TSEC1_PHY_ADDR 1
|
||||
#define TSEC1_PHYIDX 0
|
||||
#define CONFIG_HAS_ETH0
|
||||
|
||||
#define CONFIG_TSEC2 1
|
||||
#define CONFIG_TSEC2_NAME "eTSEC2"
|
||||
#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
|
||||
#define TSEC2_PHY_ADDR 2
|
||||
#define TSEC2_PHYIDX 0
|
||||
#define CONFIG_HAS_ETH1
|
||||
|
||||
/*
|
||||
* Command configuration.
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#define CONFIG_CMD_ASKENV
|
||||
#define CONFIG_CMD_DATE
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_DS4510
|
||||
#define CONFIG_CMD_DS4510_INFO
|
||||
#define CONFIG_CMD_DTT
|
||||
#define CONFIG_CMD_EEPROM
|
||||
#define CONFIG_CMD_ELF
|
||||
#define CONFIG_CMD_ENV
|
||||
#define CONFIG_CMD_FLASH
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_CMD_JFFS2
|
||||
#define CONFIG_CMD_MII
|
||||
#define CONFIG_CMD_NET
|
||||
#define CONFIG_CMD_PCA953X
|
||||
#define CONFIG_CMD_PCA953X_INFO
|
||||
#define CONFIG_CMD_PCI
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_SNTP
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
|
||||
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
|
||||
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
|
||||
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
|
||||
#define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
|
||||
#define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */
|
||||
#define CONFIG_PANIC_HANG /* do not reset board on panic */
|
||||
#define CONFIG_PREBOOT /* enable preboot variable */
|
||||
#define CONFIG_FIT 1
|
||||
#define CONFIG_FIT_VERBOSE 1
|
||||
#define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 16 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
|
||||
|
||||
/*
|
||||
* Boot Flags
|
||||
*/
|
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
|
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
||||
|
||||
/*
|
||||
* Environment Configuration
|
||||
*/
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1
|
||||
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */
|
||||
#define CONFIG_ENV_SIZE 0x8000
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024))
|
||||
|
||||
/*
|
||||
* Flash memory map:
|
||||
* fff80000 - ffffffff Pri U-Boot (512 KB)
|
||||
* fff40000 - fff7ffff Pri U-Boot Environment (256 KB)
|
||||
* fff00000 - fff3ffff Pri FDT (256KB)
|
||||
* fef00000 - ffefffff Pri OS image (16MB)
|
||||
* f8000000 - feefffff Pri OS Use/Filesystem (111MB)
|
||||
*
|
||||
* f7f80000 - f7ffffff Sec U-Boot (512 KB)
|
||||
* f7f40000 - f7f7ffff Sec U-Boot Environment (256 KB)
|
||||
* f7f00000 - f7f3ffff Sec FDT (256KB)
|
||||
* f6f00000 - f7efffff Sec OS image (16MB)
|
||||
* f0000000 - f6efffff Sec OS Use/Filesystem (111MB)
|
||||
*/
|
||||
#define CONFIG_UBOOT1_ENV_ADDR MK_STR(0xfff80000)
|
||||
#define CONFIG_UBOOT2_ENV_ADDR MK_STR(0xf7f80000)
|
||||
#define CONFIG_FDT1_ENV_ADDR MK_STR(0xfff00000)
|
||||
#define CONFIG_FDT2_ENV_ADDR MK_STR(0xf7f00000)
|
||||
#define CONFIG_OS1_ENV_ADDR MK_STR(0xfef00000)
|
||||
#define CONFIG_OS2_ENV_ADDR MK_STR(0xf6f00000)
|
||||
|
||||
#define CONFIG_PROG_UBOOT1 \
|
||||
"$download_cmd $loadaddr $ubootfile; " \
|
||||
"if test $? -eq 0; then " \
|
||||
"protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
|
||||
"erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
|
||||
"cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \
|
||||
"protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
|
||||
"cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \
|
||||
"if test $? -ne 0; then " \
|
||||
"echo PROGRAM FAILED; " \
|
||||
"else; " \
|
||||
"echo PROGRAM SUCCEEDED; " \
|
||||
"fi; " \
|
||||
"else; " \
|
||||
"echo DOWNLOAD FAILED; " \
|
||||
"fi;"
|
||||
|
||||
#define CONFIG_PROG_UBOOT2 \
|
||||
"$download_cmd $loadaddr $ubootfile; " \
|
||||
"if test $? -eq 0; then " \
|
||||
"protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
|
||||
"erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
|
||||
"cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \
|
||||
"protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
|
||||
"cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \
|
||||
"if test $? -ne 0; then " \
|
||||
"echo PROGRAM FAILED; " \
|
||||
"else; " \
|
||||
"echo PROGRAM SUCCEEDED; " \
|
||||
"fi; " \
|
||||
"else; " \
|
||||
"echo DOWNLOAD FAILED; " \
|
||||
"fi;"
|
||||
|
||||
#define CONFIG_BOOT_OS_NET \
|
||||
"$download_cmd $osaddr $osfile; " \
|
||||
"if test $? -eq 0; then " \
|
||||
"if test -n $fdtaddr; then " \
|
||||
"$download_cmd $fdtaddr $fdtfile; " \
|
||||
"if test $? -eq 0; then " \
|
||||
"bootm $osaddr - $fdtaddr; " \
|
||||
"else; " \
|
||||
"echo FDT DOWNLOAD FAILED; " \
|
||||
"fi; " \
|
||||
"else; " \
|
||||
"bootm $osaddr; " \
|
||||
"fi; " \
|
||||
"else; " \
|
||||
"echo OS DOWNLOAD FAILED; " \
|
||||
"fi;"
|
||||
|
||||
#define CONFIG_PROG_OS1 \
|
||||
"$download_cmd $osaddr $osfile; " \
|
||||
"if test $? -eq 0; then " \
|
||||
"erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \
|
||||
"cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
|
||||
"cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
|
||||
"if test $? -ne 0; then " \
|
||||
"echo OS PROGRAM FAILED; " \
|
||||
"else; " \
|
||||
"echo OS PROGRAM SUCCEEDED; " \
|
||||
"fi; " \
|
||||
"else; " \
|
||||
"echo OS DOWNLOAD FAILED; " \
|
||||
"fi;"
|
||||
|
||||
#define CONFIG_PROG_OS2 \
|
||||
"$download_cmd $osaddr $osfile; " \
|
||||
"if test $? -eq 0; then " \
|
||||
"erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \
|
||||
"cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
|
||||
"cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
|
||||
"if test $? -ne 0; then " \
|
||||
"echo OS PROGRAM FAILED; " \
|
||||
"else; " \
|
||||
"echo OS PROGRAM SUCCEEDED; " \
|
||||
"fi; " \
|
||||
"else; " \
|
||||
"echo OS DOWNLOAD FAILED; " \
|
||||
"fi;"
|
||||
|
||||
#define CONFIG_PROG_FDT1 \
|
||||
"$download_cmd $fdtaddr $fdtfile; " \
|
||||
"if test $? -eq 0; then " \
|
||||
"erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \
|
||||
"cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
|
||||
"cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
|
||||
"if test $? -ne 0; then " \
|
||||
"echo FDT PROGRAM FAILED; " \
|
||||
"else; " \
|
||||
"echo FDT PROGRAM SUCCEEDED; " \
|
||||
"fi; " \
|
||||
"else; " \
|
||||
"echo FDT DOWNLOAD FAILED; " \
|
||||
"fi;"
|
||||
|
||||
#define CONFIG_PROG_FDT2 \
|
||||
"$download_cmd $fdtaddr $fdtfile; " \
|
||||
"if test $? -eq 0; then " \
|
||||
"erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \
|
||||
"cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
|
||||
"cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
|
||||
"if test $? -ne 0; then " \
|
||||
"echo FDT PROGRAM FAILED; " \
|
||||
"else; " \
|
||||
"echo FDT PROGRAM SUCCEEDED; " \
|
||||
"fi; " \
|
||||
"else; " \
|
||||
"echo FDT DOWNLOAD FAILED; " \
|
||||
"fi;"
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"autoload=yes\0" \
|
||||
"download_cmd=tftp\0" \
|
||||
"console_args=console=ttyS0,115200\0" \
|
||||
"root_args=root=/dev/nfs rw\0" \
|
||||
"misc_args=ip=on\0" \
|
||||
"set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
|
||||
"bootfile=/home/user/file\0" \
|
||||
"osfile=/home/user/uImage-XPedite5370\0" \
|
||||
"fdtfile=/home/user/xpedite5370.dtb\0" \
|
||||
"ubootfile=/home/user/u-boot.bin\0" \
|
||||
"fdtaddr=c00000\0" \
|
||||
"osaddr=0x1000000\0" \
|
||||
"loadaddr=0x1000000\0" \
|
||||
"prog_uboot1="CONFIG_PROG_UBOOT1"\0" \
|
||||
"prog_uboot2="CONFIG_PROG_UBOOT2"\0" \
|
||||
"prog_os1="CONFIG_PROG_OS1"\0" \
|
||||
"prog_os2="CONFIG_PROG_OS2"\0" \
|
||||
"prog_fdt1="CONFIG_PROG_FDT1"\0" \
|
||||
"prog_fdt2="CONFIG_PROG_FDT2"\0" \
|
||||
"bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
|
||||
"bootcmd_flash1=run set_bootargs; " \
|
||||
"bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
|
||||
"bootcmd_flash2=run set_bootargs; " \
|
||||
"bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
|
||||
"bootcmd=run bootcmd_flash1\0"
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in New Issue