Modify SBC8641D to use new Freescale PCI routines
PCI-Express sockets 1 and 2 verified working with Intel Pro/1000 PT adapter. Signed-off-by: Joe Hamman <joe.hamman@embeddedspecialties.com> Signde-off-by: Jon Loeliger <jdl@freescale.com>
This commit is contained in:
Joe Hamman
Jon Loeliger
parent
c646bba646
commit
cca34967cb
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@ -33,6 +33,7 @@
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#include <pci.h>
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#include <asm/processor.h>
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#include <asm/immap_86xx.h>
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#include <asm/immap_fsl_pci.h>
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#include <spd.h>
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#if defined(CONFIG_OF_FLAT_TREE)
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@ -60,36 +61,6 @@ int checkboard (void)
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{
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puts ("Board: Wind River SBC8641D\n");
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#ifdef CONFIG_PCI
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volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
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volatile ccsr_gur_t *gur = &immap->im_gur;
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volatile ccsr_pex_t *pex1 = &immap->im_pex1;
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uint devdisr = gur->devdisr;
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uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16;
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uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17;
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uint pex1_agent = (host1_agent == 0) || (host1_agent == 1);
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if ((io_sel == 2 || io_sel == 3 || io_sel == 5
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|| io_sel == 6 || io_sel == 7 || io_sel == 0xF)
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&& !(devdisr & MPC86xx_DEVDISR_PCIEX1)) {
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debug ("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host");
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debug ("0x%08x=0x%08x ", &pex1->pme_msg_det, pex1->pme_msg_det);
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if (pex1->pme_msg_det) {
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pex1->pme_msg_det = 0xffffffff;
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debug (" with errors. Clearing. Now 0x%08x",
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pex1->pme_msg_det);
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}
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debug ("\n");
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} else {
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puts ("PCI-EXPRESS 1: Disabled in hardware\n");
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}
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#else
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puts ("PCI-EXPRESS1: Disabled in configuration\n");
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#endif
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return 0;
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}
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@ -244,21 +215,130 @@ static struct pci_config_table pci_fsl86xxads_config_table[] = {
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};
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#endif
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static struct pci_controller hose = {
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static struct pci_controller pci1_hose = {
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#ifndef CONFIG_PCI_PNP
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config_table:pci_mpc86xxcts_config_table,
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config_table:pci_mpc86xxcts_config_table
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#endif
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};
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#endif /* CONFIG_PCI */
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#endif /* CONFIG_PCI */
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#ifdef CONFIG_PCI2
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static struct pci_controller pci2_hose;
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#endif /* CONFIG_PCI2 */
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void pci_init_board (void)
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int first_free_busno = 0;
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void pci_init_board(void)
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{
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#ifdef CONFIG_PCI
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extern void pci_mpc86xx_init (struct pci_controller *hose);
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volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
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volatile ccsr_gur_t *gur = &immap->im_gur;
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uint devdisr = gur->devdisr;
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uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16;
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#ifdef CONFIG_PCI1
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{
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volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
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extern void fsl_pci_init(struct pci_controller *hose);
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struct pci_controller *hose = &pci1_hose;
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#ifdef DEBUG
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uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17;
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uint pex1_agent = (host1_agent == 0) || (host1_agent == 1);
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#endif
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if ((io_sel == 2 || io_sel == 3 || io_sel == 5
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|| io_sel == 6 || io_sel == 7 || io_sel == 0xF)
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&& !(devdisr & MPC86xx_DEVDISR_PCIEX1)) {
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debug("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host");
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debug("0x%08x=0x%08x ", &pci->pme_msg_det, pci->pme_msg_det);
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if (pci->pme_msg_det) {
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pci->pme_msg_det = 0xffffffff;
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debug(" with errors. Clearing. Now 0x%08x",
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pci->pme_msg_det);
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}
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debug("\n");
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/* inbound */
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pci_set_region(hose->regions + 0,
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CFG_PCI_MEMORY_BUS,
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CFG_PCI_MEMORY_PHYS,
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CFG_PCI_MEMORY_SIZE,
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PCI_REGION_MEM | PCI_REGION_MEMORY);
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/* outbound memory */
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pci_set_region(hose->regions + 1,
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CFG_PCI1_MEM_BASE,
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CFG_PCI1_MEM_PHYS,
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CFG_PCI1_MEM_SIZE,
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PCI_REGION_MEM);
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/* outbound io */
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pci_set_region(hose->regions + 2,
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CFG_PCI1_IO_BASE,
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CFG_PCI1_IO_PHYS,
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CFG_PCI1_IO_SIZE,
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PCI_REGION_IO);
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hose->region_count = 3;
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hose->first_busno=first_free_busno;
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pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
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fsl_pci_init(hose);
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first_free_busno=hose->last_busno+1;
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printf (" PCI-EXPRESS 1 on bus %02x - %02x\n",
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hose->first_busno,hose->last_busno);
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} else {
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puts("PCI-EXPRESS 1: Disabled\n");
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}
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}
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#else
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puts("PCI-EXPRESS1: Disabled\n");
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#endif /* CONFIG_PCI1 */
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#ifdef CONFIG_PCI2
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{
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volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI2_ADDR;
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extern void fsl_pci_init(struct pci_controller *hose);
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struct pci_controller *hose = &pci2_hose;
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/* inbound */
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pci_set_region(hose->regions + 0,
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CFG_PCI_MEMORY_BUS,
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CFG_PCI_MEMORY_PHYS,
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CFG_PCI_MEMORY_SIZE,
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PCI_REGION_MEM | PCI_REGION_MEMORY);
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/* outbound memory */
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pci_set_region(hose->regions + 1,
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CFG_PCI2_MEM_BASE,
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CFG_PCI2_MEM_PHYS,
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CFG_PCI2_MEM_SIZE,
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PCI_REGION_MEM);
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/* outbound io */
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pci_set_region(hose->regions + 2,
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CFG_PCI2_IO_BASE,
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CFG_PCI2_IO_PHYS,
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CFG_PCI2_IO_SIZE,
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PCI_REGION_IO);
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hose->region_count = 3;
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hose->first_busno=first_free_busno;
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pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
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fsl_pci_init(hose);
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first_free_busno=hose->last_busno+1;
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printf (" PCI-EXPRESS 2 on bus %02x - %02x\n",
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hose->first_busno,hose->last_busno);
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}
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#else
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puts("PCI-EXPRESS 2: Disabled\n");
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#endif /* CONFIG_PCI2 */
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pci_mpc86xx_init (&hose);
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#endif /* CONFIG_PCI */
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}
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#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
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@ -49,8 +49,10 @@
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#define CFG_RESET_ADDRESS 0xfff00100
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#undef CONFIG_PCI
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#define CONFIG_FSL_PCI_INIT 1
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#define CONFIG_PCI 1 /* Enable PCIE */
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#define CONFIG_PCI1 1 /* PCIE controler 1 (slot 1) */
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#define CONFIG_PCI2 1 /* PCIE controler 2 (slot 2) */
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#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
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#define CONFIG_TSEC_ENET /* tsec ethernet support */
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#define CONFIG_ENV_OVERWRITE
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@ -95,6 +97,9 @@
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#define CFG_CCSRBAR 0xf8000000 /* relocated CCSRBAR */
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#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
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#define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000)
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#define CFG_PCI2_ADDR (CFG_CCSRBAR+0x9000)
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/*
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* DDR Setup
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*/
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