ARM: Add support for Lyrtech SFF-SDR board (ARM926EJS)
This patch adds support for the Lyrtech SFF-SDR board, based on the TI DaVinci architecture (ARM926EJS). Signed-off-by: Hugo Villeneuve <hugo.villeneuve@lyrtech.com> Signed-off-by: Philip Balister <philip@balister.org> Signed-off-by: Wolfgang Denk <wd@denx.de>
This commit is contained in:
Hugo Villeneuve
Wolfgang Denk
parent
341188b9cc
commit
c7f879ec2b
1
MAKEALL
1
MAKEALL
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@ -503,6 +503,7 @@ LIST_ARM9=" \
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voiceblue \
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davinci_dvevm \
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davinci_schmoogie \
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davinci_sffsdr \
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davinci_sonata \
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"
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3
Makefile
3
Makefile
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@ -2428,6 +2428,9 @@ davinci_dvevm_config : unconfig
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davinci_schmoogie_config : unconfig
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@$(MKCONFIG) $(@:_config=) arm arm926ejs schmoogie davinci davinci
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davinci_sffsdr_config : unconfig
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@$(MKCONFIG) $(@:_config=) arm arm926ejs sffsdr davinci davinci
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davinci_sonata_config : unconfig
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@$(MKCONFIG) $(@:_config=) arm arm926ejs sonata davinci davinci
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@ -0,0 +1,52 @@
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#
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# (C) Copyright 2000, 2001, 2002
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).a
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COBJS := dv_board.o
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SOBJS := board_init.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS)
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$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
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clean:
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rm -f $(SOBJS) $(OBJS)
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distclean: clean
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rm -f $(LIB) core *.bak *~ $(obj).depend
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#########################################################################
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# This is for $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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@ -0,0 +1,29 @@
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/*
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* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
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*
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* Board-specific low level initialization code. Called at the very end
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* of cpu/arm926ejs/davinci/lowlevel_init.S. Just returns if there is no
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* initialization required.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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.globl dv_board_init
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dv_board_init:
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mov pc, lr
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@ -0,0 +1,24 @@
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#
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# (C) Copyright 2002
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# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
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# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
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#
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# Lyrtech SFF SDR board (ARM926EJS) cpu
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# see http://www.lyrtech.com/ for more information on Lyrtech
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#
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# SFF SDR board has 1 bank of 128 MB DDR RAM
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# Physical Address:
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# 8000'0000 to 87FF'FFFF
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#
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# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
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# (mem base + reserved)
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#
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# Integrity kernel is expected to be at 8000'0000, entry 8000'00D0,
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# up to 81FF'FFFF (uses up to 32 MB of memory for text, heap, etc).
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#
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# we load ourself to 8400'0000
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#
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#
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# Provide at least 32MB spacing between us and the Integrity kernel image
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TEXT_BASE = 0x84000000
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@ -0,0 +1,212 @@
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/*
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* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
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*
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* Parts are shamelessly stolen from various TI sources, original copyright
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* follows:
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* -----------------------------------------------------------------
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*
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* Copyright (C) 2004 Texas Instruments.
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*
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* ----------------------------------------------------------------------------
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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* ----------------------------------------------------------------------------
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*/
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#include <common.h>
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#include <i2c.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/emac_defs.h>
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DECLARE_GLOBAL_DATA_PTR;
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extern void timer_init(void);
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extern int eth_hw_init(void);
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extern phy_t phy;
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/* Works on Always On power domain only (no PD argument) */
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void lpsc_on(unsigned int id)
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{
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dv_reg_p mdstat, mdctl;
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if (id >= DAVINCI_LPSC_GEM)
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return; /* Don't work on DSP Power Domain */
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mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4));
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mdctl = REG_P(PSC_MDCTL_BASE + (id * 4));
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while (REG(PSC_PTSTAT) & 0x01);
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if ((*mdstat & 0x1f) == 0x03)
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return; /* Already on and enabled */
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*mdctl |= 0x03;
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/* Special treatment for some modules as for sprue14 p.7.4.2 */
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if ((id == DAVINCI_LPSC_VPSSSLV) ||
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(id == DAVINCI_LPSC_EMAC) ||
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(id == DAVINCI_LPSC_EMAC_WRAPPER) ||
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(id == DAVINCI_LPSC_MDIO) ||
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(id == DAVINCI_LPSC_USB) ||
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(id == DAVINCI_LPSC_ATA) ||
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(id == DAVINCI_LPSC_VLYNQ) ||
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(id == DAVINCI_LPSC_UHPI) ||
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(id == DAVINCI_LPSC_DDR_EMIF) ||
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(id == DAVINCI_LPSC_AEMIF) ||
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(id == DAVINCI_LPSC_MMC_SD) ||
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(id == DAVINCI_LPSC_MEMSTICK) ||
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(id == DAVINCI_LPSC_McBSP) ||
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(id == DAVINCI_LPSC_GPIO))
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* mdctl |= 0x200;
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REG(PSC_PTCMD) = 0x01;
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while (REG(PSC_PTSTAT) & 0x03);
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while ((*mdstat & 0x1f) != 0x03); /* Probably an overkill... */
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}
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void dsp_on(void)
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{
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int i;
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if (REG(PSC_PDSTAT1) & 0x1f)
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return; /* Already on */
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REG(PSC_GBLCTL) |= 0x01;
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REG(PSC_PDCTL1) |= 0x01;
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REG(PSC_PDCTL1) &= ~0x100;
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REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) |= 0x03;
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REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) &= 0xfffffeff;
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REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) |= 0x03;
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REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) &= 0xfffffeff;
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REG(PSC_PTCMD) = 0x02;
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for (i = 0; i < 100; i++) {
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if (REG(PSC_EPCPR) & 0x02)
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break;
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}
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REG(PSC_CHP_SHRTSW) = 0x01;
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REG(PSC_PDCTL1) |= 0x100;
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REG(PSC_EPCCR) = 0x02;
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for (i = 0; i < 100; i++) {
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if (!(REG(PSC_PTSTAT) & 0x02))
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break;
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}
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REG(PSC_GBLCTL) &= ~0x1f;
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}
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int board_init(void)
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{
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/* arch number of the board */
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gd->bd->bi_arch_number = MACH_TYPE_SFFSDR;
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/* address of boot parameters */
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gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
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/* Workaround for TMS320DM6446 errata 1.3.22 */
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REG(PSC_SILVER_BULLET) = 0;
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/* Power on required peripherals */
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lpsc_on(DAVINCI_LPSC_EMAC);
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lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER);
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lpsc_on(DAVINCI_LPSC_MDIO);
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lpsc_on(DAVINCI_LPSC_I2C);
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lpsc_on(DAVINCI_LPSC_UART0);
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lpsc_on(DAVINCI_LPSC_TIMER1);
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lpsc_on(DAVINCI_LPSC_GPIO);
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/* Powerup the DSP */
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dsp_on();
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/* Bringup UART0 out of reset */
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REG(UART0_PWREMU_MGMT) = 0x0000e003;
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/* Enable GIO3.3V cells used for EMAC */
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REG(VDD3P3V_PWDN) = 0;
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/* Enable UART0 MUX lines */
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REG(PINMUX1) |= 1;
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/* Enable EMAC and AEMIF pins */
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REG(PINMUX0) = 0x80000c1f;
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/* Enable I2C pin Mux */
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REG(PINMUX1) |= (1 << 7);
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/* Set the Bus Priority Register to appropriate value */
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REG(VBPR) = 0x20;
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timer_init();
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return(0);
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}
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int misc_init_r(void)
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{
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u_int8_t tmp[20], buf[10];
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int i = 0;
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int clk = 0;
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clk = ((REG(PLL2_PLLM) + 1) * 27) / ((REG(PLL2_DIV2) & 0x1f) + 1);
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printf("ARM Clock: %dMHz\n", ((REG(PLL1_PLLM) + 1) * 27) / 2);
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printf("DDR Clock: %dMHz\n", (clk / 2));
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/* Configure I2C switch (PCA9543) to enable channel 0. */
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tmp[0] = CFG_I2C_PCA9543_ENABLE_CH0;
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if (i2c_write(CFG_I2C_PCA9543_ADDR, 0,
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CFG_I2C_PCA9543_ADDR_LEN, tmp, 1))
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printf("Write to MUX @ 0x%02x failed\n", CFG_I2C_PCA9543_ADDR);
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/* Set Ethernet MAC address from EEPROM.
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* We must read 8 bytes because data is stored in little-endian. */
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if (i2c_read(CFG_I2C_EEPROM_ADDR, 0x05A8,
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CFG_I2C_EEPROM_ADDR_LEN, buf, 8)) {
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printf("Read from EEPROM @ 0x%02x failed\n",
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CFG_I2C_EEPROM_ADDR);
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} else {
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tmp[0] = 0xff;
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for (i = 0; i < 6; i++)
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tmp[0] &= buf[i];
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if ((tmp[0] != 0xff) && (getenv("ethaddr") == NULL)) {
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sprintf((char *)&tmp[0],
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"%02x:%02x:%02x:%02x:%02x:%02x",
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buf[3], buf[2], buf[1], buf[0],
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buf[7], buf[6]);
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setenv("ethaddr", (char *)&tmp[0]);
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}
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}
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if (!eth_hw_init()) {
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printf("Ethernet init failed\n");
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} else {
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printf("ETH PHY: %s\n", phy.name);
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}
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return(0);
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}
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int dram_init(void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
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gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
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return(0);
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}
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@ -0,0 +1,52 @@
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/*
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* (C) Copyright 2002
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* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
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*
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* See file CREDITS for list of people who contributed to this
|
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* project.
|
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*
|
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* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
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* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
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* MA 02111-1307 USA
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*/
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OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
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OUTPUT_ARCH(arm)
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ENTRY(_start)
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SECTIONS
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{
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. = 0x00000000;
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. = ALIGN(4);
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.text :
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{
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cpu/arm926ejs/start.o (.text)
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*(.text)
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}
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. = ALIGN(4);
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.rodata : { *(.rodata) }
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. = ALIGN(4);
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.data : { *(.data) }
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. = ALIGN(4);
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.got : { *(.got) }
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. = .;
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__u_boot_cmd_start = .;
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.u_boot_cmd : { *(.u_boot_cmd) }
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__u_boot_cmd_end = .;
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. = ALIGN(4);
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__bss_start = .;
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.bss (NOLOAD) : { *(.bss) }
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_end = .;
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}
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@ -1595,6 +1595,7 @@ extern unsigned int __machine_arch_type;
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#define MACH_TYPE_P300 1602
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#define MACH_TYPE_XDACOMET 1603
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#define MACH_TYPE_DEXFLEX2 1604
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#define MACH_TYPE_SFFSDR 1657
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#ifdef CONFIG_ARCH_EBSA110
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# ifdef machine_arch_type
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@ -16500,6 +16501,18 @@ extern unsigned int __machine_arch_type;
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# define machine_is_schmoogie() (0)
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#endif
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#ifdef CONFIG_MACH_SFFSDR
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# ifdef machine_arch_type
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# undef machine_arch_type
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# define machine_arch_type __machine_arch_type
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# else
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# define machine_arch_type MACH_TYPE_SFFSDR
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# endif
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# define machine_is_sffsdr() (machine_arch_type == MACH_TYPE_SFFSDR)
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#else
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# define machine_is_sffsdr() (0)
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#endif
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#ifdef CONFIG_MACH_AZTOOL
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# ifdef machine_arch_type
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# undef machine_arch_type
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|
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@ -0,0 +1,177 @@
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/*
|
||||
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
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#define __CONFIG_H
|
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#include <asm/sizes.h>
|
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|
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/*=======*/
|
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/* Board */
|
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/*=======*/
|
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#define SFFSDR
|
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#define CFG_NAND_LARGEPAGE
|
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#define CFG_USE_NAND
|
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/*===================*/
|
||||
/* SoC Configuration */
|
||||
/*===================*/
|
||||
#define CONFIG_ARM926EJS /* arm926ejs CPU core */
|
||||
#define CONFIG_SYS_CLK_FREQ 297000000 /* Arm Clock frequency */
|
||||
#define CFG_TIMERBASE 0x01c21400 /* use timer 0 */
|
||||
#define CFG_HZ_CLOCK 27000000 /* Timer Input clock freq */
|
||||
#define CFG_HZ 1000
|
||||
/*==================================================*/
|
||||
/* EEPROM definitions for Atmel 24LC64 EEPROM chip */
|
||||
/*==================================================*/
|
||||
#define CFG_I2C_EEPROM_ADDR_LEN 2
|
||||
#define CFG_I2C_EEPROM_ADDR 0x50
|
||||
#define CFG_EEPROM_PAGE_WRITE_BITS 5
|
||||
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
|
||||
/*=============*/
|
||||
/* Memory Info */
|
||||
/*=============*/
|
||||
#define CFG_MALLOC_LEN (0x10000 + 256*1024) /* malloc() len */
|
||||
#define CFG_GBL_DATA_SIZE 128 /* reserved for initial data */
|
||||
#define CFG_MEMTEST_START 0x80000000 /* memtest start address */
|
||||
#define CFG_MEMTEST_END 0x81000000 /* 16MB RAM test */
|
||||
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
|
||||
#define CONFIG_STACKSIZE (256*1024) /* regular stack */
|
||||
#define PHYS_SDRAM_1 0x80000000 /* DDR Start */
|
||||
#define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */
|
||||
#define DDR_4BANKS /* 4-bank DDR2 (128MB) */
|
||||
/*====================*/
|
||||
/* Serial Driver info */
|
||||
/*====================*/
|
||||
#define CFG_NS16550
|
||||
#define CFG_NS16550_SERIAL
|
||||
#define CFG_NS16550_REG_SIZE 4 /* NS16550 register size */
|
||||
#define CFG_NS16550_COM1 0x01c20000 /* Base address of UART0 */
|
||||
#define CFG_NS16550_CLK 27000000 /* Input clock to NS16550 */
|
||||
#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
|
||||
#define CONFIG_BAUDRATE 115200 /* Default baud rate */
|
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
|
||||
/*===================*/
|
||||
/* I2C Configuration */
|
||||
/*===================*/
|
||||
#define CONFIG_HARD_I2C
|
||||
#define CONFIG_DRIVER_DAVINCI_I2C
|
||||
#define CFG_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */
|
||||
#define CFG_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
|
||||
/*==================================*/
|
||||
/* Network & Ethernet Configuration */
|
||||
/*==================================*/
|
||||
#define CONFIG_DRIVER_TI_EMAC
|
||||
#define CONFIG_MII
|
||||
#define CONFIG_BOOTP_DEFAULT
|
||||
#define CONFIG_BOOTP_DNS
|
||||
#define CONFIG_BOOTP_DNS2
|
||||
#define CONFIG_BOOTP_SEND_HOSTNAME
|
||||
#define CONFIG_NET_RETRY_COUNT 10
|
||||
#define CONFIG_OVERWRITE_ETHADDR_ONCE
|
||||
/*=====================*/
|
||||
/* Flash & Environment */
|
||||
/*=====================*/
|
||||
#undef CFG_ENV_IS_IN_FLASH
|
||||
#define CFG_NO_FLASH
|
||||
#define CFG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
|
||||
#define CFG_ENV_SECT_SIZE 2048 /* Env sector Size */
|
||||
#define CFG_ENV_SIZE SZ_128K
|
||||
#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */
|
||||
#define CONFIG_SKIP_RELOCATE_UBOOT /* to a proper address, init done */
|
||||
#define CFG_NAND_BASE 0x02000000
|
||||
#define CFG_NAND_HW_ECC
|
||||
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
|
||||
#define NAND_MAX_CHIPS 1
|
||||
#define CFG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
|
||||
/*=====================*/
|
||||
/* Board related stuff */
|
||||
/*=====================*/
|
||||
/*==========================================*/
|
||||
/* I2C switch definitions for PCA9543 chip */
|
||||
/* on Lyrtech SFF SDR board. */
|
||||
/* This chip has a single register. */
|
||||
/*==========================================*/
|
||||
#define CFG_I2C_PCA9543_ADDR 0x70
|
||||
#define CFG_I2C_PCA9543_ADDR_LEN 0
|
||||
#define CFG_I2C_PCA9543_ENABLE_CH0 0x01 /* Enable channel 0. */
|
||||
/*==============================*/
|
||||
/* U-Boot general configuration */
|
||||
/*==============================*/
|
||||
#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */
|
||||
#define CONFIG_MISC_INIT_R
|
||||
#undef CONFIG_BOOTDELAY
|
||||
#define CONFIG_BOOTFILE "uImage" /* Boot file name */
|
||||
#define CFG_PROMPT "U-Boot > " /* Monitor Command Prompt */
|
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
/* Print buffer size */
|
||||
#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
|
||||
#define CFG_MAXARGS 16 /* max number of command args */
|
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
||||
#define CFG_LOAD_ADDR 0x80700000 /* Default Linux kernel
|
||||
* load address. */
|
||||
#define CONFIG_VERSION_VARIABLE
|
||||
#define CONFIG_AUTO_COMPLETE /* Won't work with hush so far,
|
||||
* may be later */
|
||||
#define CFG_HUSH_PARSER
|
||||
#define CFG_PROMPT_HUSH_PS2 "> "
|
||||
#define CONFIG_CMDLINE_EDITING
|
||||
#define CFG_LONGHELP
|
||||
#define CONFIG_CRC32_VERIFY
|
||||
#define CONFIG_MX_CYCLIC
|
||||
/*
|
||||
* Define this to load an Integrity kernel.
|
||||
*
|
||||
#define CONFIG_CMD_ELF
|
||||
*/
|
||||
|
||||
/*===================*/
|
||||
/* Linux Information */
|
||||
/*===================*/
|
||||
#define LINUX_BOOT_PARAM_ADDR 0x80000100
|
||||
#define CONFIG_CMDLINE_TAG
|
||||
#define CONFIG_SETUP_MEMORY_TAGS
|
||||
#define CONFIG_BOOTARGS \
|
||||
"mem=56M console=ttyS0,115200n8 root=/dev/hda1 rw noinitrd ip=dhcp"
|
||||
#define CONFIG_BOOTCOMMAND "setenv setboot setenv bootargs \\$(bootargs) video=dm64xxfb:output=\\$(videostd);run setboot"
|
||||
|
||||
/*=================*/
|
||||
/* U-Boot commands */
|
||||
/*=================*/
|
||||
#include <config_cmd_default.h>
|
||||
#define CONFIG_CMD_ASKENV
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_DIAG
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_CMD_MII
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_SAVES
|
||||
#define CONFIG_CMD_NAND
|
||||
#define CONFIG_CMD_EEPROM
|
||||
#undef CONFIG_CMD_BDI
|
||||
#undef CONFIG_CMD_FPGA
|
||||
#undef CONFIG_CMD_SETGETDCR
|
||||
#undef CONFIG_CMD_FLASH
|
||||
#undef CONFIG_CMD_IMLS
|
||||
/*=======================*/
|
||||
/* KGDB support (if any) */
|
||||
/*=======================*/
|
||||
#ifdef CONFIG_CMD_KGDB
|
||||
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
|
||||
#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
|
||||
#endif
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in New Issue