phone-side
/
uboot-mt623x
9
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

s5pc1xx: Add support for Samsung Goni board 

This patch adds support for the Samsung Goni board (S5PC110 SoC)

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
This commit is contained in:
Minkyu Kang 2010-05-31 22:02:42 +09:00 committed by Tom
parent ffb4b02554
commit c474a8ebb8
10 changed files with 1237 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
MAINTAINERS
View File

@ -635,14 +635,15 @@ Simon Kagstrom <simon.kagstrom@netinsight.net>
openrd_base ARM926EJS (Kirkwood SoC)
Minkyu Kang <mk7.kang@samsung.com>
SMDKC100 ARM CORTEX-A8 (S5PC100 SoC)
Nishant Kamat <nskamat@ti.com>
omap1610h2 ARM926EJS
Minkyu Kang <mk7.kang@samsung.com>
s5p_goni ARM CORTEX-A8 (S5PC110 SoC)
SMDKC100 ARM CORTEX-A8 (S5PC100 SoC)
Frederik Kriewitz <frederik@kriewitz.eu>
devkit8000 ARM CORTEX-A8 (OMAP3530 SoC)

1
MAKEALL
View File

@ -652,6 +652,7 @@ LIST_ARM_CORTEX_A8=" \
omap3_sdp3430 \
omap3_zoom1 \
omap3_zoom2 \
s5p_goni \
smdkc100 \
"

3
Makefile
View File

@ -3186,6 +3186,9 @@ omap3_zoom1_config : unconfig
omap3_zoom2_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 zoom2 logicpd omap3
s5p_goni_config: unconfig
@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 goni samsung s5pc1xx
smdkc100_config: unconfig
@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 smdkc100 samsung s5pc1xx

54
board/samsung/goni/Makefile Normal file
View File

@ -0,0 +1,54 @@
#
# (C) Copyright 2000, 2001, 2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2008
# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS-y := goni.o onenand.o
SOBJS := lowlevel_init.o
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(SOBJS) $(OBJS)
$(AR) $(ARFLAGS) $@ $(SOBJS) $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

16
board/samsung/goni/config.mk Normal file
View File

@ -0,0 +1,16 @@
#
# Copyright (C) 2008 # Samsung Elecgtronics
# Kyungmin Park <kyungmin.park@samsung.com>
#
# On S5PC100 we use the 128 MiB OneDRAM bank at
#
# 0x30000000 to 0x35000000 (80MiB)
# 0x38000000 to 0x40000000 (128MiB)
#
# On S5PC110 we use the 128 MiB OneDRAM bank at
#
# 0x30000000 to 0x35000000 (80MiB)
# 0x40000000 to 0x50000000 (256MiB)
#
TEXT_BASE = 0x34800000

55
board/samsung/goni/goni.c Normal file
View File

@ -0,0 +1,55 @@
/*
* Copyright (C) 2008-2009 Samsung Electronics
* Minkyu Kang <mk7.kang@samsung.com>
* Kyungmin Park <kyungmin.park@samsung.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
{
gd->bd->bi_arch_number = MACH_TYPE_GONI;
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
return 0;
}
int dram_init(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
return 0;
}
#ifdef CONFIG_DISPLAY_BOARDINFO
int checkboard(void)
{
puts("Board:\tGoni\n");
return 0;
}
#endif

585
board/samsung/goni/lowlevel_init.S Normal file
View File

@ -0,0 +1,585 @@
/*
* Memory Setup stuff - taken from blob memsetup.S
*
* Copyright (C) 2009 Samsung Electronics
* Kyungmin Park <kyungmin.park@samsung.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <version.h>
#include <asm/arch/cpu.h>
#include <asm/arch/clock.h>
#include <asm/arch/power.h>
/*
* Register usages:
*
* r5 has zero always
* r7 has S5PC100 GPIO base, 0xE0300000
* r8 has real GPIO base, 0xE0300000, 0xE0200000 at S5PC100, S5PC110 repectively
* r9 has Mobile DDR size, 1 means 1GiB, 2 means 2GiB and so on
*/
_TEXT_BASE:
.word TEXT_BASE
.globl lowlevel_init
lowlevel_init:
mov r11, lr
/* r5 has always zero */
mov r5, #0
ldr r7, =S5PC100_GPIO_BASE
ldr r8, =S5PC100_GPIO_BASE
/* Read CPU ID */
ldr r2, =S5PC1XX_PRO_ID
ldr r0, [r2]
mov r1, #0x00010000
and r0, r0, r1
cmp r0, r5
beq 100f
ldr r8, =S5PC110_GPIO_BASE
100:
/* Turn on KEY_LED_ON [GPJ4(1)] XMSMWEN */
cmp r7, r8
beq skip_check_didle @ Support C110 only
ldr r0, =S5PC110_RST_STAT
ldr r1, [r0]
and r1, r1, #0x000D0000
cmp r1, #(0x1 << 19) @ DEEPIDLE_WAKEUP
beq didle_wakeup
cmp r7, r8
skip_check_didle:
addeq r0, r8, #0x280 @ S5PC100_GPIO_J4
addne r0, r8, #0x2C0 @ S5PC110_GPIO_J4
ldr r1, [r0, #0x0] @ GPIO_CON_OFFSET
bic r1, r1, #(0xf << 4) @ 1 * 4-bit
orr r1, r1, #(0x1 << 4)
str r1, [r0, #0x0] @ GPIO_CON_OFFSET
ldr r1, [r0, #0x4] @ GPIO_DAT_OFFSET
#ifdef CONFIG_ONENAND_IPL
orr r1, r1, #(1 << 1) @ 1 * 1-bit
#else
bic r1, r1, #(1 << 1)
#endif
str r1, [r0, #0x4] @ GPIO_DAT_OFFSET
/* Don't setup at s5pc100 */
beq 100f
/*
* Initialize Async Register Setting for EVT1
* Because we are setting EVT1 as the default value of EVT0,
* setting EVT0 as well does not make things worse.
* Thus, for the simplicity, we set for EVT0, too
*
* The "Async Registers" are:
* 0xE0F0_0000
* 0xE1F0_0000
* 0xF180_0000
* 0xF190_0000
* 0xF1A0_0000
* 0xF1B0_0000
* 0xF1C0_0000
* 0xF1D0_0000
* 0xF1E0_0000
* 0xF1F0_0000
* 0xFAF0_0000
*/
ldr r0, =0xe0f00000
ldr r1, [r0]
bic r1, r1, #0x1
str r1, [r0]
ldr r0, =0xe1f00000
ldr r1, [r0]
bic r1, r1, #0x1
str r1, [r0]
ldr r0, =0xf1800000
ldr r1, [r0]
bic r1, r1, #0x1
str r1, [r0]
ldr r0, =0xf1900000
ldr r1, [r0]
bic r1, r1, #0x1
str r1, [r0]
ldr r0, =0xf1a00000
ldr r1, [r0]
bic r1, r1, #0x1
str r1, [r0]
ldr r0, =0xf1b00000
ldr r1, [r0]
bic r1, r1, #0x1
str r1, [r0]
ldr r0, =0xf1c00000
ldr r1, [r0]
bic r1, r1, #0x1
str r1, [r0]
ldr r0, =0xf1d00000
ldr r1, [r0]
bic r1, r1, #0x1
str r1, [r0]
ldr r0, =0xf1e00000
ldr r1, [r0]
bic r1, r1, #0x1
str r1, [r0]
ldr r0, =0xf1f00000
ldr r1, [r0]
bic r1, r1, #0x1
str r1, [r0]
ldr r0, =0xfaf00000
ldr r1, [r0]
bic r1, r1, #0x1
str r1, [r0]
/*
* Diable ABB block to reduce sleep current at low temperature
* Note that it's hidden register setup don't modify it
*/
ldr r0, =0xE010C300
ldr r1, =0x00800000
str r1, [r0]
100:
/* IO retension release */
ldreq r0, =S5PC100_OTHERS @ 0xE0108200
ldrne r0, =S5PC110_OTHERS @ 0xE010E000
ldr r1, [r0]
ldreq r2, =(1 << 31) @ IO_RET_REL
ldrne r2, =((1 << 31) | (1 << 30) | (1 << 29) | (1 << 28))
orr r1, r1, r2
/* Do not release retention here for S5PC110 */
streq r1, [r0]
#ifndef CONFIG_ONENAND_IPL
/* Disable Watchdog */
ldreq r0, =S5PC100_WATCHDOG_BASE @ 0xEA200000
ldrne r0, =S5PC110_WATCHDOG_BASE @ 0xE2700000
str r5, [r0]
/* setting SRAM */
ldreq r0, =S5PC100_SROMC_BASE
ldrne r0, =S5PC110_SROMC_BASE
ldr r1, =0x9
str r1, [r0]
#endif
/* S5PC100 has 3 groups of interrupt sources */
ldreq r0, =S5PC100_VIC0_BASE @ 0xE4000000
ldrne r0, =S5PC110_VIC0_BASE @ 0xF2000000
add r1, r0, #0x00100000
add r2, r0, #0x00200000
/* Disable all interrupts (VIC0, VIC1 and VIC2) */
mvn r3, #0x0
str r3, [r0, #0x14] @ INTENCLEAR
str r3, [r1, #0x14] @ INTENCLEAR
str r3, [r2, #0x14] @ INTENCLEAR
#ifndef CONFIG_ONENAND_IPL
/* Set all interrupts as IRQ */
str r5, [r0, #0xc] @ INTSELECT
str r5, [r1, #0xc] @ INTSELECT
str r5, [r2, #0xc] @ INTSELECT
/* Pending Interrupt Clear */
str r5, [r0, #0xf00] @ INTADDRESS
str r5, [r1, #0xf00] @ INTADDRESS
str r5, [r2, #0xf00] @ INTADDRESS
#endif
#ifndef CONFIG_ONENAND_IPL
/* for UART */
bl uart_asm_init
bl internal_ram_init
#endif
#ifdef CONFIG_ONENAND_IPL
/* init system clock */
bl system_clock_init
/* OneNAND Sync Read Support at S5PC110 only
* RM[15] : Sync Read
* BRWL[14:12] : 7 CLK
* BL[11:9] : Continuous
* VHF[3] : Very High Frequency Enable (Over 83MHz)
* HF[2] : High Frequency Enable (Over 66MHz)
* WM[1] : Sync Write
*/
cmp r7, r8
ldrne r1, =0xE006
ldrne r0, =0xB001E442
strneh r1, [r0]
/*
* GCE[26] : Gated Clock Enable
* RPE[17] : Enables Read Prefetch
*/
ldrne r1, =((1 << 26) | (1 << 17) | 0xE006)
ldrne r0, =0xB0600000
strne r1, [r0, #0x100] @ ONENAND_IF_CTRL
ldrne r1, =0x1212
strne r1, [r0, #0x108]
/* Board detection to set proper memory configuration */
cmp r7, r8
moveq r9, #1 /* r9 has 1Gib default at s5pc100 */
movne r9, #2 /* r9 has 2Gib default at s5pc110 */
ldr r2, =0xE0200200
ldr r4, [r2, #0x48]
bic r1, r4, #(0x3F << 4) /* PULLUP_DISABLE: 3 * 2-bit */
bic r1, r1, #(0x3 << 2) /* PULLUP_DISABLE: 2 * 2-bit */
bic r1, r1, #(0x3 << 14) /* PULLUP_DISABLE: 2 * 2-bit */
str r1, [r2, #0x48]
/* For write completion */
nop
nop
ldr r3, [r2, #0x44]
and r1, r3, #(0x7 << 2)
mov r1, r1, lsr #2
cmp r1, #0x5
moveq r9, #3
cmp r1, #0x6
moveq r9, #1
cmp r1, #0x7
moveq r9, #2
and r0, r3, #(0x1 << 1)
mov r0, r0, lsr #1
orr r1, r1, r0, lsl #3
cmp r1, #0x8
moveq r9, #3
and r1, r3, #(0x7 << 2)
mov r1, r1, lsr #2
and r0, r3, #(0x1 << 7)
mov r0, r0, lsr #7
orr r1, r1, r0, lsl #3
cmp r1, #0x9
moveq r9, #3
str r4, [r2, #0x48] /* Restore PULLUP configuration */
bl mem_ctrl_asm_init
/* Wakeup support. Don't know if it's going to be used, untested. */
ldreq r0, =S5PC100_RST_STAT
ldrne r0, =S5PC110_RST_STAT
ldr r1, [r0]
biceq r1, r1, #0xfffffff7
moveq r2, #(1 << 3)
bicne r1, r1, #0xfffeffff
movne r2, #(1 << 16)
cmp r1, r2
bne 1f
wakeup:
/* turn off L2 cache */
bl l2_cache_disable
cmp r7, r8
ldreq r0, =0xC100
ldrne r0, =0xC110
/* invalidate L2 cache also */
bl invalidate_dcache
/* turn on L2 cache */
bl l2_cache_enable
cmp r7, r8
/* Load return address and jump to kernel */
ldreq r0, =S5PC100_INFORM0
ldrne r0, =S5PC110_INFORM0
/* r1 = physical address of s5pc1xx_cpu_resume function */
ldr r1, [r0]
/* Jump to kernel (sleep-s5pc1xx.S) */
mov pc, r1
nop
nop
#else
cmp r7, r8
/* Clear wakeup status register */
ldreq r0, =S5PC100_WAKEUP_STAT
ldrne r0, =S5PC110_WAKEUP_STAT
ldr r1, [r0]
str r1, [r0]
/* IO retension release */
ldreq r0, =S5PC100_OTHERS @ 0xE0108200
ldrne r0, =S5PC110_OTHERS @ 0xE010E000
ldr r1, [r0]
ldreq r2, =(1 << 31) @ IO_RET_REL
ldrne r2, =((1 << 31) | (1 << 30) | (1 << 29) | (1 << 28))
orr r1, r1, r2
str r1, [r0]
#endif
b 1f
didle_wakeup:
/* Wait when APLL is locked */
ldr r0, =0xE0100100 @ S5PC110_APLL_CON
lockloop:
ldr r1, [r0]
and r1, r1, #(1 << 29)
cmp r1, #(1 << 29)
bne lockloop
ldr r0, =S5PC110_INFORM0
ldr r1, [r0]
mov pc, r1
nop
nop
nop
nop
nop
1:
mov lr, r11
mov pc, lr
/*
* system_clock_init: Initialize core clock and bus clock.
* void system_clock_init(void)
*/
system_clock_init:
ldr r0, =S5PC1XX_CLOCK_BASE @ 0xE0100000
/* Check S5PC100 */
cmp r7, r8
bne 110f
100:
/* Set Lock Time */
ldr r1, =0xe10 @ Locktime : 0xe10 = 3600
str r1, [r0, #0x000] @ S5PC100_APLL_LOCK
str r1, [r0, #0x004] @ S5PC100_MPLL_LOCK
str r1, [r0, #0x008] @ S5PC100_EPLL_LOCK
str r1, [r0, #0x00C] @ S5PC100_HPLL_LOCK
/* S5P_APLL_CON */
ldr r1, =0x81bc0400 @ SDIV 0, PDIV 4, MDIV 444 (1333MHz)
str r1, [r0, #0x100]
/* S5P_MPLL_CON */
ldr r1, =0x80590201 @ SDIV 1, PDIV 2, MDIV 89 (267MHz)
str r1, [r0, #0x104]
/* S5P_EPLL_CON */
ldr r1, =0x80870303 @ SDIV 3, PDIV 3, MDIV 135 (67.5MHz)
str r1, [r0, #0x108]
/* S5P_HPLL_CON */
ldr r1, =0x80600603 @ SDIV 3, PDIV 6, MDIV 96
str r1, [r0, #0x10C]
ldr r1, [r0, #0x300]
ldr r2, =0x00003fff
bic r1, r1, r2
ldr r2, =0x00011301
orr r1, r1, r2
str r1, [r0, #0x300]
ldr r1, [r0, #0x304]
ldr r2, =0x00011110
orr r1, r1, r2
str r1, [r0, #0x304]
ldr r1, =0x00000001
str r1, [r0, #0x308]
/* Set Source Clock */
ldr r1, =0x00001111 @ A, M, E, HPLL Muxing
str r1, [r0, #0x200] @ S5PC1XX_CLK_SRC0
b 200f
110:
ldr r0, =0xE010C000 @ S5PC110_PWR_CFG
/* Set OSC_FREQ value */
ldr r1, =0xf
str r1, [r0, #0x100] @ S5PC110_OSC_FREQ
/* Set MTC_STABLE value */
ldr r1, =0xffffffff
str r1, [r0, #0x110] @ S5PC110_MTC_STABLE
/* Set CLAMP_STABLE value */
ldr r1, =0x3ff03ff
str r1, [r0, #0x114] @ S5PC110_CLAMP_STABLE
ldr r0, =S5PC1XX_CLOCK_BASE @ 0xE0100000
/* Set Clock divider */
ldr r1, =0x14131330 @ 1:1:4:4, 1:4:5
str r1, [r0, #0x300]
ldr r1, =0x11110111 @ UART[3210]: MMC[3210]
str r1, [r0, #0x310]
/* Set Lock Time */
ldr r1, =0x2cf @ Locktime : 30us
str r1, [r0, #0x000] @ S5PC110_APLL_LOCK
ldr r1, =0xe10 @ Locktime : 0xe10 = 3600
str r1, [r0, #0x008] @ S5PC110_MPLL_LOCK
str r1, [r0, #0x010] @ S5PC110_EPLL_LOCK
str r1, [r0, #0x020] @ S5PC110_VPLL_LOCK
/* S5PC110_APLL_CON */
ldr r1, =0x80C80601 @ 800MHz
str r1, [r0, #0x100]
/* S5PC110_MPLL_CON */
ldr r1, =0x829B0C01 @ 667MHz
str r1, [r0, #0x108]
/* S5PC110_EPLL_CON */
ldr r1, =0x80600602 @ 96MHz VSEL 0 P 6 M 96 S 2
str r1, [r0, #0x110]
/* S5PC110_VPLL_CON */
ldr r1, =0x806C0603 @ 54MHz
str r1, [r0, #0x120]
/* Set Source Clock */
ldr r1, =0x10001111 @ A, M, E, VPLL Muxing
str r1, [r0, #0x200] @ S5PC1XX_CLK_SRC0
/* OneDRAM(DMC0) clock setting */
ldr r1, =0x01000000 @ ONEDRAM_SEL[25:24] 1 SCLKMPLL
str r1, [r0, #0x218] @ S5PC110_CLK_SRC6
ldr r1, =0x30000000 @ ONEDRAM_RATIO[31:28] 3 + 1
str r1, [r0, #0x318] @ S5PC110_CLK_DIV6
/* XCLKOUT = XUSBXTI 24MHz */
add r2, r0, #0xE000 @ S5PC110_OTHERS
ldr r1, [r2]
orr r1, r1, #(0x3 << 8) @ CLKOUT[9:8] 3 XUSBXTI
str r1, [r2]
/* CLK_IP0 */
ldr r1, =0x8fefeeb @ DMC[1:0] PDMA0[3] IMEM[5]
str r1, [r0, #0x460] @ S5PC110_CLK_IP0
/* CLK_IP1 */
ldr r1, =0xe9fdf0f9 @ FIMD[0] USBOTG[16]
@ NANDXL[24]
str r1, [r0, #0x464] @ S5PC110_CLK_IP1
/* CLK_IP2 */
ldr r1, =0xf75f7fc @ CORESIGHT[8] MODEM[9]
@ HOSTIF[10] HSMMC0[16]
@ HSMMC2[18] VIC[27:24]
str r1, [r0, #0x468] @ S5PC110_CLK_IP2
/* CLK_IP3 */
ldr r1, =0x8eff038c @ I2C[8:6]
@ SYSTIMER[16] UART0[17]
@ UART1[18] UART2[19]
@ UART3[20] WDT[22]
@ PWM[23] GPIO[26] SYSCON[27]
str r1, [r0, #0x46c] @ S5PC110_CLK_IP3
/* CLK_IP4 */
ldr r1, =0xfffffff1 @ CHIP_ID[0] TZPC[8:5]
str r1, [r0, #0x470] @ S5PC110_CLK_IP3
200:
/* wait at least 200us to stablize all clock */
mov r2, #0x10000
1: subs r2, r2, #1
bne 1b
mov pc, lr
#ifndef CONFIG_ONENAND_IPL
internal_ram_init:
ldreq r0, =0xE3800000
ldrne r0, =0xF1500000
ldr r1, =0x0
str r1, [r0]
mov pc, lr
#endif
#ifndef CONFIG_ONENAND_IPL
/*
* uart_asm_init: Initialize UART's pins
*/
uart_asm_init:
/* set GPIO to enable UART0-UART4 */
mov r0, r8
ldr r1, =0x22222222
str r1, [r0, #0x0] @ S5PC100_GPIO_A0_OFFSET
ldr r1, =0x00002222
str r1, [r0, #0x20] @ S5PC100_GPIO_A1_OFFSET
/* Check S5PC100 */
cmp r7, r8
bne 110f
/* UART_SEL GPK0[5] at S5PC100 */
add r0, r8, #0x2A0 @ S5PC100_GPIO_K0_OFFSET
ldr r1, [r0, #0x0] @ S5PC1XX_GPIO_CON_OFFSET
bic r1, r1, #(0xf << 20) @ 20 = 5 * 4-bit
orr r1, r1, #(0x1 << 20) @ Output
str r1, [r0, #0x0] @ S5PC1XX_GPIO_CON_OFFSET
ldr r1, [r0, #0x8] @ S5PC1XX_GPIO_PULL_OFFSET
bic r1, r1, #(0x3 << 10) @ 10 = 5 * 2-bit
orr r1, r1, #(0x2 << 10) @ Pull-up enabled
str r1, [r0, #0x8] @ S5PC1XX_GPIO_PULL_OFFSET
ldr r1, [r0, #0x4] @ S5PC1XX_GPIO_DAT_OFFSET
orr r1, r1, #(1 << 5) @ 5 = 5 * 1-bit
str r1, [r0, #0x4] @ S5PC1XX_GPIO_DAT_OFFSET
b 200f
110:
/*
* Note that the following address
* 0xE020'0360 is reserved address at S5PC100
*/
/* UART_SEL MP0_5[7] at S5PC110 */
add r0, r8, #0x360 @ S5PC110_GPIO_MP0_5_OFFSET
ldr r1, [r0, #0x0] @ S5PC1XX_GPIO_CON_OFFSET
bic r1, r1, #(0xf << 28) @ 28 = 7 * 4-bit
orr r1, r1, #(0x1 << 28) @ Output
str r1, [r0, #0x0] @ S5PC1XX_GPIO_CON_OFFSET
ldr r1, [r0, #0x8] @ S5PC1XX_GPIO_PULL_OFFSET
bic r1, r1, #(0x3 << 14) @ 14 = 7 * 2-bit
orr r1, r1, #(0x2 << 14) @ Pull-up enabled
str r1, [r0, #0x8] @ S5PC1XX_GPIO_PULL_OFFSET
ldr r1, [r0, #0x4] @ S5PC1XX_GPIO_DAT_OFFSET
orr r1, r1, #(1 << 7) @ 7 = 7 * 1-bit
str r1, [r0, #0x4] @ S5PC1XX_GPIO_DAT_OFFSET
200:
mov pc, lr
#endif

265
board/samsung/goni/mem_setup.S Normal file
View File

@ -0,0 +1,265 @@
/*
* Copyright (C) 2009 Samsung Electrnoics
* Minkyu Kang <mk7.kang@samsung.com>
* Kyungmin Park <kyungmin.park@samsung.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
.globl mem_ctrl_asm_init
mem_ctrl_asm_init:
cmp r7, r8
ldreq r0, =S5PC100_DMC_BASE @ 0xE6000000
ldrne r0, =S5PC110_DMC0_BASE @ 0xF0000000
ldrne r6, =S5PC110_DMC1_BASE @ 0xF1400000
/* DLL parameter setting */
ldr r1, =0x50101000
str r1, [r0, #0x018] @ PHYCONTROL0_OFFSET
strne r1, [r6, #0x018] @ PHYCONTROL0_OFFSET
ldr r1, =0x000000f4
str r1, [r0, #0x01C] @ PHYCONTROL1_OFFSET
strne r1, [r6, #0x01C] @ PHYCONTROL1_OFFSET
ldreq r1, =0x0
streq r1, [r0, #0x020] @ PHYCONTROL2_OFFSET
/* DLL on */
ldr r1, =0x50101002
str r1, [r0, #0x018] @ PHYCONTROL0_OFFSET
strne r1, [r6, #0x018] @ PHYCONTROL0_OFFSET
/* DLL start */
ldr r1, =0x50101003
str r1, [r0, #0x018] @ PHYCONTROL0_OFFSET
strne r1, [r6, #0x018] @ PHYCONTROL0_OFFSET
mov r2, #0x4000
wait: subs r2, r2, #0x1
cmp r2, #0x0
bne wait
cmp r7, r8
/* Force value locking for DLL off */
str r1, [r0, #0x018] @ PHYCONTROL0_OFFSET
strne r1, [r6, #0x018] @ PHYCONTROL0_OFFSET
/* DLL off */
ldr r1, =0x50101009
str r1, [r0, #0x018] @ PHYCONTROL0_OFFSET
strne r1, [r6, #0x018] @ PHYCONTROL0_OFFSET
/* auto refresh off */
ldr r1, =0xff001010 | (1 << 7)
ldr r2, =0xff001010 | (1 << 7)
str r1, [r0, #0x000] @ CONCONTROL_OFFSET
strne r2, [r6, #0x000] @ CONCONTROL_OFFSET
/*
* Burst Length 4, 2 chips, 32-bit, LPDDR
* OFF: dynamic self refresh, force precharge, dynamic power down off
*/
ldr r1, =0x00212100
ldr r2, =0x00212100
str r1, [r0, #0x004] @ MEMCONTROL_OFFSET
strne r2, [r6, #0x004] @ MEMCONTROL_OFFSET
/*
* Note:
* If Bank0 has Mobile RAM we place it at 0x3800'0000 (s5pc100 only)
* So finally Bank1 OneDRAM should address start at at 0x3000'0000
*/
/*
* DMC0: CS0 : S5PC100/S5PC110
* 0x30 -> 0x30000000
* 0xf8 -> 0x37FFFFFF
* [15:12] 0: Linear
* [11:8 ] 2: 9 bits
* [ 7:4 ] 2: 14 bits
* [ 3:0 ] 2: 4 banks
*/
ldr r3, =0x30f80222
ldr r4, =0x40f00222
swap_memory:
str r3, [r0, #0x008] @ MEMCONFIG0_OFFSET
str r4, [r0, #0x00C] @ dummy write
/*
* DMC1: CS0 : S5PC110
* 0x40 -> 0x40000000
* 0xf8 -> 0x47FFFFFF (1Gib)
* 0x40 -> 0x40000000
* 0xf0 -> 0x4FFFFFFF (2Gib)
* [15:12] 0: Linear
* [11:8 ] 2: 9 bits - Col (1Gib)
* [11:8 ] 3: 10 bits - Col (2Gib)
* [ 7:4 ] 2: 14 bits - Row
* [ 3:0 ] 2: 4 banks
*/
/* Default : 2GiB */
ldr r4, =0x40f01322 @ 2Gib: MCP B
ldr r5, =0x50f81312 @ dummy: MCP D
cmp r9, #1
ldreq r4, =0x40f81222 @ 1Gib: MCP A
cmp r9, #3
ldreq r5, =0x50f81312 @ 2Gib + 1Gib: MCP D
cmp r9, #4
ldreq r5, =0x50f01312 @ 2Gib + 2Gib: MCP E
cmp r7, r8
strne r4, [r6, #0x008] @ MEMCONFIG0_OFFSET
strne r5, [r6, #0x00C] @ MEMCONFIG1_OFFSET
/*
* DMC0: CS1: S5PC100
* 0x38 -> 0x38000000
* 0xf8 -> 0x3fFFFFFF
* [15:12] 0: Linear
* [11:8 ] 2: 9 bits
* [ 7:4 ] 2: 14 bits
* [ 3:0 ] 2: 4 banks
*/
eoreq r3, r3, #0x08000000
streq r3, [r0, #0xc] @ MEMCONFIG1_OFFSET
ldr r1, =0x20000000
str r1, [r0, #0x014] @ PRECHCONFIG_OFFSET
strne r1, [r0, #0x014] @ PRECHCONFIG_OFFSET
strne r1, [r6, #0x014] @ PRECHCONFIG_OFFSET
/*
* S5PC100:
* DMC: CS0: 166MHz
* CS1: 166MHz
* S5PC110:
* DMC0: CS0: 166MHz
* DMC1: CS0: 200MHz
*
* 7.8us * 200MHz %LE %LONG1560(0x618)
* 7.8us * 166MHz %LE %LONG1294(0x50E)
* 7.8us * 133MHz %LE %LONG1038(0x40E),
* 7.8us * 100MHz %LE %LONG780(0x30C),
*/
ldr r1, =0x0000050E
str r1, [r0, #0x030] @ TIMINGAREF_OFFSET
ldrne r1, =0x00000618
strne r1, [r6, #0x030] @ TIMINGAREF_OFFSET
ldr r1, =0x14233287
str r1, [r0, #0x034] @ TIMINGROW_OFFSET
ldrne r1, =0x182332c8
strne r1, [r6, #0x034] @ TIMINGROW_OFFSET
ldr r1, =0x12130005
str r1, [r0, #0x038] @ TIMINGDATA_OFFSET
ldrne r1, =0x13130005
strne r1, [r6, #0x038] @ TIMINGDATA_OFFSET
ldr r1, =0x0E140222
str r1, [r0, #0x03C] @ TIMINGPOWER_OFFSET
ldrne r1, =0x0E180222
strne r1, [r6, #0x03C] @ TIMINGPOWER_OFFSET
/* chip0 Deselect */
ldr r1, =0x07000000
str r1, [r0, #0x010] @ DIRECTCMD_OFFSET
strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET
/* chip0 PALL */
ldr r1, =0x01000000
str r1, [r0, #0x010] @ DIRECTCMD_OFFSET
strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET
/* chip0 REFA */
ldr r1, =0x05000000
str r1, [r0, #0x010] @ DIRECTCMD_OFFSET
strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET
/* chip0 REFA */
str r1, [r0, #0x010] @ DIRECTCMD_OFFSET
strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET
/* chip0 MRS */
ldr r1, =0x00000032
str r1, [r0, #0x010] @ DIRECTCMD_OFFSET
strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET
/* chip0 EMRS */
ldr r1, =0x00020020
str r1, [r0, #0x010] @ DIRECTCMD_OFFSET
strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET
/* chip1 Deselect */
ldr r1, =0x07100000
str r1, [r0, #0x010] @ DIRECTCMD_OFFSET
strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET
/* chip1 PALL */
ldr r1, =0x01100000
str r1, [r0, #0x010] @ DIRECTCMD_OFFSET
strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET
/* chip1 REFA */
ldr r1, =0x05100000
str r1, [r0, #0x010] @ DIRECTCMD_OFFSET
strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET
/* chip1 REFA */
str r1, [r0, #0x010] @ DIRECTCMD_OFFSET
strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET
/* chip1 MRS */
ldr r1, =0x00100032
str r1, [r0, #0x010] @ DIRECTCMD_OFFSET
strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET
/* chip1 EMRS */
ldr r1, =0x00120020
str r1, [r0, #0x010] @ DIRECTCMD_OFFSET
strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET
/* auto refresh on */
ldr r1, =0xFF002030 | (1 << 7)
str r1, [r0, #0x000] @ CONCONTROL_OFFSET
strne r1, [r6, #0x000] @ CONCONTROL_OFFSET
/* PwrdnConfig */
ldr r1, =0x00100002
str r1, [r0, #0x028] @ PWRDNCONFIG_OFFSET
strne r1, [r6, #0x028] @ PWRDNCONFIG_OFFSET
ldr r1, =0x00212113
str r1, [r0, #0x004] @ MEMCONTROL_OFFSET
strne r1, [r6, #0x004] @ MEMCONTROL_OFFSET
/* Skip when S5PC110 */
bne 1f
/* Check OneDRAM access area at s5pc100 */
ldreq r3, =0x38f80222
ldreq r1, =0x37ffff00
str r3, [r1]
ldr r2, [r1]
cmp r2, r3
beq swap_memory
1:
mov pc, lr
.ltorg

36
board/samsung/goni/onenand.c Normal file
View File

@ -0,0 +1,36 @@
/*
* Copyright (C) 2008-2009 Samsung Electronics
* Kyungmin Park <kyungmin.park@samsung.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/onenand.h>
#include <linux/mtd/samsung_onenand.h>
#include <onenand_uboot.h>
void onenand_board_init(struct mtd_info *mtd)
{
struct onenand_chip *this = mtd->priv;
this->base = (void *)CONFIG_SYS_ONENAND_BASE;
this->options |= ONENAND_RUNTIME_BADBLOCK_CHECK;
}

217
include/configs/s5p_goni.h Normal file
View File

@ -0,0 +1,217 @@
/*
* Copyright (C) 2009 Samsung Electronics
* Minkyu Kang <mk7.kang@samsung.com>
* Kyungmin Park <kyungmin.park@samsung.com>
*
* Configuation settings for the SAMSUNG Universal (s5pc100) board.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/* High Level Configuration Options */
#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */
#define CONFIG_SAMSUNG 1 /* in a SAMSUNG core */
#define CONFIG_S5PC1XX 1 /* which is in a S5PC1XX Family */
#define CONFIG_S5PC110 1 /* which is in a S5PC110 */
#define CONFIG_MACH_GONI 1 /* working with Goni */
#include <asm/arch/cpu.h> /* get chip and board defs */
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#undef CONFIG_SKIP_RELOCATE_UBOOT
/* input clock of PLL: has 24MHz input clock at S5PC110 */
#define CONFIG_SYS_CLK_FREQ_C110 24000000
/* DRAM Base */
#define CONFIG_SYS_SDRAM_BASE 0x30000000
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_CMDLINE_TAG
#define CONFIG_INITRD_TAG
#define CONFIG_CMDLINE_EDITING
/*
* Size of malloc() pool
* 1MB = 0x100000, 0x100000 = 1024 * 1024
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20))
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes for */
/* initial data */
/*
* select serial console configuration
*/
#define CONFIG_SERIAL2 1 /* use SERIAL2 */
#define CONFIG_SERIAL_MULTI 1
#define CONFIG_BAUDRATE 115200
/* It should define before config_cmd_default.h */
#define CONFIG_SYS_NO_FLASH 1
/* Command definition */
#include <config_cmd_default.h>
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_MISC
#undef CONFIG_CMD_NET
#undef CONFIG_CMD_NFS
#undef CONFIG_CMD_XIMG
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_ONENAND
#define CONFIG_CMD_MTDPARTS
#define CONFIG_BOOTDELAY 1
#define CONFIG_ZERO_BOOTDELAY_CHECK
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
/* Actual modem binary size is 16MiB. Add 2MiB for bad block handling */
#define MTDIDS_DEFAULT "onenand0=samsung-onenand"
#define MTDPARTS_DEFAULT "mtdparts=samsung-onenand:1m(bootloader)"\
",256k(params)"\
",2816k(config)"\
",8m(csa)"\
",7m(kernel)"\
",1m(log)"\
",12m(modem)"\
",60m(qboot)"\
",-(UBI)\0"
#define NORMAL_MTDPARTS_DEFAULT MTDPARTS_DEFAULT
#define CONFIG_BOOTCOMMAND "run ubifsboot"
#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0"
#define CONFIG_RAMDISK_BOOT "root=/dev/ram0 rw rootfstype=ext2" \
" ${console} ${meminfo}"
#define CONFIG_COMMON_BOOT "${console} ${meminfo} ${mtdparts}"
#define CONFIG_BOOTARGS "root=/dev/mtdblock8 ubi.mtd=8 ubi.mtd=3 ubi.mtd=6" \
" rootfstype=cramfs " CONFIG_COMMON_BOOT
#define CONFIG_UPDATEB "updateb=onenand erase 0x0 0x100000;" \
" onenand write 0x32008000 0x0 0x100000\0"
#define CONFIG_UBI_MTD " ubi.mtd=${ubiblock} ubi.mtd=3 ubi.mtd=6"
#define CONFIG_UBIFS_OPTION "rootflags=bulk_read,no_chk_data_crc"
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define CONFIG_EXTRA_ENV_SETTINGS \
CONFIG_UPDATEB \
"updatek=" \
"onenand erase 0xc00000 0x600000;" \
"onenand write 0x31008000 0xc00000 0x600000\0" \
"updateu=" \
"onenand erase 0x01560000 0x1eaa0000;" \
"onenand write 0x32000000 0x1260000 0x8C0000\0" \
"bootk=" \
"onenand read 0x30007FC0 0xc00000 0x600000;" \
"bootm 0x30007FC0\0" \
"flashboot=" \
"set bootargs root=/dev/mtdblock${bootblock} " \
"rootfstype=${rootfstype}" CONFIG_UBI_MTD " ${opts} " \
"${lcdinfo} " CONFIG_COMMON_BOOT "; run bootk\0" \
"ubifsboot=" \
"set bootargs root=ubi0!rootfs rootfstype=ubifs " \
CONFIG_UBIFS_OPTION CONFIG_UBI_MTD " ${opts} ${lcdinfo} " \
CONFIG_COMMON_BOOT "; run bootk\0" \
"tftpboot=" \
"set bootargs root=ubi0!rootfs rootfstype=ubifs " \
CONFIG_UBIFS_OPTION CONFIG_UBI_MTD " ${opts} ${lcdinfo} " \
CONFIG_COMMON_BOOT "; tftp 0x30007FC0 uImage; " \
"bootm 0x30007FC0\0" \
"ramboot=" \
"set bootargs " CONFIG_RAMDISK_BOOT \
" initrd=0x33000000,8M ramdisk=8192\0" \
"mmcboot=" \
"set bootargs root=${mmcblk} rootfstype=${rootfstype}" \
CONFIG_UBI_MTD " ${opts} ${lcdinfo} " \
CONFIG_COMMON_BOOT "; run bootk\0" \
"boottrace=setenv opts initcall_debug; run bootcmd\0" \
"bootchart=set opts init=/sbin/bootchartd; run bootcmd\0" \
"verify=n\0" \
"rootfstype=cramfs\0" \
"console=" CONFIG_DEFAULT_CONSOLE \
"mtdparts=" MTDPARTS_DEFAULT \
"meminfo=mem=80M mem=256M@0x40000000 mem=128M@0x50000000\0" \
"mmcblk=/dev/mmcblk1p1\0" \
"bootblock=9\0" \
"ubiblock=8\0" \
"ubi=enabled\0" \
"opts=always_resume=1"
/* Miscellaneous configurable options */
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_SYS_PROMPT "Goni # "
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
/* memtest works on */
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5000000)
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4000000)
#define CONFIG_SYS_HZ 1000
/* valid baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
/* Stack sizes */
#define CONFIG_STACKSIZE (256 << 10) /* 256 KiB */
/* Goni has 3 banks of DRAM, but swap the bank */
#define CONFIG_NR_DRAM_BANKS 3
#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* OneDRAM Bank #0 */
#define PHYS_SDRAM_1_SIZE (80 << 20) /* 80 MB in Bank #0 */
#define PHYS_SDRAM_2 0x40000000 /* mDDR DMC1 Bank #1 */
#define PHYS_SDRAM_2_SIZE (256 << 20) /* 256 MB in Bank #1 */
#define PHYS_SDRAM_3 0x50000000 /* mDDR DMC2 Bank #2 */
#define PHYS_SDRAM_3_SIZE (128 << 20) /* 128 MB in Bank #2 */
#define CONFIG_SYS_MONITOR_BASE 0x00000000
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* 256 KiB */
/* FLASH and environment organization */
#define CONFIG_ENV_IS_IN_ONENAND 1
#define CONFIG_ENV_SIZE (256 << 10) /* 256 KiB, 0x40000 */
#define CONFIG_ENV_ADDR (1 << 20) /* 1 MB, 0x100000 */
#define CONFIG_USE_ONENAND_BOARD_INIT
#define CONFIG_SAMSUNG_ONENAND 1
#define CONFIG_SYS_ONENAND_BASE 0xB0000000
#define CONFIG_DOS_PARTITION 1
#endif /* __CONFIG_H */