XPedite5500 board support
Initial support for Extreme Engineering Solutions XPedite5500 - a P2020-based PMC/XMC single board computer. Signed-off-by: John Schmoller <jschmoller@xes-inc.com> Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
John Schmoller
Kumar Gala
parent
66a8b440af
commit
bfe18815e8
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@ -466,6 +466,7 @@ Peter Tyser <ptyser@xes-inc.com>
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xpedite5170 MPC8640
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xpedite5200 MPC8548
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xpedite5370 MPC8572
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xpedite5500 P2020
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David Updegraff <dave@cray.com>
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@ -32,7 +32,9 @@ LIB = $(obj)lib$(VENDOR).a
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COBJS-$(CONFIG_FSL_PCI_INIT) += fsl_8xxx_pci.o
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COBJS-$(CONFIG_MPC8572) += fsl_8xxx_clk.o
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COBJS-$(CONFIG_MPC86xx) += fsl_8xxx_clk.o
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COBJS-$(CONFIG_P2020) += fsl_8xxx_clk.o
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COBJS-$(CONFIG_FSL_DDR2) += fsl_8xxx_ddr.o
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COBJS-$(CONFIG_FSL_DDR3) += fsl_8xxx_ddr.o
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COBJS-$(CONFIG_MPC85xx) += fsl_8xxx_misc.o board.o
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COBJS-$(CONFIG_MPC86xx) += fsl_8xxx_misc.o board.o
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COBJS-$(CONFIG_NAND_ACTL) += actl_nand.o
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@ -38,7 +38,11 @@ unsigned long get_board_sys_clk(ulong dummy)
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if (in_be32(&gur->gpporcr) & 0x10000)
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return 66666666;
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else
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#ifdef CONFIG_P2020
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return 100000000;
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#else
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return 50000000;
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#endif
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}
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#ifdef CONFIG_MPC85xx
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@ -54,6 +58,13 @@ unsigned long get_board_ddr_clk(ulong dummy)
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if (ddr_ratio == 0x7)
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return get_board_sys_clk(dummy);
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#ifdef CONFIG_P2020
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if (in_be32(&gur->gpporcr) & 0x20000)
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return 66666666;
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else
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return 100000000;
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#else
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return 66666666;
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#endif
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}
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#endif
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@ -0,0 +1,39 @@
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#
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# Copyright 2007-2008 Freescale Semiconductor, Inc.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).a
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COBJS-y += $(BOARD).o
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COBJS-y += ddr.o
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COBJS-y += law.o
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COBJS-y += tlb.o
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SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS-y))
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SOBJS := $(addprefix $(obj),$(SOBJS-y))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS)
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$(AR) $(ARFLAGS) $@ $(OBJS)
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clean:
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rm -f $(OBJS) $(SOBJS)
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distclean: clean
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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@ -0,0 +1,165 @@
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/*
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* Copyright 2010 Extreme Engineering Solutions, Inc.
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* Copyright 2007-2008 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <i2c.h>
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#include <asm/fsl_ddr_sdram.h>
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#include <asm/fsl_ddr_dimm_params.h>
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static void get_spd(ddr3_spd_eeprom_t *spd, unsigned char i2c_address)
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{
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i2c_read(i2c_address, SPD_EEPROM_OFFSET, 2, (uchar *)spd,
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sizeof(ddr3_spd_eeprom_t));
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}
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void fsl_ddr_get_spd(ddr3_spd_eeprom_t *ctrl_dimms_spd,
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unsigned int ctrl_num)
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{
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unsigned int i;
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unsigned int i2c_address = 0;
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for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
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if (ctrl_num == 0 && i == 0)
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i2c_address = SPD_EEPROM_ADDRESS1;
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get_spd(&(ctrl_dimms_spd[i]), i2c_address);
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}
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}
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unsigned int fsl_ddr_get_mem_data_rate(void)
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{
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return get_ddr_freq(0);
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}
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/*
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* There are traditionally three board-specific SDRAM timing parameters
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* which must be calculated based on the particular PCB artwork. These are:
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* 1.) CPO (Read Capture Delay)
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* - TIMING_CFG_2 register
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* Source: Calculation based on board trace lengths and
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* chip-specific internal delays.
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* 2.) CLK_ADJUST (Clock and Addr/Cmd alignment control)
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* - DDR_SDRAM_CLK_CNTL register
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* Source: Signal Integrity Simulations
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* 3.) 2T Timing on Addr/Ctl
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* - TIMING_CFG_2 register
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* Source: Signal Integrity Simulations
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* Usually only needed with heavy load/very high speed (>DDR2-800)
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*
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* ====== XPedite550x DDR3-800 read delay calculations ======
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*
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* The P2020 processor provides an autoleveling option. Setting CPO to
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* 0x1f enables this auto configuration.
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*/
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typedef struct {
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unsigned short datarate_mhz_low;
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unsigned short datarate_mhz_high;
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unsigned char clk_adjust;
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unsigned char cpo;
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} board_specific_parameters_t;
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const board_specific_parameters_t board_specific_parameters[][20] = {
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{
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/* Controller 0 */
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{
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/* DDR3-600/667 */
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.datarate_mhz_low = 500,
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.datarate_mhz_high = 750,
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.clk_adjust = 5,
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.cpo = 31,
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},
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{
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/* DDR3-800 */
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.datarate_mhz_low = 750,
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.datarate_mhz_high = 850,
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.clk_adjust = 5,
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.cpo = 31,
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},
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},
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};
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void fsl_ddr_board_options(memctl_options_t *popts,
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dimm_params_t *pdimm,
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unsigned int ctrl_num)
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{
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const board_specific_parameters_t *pbsp =
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&(board_specific_parameters[ctrl_num][0]);
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u32 num_params = sizeof(board_specific_parameters[ctrl_num]) /
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sizeof(board_specific_parameters[0][0]);
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u32 i;
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ulong ddr_freq;
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/*
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* Set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in
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* that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If
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* there are two dimms in the controller, set odt_rd_cfg to 3 and
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* odt_wr_cfg to 3 for the even CS, 0 for the odd CS.
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*/
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for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
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if (i&1) { /* odd CS */
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popts->cs_local_opts[i].odt_rd_cfg = 0;
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popts->cs_local_opts[i].odt_wr_cfg = 0;
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} else { /* even CS */
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if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) {
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popts->cs_local_opts[i].odt_rd_cfg = 0;
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popts->cs_local_opts[i].odt_wr_cfg = 4;
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} else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) {
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popts->cs_local_opts[i].odt_rd_cfg = 3;
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popts->cs_local_opts[i].odt_wr_cfg = 3;
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}
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}
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}
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/*
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* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
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* freqency and n_banks specified in board_specific_parameters table.
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*/
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ddr_freq = get_ddr_freq(0) / 1000000;
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for (i = 0; i < num_params; i++) {
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if (ddr_freq >= pbsp->datarate_mhz_low &&
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ddr_freq <= pbsp->datarate_mhz_high) {
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popts->clk_adjust = pbsp->clk_adjust;
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popts->cpo_override = pbsp->cpo;
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popts->twoT_en = 0;
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}
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pbsp++;
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}
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/*
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* Factors to consider for half-strength driver enable:
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* - number of DIMMs installed
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*/
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popts->half_strength_driver_enable = 0;
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/*
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* Enable on-die termination.
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* From the Micron Technical Node TN-41-04, RTT_Nom should typically
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* be 30 to 40 ohms, while RTT_WR should be 120 ohms. Setting RTT_WR
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* is handled in the Freescale DDR3 driver. Set RTT_Nom here.
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*/
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popts->rtt_override = 1;
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popts->rtt_override_value = 3;
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}
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@ -0,0 +1,54 @@
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/*
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* Copyright 2010 Extreme Engineering Solutions, Inc.
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* Copyright 2008 Freescale Semiconductor, Inc.
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*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/fsl_law.h>
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#include <asm/mmu.h>
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/*
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* Notes:
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* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
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* If flash is 8M at default position (last 8M), no LAW needed.
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*/
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struct law_entry law_table[] = {
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SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
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SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
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#ifdef CONFIG_SYS_PCIE1_MEM_PHYS
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SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_1G, LAW_TRGT_IF_PCIE_1),
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SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1),
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#endif
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#ifdef CONFIG_SYS_PCIE2_MEM_PHYS
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SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_2),
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SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_2),
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#endif
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#ifdef CONFIG_SYS_PCIE3_MEM_PHYS
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SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_3),
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SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_3),
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#endif
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};
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int num_law_entries = ARRAY_SIZE(law_table);
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@ -0,0 +1,98 @@
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/*
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* Copyright 2008 Extreme Engineering Solutions, Inc.
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* Copyright 2008 Freescale Semiconductor, Inc.
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*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
|
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* project.
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*
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* This program is free software; you can redistribute it and/or
|
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* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
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*
|
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* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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* GNU General Public License for more details.
|
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*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/mmu.h>
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struct fsl_e_tlb_entry tlb_table[] = {
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/* TLB 0 - for temp stack in cache */
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SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
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MAS3_SX|MAS3_SW|MAS3_SR, 0,
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0, 0, BOOKE_PAGESZ_4K, 0),
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SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
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CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
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MAS3_SX|MAS3_SW|MAS3_SR, 0,
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0, 0, BOOKE_PAGESZ_4K, 0),
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SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
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CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
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MAS3_SX|MAS3_SW|MAS3_SR, 0,
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0, 0, BOOKE_PAGESZ_4K, 0),
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SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
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CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
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MAS3_SX|MAS3_SW|MAS3_SR, 0,
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0, 0, BOOKE_PAGESZ_4K, 0),
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/* W**G* - NOR flashes */
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/* This will be changed to *I*G* after relocation to RAM. */
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SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE2, CONFIG_SYS_FLASH_BASE2,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
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0, 0, BOOKE_PAGESZ_256M, 1),
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/* *I*G* - CCSRBAR */
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SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 1, BOOKE_PAGESZ_1M, 1),
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/* *I*G* - NAND flash */
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SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 2, BOOKE_PAGESZ_1M, 1),
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/* **M** - Boot page for secondary processors */
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SET_TLB_ENTRY(1, CONFIG_BPTR_VIRT_ADDR, CONFIG_BPTR_VIRT_ADDR,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
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0, 3, BOOKE_PAGESZ_4K, 1),
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#ifdef CONFIG_PCIE1
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/* *I*G* - PCIe */
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SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_PHYS, CONFIG_SYS_PCIE1_MEM_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 4, BOOKE_PAGESZ_1G, 1),
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#endif
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#ifdef CONFIG_PCIE2
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/* *I*G* - PCIe */
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SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_PHYS, CONFIG_SYS_PCIE2_MEM_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 5, BOOKE_PAGESZ_256M, 1),
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#endif
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#ifdef CONFIG_PCIE3
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/* *I*G* - PCIe */
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SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_PHYS, CONFIG_SYS_PCIE3_MEM_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 6, BOOKE_PAGESZ_256M, 1),
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#endif
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#if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || defined(CONFIG_PCIE3)
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/* *I*G* - PCIe */
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SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_PHYS, CONFIG_SYS_PCIE1_IO_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 7, BOOKE_PAGESZ_64M, 1),
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#endif
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};
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int num_tlb_entries = ARRAY_SIZE(tlb_table);
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@ -0,0 +1,107 @@
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/*
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* Copyright 2010 Extreme Engineering Solutions, Inc.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/mmu.h>
|
||||
#include <asm/immap_85xx.h>
|
||||
#include <asm/fsl_pci.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/cache.h>
|
||||
#include <libfdt.h>
|
||||
#include <fdt_support.h>
|
||||
#include <pca953x.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
extern void ft_board_pci_setup(void *blob, bd_t *bd);
|
||||
|
||||
static void flash_cs_fixup(void)
|
||||
{
|
||||
int flash_sel;
|
||||
|
||||
/*
|
||||
* Print boot dev and swap flash flash chip selects if booted from 2nd
|
||||
* flash. Swapping chip selects presents user with a common memory
|
||||
* map regardless of which flash was booted from.
|
||||
*/
|
||||
flash_sel = !((pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) &
|
||||
CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS));
|
||||
printf("FLASH: Executed from FLASH%d\n", flash_sel ? 2 : 1);
|
||||
|
||||
if (flash_sel) {
|
||||
set_lbc_br(0, CONFIG_SYS_BR1_PRELIM);
|
||||
set_lbc_or(0, CONFIG_SYS_OR1_PRELIM);
|
||||
|
||||
set_lbc_br(1, CONFIG_SYS_BR0_PRELIM);
|
||||
set_lbc_or(1, CONFIG_SYS_OR0_PRELIM);
|
||||
}
|
||||
}
|
||||
|
||||
int board_early_init_r(void)
|
||||
{
|
||||
/* Initialize PCA9557 devices */
|
||||
pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0);
|
||||
pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR1, 0xff, 0);
|
||||
pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR2, 0xff, 0);
|
||||
pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR3, 0xff, 0);
|
||||
|
||||
/*
|
||||
* Remap NOR flash region to caching-inhibited
|
||||
* so that flash can be erased/programmed properly.
|
||||
*/
|
||||
|
||||
/* Flush d-cache and invalidate i-cache of any FLASH data */
|
||||
flush_dcache();
|
||||
invalidate_icache();
|
||||
|
||||
/* Invalidate existing TLB entry for NOR flash */
|
||||
disable_tlb(0);
|
||||
set_tlb(1, (CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
|
||||
(CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 0, BOOKE_PAGESZ_256M, 1);
|
||||
|
||||
flash_cs_fixup();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_OF_BOARD_SETUP)
|
||||
void ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
#ifdef CONFIG_PCI
|
||||
ft_board_pci_setup(blob, bd);
|
||||
#endif
|
||||
ft_cpu_setup(blob, bd);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MP
|
||||
extern void cpu_mp_lmb_reserve(struct lmb *lmb);
|
||||
|
||||
void board_lmb_reserve(struct lmb *lmb)
|
||||
{
|
||||
cpu_mp_lmb_reserve(lmb);
|
||||
}
|
||||
#endif
|
||||
|
|
@ -558,6 +558,7 @@ MPC8560ADS powerpc mpc85xx mpc8560ads freescale
|
|||
MPC8568MDS powerpc mpc85xx mpc8568mds freescale
|
||||
xpedite520x powerpc mpc85xx - xes
|
||||
xpedite537x powerpc mpc85xx - xes
|
||||
xpedite550x powerpc mpc85xx - xes
|
||||
sbc8540_33 powerpc mpc85xx sbc8560 - - SBC8540
|
||||
sbc8540_66 powerpc mpc85xx sbc8560 - - SBC8540
|
||||
sbc8548_PCI_33 powerpc mpc85xx sbc8548 - - sbc8548:PCI,33
|
||||
|
|
|
|||
|
|
@ -0,0 +1,607 @@
|
|||
/*
|
||||
* Copyright 2010 Extreme Engineering Solutions, Inc.
|
||||
* Copyright 2007-2008 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* xpedite550x board configuration file
|
||||
*/
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
*/
|
||||
#define CONFIG_BOOKE 1 /* BOOKE */
|
||||
#define CONFIG_E500 1 /* BOOKE e500 family */
|
||||
#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
|
||||
#define CONFIG_P2020 1
|
||||
#define CONFIG_XPEDITE550X 1
|
||||
#define CONFIG_SYS_BOARD_NAME "XPedite5500"
|
||||
#define CONFIG_SYS_FORM_PMC_XMC 1
|
||||
#define CONFIG_PRPMC_PCI_ALIAS "pci0" /* Processor PMC interface on pci0 */
|
||||
#define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */
|
||||
|
||||
#ifndef CONFIG_SYS_TEXT_BASE
|
||||
#define CONFIG_SYS_TEXT_BASE 0xfff80000
|
||||
#endif
|
||||
|
||||
#define CONFIG_PCI 1 /* Enable PCI/PCIE */
|
||||
#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
|
||||
#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
|
||||
#define CONFIG_PCIE1 1 /* PCIE controler 1 (PEX8112 or XMC) */
|
||||
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
|
||||
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
|
||||
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
|
||||
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
|
||||
#define CONFIG_FSL_ELBC 1
|
||||
|
||||
/*
|
||||
* Multicore config
|
||||
*/
|
||||
#define CONFIG_MP
|
||||
#define CONFIG_BPTR_VIRT_ADDR 0xee000000 /* virt boot page address */
|
||||
#define CONFIG_MPC8xxx_DISABLE_BPTR /* Don't leave BPTR enabled */
|
||||
|
||||
/*
|
||||
* DDR config
|
||||
*/
|
||||
#define CONFIG_FSL_DDR3
|
||||
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
|
||||
#define CONFIG_DDR_SPD
|
||||
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
|
||||
#define SPD_EEPROM_ADDRESS1 0x54
|
||||
#define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */
|
||||
#define CONFIG_NUM_DDR_CONTROLLERS 1
|
||||
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
|
||||
#define CONFIG_CHIP_SELECTS_PER_CTRL 2
|
||||
#define CONFIG_DDR_ECC
|
||||
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
|
||||
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
|
||||
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
|
||||
#define CONFIG_VERY_BIG_RAM
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
extern unsigned long get_board_sys_clk(unsigned long dummy);
|
||||
extern unsigned long get_board_ddr_clk(unsigned long dummy);
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */
|
||||
#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */
|
||||
|
||||
/*
|
||||
* These can be toggled for performance analysis, otherwise use default.
|
||||
*/
|
||||
#define CONFIG_L2_CACHE /* toggle L2 cache */
|
||||
#define CONFIG_BTB /* toggle branch predition */
|
||||
#define CONFIG_ENABLE_36BIT_PHYS 1
|
||||
|
||||
/*
|
||||
* Base addresses -- Note these are effective addresses where the
|
||||
* actual resources get mapped (not physical addresses)
|
||||
*/
|
||||
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
|
||||
#define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */
|
||||
#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
|
||||
#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
|
||||
|
||||
/*
|
||||
* Diagnostics
|
||||
*/
|
||||
#define CONFIG_SYS_ALT_MEMTEST
|
||||
#define CONFIG_SYS_MEMTEST_START 0x10000000
|
||||
#define CONFIG_SYS_MEMTEST_END 0x20000000
|
||||
#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
|
||||
CONFIG_SYS_POST_I2C)
|
||||
#define I2C_ADDR_LIST {CONFIG_SYS_I2C_EEPROM_ADDR, \
|
||||
CONFIG_SYS_I2C_LM75_ADDR, \
|
||||
CONFIG_SYS_I2C_LM90_ADDR, \
|
||||
CONFIG_SYS_I2C_PCA953X_ADDR0, \
|
||||
CONFIG_SYS_I2C_PCA953X_ADDR2, \
|
||||
CONFIG_SYS_I2C_PCA953X_ADDR3, \
|
||||
CONFIG_SYS_I2C_RTC_ADDR}
|
||||
|
||||
/*
|
||||
* Memory map
|
||||
* 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
|
||||
* 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable
|
||||
* 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
|
||||
* 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable
|
||||
* 0xee00_0000 0xee00_ffff Boot page translation 4K non-cacheable
|
||||
* 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
|
||||
* 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
|
||||
* 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable
|
||||
* 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable
|
||||
*/
|
||||
|
||||
#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3)
|
||||
|
||||
/*
|
||||
* NAND flash configuration
|
||||
*/
|
||||
#define CONFIG_SYS_NAND_BASE 0xef800000
|
||||
#define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */
|
||||
#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, \
|
||||
CONFIG_SYS_NAND_BASE2}
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 2
|
||||
#define CONFIG_MTD_NAND_VERIFY_WRITE
|
||||
#define CONFIG_SYS_NAND_QUIET_TEST /* 2nd NAND flash not always populated */
|
||||
#define CONFIG_NAND_FSL_ELBC
|
||||
|
||||
/*
|
||||
* NOR flash configuration
|
||||
*/
|
||||
#define CONFIG_SYS_FLASH_BASE 0xf8000000
|
||||
#define CONFIG_SYS_FLASH_BASE2 0xf0000000
|
||||
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
|
||||
#define CONFIG_FLASH_CFI_DRIVER
|
||||
#define CONFIG_SYS_FLASH_CFI
|
||||
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
|
||||
#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \
|
||||
{0xf7f40000, 0xc0000} }
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
|
||||
|
||||
/*
|
||||
* Chip select configuration
|
||||
*/
|
||||
/* NOR Flash 0 on CS0 */
|
||||
#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
|
||||
BR_PS_16 | \
|
||||
BR_V)
|
||||
#define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB | \
|
||||
OR_GPCM_CSNT | \
|
||||
OR_GPCM_XACS | \
|
||||
OR_GPCM_ACS_DIV2 | \
|
||||
OR_GPCM_SCY_8 | \
|
||||
OR_GPCM_TRLX | \
|
||||
OR_GPCM_EHTR | \
|
||||
OR_GPCM_EAD)
|
||||
|
||||
/* NOR Flash 1 on CS1 */
|
||||
#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \
|
||||
BR_PS_16 | \
|
||||
BR_V)
|
||||
#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
|
||||
|
||||
/* NAND flash on CS2 */
|
||||
#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \
|
||||
(2<<BR_DECC_SHIFT) | \
|
||||
BR_PS_8 | \
|
||||
BR_MS_FCM | \
|
||||
BR_V)
|
||||
|
||||
/* NAND flash on CS2 */
|
||||
#define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB | \
|
||||
OR_FCM_PGS | \
|
||||
OR_FCM_CSCT | \
|
||||
OR_FCM_CST | \
|
||||
OR_FCM_CHT | \
|
||||
OR_FCM_SCY_1 | \
|
||||
OR_FCM_TRLX | \
|
||||
OR_FCM_EHTR)
|
||||
|
||||
/* NAND flash on CS3 */
|
||||
#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 | \
|
||||
(2<<BR_DECC_SHIFT) | \
|
||||
BR_PS_8 | \
|
||||
BR_MS_FCM | \
|
||||
BR_V)
|
||||
#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
|
||||
|
||||
/*
|
||||
* Use L1 as initial stack
|
||||
*/
|
||||
#define CONFIG_SYS_INIT_RAM_LOCK 1
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
|
||||
#define CONFIG_SYS_INIT_RAM_END 0x00004000
|
||||
|
||||
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
|
||||
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
|
||||
|
||||
/*
|
||||
* Serial Port
|
||||
*/
|
||||
#define CONFIG_CONS_INDEX 1
|
||||
#define CONFIG_SYS_NS16550
|
||||
#define CONFIG_SYS_NS16550_SERIAL
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE 1
|
||||
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
|
||||
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
|
||||
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE \
|
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
|
||||
|
||||
/*
|
||||
* Use the HUSH parser
|
||||
*/
|
||||
#define CONFIG_SYS_HUSH_PARSER
|
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
|
||||
|
||||
/*
|
||||
* Pass open firmware flat tree
|
||||
*/
|
||||
#define CONFIG_OF_LIBFDT 1
|
||||
#define CONFIG_OF_BOARD_SETUP 1
|
||||
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
|
||||
#define CONFIG_FDT_FIXUP_PCI_IRQ 1
|
||||
|
||||
/*
|
||||
* I2C
|
||||
*/
|
||||
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support */
|
||||
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_I2C2_OFFSET 0x3100
|
||||
#define CONFIG_I2C_MULTI_BUS
|
||||
|
||||
/* I2C DS7505 temperature sensor */
|
||||
#define CONFIG_DTT_LM75
|
||||
#define CONFIG_DTT_SENSORS { 0 }
|
||||
#define CONFIG_SYS_I2C_LM75_ADDR 0x48
|
||||
|
||||
/* I2C ADT7461 temperature sensor */
|
||||
#define CONFIG_SYS_I2C_LM90_ADDR 0x4C
|
||||
|
||||
/* I2C EEPROM - AT24C128B */
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
|
||||
|
||||
/* I2C RTC */
|
||||
#define CONFIG_RTC_M41T11 1
|
||||
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
|
||||
#define CONFIG_SYS_M41T11_BASE_YEAR 2000
|
||||
|
||||
/* GPIO */
|
||||
#define CONFIG_PCA953X
|
||||
#define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
|
||||
#define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c
|
||||
#define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e
|
||||
#define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f
|
||||
#define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0
|
||||
|
||||
/*
|
||||
* GPIO pin definitions, PU = pulled high, PD = pulled low
|
||||
*/
|
||||
/* PCA9557 @ 0x18*/
|
||||
#define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */
|
||||
#define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select (1: RS-485, 0: RS-232) */
|
||||
#define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */
|
||||
#define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select (1: RS-485, 0: RS-232) */
|
||||
#define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */
|
||||
#define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Write protection (0: disabled, 1: enabled) */
|
||||
|
||||
/* PCA9557 @ 0x1e*/
|
||||
#define CONFIG_SYS_PCA953X_XMC_GA0 0x01 /* PU; */
|
||||
#define CONFIG_SYS_PCA953X_XMC_GA1 0x02 /* PU; */
|
||||
#define CONFIG_SYS_PCA953X_XMC_GA2 0x04 /* PU; */
|
||||
#define CONFIG_SYS_PCA953X_XMC_WAKE 0x10 /* PU; */
|
||||
#define CONFIG_SYS_PCA953X_XMC_BIST 0x20 /* Enable XMC BIST */
|
||||
#define CONFIG_SYS_PCA953X_PMC_EREADY 0x40 /* PU; PMC PCI eready */
|
||||
#define CONFIG_SYS_PCA953X_PMC_MONARCH 0x80 /* PMC monarch mode enable */
|
||||
|
||||
/* PCA9557 @ 0x1f */
|
||||
#define CONFIG_SYS_PCA953X_MC_GPIO0 0x01 /* PU; */
|
||||
#define CONFIG_SYS_PCA953X_MC_GPIO1 0x02 /* PU; */
|
||||
#define CONFIG_SYS_PCA953X_MC_GPIO2 0x04 /* PU; */
|
||||
#define CONFIG_SYS_PCA953X_MC_GPIO3 0x08 /* PU; */
|
||||
#define CONFIG_SYS_PCA953X_MC_GPIO4 0x10 /* PU; */
|
||||
#define CONFIG_SYS_PCA953X_MC_GPIO5 0x20 /* PU; */
|
||||
#define CONFIG_SYS_PCA953X_MC_GPIO6 0x40 /* PU; */
|
||||
#define CONFIG_SYS_PCA953X_MC_GPIO7 0x80 /* PU; */
|
||||
|
||||
/*
|
||||
* General PCI
|
||||
* Memory space is mapped 1-1, but I/O space must start from 0.
|
||||
*/
|
||||
|
||||
/* controller 1 - PEX8112 or XMC, depending on build option */
|
||||
#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
|
||||
#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
|
||||
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */
|
||||
#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
|
||||
#define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000
|
||||
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
|
||||
|
||||
|
||||
/*
|
||||
* Networking options
|
||||
*/
|
||||
#define CONFIG_TSEC_ENET /* tsec ethernet support */
|
||||
#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
|
||||
#define CONFIG_NET_MULTI 1
|
||||
#define CONFIG_TSEC_TBI
|
||||
#define CONFIG_MII 1 /* MII PHY management */
|
||||
#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
|
||||
#define CONFIG_ETHPRIME "eTSEC2"
|
||||
|
||||
#define CONFIG_TSEC1 1
|
||||
#define CONFIG_TSEC1_NAME "eTSEC1"
|
||||
#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
|
||||
#define TSEC1_PHY_ADDR 1
|
||||
#define TSEC1_PHYIDX 0
|
||||
#define CONFIG_HAS_ETH0
|
||||
|
||||
#define CONFIG_TSEC2 1
|
||||
#define CONFIG_TSEC2_NAME "eTSEC2"
|
||||
#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
|
||||
#define TSEC2_PHY_ADDR 2
|
||||
#define TSEC2_PHYIDX 0
|
||||
#define CONFIG_HAS_ETH1
|
||||
|
||||
#define CONFIG_TSEC3 1
|
||||
#define CONFIG_TSEC3_NAME "eTSEC3"
|
||||
#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
|
||||
#define TSEC3_PHY_ADDR 3
|
||||
#define TSEC3_PHYIDX 0
|
||||
#define CONFIG_HAS_ETH2
|
||||
|
||||
/*
|
||||
* USB
|
||||
*/
|
||||
#define CONFIG_USB_STORAGE
|
||||
#define CONFIG_USB_EHCI
|
||||
#define CONFIG_USB_EHCI_FSL
|
||||
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
|
||||
#define CONFIG_DOS_PARTITION
|
||||
|
||||
/*
|
||||
* Command configuration.
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#define CONFIG_CMD_ASKENV
|
||||
#define CONFIG_CMD_DATE
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_DTT
|
||||
#define CONFIG_CMD_EEPROM
|
||||
#define CONFIG_CMD_ELF
|
||||
#define CONFIG_CMD_FLASH
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_CMD_JFFS2
|
||||
#define CONFIG_CMD_MII
|
||||
#define CONFIG_CMD_NAND
|
||||
#define CONFIG_CMD_NET
|
||||
#define CONFIG_CMD_PCA953X
|
||||
#define CONFIG_CMD_PCA953X_INFO
|
||||
#define CONFIG_CMD_PCI
|
||||
#define CONFIG_CMD_PCI_ENUM
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_REGINFO
|
||||
#define CONFIG_CMD_SAVEENV
|
||||
#define CONFIG_CMD_SNTP
|
||||
#define CONFIG_CMD_USB
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
|
||||
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
|
||||
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
|
||||
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
|
||||
#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
|
||||
#define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
|
||||
#define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */
|
||||
#define CONFIG_PANIC_HANG /* do not reset board on panic */
|
||||
#define CONFIG_PREBOOT /* enable preboot variable */
|
||||
#define CONFIG_FIT 1
|
||||
#define CONFIG_FIT_VERBOSE 1
|
||||
#define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 16 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
|
||||
#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
|
||||
|
||||
/*
|
||||
* Boot Flags
|
||||
*/
|
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
|
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
||||
|
||||
/*
|
||||
* Environment Configuration
|
||||
*/
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1
|
||||
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */
|
||||
#define CONFIG_ENV_SIZE 0x8000
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024))
|
||||
|
||||
/*
|
||||
* Flash memory map:
|
||||
* fff80000 - ffffffff Pri U-Boot (512 KB)
|
||||
* fff40000 - fff7ffff Pri U-Boot Environment (256 KB)
|
||||
* fff00000 - fff3ffff Pri FDT (256KB)
|
||||
* fef00000 - ffefffff Pri OS image (16MB)
|
||||
* f8000000 - feefffff Pri OS Use/Filesystem (111MB)
|
||||
*
|
||||
* f7f80000 - f7ffffff Sec U-Boot (512 KB)
|
||||
* f7f40000 - f7f7ffff Sec U-Boot Environment (256 KB)
|
||||
* f7f00000 - f7f3ffff Sec FDT (256KB)
|
||||
* f6f00000 - f7efffff Sec OS image (16MB)
|
||||
* f0000000 - f6efffff Sec OS Use/Filesystem (111MB)
|
||||
*/
|
||||
#define CONFIG_UBOOT1_ENV_ADDR MK_STR(0xfff80000)
|
||||
#define CONFIG_UBOOT2_ENV_ADDR MK_STR(0xf7f80000)
|
||||
#define CONFIG_FDT1_ENV_ADDR MK_STR(0xfff00000)
|
||||
#define CONFIG_FDT2_ENV_ADDR MK_STR(0xf7f00000)
|
||||
#define CONFIG_OS1_ENV_ADDR MK_STR(0xfef00000)
|
||||
#define CONFIG_OS2_ENV_ADDR MK_STR(0xf6f00000)
|
||||
|
||||
#define CONFIG_PROG_UBOOT1 \
|
||||
"$download_cmd $loadaddr $ubootfile; " \
|
||||
"if test $? -eq 0; then " \
|
||||
"protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
|
||||
"erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
|
||||
"cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \
|
||||
"protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
|
||||
"cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \
|
||||
"if test $? -ne 0; then " \
|
||||
"echo PROGRAM FAILED; " \
|
||||
"else; " \
|
||||
"echo PROGRAM SUCCEEDED; " \
|
||||
"fi; " \
|
||||
"else; " \
|
||||
"echo DOWNLOAD FAILED; " \
|
||||
"fi;"
|
||||
|
||||
#define CONFIG_PROG_UBOOT2 \
|
||||
"$download_cmd $loadaddr $ubootfile; " \
|
||||
"if test $? -eq 0; then " \
|
||||
"protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
|
||||
"erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
|
||||
"cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \
|
||||
"protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
|
||||
"cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \
|
||||
"if test $? -ne 0; then " \
|
||||
"echo PROGRAM FAILED; " \
|
||||
"else; " \
|
||||
"echo PROGRAM SUCCEEDED; " \
|
||||
"fi; " \
|
||||
"else; " \
|
||||
"echo DOWNLOAD FAILED; " \
|
||||
"fi;"
|
||||
|
||||
#define CONFIG_BOOT_OS_NET \
|
||||
"$download_cmd $osaddr $osfile; " \
|
||||
"if test $? -eq 0; then " \
|
||||
"if test -n $fdtaddr; then " \
|
||||
"$download_cmd $fdtaddr $fdtfile; " \
|
||||
"if test $? -eq 0; then " \
|
||||
"bootm $osaddr - $fdtaddr; " \
|
||||
"else; " \
|
||||
"echo FDT DOWNLOAD FAILED; " \
|
||||
"fi; " \
|
||||
"else; " \
|
||||
"bootm $osaddr; " \
|
||||
"fi; " \
|
||||
"else; " \
|
||||
"echo OS DOWNLOAD FAILED; " \
|
||||
"fi;"
|
||||
|
||||
#define CONFIG_PROG_OS1 \
|
||||
"$download_cmd $osaddr $osfile; " \
|
||||
"if test $? -eq 0; then " \
|
||||
"erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \
|
||||
"cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
|
||||
"cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
|
||||
"if test $? -ne 0; then " \
|
||||
"echo OS PROGRAM FAILED; " \
|
||||
"else; " \
|
||||
"echo OS PROGRAM SUCCEEDED; " \
|
||||
"fi; " \
|
||||
"else; " \
|
||||
"echo OS DOWNLOAD FAILED; " \
|
||||
"fi;"
|
||||
|
||||
#define CONFIG_PROG_OS2 \
|
||||
"$download_cmd $osaddr $osfile; " \
|
||||
"if test $? -eq 0; then " \
|
||||
"erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \
|
||||
"cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
|
||||
"cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
|
||||
"if test $? -ne 0; then " \
|
||||
"echo OS PROGRAM FAILED; " \
|
||||
"else; " \
|
||||
"echo OS PROGRAM SUCCEEDED; " \
|
||||
"fi; " \
|
||||
"else; " \
|
||||
"echo OS DOWNLOAD FAILED; " \
|
||||
"fi;"
|
||||
|
||||
#define CONFIG_PROG_FDT1 \
|
||||
"$download_cmd $fdtaddr $fdtfile; " \
|
||||
"if test $? -eq 0; then " \
|
||||
"erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \
|
||||
"cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
|
||||
"cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
|
||||
"if test $? -ne 0; then " \
|
||||
"echo FDT PROGRAM FAILED; " \
|
||||
"else; " \
|
||||
"echo FDT PROGRAM SUCCEEDED; " \
|
||||
"fi; " \
|
||||
"else; " \
|
||||
"echo FDT DOWNLOAD FAILED; " \
|
||||
"fi;"
|
||||
|
||||
#define CONFIG_PROG_FDT2 \
|
||||
"$download_cmd $fdtaddr $fdtfile; " \
|
||||
"if test $? -eq 0; then " \
|
||||
"erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \
|
||||
"cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
|
||||
"cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
|
||||
"if test $? -ne 0; then " \
|
||||
"echo FDT PROGRAM FAILED; " \
|
||||
"else; " \
|
||||
"echo FDT PROGRAM SUCCEEDED; " \
|
||||
"fi; " \
|
||||
"else; " \
|
||||
"echo FDT DOWNLOAD FAILED; " \
|
||||
"fi;"
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"autoload=yes\0" \
|
||||
"download_cmd=tftp\0" \
|
||||
"console_args=console=ttyS0,115200\0" \
|
||||
"root_args=root=/dev/nfs rw\0" \
|
||||
"misc_args=ip=on\0" \
|
||||
"set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
|
||||
"bootfile=/home/user/file\0" \
|
||||
"osfile=/home/user/board.uImage\0" \
|
||||
"fdtfile=/home/user/board.dtb\0" \
|
||||
"ubootfile=/home/user/u-boot.bin\0" \
|
||||
"fdtaddr=c00000\0" \
|
||||
"osaddr=0x1000000\0" \
|
||||
"loadaddr=0x1000000\0" \
|
||||
"prog_uboot1="CONFIG_PROG_UBOOT1"\0" \
|
||||
"prog_uboot2="CONFIG_PROG_UBOOT2"\0" \
|
||||
"prog_os1="CONFIG_PROG_OS1"\0" \
|
||||
"prog_os2="CONFIG_PROG_OS2"\0" \
|
||||
"prog_fdt1="CONFIG_PROG_FDT1"\0" \
|
||||
"prog_fdt2="CONFIG_PROG_FDT2"\0" \
|
||||
"bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
|
||||
"bootcmd_flash1=run set_bootargs; " \
|
||||
"bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
|
||||
"bootcmd_flash2=run set_bootargs; " \
|
||||
"bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
|
||||
"bootcmd=run bootcmd_flash1\0"
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in New Issue