ColdFire: Add M5208EVB and MCF520x CPU support
Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
This commit is contained in:
TsiChung Liew
TsiChung Liew
parent
709b384b64
commit
bf9a521529
1
MAKEALL
1
MAKEALL
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@ -769,6 +769,7 @@ LIST_coldfire=" \
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EB+MCF-EV123 \
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EB+MCF-EV123_internal \
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idmr \
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M5208EVBE \
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M52277EVB \
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M5235EVB \
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M5249EVB \
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3
Makefile
3
Makefile
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@ -2004,6 +2004,9 @@ ZPC1900_config: unconfig
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## Coldfire
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#########################################################################
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M5208EVBE_config : unconfig
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@$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5208evbe freescale
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M52277EVB_config \
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M52277EVB_spansion_config \
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M52277EVB_stmicro_config : unconfig
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@ -0,0 +1,44 @@
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#
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# (C) Copyright 2000-2003
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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||||
# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).a
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COBJS = $(BOARD).o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS)
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$(AR) $(ARFLAGS) $@ $(OBJS)
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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@ -0,0 +1,25 @@
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#
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# (C) Copyright 2000-2003
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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TEXT_BASE = 0
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@ -0,0 +1,94 @@
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/*
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* (C) Copyright 2000-2003
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <common.h>
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#include <asm/immap.h>
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DECLARE_GLOBAL_DATA_PTR;
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int checkboard(void)
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{
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puts("Board: ");
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puts("Freescale M5208EVBe\n");
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return 0;
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};
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phys_size_t initdram(int board_type)
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{
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volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
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u32 dramsize, i;
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dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
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for (i = 0x13; i < 0x20; i++) {
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if (dramsize == (1 << i))
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break;
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}
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i--;
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sdram->cs0 = (CONFIG_SYS_SDRAM_BASE | i);
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#ifdef CONFIG_SYS_SDRAM_BASE1
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sdram->cs1 = (CONFIG_SYS_SDRAM_BASE | i);
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#endif
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sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1;
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sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2;
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udelay(500);
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/* Issue PALL */
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sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
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asm("nop");
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/* Perform two refresh cycles */
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sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
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sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
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asm("nop");
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/* Issue LEMR */
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sdram->mode = CONFIG_SYS_SDRAM_MODE;
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asm("nop");
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sdram->mode = CONFIG_SYS_SDRAM_EMOD;
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asm("nop");
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sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
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asm("nop");
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sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00;
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asm("nop");
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udelay(100);
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return dramsize;
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};
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int testdram(void)
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{
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/* TODO: XXX XXX XXX */
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printf("DRAM test not implemented!\n");
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return (0);
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}
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@ -0,0 +1,142 @@
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/*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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OUTPUT_ARCH(m68k)
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/* Do we need any of these for elf?
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__DYNAMIC = 0; */
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SECTIONS
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{
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/* Read-only sections, merged into text segment: */
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. = + SIZEOF_HEADERS;
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.interp : { *(.interp) }
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.hash : { *(.hash) }
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.dynsym : { *(.dynsym) }
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.dynstr : { *(.dynstr) }
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.rel.text : { *(.rel.text) }
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.rela.text : { *(.rela.text) }
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.rel.data : { *(.rel.data) }
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.rela.data : { *(.rela.data) }
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.rel.rodata : { *(.rel.rodata) }
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.rela.rodata : { *(.rela.rodata) }
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.rel.got : { *(.rel.got) }
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.rela.got : { *(.rela.got) }
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.rel.ctors : { *(.rel.ctors) }
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.rela.ctors : { *(.rela.ctors) }
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.rel.dtors : { *(.rel.dtors) }
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.rela.dtors : { *(.rela.dtors) }
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.rel.bss : { *(.rel.bss) }
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.rela.bss : { *(.rela.bss) }
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.rel.plt : { *(.rel.plt) }
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.rela.plt : { *(.rela.plt) }
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.init : { *(.init) }
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.plt : { *(.plt) }
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.text :
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{
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/* WARNING - the following is hand-optimized to fit within */
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/* the sector layout of our flash chips! XXX FIXME XXX */
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cpu/mcf52x2/start.o (.text)
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cpu/mcf52x2/libmcf52x2.a (.text)
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lib_m68k/libm68k.a (.text)
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common/dlmalloc.o (.text)
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. = DEFINED(env_offset) ? env_offset : .;
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common/env_embedded.o (.text)
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*(.text)
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*(.fixup)
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*(.got1)
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}
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_etext = .;
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PROVIDE (etext = .);
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.rodata :
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{
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*(.rodata)
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*(.rodata1)
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}
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.fini : { *(.fini) } =0
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.ctors : { *(.ctors) }
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.dtors : { *(.dtors) }
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/* Read-write section, merged into data segment: */
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. = (. + 0x00FF) & 0xFFFFFF00;
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_erotext = .;
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PROVIDE (erotext = .);
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.reloc :
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{
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__got_start = .;
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*(.got)
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__got_end = .;
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_GOT2_TABLE_ = .;
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*(.got2)
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_FIXUP_TABLE_ = .;
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*(.fixup)
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}
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__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
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__fixup_entries = (. - _FIXUP_TABLE_)>>2;
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.data :
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{
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*(.data)
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*(.data1)
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*(.sdata)
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*(.sdata2)
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*(.dynamic)
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CONSTRUCTORS
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}
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_edata = .;
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PROVIDE (edata = .);
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. = .;
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__u_boot_cmd_start = .;
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.u_boot_cmd : { *(.u_boot_cmd) }
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__u_boot_cmd_end = .;
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. = .;
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__start___ex_table = .;
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__ex_table : { *(__ex_table) }
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__stop___ex_table = .;
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. = ALIGN(256);
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__init_begin = .;
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.text.init : { *(.text.init) }
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.data.init : { *(.data.init) }
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. = ALIGN(256);
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__init_end = .;
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__bss_start = .;
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.bss (NOLOAD) :
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{
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_sbss = .;
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*(.sbss) *(.scommon)
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*(.dynbss)
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*(.bss)
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*(COMMON)
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. = ALIGN(4);
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_ebss = .;
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}
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_end = . ;
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PROVIDE (end = .);
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}
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@ -26,6 +26,7 @@
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PLATFORM_RELFLAGS += -ffixed-d7 -msep-data
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cfg=$(shell grep configs $(OBJTREE)/include/config.h | sed 's/.*<\(configs.*\)>/\1/')
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is5208:=$(shell grep CONFIG_M5208 $(TOPDIR)/include/$(cfg))
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is5249:=$(shell grep CONFIG_M5249 $(TOPDIR)/include/$(cfg))
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is5253:=$(shell grep CONFIG_M5253 $(TOPDIR)/include/$(cfg))
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is5271:=$(shell grep CONFIG_M5271 $(TOPDIR)/include/$(cfg))
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@ -36,6 +37,9 @@ is5282:=$(shell grep CONFIG_M5282 $(TOPDIR)/include/$(cfg))
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ifneq ($(findstring 4.1,$(shell $(CC) --version)),4.1)
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ifneq (,$(findstring CONFIG_M5208,$(is5208)))
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PLATFORM_CPPFLAGS += -mcpu=5208
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endif
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ifneq (,$(findstring CONFIG_M5249,$(is5249)))
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PLATFORM_CPPFLAGS += -mcpu=5249
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endif
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@ -34,6 +34,72 @@
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#include <asm/immap.h>
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#include <netdev.h>
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_M5208
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int do_reset(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
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{
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volatile rcm_t *rcm = (rcm_t *)(MMAP_RCM);
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udelay(1000);
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rcm->rcr = RCM_RCR_SOFTRST;
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/* we don't return! */
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return 0;
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};
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int checkcpu(void)
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{
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char buf1[32], buf2[32];
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printf("CPU: Freescale Coldfire MCF5208\n"
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" CPU CLK %s MHz BUS CLK %s MHz\n",
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strmhz(buf1, gd->cpu_clk),
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strmhz(buf2, gd->bus_clk));
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return 0;
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};
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#if defined(CONFIG_WATCHDOG)
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/* Called by macro WATCHDOG_RESET */
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void watchdog_reset(void)
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{
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volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
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wdt->sr = 0x5555;
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wdt->sr = 0xAAAA;
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}
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int watchdog_disable(void)
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{
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volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
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||||
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wdt->sr = 0x5555; /* reset watchdog counteDECLARE_GLOBAL_DATA_PTR;
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||||
r */
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||||
wdt->sr = 0xAAAA;
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wdt->cr = 0; /* disable watchdog timer */
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puts("WATCHDOG:disabled\n");
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return (0);
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}
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int watchdog_init(void)
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{
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volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
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||||
wdt->cr = 0; /* disable watchdog */
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||||
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||||
/* set timeout and enable watchdog */
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wdt->mr =
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((CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000)) - 1;
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wdt->sr = 0x5555; /* reset watchdog counter */
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||||
wdt->sr = 0xAAAA;
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||||
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||||
puts("WATCHDOG:enabled\n");
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return (0);
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||||
}
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||||
#endif /* #ifdef CONFIG_WATCHDOG */
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||||
#endif /* #ifdef CONFIG_M5208 */
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||||
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#ifdef CONFIG_M5271
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/*
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* Both MCF5270 and MCF5271 are members of the MPC5271 family. Try to
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@ -101,6 +101,95 @@ void init_fbcs(void)
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}
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#endif
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||||
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||||
#if defined(CONFIG_M5208)
|
||||
void cpu_init_f(void)
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{
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volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
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||||
|
||||
#ifndef CONFIG_WATCHDOG
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||||
volatile wdog_t *wdg = (wdog_t *) MMAP_WDOG;
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||||
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||||
/* Disable the watchdog if we aren't using it */
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wdg->cr = 0;
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#endif
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||||
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||||
scm1->mpr = 0x77777777;
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scm1->pacra = 0;
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||||
scm1->pacrb = 0;
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||||
scm1->pacrc = 0;
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||||
scm1->pacrd = 0;
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scm1->pacre = 0;
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scm1->pacrf = 0;
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||||
/* FlexBus Chipselect */
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init_fbcs();
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||||
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||||
icache_enable();
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||||
}
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||||
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||||
/* initialize higher level parts of CPU like timers */
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int cpu_init_r(void)
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||||
{
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||||
return (0);
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||||
}
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||||
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||||
void uart_port_conf(void)
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||||
{
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||||
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
|
||||
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||||
/* Setup Ports: */
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||||
switch (CONFIG_SYS_UART_PORT) {
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||||
case 0:
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||||
gpio->par_uart &= GPIO_PAR_UART0_MASK;
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||||
gpio->par_uart |= (GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD);
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||||
break;
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case 1:
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gpio->par_uart &= GPIO_PAR_UART0_MASK;
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||||
gpio->par_uart |= (GPIO_PAR_UART_U1TXD | GPIO_PAR_UART_U1RXD);
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||||
break;
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||||
case 2:
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||||
#ifdef CONFIG_SYS_UART2_PRI_GPIO
|
||||
gpio->par_timer &=
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||||
(GPIO_PAR_TMR_TIN0_MASK | GPIO_PAR_TMR_TIN1_MASK);
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||||
gpio->par_timer |=
|
||||
(GPIO_PAR_TMR_TIN0_U2TXD | GPIO_PAR_TMR_TIN1_U2RXD);
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_UART2_ALT1_GPIO
|
||||
gpio->par_feci2c &=
|
||||
(GPIO_PAR_FECI2C_MDC_MASK | GPIO_PAR_FECI2C_MDIO_MASK);
|
||||
gpio->par_feci2c |=
|
||||
(GPIO_PAR_FECI2C_MDC_U2TXD | GPIO_PAR_FECI2C_MDIO_U2RXD);
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_UART2_ALT1_GPIO
|
||||
gpio->par_feci2c &=
|
||||
(GPIO_PAR_FECI2C_SDA_MASK | GPIO_PAR_FECI2C_SCL_MASK);
|
||||
gpio->par_feci2c |=
|
||||
(GPIO_PAR_FECI2C_SDA_U2TXD | GPIO_PAR_FECI2C_SCL_U2RXD);
|
||||
#endif
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
#if defined(CONFIG_CMD_NET)
|
||||
int fecpin_setclear(struct eth_device *dev, int setclear)
|
||||
{
|
||||
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
|
||||
|
||||
if (setclear) {
|
||||
gpio->par_fec |=
|
||||
GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC;
|
||||
gpio->par_feci2c |=
|
||||
GPIO_PAR_FECI2C_MDC_MDC | GPIO_PAR_FECI2C_MDIO_MDIO;
|
||||
} else {
|
||||
gpio->par_fec &=
|
||||
(GPIO_PAR_FEC_7W_MASK & GPIO_PAR_FEC_MII_MASK);
|
||||
gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII_MASK;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_CMD_NET */
|
||||
#endif /* CONFIG_M5208 */
|
||||
|
||||
#if defined(CONFIG_M5253)
|
||||
/*
|
||||
* Breath some life into the CPU...
|
||||
|
|
|
|||
|
|
@ -59,13 +59,19 @@ void dtimer_intr_setup(void)
|
|||
#endif /* CONFIG_MCFTMR */
|
||||
#endif /* CONFIG_M5272 */
|
||||
|
||||
#if defined(CONFIG_M5282) || defined(CONFIG_M5271) || defined(CONFIG_M5275)
|
||||
#if defined(CONFIG_M5208) || defined(CONFIG_M5282) || \
|
||||
defined(CONFIG_M5271) || defined(CONFIG_M5275)
|
||||
int interrupt_init(void)
|
||||
{
|
||||
volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
|
||||
|
||||
/* Make sure all interrupts are disabled */
|
||||
#if defined(CONFIG_M5208)
|
||||
intp->imrl0 = 0xFFFFFFFF;
|
||||
intp->imrh0 = 0xFFFFFFFF;
|
||||
#else
|
||||
intp->imrl0 |= 0x1;
|
||||
#endif
|
||||
|
||||
enable_interrupts();
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -30,11 +30,16 @@
|
|||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
/*
|
||||
* get_clocks() fills in gd->cpu_clock and gd->bus_clk
|
||||
*/
|
||||
/* get_clocks() fills in gd->cpu_clock and gd->bus_clk */
|
||||
int get_clocks (void)
|
||||
{
|
||||
#if defined(CONFIG_M5208)
|
||||
volatile pll_t *pll = (pll_t *) MMAP_PLL;
|
||||
|
||||
pll->odr = CONFIG_SYS_PLL_ODR;
|
||||
pll->fdr = CONFIG_SYS_PLL_FDR;
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_M5249) || defined(CONFIG_M5253)
|
||||
volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR);
|
||||
unsigned long pllcr;
|
||||
|
|
@ -77,7 +82,7 @@ int get_clocks (void)
|
|||
#endif
|
||||
|
||||
gd->cpu_clk = CONFIG_SYS_CLK;
|
||||
#if defined(CONFIG_M5249) || defined(CONFIG_M5253) || \
|
||||
#if defined(CONFIG_M5208) || defined(CONFIG_M5249) || defined(CONFIG_M5253) || \
|
||||
defined(CONFIG_M5271) || defined(CONFIG_M5275)
|
||||
gd->bus_clk = gd->cpu_clk / 2;
|
||||
#else
|
||||
|
|
|
|||
|
|
@ -120,6 +120,12 @@ _start:
|
|||
nop
|
||||
move.w #0x2700,%sr
|
||||
|
||||
#if defined(CONFIG_M5208)
|
||||
/* Initialize RAMBAR: locate SRAM and validate it */
|
||||
move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
|
||||
movec %d0, %RAMBAR1
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_M5272) || defined(CONFIG_M5249) || defined(CONFIG_M5253)
|
||||
move.l #(CONFIG_SYS_MBAR + 1), %d0 /* set MBAR address + valid flag */
|
||||
move.c %d0, %MBAR
|
||||
|
|
@ -195,15 +201,6 @@ _after_flashbar_copy:
|
|||
movec %d0, %RAMBAR1
|
||||
#endif
|
||||
|
||||
#if 0
|
||||
/* invalidate and disable cache */
|
||||
move.l #0x01000000, %d0 /* Invalidate cache cmd */
|
||||
movec %d0, %CACR /* Invalidate cache */
|
||||
move.l #0, %d0
|
||||
movec %d0, %ACR0
|
||||
movec %d0, %ACR1
|
||||
#endif
|
||||
|
||||
/* set stackpointer to end of internal ram to get some stackspace for the first c-code */
|
||||
move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
|
||||
clr.l %sp@-
|
||||
|
|
@ -340,6 +337,24 @@ _int_handler:
|
|||
|
||||
/*------------------------------------------------------------------------------*/
|
||||
/* cache functions */
|
||||
#ifdef CONFIG_M5208
|
||||
.globl icache_enable
|
||||
icache_enable:
|
||||
move.l #0x01000000, %d0 /* Invalidate cache cmd */
|
||||
movec %d0, %CACR /* Invalidate cache */
|
||||
move.l #(CONFIG_SYS_SDRAM_BASE + 0xC000), %d0 /* Setup cache mask */
|
||||
movec %d0, %ACR0 /* Enable cache */
|
||||
|
||||
move.l #0x80000200, %d0 /* Setup cache mask */
|
||||
movec %d0, %CACR /* Enable cache */
|
||||
nop
|
||||
|
||||
move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1
|
||||
moveq #1, %d0
|
||||
move.l %d0, (%a1)
|
||||
rts
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_M5271
|
||||
.globl icache_enable
|
||||
icache_enable:
|
||||
|
|
|
|||
|
|
@ -26,6 +26,35 @@
|
|||
#ifndef __IMMAP_H
|
||||
#define __IMMAP_H
|
||||
|
||||
#if defined(CONFIG_MCF520x)
|
||||
#include <asm/immap_520x.h>
|
||||
#include <asm/m520x.h>
|
||||
|
||||
#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
|
||||
#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000))
|
||||
|
||||
/* Timer */
|
||||
#ifdef CONFIG_MCFTMR
|
||||
#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
|
||||
#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
|
||||
#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
|
||||
#define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
|
||||
#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
|
||||
#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
|
||||
#define CONFIG_SYS_TMRINTR_PRI (6)
|
||||
#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MCFPIT
|
||||
#define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0)
|
||||
#define CONFIG_SYS_PIT_BASE (MMAP_PIT1)
|
||||
#define CONFIG_SYS_PIT_PRESCALE (6)
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
|
||||
#define CONFIG_SYS_NUM_IRQS (128)
|
||||
#endif /* CONFIG_M520x */
|
||||
|
||||
#ifdef CONFIG_M52277
|
||||
#include <asm/immap_5227x.h>
|
||||
#include <asm/m5227x.h>
|
||||
|
|
|
|||
|
|
@ -0,0 +1,212 @@
|
|||
/*
|
||||
* MCF520x Internal Memory Map
|
||||
*
|
||||
* Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __IMMAP_520X__
|
||||
#define __IMMAP_520X__
|
||||
|
||||
#define MMAP_SCM1 (CONFIG_SYS_MBAR + 0x00000000)
|
||||
#define MMAP_XBS (CONFIG_SYS_MBAR + 0x00004000)
|
||||
#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00008000)
|
||||
#define MMAP_FEC0 (CONFIG_SYS_MBAR + 0x00030000)
|
||||
#define MMAP_SCM2 (CONFIG_SYS_MBAR + 0x00040000)
|
||||
#define MMAP_EDMA (CONFIG_SYS_MBAR + 0x00044000)
|
||||
#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00048000)
|
||||
#define MMAP_INTCACK (CONFIG_SYS_MBAR + 0x00054000)
|
||||
#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00058000)
|
||||
#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x0005C000)
|
||||
#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00060000)
|
||||
#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00064000)
|
||||
#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00068000)
|
||||
#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00070000)
|
||||
#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00074000)
|
||||
#define MMAP_DTMR2 (CONFIG_SYS_MBAR + 0x00078000)
|
||||
#define MMAP_DTMR3 (CONFIG_SYS_MBAR + 0x0007C000)
|
||||
#define MMAP_PIT0 (CONFIG_SYS_MBAR + 0x00080000)
|
||||
#define MMAP_PIT1 (CONFIG_SYS_MBAR + 0x00084000)
|
||||
#define MMAP_EPORT0 (CONFIG_SYS_MBAR + 0x00088000)
|
||||
#define MMAP_WDOG (CONFIG_SYS_MBAR + 0x0008C000)
|
||||
#define MMAP_PLL (CONFIG_SYS_MBAR + 0x00090000)
|
||||
#define MMAP_RCM (CONFIG_SYS_MBAR + 0x000A0000)
|
||||
#define MMAP_CCM (CONFIG_SYS_MBAR + 0x000A0004)
|
||||
#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x000A4000)
|
||||
#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x000A8000)
|
||||
|
||||
#include <asm/coldfire/crossbar.h>
|
||||
#include <asm/coldfire/edma.h>
|
||||
#include <asm/coldfire/eport.h>
|
||||
#include <asm/coldfire/flexbus.h>
|
||||
#include <asm/coldfire/intctrl.h>
|
||||
#include <asm/coldfire/qspi.h>
|
||||
|
||||
/* System Controller Module */
|
||||
typedef struct scm1 {
|
||||
u32 mpr; /* 0x00 Master Privilege */
|
||||
u32 rsvd1[7];
|
||||
u32 pacra; /* 0x20 Peripheral Access Ctrl A */
|
||||
u32 pacrb; /* 0x24 Peripheral Access Ctrl B */
|
||||
u32 pacrc; /* 0x28 Peripheral Access Ctrl C */
|
||||
u32 pacrd; /* 0x2C Peripheral Access Ctrl D */
|
||||
u32 rsvd2[4];
|
||||
u32 pacre; /* 0x40 Peripheral Access Ctrl E */
|
||||
u32 pacrf; /* 0x44 Peripheral Access Ctrl F */
|
||||
u32 rsvd3[3];
|
||||
u32 bmt; /* 0x50 bus monitor */
|
||||
} scm1_t;
|
||||
|
||||
typedef struct scm2 {
|
||||
u8 rsvd1[19]; /* 0x00 - 0x12 */
|
||||
u8 wcr; /* 0x13 */
|
||||
u16 rsvd2; /* 0x14 - 0x15 */
|
||||
u16 cwcr; /* 0x16 */
|
||||
u8 rsvd3[3]; /* 0x18 - 0x1A */
|
||||
u8 cwsr; /* 0x1B */
|
||||
u8 rsvd4[3]; /* 0x1C - 0x1E */
|
||||
u8 scmisr; /* 0x1F */
|
||||
u8 rsvd5[79]; /* 0x20 - 0x6F */
|
||||
u32 cfadr; /* 0x70 */
|
||||
u8 rsvd7; /* 0x74 */
|
||||
u8 cfier; /* 0x75 */
|
||||
u8 cfloc; /* 0x76 */
|
||||
u8 cfatr; /* 0x77 */
|
||||
u32 rsvd8; /* 0x78 - 0x7B */
|
||||
u32 cfdtr; /* 0x7C */
|
||||
} scm2_t;
|
||||
|
||||
/* Chip configuration module */
|
||||
typedef struct rcm {
|
||||
u8 rcr;
|
||||
u8 rsr;
|
||||
} rcm_t;
|
||||
|
||||
typedef struct ccm_ctrl {
|
||||
u16 ccr; /* 0x00 Chip Cfg */
|
||||
u16 res1; /* 0x02 */
|
||||
u16 rcon; /* 0x04 Reset Cfg */
|
||||
u16 cir; /* 0x06 Chip ID */
|
||||
} ccm_t;
|
||||
|
||||
/* GPIO port */
|
||||
typedef struct gpio_ctrl {
|
||||
/* Port Output Data */
|
||||
u8 podr_busctl; /* 0x00 */
|
||||
u8 podr_be; /* 0x01 */
|
||||
u8 podr_cs; /* 0x02 */
|
||||
u8 podr_feci2c; /* 0x03 */
|
||||
u8 podr_qspi; /* 0x04 */
|
||||
u8 podr_timer; /* 0x05 */
|
||||
u8 podr_uart; /* 0x06 */
|
||||
u8 podr_fech; /* 0x07 */
|
||||
u8 podr_fecl; /* 0x08 */
|
||||
u8 res01[3]; /* 0x9 - 0x0B */
|
||||
|
||||
/* Port Data Direction */
|
||||
u8 pddr_busctl; /* 0x0C */
|
||||
u8 pddr_be; /* 0x0D */
|
||||
u8 pddr_cs; /* 0x0E */
|
||||
u8 pddr_feci2c; /* 0x0F */
|
||||
u8 pddr_qspi; /* 0x10*/
|
||||
u8 pddr_timer; /* 0x11 */
|
||||
u8 pddr_uart; /* 0x12 */
|
||||
u8 pddr_fech; /* 0x13 */
|
||||
u8 pddr_fecl; /* 0x14 */
|
||||
u8 res02[5]; /* 0x15 - 0x19 */
|
||||
|
||||
/* Port Data Direction */
|
||||
u8 ppdr_cs; /* 0x1A */
|
||||
u8 ppdr_feci2c; /* 0x1B */
|
||||
u8 ppdr_qspi; /* 0x1C */
|
||||
u8 ppdr_timer; /* 0x1D */
|
||||
u8 ppdr_uart; /* 0x1E */
|
||||
u8 ppdr_fech; /* 0x1F */
|
||||
u8 ppdr_fecl; /* 0x20 */
|
||||
u8 res03[3]; /* 0x21 - 0x23 */
|
||||
|
||||
/* Port Clear Output Data */
|
||||
u8 pclrr_busctl; /* 0x24 */
|
||||
u8 pclrr_be; /* 0x25 */
|
||||
u8 pclrr_cs; /* 0x26 */
|
||||
u8 pclrr_feci2c; /* 0x27 */
|
||||
u8 pclrr_qspi; /* 0x28 */
|
||||
u8 pclrr_timer; /* 0x29 */
|
||||
u8 pclrr_uart; /* 0x2A */
|
||||
u8 pclrr_fech; /* 0x2B */
|
||||
u8 pclrr_fecl; /* 0x2C */
|
||||
u8 res04[3]; /* 0x2D - 0x2F */
|
||||
|
||||
/* Pin Assignment */
|
||||
u8 par_busctl; /* 0x30 */
|
||||
u8 par_be; /* 0x31 */
|
||||
u8 par_cs; /* 0x32 */
|
||||
u8 par_feci2c; /* 0x33 */
|
||||
u8 par_qspi; /* 0x34 */
|
||||
u8 par_timer; /* 0x35 */
|
||||
u16 par_uart; /* 0x36 */
|
||||
u8 par_fec; /* 0x38 */
|
||||
u8 par_irq; /* 0x39 */
|
||||
|
||||
/* Mode Select Control */
|
||||
/* Drive Strength Control */
|
||||
u8 mscr_fb; /* 0x3A */
|
||||
u8 mscr_sdram; /* 0x3B */
|
||||
|
||||
u8 dscr_i2c; /* 0x3C */
|
||||
u8 dscr_misc; /* 0x3D */
|
||||
u8 dscr_fec; /* 0x3E */
|
||||
u8 dscr_uart; /* 0x3F */
|
||||
u8 dscr_qspi; /* 0x40 */
|
||||
} gpio_t;
|
||||
|
||||
/* SDRAM controller */
|
||||
typedef struct sdram_ctrl {
|
||||
u32 mode; /* 0x00 Mode/Extended Mode */
|
||||
u32 ctrl; /* 0x04 Ctrl */
|
||||
u32 cfg1; /* 0x08 Cfg 1 */
|
||||
u32 cfg2; /* 0x0C Cfg 2 */
|
||||
u32 res1[64]; /* 0x10 - 0x10F */
|
||||
u32 cs0; /* 0x110 Chip Select 0 Cfg */
|
||||
u32 cs1; /* 0x114 Chip Select 1 Cfg */
|
||||
} sdram_t;
|
||||
|
||||
/* Clock Module */
|
||||
typedef struct pll_ctrl {
|
||||
u8 odr; /* 0x00 Output divider */
|
||||
u8 rsvd1;
|
||||
u8 cr; /* 0x02 Control */
|
||||
u8 rsvd2;
|
||||
u8 mdr; /* 0x04 Modulation Divider */
|
||||
u8 rsvd3;
|
||||
u8 fdr; /* 0x06 Feedback Divider */
|
||||
u8 rsvd4;
|
||||
} pll_t;
|
||||
|
||||
/* Watchdog registers */
|
||||
typedef struct wdog_ctrl {
|
||||
u16 cr; /* 0x00 Control */
|
||||
u16 mr; /* 0x02 Modulus */
|
||||
u16 cntr; /* 0x04 Count */
|
||||
u16 sr; /* 0x06 Service */
|
||||
} wdog_t;
|
||||
|
||||
#endif /* __IMMAP_520X__ */
|
||||
|
|
@ -0,0 +1,358 @@
|
|||
/*
|
||||
* m520x.h -- Definitions for Freescale Coldfire 520x
|
||||
*
|
||||
* Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __M520X__
|
||||
#define __M520X__
|
||||
|
||||
/* *** System Control Module (SCM) *** */
|
||||
#define SCM_MPR_MPROT0(x) (((x) & 0x0F) << 28)
|
||||
#define SCM_MPR_MPROT1(x) (((x) & 0x0F) << 24)
|
||||
#define SCM_MPR_MPROT2(x) (((x) & 0x0F) << 20)
|
||||
#define MPROT_MTR 4
|
||||
#define MPROT_MTW 2
|
||||
#define MPROT_MPL 1
|
||||
|
||||
#define SCM_PACRA_PACR0(x) (((x) & 0x0F) << 28)
|
||||
#define SCM_PACRA_PACR1(x) (((x) & 0x0F) << 24)
|
||||
#define SCM_PACRA_PACR2(x) (((x) & 0x0F) << 20)
|
||||
|
||||
#define SCM_PACRB_PACR12(x) (((x) & 0x0F) << 12)
|
||||
|
||||
#define SCM_PACRC_PACR16(x) (((x) & 0x0F) << 28)
|
||||
#define SCM_PACRC_PACR17(x) (((x) & 0x0F) << 24)
|
||||
#define SCM_PACRC_PACR18(x) (((x) & 0x0F) << 20)
|
||||
#define SCM_PACRC_PACR21(x) (((x) & 0x0F) << 8)
|
||||
#define SCM_PACRC_PACR22(x) (((x) & 0x0F) << 4)
|
||||
#define SCM_PACRC_PACR23(x) ((x) & 0x0F)
|
||||
|
||||
#define SCM_PACRD_PACR24(x) (((x) & 0x0F) << 28)
|
||||
#define SCM_PACRD_PACR25(x) (((x) & 0x0F) << 24)
|
||||
#define SCM_PACRD_PACR26(x) (((x) & 0x0F) << 20)
|
||||
#define SCM_PACRD_PACR28(x) (((x) & 0x0F) << 12)
|
||||
#define SCM_PACRD_PACR29(x) (((x) & 0x0F) << 8)
|
||||
#define SCM_PACRD_PACR30(x) (((x) & 0x0F) << 4)
|
||||
#define SCM_PACRD_PACR31(x) ((x) & 0x0F)
|
||||
|
||||
#define SCM_PACRE_PACR32(x) (((x) & 0x0F) << 28)
|
||||
#define SCM_PACRE_PACR33(x) (((x) & 0x0F) << 24)
|
||||
#define SCM_PACRE_PACR34(x) (((x) & 0x0F) << 20)
|
||||
#define SCM_PACRE_PACR35(x) (((x) & 0x0F) << 16)
|
||||
#define SCM_PACRE_PACR36(x) (((x) & 0x0F) << 12)
|
||||
|
||||
#define SCM_PACRF_PACR40(x) (((x) & 0x0F) << 28)
|
||||
#define SCM_PACRF_PACR41(x) (((x) & 0x0F) << 24)
|
||||
#define SCM_PACRF_PACR42(x) (((x) & 0x0F) << 20)
|
||||
|
||||
#define PACR_SP 4
|
||||
#define PACR_WP 2
|
||||
#define PACR_TP 1
|
||||
|
||||
#define SCM_BMT_BME (0x00000008)
|
||||
#define SCM_BMT_BMT_MASK (0x07)
|
||||
#define SCM_BMT_BMT(x) ((x) & 0x07)
|
||||
#define SCM_BMT_BMT1024 (0x0000)
|
||||
#define SCM_BMT_BMT512 (0x0001)
|
||||
#define SCM_BMT_BMT256 (0x0002)
|
||||
#define SCM_BMT_BMT128 (0x0003)
|
||||
#define SCM_BMT_BMT64 (0x0004)
|
||||
#define SCM_BMT_BMT32 (0x0005)
|
||||
#define SCM_BMT_BMT16 (0x0006)
|
||||
#define SCM_BMT_BMT8 (0x0007)
|
||||
|
||||
#define SCM_CWCR_RO (0x8000)
|
||||
#define SCM_CWCR_CWR_WH (0x0100)
|
||||
#define SCM_CWCR_CWE (0x0080)
|
||||
#define SCM_CWRI_WINDOW (0x0060)
|
||||
#define SCM_CWRI_RESET (0x0040)
|
||||
#define SCM_CWRI_INT_RESET (0x0020)
|
||||
#define SCM_CWRI_INT (0x0000)
|
||||
#define SCM_CWCR_CWT(x) (((x) & 0x001F))
|
||||
|
||||
#define SCM_ISR_CFEI (0x02)
|
||||
#define SCM_ISR_CWIC (0x01)
|
||||
|
||||
#define SCM_CFIER_ECFEI (0x01)
|
||||
|
||||
#define SCM_CFLOC_LOC (0x80)
|
||||
|
||||
#define SCM_CFATR_WRITE (0x80)
|
||||
#define SCM_CFATR_SZ32 (0x20)
|
||||
#define SCM_CFATR_SZ16 (0x10)
|
||||
#define SCM_CFATR_SZ08 (0x00)
|
||||
#define SCM_CFATR_CACHE (0x08)
|
||||
#define SCM_CFATR_MODE (0x02)
|
||||
#define SCM_CFATR_TYPE (0x01)
|
||||
|
||||
/* *** Interrupt Controller (INTC) *** */
|
||||
#define INT0_LO_RSVD0 (0)
|
||||
#define INT0_LO_EPORT_F1 (1)
|
||||
#define INT0_LO_EPORT_F4 (2)
|
||||
#define INT0_LO_EPORT_F7 (3)
|
||||
#define INT1_LO_PIT0 (4)
|
||||
#define INT1_LO_PIT1 (5)
|
||||
/* 6 - 7 rsvd */
|
||||
#define INT0_LO_EDMA_00 (8)
|
||||
#define INT0_LO_EDMA_01 (9)
|
||||
#define INT0_LO_EDMA_02 (10)
|
||||
#define INT0_LO_EDMA_03 (11)
|
||||
#define INT0_LO_EDMA_04 (12)
|
||||
#define INT0_LO_EDMA_05 (13)
|
||||
#define INT0_LO_EDMA_06 (14)
|
||||
#define INT0_LO_EDMA_07 (15)
|
||||
#define INT0_LO_EDMA_08 (16)
|
||||
#define INT0_LO_EDMA_09 (17)
|
||||
#define INT0_LO_EDMA_10 (18)
|
||||
#define INT0_LO_EDMA_11 (19)
|
||||
#define INT0_LO_EDMA_12 (20)
|
||||
#define INT0_LO_EDMA_13 (21)
|
||||
#define INT0_LO_EDMA_14 (22)
|
||||
#define INT0_LO_EDMA_15 (23)
|
||||
#define INT0_LO_EDMA_ERR (24)
|
||||
#define INT0_LO_SCM_CWIC (25)
|
||||
#define INT0_LO_UART0 (26)
|
||||
#define INT0_LO_UART1 (27)
|
||||
#define INT0_LO_UART2 (28)
|
||||
/* 29 rsvd */
|
||||
#define INT0_LO_I2C (30)
|
||||
#define INT0_LO_QSPI (31)
|
||||
|
||||
#define INT0_HI_DTMR0 (32)
|
||||
#define INT0_HI_DTMR1 (33)
|
||||
#define INT0_HI_DTMR2 (34)
|
||||
#define INT0_HI_DTMR3 (35)
|
||||
#define INT0_HI_FEC0_TXF (36)
|
||||
#define INT0_HI_FEC0_TXB (37)
|
||||
#define INT0_HI_FEC0_UN (38)
|
||||
#define INT0_HI_FEC0_RL (39)
|
||||
#define INT0_HI_FEC0_RXF (40)
|
||||
#define INT0_HI_FEC0_RXB (41)
|
||||
#define INT0_HI_FEC0_MII (42)
|
||||
#define INT0_HI_FEC0_LC (43)
|
||||
#define INT0_HI_FEC0_HBERR (44)
|
||||
#define INT0_HI_FEC0_GRA (45)
|
||||
#define INT0_HI_FEC0_EBERR (46)
|
||||
#define INT0_HI_FEC0_BABT (47)
|
||||
#define INT0_HI_FEC0_BABR (48)
|
||||
/* 49 - 61 rsvd */
|
||||
#define INT0_HI_SCMISR_CFEI (62)
|
||||
|
||||
/* *** Reset Controller Module (RCM) *** */
|
||||
#define RCM_RCR_SOFTRST (0x80)
|
||||
#define RCM_RCR_FRCRSTOUT (0x40)
|
||||
|
||||
#define RCM_RSR_SOFT (0x20)
|
||||
#define RCM_RSR_WDOG (0x10)
|
||||
#define RCM_RSR_POR (0x08)
|
||||
#define RCM_RSR_EXT (0x04)
|
||||
#define RCM_RSR_WDR_CORE (0x02)
|
||||
#define RCM_RSR_LOL (0x01)
|
||||
|
||||
/* *** Chip Configuration Module (CCM) *** */
|
||||
#define CCM_CCR_CSC (0x0200)
|
||||
#define CCM_CCR_OSCFREQ (0x0080)
|
||||
#define CCM_CCR_LIMP (0x0040)
|
||||
#define CCM_CCR_LOAD (0x0020)
|
||||
#define CCM_CCR_BOOTPS(x) (((x) & 0x0003) << 3)
|
||||
#define CCM_CCR_OSC_MODE (0x0004)
|
||||
#define CCM_CCR_PLL_MODE (0x0002)
|
||||
#define CCM_CCR_RESERVED (0x0001)
|
||||
|
||||
#define CCM_CIR_PIN(x) (((x) & 0x03FF) << 6)
|
||||
#define CCM_CIR_PRN(x) ((x) & 0x003F)
|
||||
|
||||
/* *** General Purpose I/O (GPIO) *** */
|
||||
#define GPIO_PDR_BUSCTL(x) ((x) & 0x0F)
|
||||
#define GPIO_PDR_BE(x) ((x) & 0x0F)
|
||||
#define GPIO_PDR_CS(x) (((x) & 0x07) << 1)
|
||||
#define GPIO_PDR_FECI2C(x) ((x) & 0x0F)
|
||||
#define GPIO_PDR_QSPI(x) ((x) & 0x0F)
|
||||
#define GPIO_PDR_TIMER(x) ((x) & 0x0F)
|
||||
#define GPIO_PDR_UART(x) ((x) & 0xFF)
|
||||
#define GPIO_PDR_FECH(x) ((x) & 0xFF)
|
||||
#define GPIO_PDR_FECL(x) ((x) & 0xFF)
|
||||
|
||||
#define GPIO_PAR_FBCTL_OE (0x10)
|
||||
#define GPIO_PAR_FBCTL_TA (0x08)
|
||||
#define GPIO_PAR_FBCTL_RWB (0x04)
|
||||
#define GPIO_PAR_FBCTL_TS_MASK (0xFC)
|
||||
#define GPIO_PAR_FBCTL_TS_TS (0x03)
|
||||
#define GPIO_PAR_FBCTL_TS_DMA (0x02)
|
||||
|
||||
#define GPIO_PAR_BE3 (0x08)
|
||||
#define GPIO_PAR_BE2 (0x04)
|
||||
#define GPIO_PAR_BE1 (0x02)
|
||||
#define GPIO_PAR_BE0 (0x01)
|
||||
|
||||
#define GPIO_PAR_CS3 (0x08)
|
||||
#define GPIO_PAR_CS2 (0x04)
|
||||
#define GPIO_PAR_CS1_MASK (0xFC)
|
||||
#define GPIO_PAR_CS1_CS1 (0x03)
|
||||
#define GPIO_PAR_CS1_SDCS1 (0x02)
|
||||
|
||||
#define GPIO_PAR_FECI2C_RMII_MASK (0x0F)
|
||||
#define GPIO_PAR_FECI2C_MDC_MASK (0x3F)
|
||||
#define GPIO_PAR_FECI2C_MDC_MDC (0xC0)
|
||||
#define GPIO_PAR_FECI2C_MDC_SCL (0x80)
|
||||
#define GPIO_PAR_FECI2C_MDC_U2TXD (0x40)
|
||||
#define GPIO_PAR_FECI2C_MDIO_MASK (0xCF)
|
||||
#define GPIO_PAR_FECI2C_MDIO_MDIO (0x30)
|
||||
#define GPIO_PAR_FECI2C_MDIO_SDA (0x20)
|
||||
#define GPIO_PAR_FECI2C_MDIO_U2RXD (0x10)
|
||||
#define GPIO_PAR_FECI2C_I2C_MASK (0xF0)
|
||||
#define GPIO_PAR_FECI2C_SCL_MASK (0xF3)
|
||||
#define GPIO_PAR_FECI2C_SCL_SCL (0x0C)
|
||||
#define GPIO_PAR_FECI2C_SCL_U2RXD (0x04)
|
||||
#define GPIO_PAR_FECI2C_SDA_MASK (0xFC)
|
||||
#define GPIO_PAR_FECI2C_SDA_SDA (0x03)
|
||||
#define GPIO_PAR_FECI2C_SDA_U2TXD (0x01)
|
||||
|
||||
#define GPIO_PAR_QSPI_PCS2_MASK (0x3F)
|
||||
#define GPIO_PAR_QSPI_PCS2_PCS2 (0xC0)
|
||||
#define GPIO_PAR_QSPI_PCS2_DACK0 (0x80)
|
||||
#define GPIO_PAR_QSPI_PCS2_U2RTS (0x40)
|
||||
#define GPIO_PAR_QSPI_DIN_MASK (0xCF)
|
||||
#define GPIO_PAR_QSPI_DIN_DIN (0x30)
|
||||
#define GPIO_PAR_QSPI_DIN_DREQ0 (0x20)
|
||||
#define GPIO_PAR_QSPI_DIN_U2CTS (0x10)
|
||||
#define GPIO_PAR_QSPI_DOUT_MASK (0xF3)
|
||||
#define GPIO_PAR_QSPI_DOUT_DOUT (0x0C)
|
||||
#define GPIO_PAR_QSPI_DOUT_SDA (0x08)
|
||||
#define GPIO_PAR_QSPI_SCK_MASK (0xFC)
|
||||
#define GPIO_PAR_QSPI_SCK_SCK (0x03)
|
||||
#define GPIO_PAR_QSPI_SCK_SCL (0x02)
|
||||
|
||||
#define GPIO_PAR_TMR_TIN3(x) (((x) & 0x03) << 6)
|
||||
#define GPIO_PAR_TMR_TIN2(x) (((x) & 0x03) << 4)
|
||||
#define GPIO_PAR_TMR_TIN1(x) (((x) & 0x03) << 2)
|
||||
#define GPIO_PAR_TMR_TIN0(x) ((x) & 0x03)
|
||||
#define GPIO_PAR_TMR_TIN3_MASK (0x3F)
|
||||
#define GPIO_PAR_TMR_TIN3_TIN3 (0xC0)
|
||||
#define GPIO_PAR_TMR_TIN3_TOUT3 (0x80)
|
||||
#define GPIO_PAR_TMR_TIN3_U2CTS (0x40)
|
||||
#define GPIO_PAR_TMR_TIN2_MASK (0xCF)
|
||||
#define GPIO_PAR_TMR_TIN2_TIN2 (0x30)
|
||||
#define GPIO_PAR_TMR_TIN2_TOUT2 (0x20)
|
||||
#define GPIO_PAR_TMR_TIN2_U2RTS (0x10)
|
||||
#define GPIO_PAR_TMR_TIN1_MASK (0xF3)
|
||||
#define GPIO_PAR_TMR_TIN1_TIN1 (0x0C)
|
||||
#define GPIO_PAR_TMR_TIN1_TOUT1 (0x08)
|
||||
#define GPIO_PAR_TMR_TIN1_U2RXD (0x04)
|
||||
#define GPIO_PAR_TMR_TIN0_MASK (0xFC)
|
||||
#define GPIO_PAR_TMR_TIN0_TIN0 (0x03)
|
||||
#define GPIO_PAR_TMR_TIN0_TOUT0 (0x02)
|
||||
#define GPIO_PAR_TMR_TIN0_U2TXD (0x01)
|
||||
|
||||
#define GPIO_PAR_UART1_MASK (0xF03F)
|
||||
#define GPIO_PAR_UART0_MASK (0xFFC0)
|
||||
#define GPIO_PAR_UART_U1CTS_MASK (0xF3FF)
|
||||
#define GPIO_PAR_UART_U1CTS_U1CTS (0x0C00)
|
||||
#define GPIO_PAR_UART_U1CTS_TIN1 (0x0800)
|
||||
#define GPIO_PAR_UART_U1CTS_PCS1 (0x0400)
|
||||
#define GPIO_PAR_UART_U1RTS_MASK (0xFCFF)
|
||||
#define GPIO_PAR_UART_U1RTS_U1RTS (0x0300)
|
||||
#define GPIO_PAR_UART_U1RTS_TOUT1 (0x0200)
|
||||
#define GPIO_PAR_UART_U1RTS_PCS1 (0x0100)
|
||||
#define GPIO_PAR_UART_U1TXD (0x0080)
|
||||
#define GPIO_PAR_UART_U1RXD (0x0040)
|
||||
#define GPIO_PAR_UART_U0CTS_MASK (0xFFCF)
|
||||
#define GPIO_PAR_UART_U0CTS_U0CTS (0x0030)
|
||||
#define GPIO_PAR_UART_U0CTS_TIN0 (0x0020)
|
||||
#define GPIO_PAR_UART_U0CTS_PCS0 (0x0010)
|
||||
#define GPIO_PAR_UART_U0RTS_MASK (0xFFF3)
|
||||
#define GPIO_PAR_UART_U0RTS_U0RTS (0x000C)
|
||||
#define GPIO_PAR_UART_U0RTS_TOUT0 (0x0008)
|
||||
#define GPIO_PAR_UART_U0RTS_PCS0 (0x0004)
|
||||
#define GPIO_PAR_UART_U0TXD (0x0002)
|
||||
#define GPIO_PAR_UART_U0RXD (0x0001)
|
||||
|
||||
#define GPIO_PAR_FEC_7W_MASK (0xF3)
|
||||
#define GPIO_PAR_FEC_7W_FEC (0x0C)
|
||||
#define GPIO_PAR_FEC_7W_U1RTS (0x04)
|
||||
#define GPIO_PAR_FEC_MII_MASK (0xFC)
|
||||
#define GPIO_PAR_FEC_MII_FEC (0x03)
|
||||
#define GPIO_PAR_FEC_MII_UnCTS (0x01)
|
||||
|
||||
#define GPIO_PAR_IRQ_IRQ4 (0x01)
|
||||
|
||||
#define GPIO_MSCR_FB_FBCLK(x) (((x) & 0x03) << 6)
|
||||
#define GPIO_MSCR_FB_DUP(x) (((x) & 0x03) << 4)
|
||||
#define GPIO_MSCR_FB_DLO(x) (((x) & 0x03) << 2)
|
||||
#define GPIO_MSCR_FB_ADRCTL(x) ((x) & 0x03)
|
||||
#define GPIO_MSCR_FB_FBCLK_MASK (0x3F)
|
||||
#define GPIO_MSCR_FB_DUP_MASK (0xCF)
|
||||
#define GPIO_MSCR_FB_DLO_MASK (0xF3)
|
||||
#define GPIO_MSCR_FB_ADRCTL_MASK (0xFC)
|
||||
|
||||
#define GPIO_MSCR_SDR_SDCLKB(x) (((x) & 0x03) << 4)
|
||||
#define GPIO_MSCR_SDR_SDCLK(x) (((x) & 0x03) << 2)
|
||||
#define GPIO_MSCR_SDR_SDRAM(x) ((x) & 0x03)
|
||||
#define GPIO_MSCR_SDR_SDCLKB_MASK (0xCF)
|
||||
#define GPIO_MSCR_SDR_SDCLK_MASK (0xF3)
|
||||
#define GPIO_MSCR_SDR_SDRAM_MASK (0xFC)
|
||||
|
||||
#define MSCR_25VDDR (0x03)
|
||||
#define MSCR_18VDDR_FULL (0x02)
|
||||
#define MSCR_OPENDRAIN (0x01)
|
||||
#define MSCR_18VDDR_HALF (0x00)
|
||||
|
||||
#define GPIO_DSCR_I2C(x) ((x) & 0x03)
|
||||
#define GPIO_DSCR_I2C_MASK (0xFC)
|
||||
|
||||
#define GPIO_DSCR_MISC_DBG(x) (((x) & 0x03) << 4)
|
||||
#define GPIO_DSCR_MISC_DBG_MASK (0xCF)
|
||||
#define GPIO_DSCR_MISC_RSTOUT(x) (((x) & 0x03) << 2)
|
||||
#define GPIO_DSCR_MISC_RSTOUT_MASK (0xF3)
|
||||
#define GPIO_DSCR_MISC_TIMER(x) ((x) & 0x03)
|
||||
#define GPIO_DSCR_MISC_TIMER_MASK (0xFC)
|
||||
|
||||
#define GPIO_DSCR_FEC(x) ((x) & 0x03)
|
||||
#define GPIO_DSCR_FEC_MASK (0xFC)
|
||||
|
||||
#define GPIO_DSCR_UART_UART1(x) (((x) & 0x03) << 4)
|
||||
#define GPIO_DSCR_UART_UART1_MASK (0xCF)
|
||||
#define GPIO_DSCR_UART_UART0(x) (((x) & 0x03) << 2)
|
||||
#define GPIO_DSCR_UART_UART0_MASK (0xF3)
|
||||
#define GPIO_DSCR_UART_IRQ(x) ((x) & 0x03)
|
||||
#define GPIO_DSCR_UART_IRQ_MASK (0xFC)
|
||||
|
||||
#define GPIO_DSCR_QSPI(x) ((x) & 0x03)
|
||||
#define GPIO_DSCR_QSPI_MASK (0xFC)
|
||||
|
||||
#define DSCR_50PF (0x03)
|
||||
#define DSCR_30PF (0x02)
|
||||
#define DSCR_20PF (0x01)
|
||||
#define DSCR_10PF (0x00)
|
||||
|
||||
/* *** Phase Locked Loop (PLL) *** */
|
||||
#define PLL_PODR_CPUDIV(x) (((x) & 0x0F) << 4)
|
||||
#define PLL_PODR_CPUDIV_MASK (0x0F)
|
||||
#define PLL_PODR_BUSDIV(x) ((x) & 0x0F)
|
||||
#define PLL_PODR_BUSDIV_MASK (0xF0)
|
||||
|
||||
#define PLL_PCR_DITHEN (0x80)
|
||||
#define PLL_PCR_DITHDEV(x) ((x) & 0x07)
|
||||
#define PLL_PCR_DITHDEV_MASK (0xF8)
|
||||
|
||||
#endif /* __M520X__ */
|
||||
|
|
@ -0,0 +1,223 @@
|
|||
/*
|
||||
* Configuation settings for the Freescale MCF5208EVBe.
|
||||
*
|
||||
* Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef _M5208EVBE_H
|
||||
#define _M5208EVBE_H
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
* (easy to change)
|
||||
*/
|
||||
#define CONFIG_MCF520x /* define processor family */
|
||||
#define CONFIG_M5208 /* define processor type */
|
||||
|
||||
#define CONFIG_MCFUART
|
||||
#define CONFIG_SYS_UART_PORT (0)
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
|
||||
|
||||
#undef CONFIG_WATCHDOG
|
||||
#define CONFIG_WATCHDOG_TIMEOUT 5000
|
||||
|
||||
/* Command line configuration */
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#define CONFIG_CMD_CACHE
|
||||
#define CONFIG_CMD_ELF
|
||||
#define CONFIG_CMD_FLASH
|
||||
#undef CONFIG_CMD_I2C
|
||||
#define CONFIG_CMD_MEMORY
|
||||
#define CONFIG_CMD_MISC
|
||||
#define CONFIG_CMD_MII
|
||||
#define CONFIG_CMD_NET
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_REGINFO
|
||||
|
||||
#define CONFIG_MCFFEC
|
||||
#ifdef CONFIG_MCFFEC
|
||||
# define CONFIG_NET_MULTI 1
|
||||
# define CONFIG_MII 1
|
||||
# define CONFIG_MII_INIT 1
|
||||
# define CONFIG_SYS_DISCOVER_PHY
|
||||
# define CONFIG_SYS_RX_ETH_BUFFER 8
|
||||
# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
|
||||
# define CONFIG_HAS_ETH1
|
||||
|
||||
# define CONFIG_SYS_FEC0_PINMUX 0
|
||||
# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
|
||||
# define MCFFEC_TOUT_LOOP 50000
|
||||
/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
|
||||
# ifndef CONFIG_SYS_DISCOVER_PHY
|
||||
# define FECDUPLEX FULL
|
||||
# define FECSPEED _100BASET
|
||||
# else
|
||||
# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
|
||||
# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
|
||||
# endif
|
||||
# endif /* CONFIG_SYS_DISCOVER_PHY */
|
||||
#endif
|
||||
|
||||
/* Timer */
|
||||
#define CONFIG_MCFTMR
|
||||
#undef CONFIG_MCFPIT
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_FSL_I2C
|
||||
#define CONFIG_HARD_I2C /* I2C with hw support */
|
||||
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
|
||||
#define CONFIG_SYS_I2C_SPEED 80000
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x58000
|
||||
#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
|
||||
|
||||
#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
|
||||
#define CONFIG_UDP_CHECKSUM
|
||||
|
||||
#ifdef CONFIG_MCFFEC
|
||||
# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
|
||||
# define CONFIG_IPADDR 192.162.1.2
|
||||
# define CONFIG_NETMASK 255.255.255.0
|
||||
# define CONFIG_SERVERIP 192.162.1.1
|
||||
# define CONFIG_GATEWAYIP 192.162.1.1
|
||||
# define CONFIG_OVERWRITE_ETHADDR_ONCE
|
||||
#endif /* CONFIG_MCFFEC */
|
||||
|
||||
#define CONFIG_HOSTNAME M5208EVBe
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"netdev=eth0\0" \
|
||||
"loadaddr=40010000\0" \
|
||||
"u-boot=u-boot.bin\0" \
|
||||
"load=tftp ${loadaddr) ${u-boot}\0" \
|
||||
"upd=run load; run prog\0" \
|
||||
"prog=prot off 0 3ffff;" \
|
||||
"era 0 3ffff;" \
|
||||
"cp.b ${loadaddr} 0 ${filesize};" \
|
||||
"save\0" \
|
||||
""
|
||||
|
||||
#define CONFIG_PRAM 512 /* 512 KB */
|
||||
#define CONFIG_SYS_PROMPT "-> "
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
|
||||
#ifdef CONFIG_CMD_KGDB
|
||||
# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of cmd args */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buf Sz */
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x40010000
|
||||
|
||||
#define CONFIG_SYS_HZ 1000
|
||||
#define CONFIG_SYS_CLK 166666666 /* CPU Core Clock */
|
||||
#define CONFIG_SYS_PLL_ODR 0x36
|
||||
#define CONFIG_SYS_PLL_FDR 0x7D
|
||||
|
||||
#define CONFIG_SYS_MBAR 0xFC000000
|
||||
|
||||
/*
|
||||
* Low Level Configuration Settings
|
||||
* (address mappings, register initial values, etc.)
|
||||
* You should know what you are doing if you make changes here.
|
||||
*/
|
||||
/* Definitions for initial stack pointer and data area (in DPRAM) */
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
|
||||
#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in internal SRAM */
|
||||
#define CONFIG_SYS_INIT_RAM_CTRL 0x221
|
||||
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) - 0x10)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
||||
|
||||
/*
|
||||
* Start addresses for the final memory configuration
|
||||
* (Set up by the startup code)
|
||||
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
|
||||
*/
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x40000000
|
||||
#define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */
|
||||
#define CONFIG_SYS_SDRAM_CFG1 0x43711630
|
||||
#define CONFIG_SYS_SDRAM_CFG2 0x56670000
|
||||
#define CONFIG_SYS_SDRAM_CTRL 0xE1002000
|
||||
#define CONFIG_SYS_SDRAM_EMOD 0x80010000
|
||||
#define CONFIG_SYS_SDRAM_MODE 0x00CD0000
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
|
||||
#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
|
||||
|
||||
#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
|
||||
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
|
||||
|
||||
#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
|
||||
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization ??
|
||||
*/
|
||||
#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
|
||||
#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
|
||||
|
||||
/* FLASH organization */
|
||||
#define CONFIG_SYS_FLASH_CFI
|
||||
#ifdef CONFIG_SYS_FLASH_CFI
|
||||
# define CONFIG_FLASH_CFI_DRIVER 1
|
||||
# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
|
||||
# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
|
||||
# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
|
||||
# define CONFIG_SYS_MAX_FLASH_SECT 254 /* max number of sectors on one chip */
|
||||
# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
|
||||
|
||||
/*
|
||||
* Configuration for environment
|
||||
* Environment is embedded in u-boot in the second sector of the flash
|
||||
*/
|
||||
#define CONFIG_ENV_OFFSET 0x2000
|
||||
#define CONFIG_ENV_SIZE 0x1000
|
||||
#define CONFIG_ENV_SECT_SIZE 0x2000
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1
|
||||
|
||||
/* Cache Configuration */
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 16
|
||||
|
||||
/* Chipselect bank definitions */
|
||||
/*
|
||||
* CS0 - NOR Flash
|
||||
* CS1 - Available
|
||||
* CS2 - Available
|
||||
* CS3 - Available
|
||||
* CS4 - Available
|
||||
* CS5 - Available
|
||||
*/
|
||||
#define CONFIG_SYS_CS0_BASE 0
|
||||
#define CONFIG_SYS_CS0_MASK 0x007F0001
|
||||
#define CONFIG_SYS_CS0_CTRL 0x00001FA0
|
||||
|
||||
#endif /* _M5208EVBE_H */
|
||||
Loading…
Reference in New Issue