[MIPS] <asm/mipsregs.h>: CodinygStyle cleanups
No functional changes. Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
This commit is contained in:
Shinya Kuribayashi
parent
89a1550ec6
commit
bf462ae450
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@ -85,8 +85,8 @@
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/*
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* Coprocessor 1 (FPU) register names
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*/
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#define CP1_REVISION $0
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#define CP1_STATUS $31
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#define CP1_REVISION $0
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#define CP1_STATUS $31
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/*
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* FPU Status Register Values
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@ -95,223 +95,226 @@
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* Status Register Values
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*/
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#define FPU_CSR_FLUSH 0x01000000 /* flush denormalised results to 0 */
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#define FPU_CSR_COND 0x00800000 /* $fcc0 */
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#define FPU_CSR_COND0 0x00800000 /* $fcc0 */
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#define FPU_CSR_COND1 0x02000000 /* $fcc1 */
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#define FPU_CSR_COND2 0x04000000 /* $fcc2 */
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#define FPU_CSR_COND3 0x08000000 /* $fcc3 */
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#define FPU_CSR_COND4 0x10000000 /* $fcc4 */
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#define FPU_CSR_COND5 0x20000000 /* $fcc5 */
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#define FPU_CSR_COND6 0x40000000 /* $fcc6 */
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#define FPU_CSR_COND7 0x80000000 /* $fcc7 */
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#define FPU_CSR_FLUSH 0x01000000 /* flush denormalised results to 0 */
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#define FPU_CSR_COND 0x00800000 /* $fcc0 */
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#define FPU_CSR_COND0 0x00800000 /* $fcc0 */
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#define FPU_CSR_COND1 0x02000000 /* $fcc1 */
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#define FPU_CSR_COND2 0x04000000 /* $fcc2 */
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#define FPU_CSR_COND3 0x08000000 /* $fcc3 */
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#define FPU_CSR_COND4 0x10000000 /* $fcc4 */
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#define FPU_CSR_COND5 0x20000000 /* $fcc5 */
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#define FPU_CSR_COND6 0x40000000 /* $fcc6 */
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#define FPU_CSR_COND7 0x80000000 /* $fcc7 */
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/*
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* X the exception cause indicator
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* E the exception enable
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* S the sticky/flag bit
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*/
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#define FPU_CSR_ALL_X 0x0003f000
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#define FPU_CSR_UNI_X 0x00020000
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#define FPU_CSR_INV_X 0x00010000
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#define FPU_CSR_DIV_X 0x00008000
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#define FPU_CSR_OVF_X 0x00004000
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#define FPU_CSR_UDF_X 0x00002000
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#define FPU_CSR_INE_X 0x00001000
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*/
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#define FPU_CSR_ALL_X 0x0003f000
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#define FPU_CSR_UNI_X 0x00020000
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#define FPU_CSR_INV_X 0x00010000
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#define FPU_CSR_DIV_X 0x00008000
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#define FPU_CSR_OVF_X 0x00004000
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#define FPU_CSR_UDF_X 0x00002000
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#define FPU_CSR_INE_X 0x00001000
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#define FPU_CSR_ALL_E 0x00000f80
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#define FPU_CSR_INV_E 0x00000800
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#define FPU_CSR_DIV_E 0x00000400
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#define FPU_CSR_OVF_E 0x00000200
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#define FPU_CSR_UDF_E 0x00000100
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#define FPU_CSR_INE_E 0x00000080
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#define FPU_CSR_ALL_E 0x00000f80
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#define FPU_CSR_INV_E 0x00000800
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#define FPU_CSR_DIV_E 0x00000400
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#define FPU_CSR_OVF_E 0x00000200
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#define FPU_CSR_UDF_E 0x00000100
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#define FPU_CSR_INE_E 0x00000080
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#define FPU_CSR_ALL_S 0x0000007c
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#define FPU_CSR_INV_S 0x00000040
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#define FPU_CSR_DIV_S 0x00000020
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#define FPU_CSR_OVF_S 0x00000010
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#define FPU_CSR_UDF_S 0x00000008
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#define FPU_CSR_INE_S 0x00000004
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#define FPU_CSR_ALL_S 0x0000007c
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#define FPU_CSR_INV_S 0x00000040
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#define FPU_CSR_DIV_S 0x00000020
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#define FPU_CSR_OVF_S 0x00000010
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#define FPU_CSR_UDF_S 0x00000008
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#define FPU_CSR_INE_S 0x00000004
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/* rounding mode */
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#define FPU_CSR_RN 0x0 /* nearest */
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#define FPU_CSR_RZ 0x1 /* towards zero */
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#define FPU_CSR_RU 0x2 /* towards +Infinity */
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#define FPU_CSR_RD 0x3 /* towards -Infinity */
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#define FPU_CSR_RN 0x0 /* nearest */
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#define FPU_CSR_RZ 0x1 /* towards zero */
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#define FPU_CSR_RU 0x2 /* towards +Infinity */
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#define FPU_CSR_RD 0x3 /* towards -Infinity */
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/*
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* Values for PageMask register
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*/
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#include <linux/config.h>
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#ifdef CONFIG_CPU_VR41XX
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#define PM_1K 0x00000000
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#define PM_4K 0x00001800
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#define PM_16K 0x00007800
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#define PM_64K 0x0001f800
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#define PM_256K 0x0007f800
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#define PM_1K 0x00000000
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#define PM_4K 0x00001800
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#define PM_16K 0x00007800
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#define PM_64K 0x0001f800
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#define PM_256K 0x0007f800
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#else
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#define PM_4K 0x00000000
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#define PM_16K 0x00006000
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#define PM_64K 0x0001e000
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#define PM_256K 0x0007e000
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#define PM_1M 0x001fe000
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#define PM_4M 0x007fe000
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#define PM_16M 0x01ffe000
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#define PM_4K 0x00000000
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#define PM_16K 0x00006000
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#define PM_64K 0x0001e000
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#define PM_256K 0x0007e000
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#define PM_1M 0x001fe000
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#define PM_4M 0x007fe000
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#define PM_16M 0x01ffe000
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#endif
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/*
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* Values used for computation of new tlb entries
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*/
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#define PL_4K 12
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#define PL_16K 14
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#define PL_64K 16
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#define PL_256K 18
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#define PL_1M 20
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#define PL_4M 22
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#define PL_16M 24
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#define PL_4K 12
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#define PL_16K 14
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#define PL_64K 16
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#define PL_256K 18
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#define PL_1M 20
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#define PL_4M 22
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#define PL_16M 24
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/*
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* Macros to access the system control coprocessor
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*/
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#define read_32bit_cp0_register(source) \
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({ int __res; \
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__asm__ __volatile__( \
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#define read_32bit_cp0_register(source) \
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({ int __res; \
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__asm__ __volatile__( \
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".set\tpush\n\t" \
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".set\treorder\n\t" \
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"mfc0\t%0,"STR(source)"\n\t" \
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"mfc0\t%0,"STR(source)"\n\t" \
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".set\tpop" \
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: "=r" (__res)); \
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: "=r" (__res)); \
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__res;})
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#define read_32bit_cp0_set1_register(source) \
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({ int __res; \
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__asm__ __volatile__( \
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#define read_32bit_cp0_set1_register(source) \
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({ int __res; \
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__asm__ __volatile__( \
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".set\tpush\n\t" \
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".set\treorder\n\t" \
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"cfc0\t%0,"STR(source)"\n\t" \
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"cfc0\t%0,"STR(source)"\n\t" \
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".set\tpop" \
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: "=r" (__res)); \
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: "=r" (__res)); \
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__res;})
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/*
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* For now use this only with interrupts disabled!
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*/
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#define read_64bit_cp0_register(source) \
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({ int __res; \
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__asm__ __volatile__( \
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".set\tmips3\n\t" \
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"dmfc0\t%0,"STR(source)"\n\t" \
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".set\tmips0" \
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: "=r" (__res)); \
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#define read_64bit_cp0_register(source) \
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({ int __res; \
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__asm__ __volatile__( \
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".set\tmips3\n\t" \
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"dmfc0\t%0,"STR(source)"\n\t" \
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".set\tmips0" \
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: "=r" (__res)); \
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__res;})
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#define write_32bit_cp0_register(register,value) \
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__asm__ __volatile__( \
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#define write_32bit_cp0_register(register,value) \
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__asm__ __volatile__( \
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"mtc0\t%0,"STR(register)"\n\t" \
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"nop" \
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: : "r" (value));
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#define write_32bit_cp0_set1_register(register,value) \
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__asm__ __volatile__( \
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#define write_32bit_cp0_set1_register(register,value) \
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__asm__ __volatile__( \
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"ctc0\t%0,"STR(register)"\n\t" \
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"nop" \
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: : "r" (value));
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#define write_64bit_cp0_register(register,value) \
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__asm__ __volatile__( \
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".set\tmips3\n\t" \
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"dmtc0\t%0,"STR(register)"\n\t" \
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".set\tmips0" \
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#define write_64bit_cp0_register(register,value) \
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__asm__ __volatile__( \
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".set\tmips3\n\t" \
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"dmtc0\t%0,"STR(register)"\n\t" \
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".set\tmips0" \
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: : "r" (value))
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/*
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* This should be changed when we get a compiler that support the MIPS32 ISA.
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*/
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#define read_mips32_cp0_config1() \
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({ int __res; \
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__asm__ __volatile__( \
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".set\tnoreorder\n\t" \
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".set\tnoat\n\t" \
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".word\t0x40018001\n\t" \
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"move\t%0,$1\n\t" \
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".set\tat\n\t" \
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".set\treorder" \
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:"=r" (__res)); \
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#define read_mips32_cp0_config1() \
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({ int __res; \
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__asm__ __volatile__( \
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".set\tnoreorder\n\t" \
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".set\tnoat\n\t" \
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".word\t0x40018001\n\t" \
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"move\t%0,$1\n\t" \
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".set\tat\n\t" \
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".set\treorder" \
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:"=r" (__res)); \
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__res;})
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#define tlb_write_indexed() \
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__asm__ __volatile__( \
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".set noreorder\n\t" \
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"tlbwi\n\t" \
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#define tlb_write_indexed() \
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__asm__ __volatile__( \
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".set noreorder\n\t" \
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"tlbwi\n\t" \
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".set reorder")
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/*
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* R4x00 interrupt enable / cause bits
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*/
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#define IE_SW0 (1<< 8)
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#define IE_SW1 (1<< 9)
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#define IE_IRQ0 (1<<10)
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#define IE_IRQ1 (1<<11)
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#define IE_IRQ2 (1<<12)
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#define IE_IRQ3 (1<<13)
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#define IE_IRQ4 (1<<14)
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#define IE_IRQ5 (1<<15)
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#define IE_SW0 (1<< 8)
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#define IE_SW1 (1<< 9)
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#define IE_IRQ0 (1<<10)
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#define IE_IRQ1 (1<<11)
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#define IE_IRQ2 (1<<12)
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#define IE_IRQ3 (1<<13)
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#define IE_IRQ4 (1<<14)
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#define IE_IRQ5 (1<<15)
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/*
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* R4x00 interrupt cause bits
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*/
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#define C_SW0 (1<< 8)
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#define C_SW1 (1<< 9)
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#define C_IRQ0 (1<<10)
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#define C_IRQ1 (1<<11)
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#define C_IRQ2 (1<<12)
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#define C_IRQ3 (1<<13)
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#define C_IRQ4 (1<<14)
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#define C_IRQ5 (1<<15)
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#define C_SW0 (1<< 8)
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#define C_SW1 (1<< 9)
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#define C_IRQ0 (1<<10)
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#define C_IRQ1 (1<<11)
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#define C_IRQ2 (1<<12)
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#define C_IRQ3 (1<<13)
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#define C_IRQ4 (1<<14)
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#define C_IRQ5 (1<<15)
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#ifndef _LANGUAGE_ASSEMBLY
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/*
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* Manipulate the status register.
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* Mostly used to access the interrupt bits.
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*/
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#define __BUILD_SET_CP0(name,register) \
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extern __inline__ unsigned int \
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#define __BUILD_SET_CP0(name,register) \
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extern __inline__ unsigned int \
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set_cp0_##name(unsigned int set) \
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{ \
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unsigned int res; \
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{ \
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unsigned int res; \
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\
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res = read_32bit_cp0_register(register); \
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res = read_32bit_cp0_register(register); \
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res |= set; \
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write_32bit_cp0_register(register, res); \
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\
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return res; \
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return res; \
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} \
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\
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extern __inline__ unsigned int \
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extern __inline__ unsigned int \
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clear_cp0_##name(unsigned int clear) \
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{ \
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unsigned int res; \
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{ \
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unsigned int res; \
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\
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res = read_32bit_cp0_register(register); \
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res = read_32bit_cp0_register(register); \
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res &= ~clear; \
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write_32bit_cp0_register(register, res); \
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\
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return res; \
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return res; \
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} \
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\
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extern __inline__ unsigned int \
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extern __inline__ unsigned int \
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change_cp0_##name(unsigned int change, unsigned int new) \
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{ \
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unsigned int res; \
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{ \
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unsigned int res; \
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\
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res = read_32bit_cp0_register(register); \
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res &= ~change; \
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res |= (new & change); \
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if(change) \
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write_32bit_cp0_register(register, res); \
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res = read_32bit_cp0_register(register); \
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res &= ~change; \
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res |= (new & change); \
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if(change) \
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write_32bit_cp0_register(register, res); \
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\
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return res; \
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return res; \
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}
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__BUILD_SET_CP0(status,CP0_STATUS)
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@ -339,7 +342,7 @@ __BUILD_SET_CP0(config,CP0_CONFIG)
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/*
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* Bitfields in the R[23]000 cp0 status register.
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*/
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#define ST0_IEC 0x00000001
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#define ST0_IEC 0x00000001
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#define ST0_KUC 0x00000002
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#define ST0_IEP 0x00000004
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#define ST0_KUP 0x00000008
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@ -353,9 +356,9 @@ __BUILD_SET_CP0(config,CP0_CONFIG)
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/*
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* Bits specific to the R4640/R4650
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*/
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#define ST0_UM (1 << 4)
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#define ST0_IL (1 << 23)
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#define ST0_DL (1 << 24)
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#define ST0_UM (1 << 4)
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#define ST0_IL (1 << 23)
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#define ST0_DL (1 << 24)
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/*
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* Bitfields in the TX39 family CP0 Configuration Register 3
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@ -485,8 +488,8 @@ __BUILD_SET_CP0(config,CP0_CONFIG)
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#define CONF_DB (1 << 4)
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#define CONF_IB (1 << 5)
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#define CONF_SC (1 << 17)
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#define CONF_AC (1 << 23)
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#define CONF_HALT (1 << 25)
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#define CONF_AC (1 << 23)
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#define CONF_HALT (1 << 25)
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/*
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* R10000 performance counter definitions.
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