phone-side
/
uboot-mt623x
9
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

Merge branch 'master' of /home/stefan/git/u-boot/u-boot into next

This commit is contained in:
Stefan Roese 2008-08-14 08:25:13 +02:00
parent bc9019e197 2fd0aad443
commit becbbc7b2a
520 changed files with 28183 additions and 8538 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

588
CHANGELOG
View File

@ -1,3 +1,579 @@
commit 17e900b8c0f38d922da47073246219dce2a847f2
Author: Wolfgang Denk <wd@denx.de>
Date: Tue Aug 12 14:54:04 2008 +0200
MVBC_P: fix compile problem
Signed-off-by: Wolfgang Denk <wd@denx.de>
commit 52b047ae48219b59bebe37ba743ab103fd4f8316
Author: Wolfgang Denk <wd@denx.de>
Date: Tue Aug 12 12:10:11 2008 +0200
MPC8272ADS: fix build error: 'bd_t' has no member named 'pci_clk'
Signed-off-by: Wolfgang Denk <wd@denx.de>
commit c9c101c660b3d1995045c61c7c6041f52b6cf335
Author: Wolfgang Denk <wd@denx.de>
Date: Tue Aug 12 00:36:53 2008 +0200
ads5121: fix compiler warnings (unused variables)
Signed-off-by: Wolfgang Denk <wd@denx.de>
commit 902ca09246039964d59bbcb519b1e1b5aed01308
Author: Kumar Gala <galak@kernel.crashing.org>
Date: Mon Aug 11 11:29:28 2008 -0500
85xx: Rename CONFIG_NR_CPUS to CONFIG_NUM_CPUS
Use CONFIG_NUM_CPUS to match existing define used by 86xx.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Jon Loeliger <jdl@freescale.com>
commit 3216ca9692ff80d7c638723ef448f3d36301d9e7
Author: Kumar Gala <galak@kernel.crashing.org>
Date: Mon Aug 11 09:20:53 2008 -0500
Fix fallout from autostart revert
The autostart revert caused a bit of duplicated code as well as
code that was using images->autostart that needs to get removed so
we can build again.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
commit 3cf8a234b8e8c02e4da1f23566043bc288b05220
Author: Kumar Gala <galak@kernel.crashing.org>
Date: Mon Aug 11 09:16:25 2008 -0500
Fix compile error related to r8a66597-hcd & usb
When building the 8544DS board we get this error:
In file included from r8a66597-hcd.c:22:
u-boot/include/usb.h:190:2: error: #error USB Lowlevel not defined
make[1]: *** [r8a66597-hcd.o] Error 1
The cleanest fix is to only build r8a66597-hcd.c if CONFIG_USB_R8A66597_HCD
is set.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
commit 2d0daa03612338a813e3c9d22680e54eabfea378
Author: Becky Bruce <becky.bruce@freescale.com>
Date: Mon Aug 4 14:02:26 2008 -0500
POWERPC 86xx: Move BAT setup code to C
This is needed because we will be possibly be locating
devices at physical addresses above 32bits, and the asm
preprocessing does not appear to deal with ULL constants
properly. We now call write_bat in lib_ppc/bat_rw.c.
Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
Acked-by: Jon Loeliger <jdl@freescale.com>
commit 9de67149db576c91b9c2a0a182652331e7e44211
Author: Becky Bruce <becky.bruce@freescale.com>
Date: Mon Aug 4 14:01:53 2008 -0500
POWERPC: Add synchronization to write_bat in lib_ppc/bat_rw.c
Perform sync/isync as required by the architecture.
Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
Acked-by: Jon Loeliger <jdl@freescale.com>
commit 23f935c073e7578c6066804fd2f9ee116cae6ffe
Author: Becky Bruce <becky.bruce@freescale.com>
Date: Mon Aug 4 14:01:16 2008 -0500
POWERPC: 86xx - add missing CONFIG_HIGH_BATS to sbc8641d config
Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
Acked-by: Jon Loeliger <jdl@freescale.com>
commit 5276a3584d26a9533404f0ec00c3b61cf9a97939
Author: Magnus Lilja <lilja.magnus@gmail.com>
Date: Sun Aug 3 21:44:10 2008 +0200
i.MX31: Fix mx31_gpio_mux() function and MUX_-macros.
Correct the mx31_gpio_mux() function to allow changing all i.MX31 IOMUX
contacts instead of only the first 256 ones as is the case prior to
this patch.
Add missing MUX_* macros and update board files to use the new macros.
Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
commit b6b183c5b2fffd4c456b7e3fcb064cceb47fe7ac
Author: Magnus Lilja <lilja.magnus@gmail.com>
Date: Sun Aug 3 21:43:37 2008 +0200
i.MX31: Fix IOMUX related typos
Correct the names of some IOMUX macros.
Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
commit 4d57b0fb2927d4f50d834884b4ec4a7ca01708b0
Author: Steve Sakoman <steve@sakoman.com>
Date: Mon Aug 11 20:26:16 2008 +0200
OneNAND: Remove unused parameters to onenand_verify_page
The block and page parameters of onenand_verify_page() are not used. This causes a compiler error when CONFIG_MTD_ONENAND_VERIFY_WRITE is enabled.
Signed-off-by: Steve Sakoman <steve@sakoman.com>
Signed-off-by: Dirk Behme <dirk.behme@gmail.com>
commit e84d568fa2a9f4ce7888141e71676368ef6b3f25
Author: Anatolij Gustschin <agust@denx.de>
Date: Fri Aug 8 18:00:40 2008 +0200
video: fix bug in cfb_console code
FILL_15BIT_555RGB macro extension for pixel swapping
by commit bed53753dd1d7e6bcbea4339be0fb7760214cc35
introduced a bug in cfb_console:
Bitmaps with odd-numbered width won't be rendered
correctly and even U-Boot crashes are observed on
some platforms while repeated rendering of such
bitmaps with "bmp display". Also if a bitmap is
rendered to an odd-numbered x starting position,
the same problem occurs. This patch is an attempt
to fix it.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
commit d9015f6a50d7258125349ef5c2af836458a0029a
Author: Anatolij Gustschin <agust@denx.de>
Date: Fri Aug 8 18:00:39 2008 +0200
video: fix bug in logo_plot
If logo_plot() should ever be called with x starting
position other than zero and for pixel depths greater
than 8bpp, logo colors distortion will be observed.
This patch fixes the issue.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
commit 406819ae94f79f5b59e01d163380ca7d83709251
Author: Wolfgang Denk <wd@denx.de>
Date: Mon Aug 11 00:17:52 2008 +0200
MAINTAINERS: sort entries
Signed-off-by: Wolfgang Denk <wd@denx.de>
commit cfc442d7913d4d1c3a9bf494f90c012c2f8c3bdc
Author: Roy Zang <tie-fei.zang@freescale.com>
Date: Thu Aug 7 18:19:28 2008 +0800
Add mpc7448hpc2 maintainer information
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
commit a9fe0c3e7ca48afa50d6a0db99fa91e7282d73d8
Author: Gururaja Hebbar K R <gururajakr@sanyo.co.in>
Date: Thu Aug 7 13:13:27 2008 +0530
common/cmd_load.c - Minor code & Coding Style cleanup
- os_data_header Variable is a carry over feature
& unused. So removed all instance of this variable
- Minor Code Style Update
Signed-off-by: Gururaja Hebbar <gururajakr@sanyo.co.in>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
commit 0d28f34bbe56d0971bd603789dcc6fe7adf11f14
Author: Magnus Lilja <lilja.magnus@gmail.com>
Date: Wed Aug 6 19:32:33 2008 +0200
Update the U-Boot wiki URL.
Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
commit aa5ffa16d7e4c461b7b77bf8e79d2ef5638cf754
Author: dirk.behme@googlemail.com <dirk.behme@googlemail.com>
Date: Sun Aug 10 17:56:36 2008 +0200
OneNAND: Remove base address offset usage
While locally preparing some U-Boot patches for ARM based OMAP3 boards, some
using OneNAND and some using NAND, we found some differences in OneNAND and
NAND command address handling.
As this might confuse users (it already confused us), we like to align OneNAND
and NAND address handling.
The issue is that cmd_onenand.c subtracts the onenand base address from the
addresses you type into the u-boot command line so, unlike nand, you can't
use addresses relative to the start of the onenand part e.g. this won't work:
onenand read 82000000 280000 400000
you have to use:
onenand read 82000000 20280000 400000
Looking at recent git, the only board currently using OneNAND is Apollon, and
for this the OneNAND base address is 0 (apollon.h)
#define CFG_ONENAND_BASE 0x00000000
so patch below won't break any existing boards and will align OneNAND and NAND
handling on boards where OneNAND base address is != 0.
Signed-off-by: Steve Sakoman <sakoman@gmail.com>
Signed-off-by: Manikandan Pillai <mani.pillai@ti.com>
Signed-off-by: Dirk Behme <dirk.behme@gmail.com>
commit c11528083ef6e55e76df742228c26e39d151813d
Author: Kumar Gala <galak@kernel.crashing.org>
Date: Thu Aug 7 09:28:20 2008 -0500
mpc85xx: workaround old binutils bug
The recent change to move the .bss outside of the image gives older
binutils (ld from eldk4.1/binutils-2.16) some headache:
ppc_85xx-ld: u-boot: Not enough room for program headers (allocated 3, need 4)
ppc_85xx-ld: final link failed: Bad value
We workaround it by being explicit about the program headers and not
assigning the .bss to a program header.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
commit 0bf202ec586d4466c900e987720fa635c594d689
Author: Wolfgang Denk <wd@denx.de>
Date: Sun Aug 10 01:26:26 2008 +0200
Revert "[new uImage] Add autostart flag to bootm_headers structure"
This reverts commit f5614e7926863bf0225ec860d9b319741a9c4004.
The commit was based on a misunderstanding of the (documented)
meaning of the 'autostart' environment variable. It might cause
boards to hang if 'autostart' was used, with the potential to brick
them. Go back to the documented behaviour.
Conflicts:
common/cmd_bootm.c
common/image.c
include/image.h
Signed-off-by: Wolfgang Denk <wd@denx.de>
commit 29f8f58ff40c67f7f2e11afd1715173094e52ac2
Author: Wolfgang Denk <wd@denx.de>
Date: Sat Aug 9 23:17:32 2008 +0200
TQM8xx{L,M}: try to normalize config files for TQM8xx? based board
- enable CFI driver where this was forgotten
- enable mtdparts support
- adjust default environment
etc.
Signed-off-by: Wolfgang Denk <wd@denx.de>
commit 41266c9b5a5f873df3ec891bb0907616958b5602
Author: Peter Tyser <ptyser@xes-inc.com>
Date: Tue Aug 5 10:51:57 2008 -0500
FIT: Fix handling of images without ramdisks
boot_get_ramdisk() should not treat the case when a FIT image does
not contain a ramdisk as an error.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Acked-by: Michal Simek <monstr@monstr.eu>
commit f77d92a3f56d88e63cc02226a1204b3bdbac6961
Author: Sergey Lapin <slapin@ossfans.org>
Date: Sat Aug 9 01:39:09 2008 +0400
DataFlash: AT45DB021 fix and AT45DB081 support
Fix for page size of AT45DB021. Also adding bigger AT45DB081
which comes with some newer boards.
Signed-off-by: Sergey Lapin <slapin@ossfans.org>
commit ba9324451b662dd393afa53e5cc36fc5d3d10966
Author: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
Date: Fri Aug 8 16:30:23 2008 +0900
sh: Update sh7763rdp config
Add sh_eth support to sh7763rdp.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
commit 21f971ec265f6042ec21636d55d06a6bc0751077
Author: Wolfgang Denk <wd@denx.de>
Date: Mon Jul 7 01:22:29 2008 +0200
TQM823L: re-enable logo support; update LCD_INFO text
Signed-off-by: Wolfgang Denk <wd@denx.de>
commit 3b8d17f0f082073346c0df017c9dfd6acdb40d6d
Author: Wolfgang Denk <wd@denx.de>
Date: Fri Aug 8 16:41:56 2008 +0200
TQM8xxL: fix support for second flash bank
When switching the TQM8xxL modules to use the CFI flash driver,
support for the second flash bank was broken because the CFI driver
did not support dynamically sized banks. This gets fixed now.
Signed-off-by: Wolfgang Denk <wd@denx.de>
commit 2a112b234d879f6390503a5f4e38246acce9d0b0
Author: Wolfgang Denk <wd@denx.de>
Date: Fri Aug 8 16:39:54 2008 +0200
CFI: allow for dynamically determined flash sizes and addresses
The CFI driver allowed only for static initializers in the
CFG_FLASH_BANKS_LIST definition, i. e. it did not allow to map
several flash banks contiguously if the bank sizes were not known in
advance, which kind of violates U-Boot's design philosophy.
(will be used for example by the TQM8xxL boards)
Signed-off-by: Wolfgang Denk <wd@denx.de>
commit d9d78ee46d9a396d0a81d00c2b003a9bd32c2e61
Author: Ben Warren <biggerbadderben@gmail.com>
Date: Thu Aug 7 23:26:35 2008 -0700
QE UEC: Fix compiler warnings
Moved static functions earlier in file so forward declarations are not needed.
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
commit d5d28fe4aad5f4535400647a5617c11039506467
Author: David Saada <David.Saada@ecitele.com>
Date: Mon Mar 31 02:37:38 2008 -0700
QE UEC: Add MII Commands
Add MII commands to the UEC driver. Note that once a UEC device is selected,
any device on its MDIO bus can be addressed.
Signed-off-by: David Saada <david.saada@ecitele.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
commit fd0f2f3796ff2a7a32d35deb1b7996e485849df7
Author: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
Date: Wed Jul 9 21:07:38 2008 +0900
usb: add support for R8A66597 usb controller
add support for Renesas R8A66597 usb controller.
This patch supports USB Host mode.
Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
Signed-off-by: Markus Klotzbuecher <mk@denx.de>
commit 1d10dcd041aaeae9fd7c821005692898a0303382
Author: Hunter, Jon <jon-hunter@ti.com>
Date: Sat Jul 26 18:59:16 2008 -0500
Add support for OMAP5912 and OMAP16xx to usbdcore_omap1510.c
Add support to drivers/usb/usbdcore_omap1510.c for OMAP5912 and OMAP16xx devices.
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Signed-off-by: Markus Klotzbuecher <mk@denx.de>
commit eab1007334b93a6209f1ec33615e26ef5311ede7
Author: Steven A. Falco <sfalco@harris.com>
Date: Wed Aug 6 15:42:52 2008 -0400
ppc4xx: Sequoia has two UARTs in "4-pin" mode. Configure the GPIOs as per schematic.
The Sequoia board has two UARTs in "4-pin" mode. This patch modifies the GPIO
configuration to match the schematic, and also sets the SDR0_PFC1 register to
select the corresponding mode for the UARTs.
Signed-off-by: Steven A. Falco <sfalco@harris.com>
Signed-off-by: Stefan Roese <sr@denx.de>
commit 6689484ccd43189322aaa5a1c6cd02cdd511ad7d
Author: Kenneth Johansson <kenneth@southpole.se>
Date: Tue Jul 15 12:13:38 2008 +0200
mpc5121: Move iopin features from board specific to common files.
And in the process eliminate some duplicate register defines.
Signed-off-by: Kenneth Johansson <kenneth@southpole.se>
commit ef11df6b66ecf5797e94ba322254b8fb7a4e2e12
Author: John Rigby <jrigby@freescale.com>
Date: Tue Aug 5 17:38:57 2008 -0600
mpc5121: squash some fdt fixup errors
On ADS5121 when booting linux the following errors are seen:
Unable to update property /soc5121@80000000:bus-frequency, err=FDT_ERR_NOTFOUND
Unable to update property /soc5121@80000000/ethernet@2800:local-mac-address, err=FDT_ERR_NOTFOUND
Unable to update property /soc5121@80000000/ethernet@2800:address, err=FDT_ERR_NOTFOUND
This is caused by ft_cpu_setup trying to deal with
both old and new soc node naming. This patch
fixes this by being smarter about what to
fixup.
Also do soc node fixups by compatible instead of by path.
A new board config called OF_SOC_COMPAT defined
to be "fsl,mpc5121-immr" replaces the old
OF_SOC node path that was defined to be "soc@80000000".
Old device trees still work, but the compatiblity
is conditional on CONFIG_OF_SUPPORT_OLD_DEVICE_TREES
which is on by default in include/configs/ads5121.h.
Signed-off-by: John Rigby <jrigby@freescale.com>
commit 81091f58f0c58ecd26c5b05de2ae20ca6cdb521c
Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Date: Sat Aug 2 23:48:30 2008 +0200
drivers/serial: Move conditional compilation to Makefile for CONFIG_* macros
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
commit 4cd7e6528f61ec669755c3754bb4f9779874fab3
Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Date: Sat Aug 2 23:48:32 2008 +0200
nios2/sysid: fix printf warning
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
commit 66da6fa0e35e7ee56628c85981709afe7180fc8e
Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Date: Sat Aug 2 23:48:33 2008 +0200
Fix remaining build issues with MPC8xx FADS boards.
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
commit 81d3f1fdddafd1eb53bbca8739f488d417eb3dd2
Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Date: Sat Aug 2 23:48:31 2008 +0200
nios2: fix phys_addr_t and phys_size_t support
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
commit 5fa62000db6d0b46ecdeadbeb50faf5197db49ef
Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Date: Sat Aug 2 23:48:34 2008 +0200
mvbc_p: Fix problem with '#if (CONFIG_CMD_KGDB)'
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
commit 1464eff77e7fdaed609ecf263a2423c9dcf96b1f
Author: Mark Jackson <mpfj@mimc.co.uk>
Date: Fri Aug 1 09:48:29 2008 +0100
Fix bitmap display for atmel lcd controller
The current lcd_display_bitmap() function does not work properly
for the Atmel LCD controller.
2 fixes need to be done:-
(a) when setting the colour map, use the lcd_setcolreg() function
as provided by the Atmel driver
(b) the data is never actually written to the lcd framebuffer !!
Signed-off-by: Mark Jackson <mpfj@mimc.co.uk>
commit 2a433c66b1e2770349fe4911be23c375f053ebd8
Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Date: Fri Aug 1 08:40:34 2008 +0200
qemu_mips: update README to follow qemu update about default machine
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
commit ac169d645f5f0e0b9a232563099209e92a355d8e
Author: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
Date: Thu Jul 31 19:53:21 2008 -0500
ColdFire: Fix compilation issue caused by a missing function
Implement usec2ticks() which is used by fsl_i2c.c in
lib_m68k/time.c
Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
commit 01ae85b58b51d2fb1fac5b93095f6042cf48ae7b
Author: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
Date: Thu Jul 31 19:53:06 2008 -0500
Fix compilation error for TASREG
TASREG is ColdFire platform, the include ppc4xx.h in
board/esd/common/flash.c causes conflict.
Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
commit 35d3bd3cc35c508a6823dac77e0fd126808e4fc7
Author: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
Date: Thu Jul 31 19:52:36 2008 -0500
Fix compilation error for MCF5275
Rename OBJ to COBJ in board/platform/Makefile
Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
commit 5c40548f01218360a1f1395198c50ff45f3035b5
Author: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
Date: Thu Jul 31 19:52:28 2008 -0500
Fix compile error caused by incorrect function return type
Rename int mii_init(void) to void mii_init(void) for idmr
ColdFire platform
Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
commit a58c78067c928976c082c758d3987e89ead5b191
Author: Wolfgang Denk <wd@denx.de>
Date: Fri Aug 1 12:06:22 2008 +0200
Fix build issues with MPC8xx FADS boards.
Signed-off-by: Wolfgang Denk <wd@denx.de>
commit 4b50cd12a3b3c644153c4cf393f4a4c12289e5aa
Author: Wolfgang Denk <wd@denx.de>
Date: Thu Jul 31 17:54:03 2008 +0200
Prepare v1.3.4-rc2: update CHANGELOG
Signed-off-by: Wolfgang Denk <wd@denx.de>
commit a48311557db6e7e9473a6163b44bb1e6c6ed64c4
Author: Mark Jackson <mpfj@mimc.co.uk>
Date: Thu Jul 31 16:09:00 2008 +0100
@ -5117,6 +5693,18 @@ Date: Mon May 5 14:06:11 2008 +0200
Signed-off-by: Jens Gehrlein <sew_s@tqs.de>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
commit 6324e5bec8825f7fee3026ffbd394454ae8b53fb
Author: Christian Eggers <ceggers@gmx.de>
Date: Wed May 21 21:29:10 2008 +0200
Fix endianess conversion in usb_ohci.c
Sorry, I forgot this line:
Signed-off-by: Christian Eggers <ceggers@gmx.de>
I think this must be swapped (result may be equal).
commit c918261c6d9f265f88baf70f8a73dfe6f0cb9596
Author: Christian Eggers <ceggers@gmx.de>
Date: Wed May 21 22:12:00 2008 +0200

5
CREDITS
View File

@ -399,6 +399,11 @@ N: Stelian Pop
E: stelian.pop@leadtechdesign.com
D: Atmel AT91CAP9ADK support
N: Ricardo Ribalda Delgado
E: ricardo.ribalda@uam.es
D: PPC440x5 (Virtex5), ML507 Board, eeprom_simul, adt7460
W: http://www.ii.uam.es/~rribalda
N: Stefan Roese
E: sr@denx.de
D: AMCC PPC4xx Support

55
MAINTAINERS
View File

@ -239,6 +239,10 @@ The LEOX team <team@leox.org>
ELPT860 MPC860T
Guennadi Liakhovetski <g.liakhovetski@gmx.de>
linkstation MPC8241
Dave Liu <daveliu@freescale.com>
MPC8315ERDB MPC8315
@ -311,6 +315,10 @@ Daniel Poirot <dan.poirot@windriver.com>
sbc8240 MPC8240
sbc405 PPC405GP
Ricardo Ribalda <ricardo.ribalda@uam.es>
ml507 PPC440x5
Stefan Roese <sr@denx.de>
P3M7448 MPC7448
@ -412,14 +420,17 @@ Stephen Williams <steve@icarus.com>
JSE PPC405GPr
Roy Zang <tie-fei.zang@freescale.com>
mpc7448hpc2 MPC7448
John Zhan <zhanz@sinovee.com>
svm_sc8xx MPC8xx
Guennadi Liakhovetski <g.liakhovetski@gmx.de>
linkstation MPC8241
Feng Kan <fkan@amcc.com>
redwood PPC4xx
-------------------------------------------------------------------------
Unknown / orphaned boards:
@ -523,6 +534,10 @@ Rolf Offermanns <rof@sysgo.de>
shannon SA1100
Kyungmin Park <kyungmin.park@samsung.com>
apollon ARM1136EJS
Peter Pearse <peter.pearse@arm.com>
integratorcp All current ARM supplied & supported core modules
-see http://www.arm.com/products/DevTools/Hardware_Platforms.html
@ -552,6 +567,13 @@ Robert Schwebel <r.schwebel@pengutronix.de>
csb226 xscale
innokom xscale
Michael Schwingen <michael@schwingen.org>
actux1 xscale
actux2 xscale
actux3 xscale
actux4 xscale
Andrea Scian <andrea.scian@dave-tech.it>
B2 ARM7TDMI (S3C44B0X)
@ -566,22 +588,11 @@ Richard Woodruff <r-woodruff2@ti.com>
omap2420h4 ARM1136EJS
Kyungmin Park <kyungmin.park@samsung.com>
apollon ARM1136EJS
Alex Züpke <azu@sysgo.de>
lart SA1100
dnp1110 SA1110
Michael Schwingen <michael@schwingen.org>
actux1 xscale
actux2 xscale
actux3 xscale
actux4 xscale
-------------------------------------------------------------------------
Unknown / orphaned boards:
@ -679,6 +690,10 @@ Matthias Fuchs <matthias.fuchs@esd-electronics.com>
TASREG MCF5249
Hayden Fraser <Hayden.Fraser@freescale.com>
M5253EVBE mcf52x2
TsiChung Liew <Tsi-Chung.Liew@freescale.com>
M52277EVB mcf5227x
@ -689,10 +704,6 @@ TsiChung Liew <Tsi-Chung.Liew@freescale.com>
M5475EVB mcf547x_8x
M5485EVB mcf547x_8x
Hayden Fraser <Hayden.Fraser@freescale.com>
M5253EVBE mcf52x2
#########################################################################
# AVR32 Systems: #
# #
@ -716,6 +727,10 @@ Haavard Skinnemoen <hskinnemoen@atmel.com>
# Board CPU #
#########################################################################
Yusuke Goda <goda.yusuke@renesas.com>
MIGO-R SH7722
Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
MS7750SE SH7750
@ -732,10 +747,6 @@ Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
MS7720SE SH7720
Yusuke Goda <goda.yusuke@renesas.com>
MIGO-R SH7722
#########################################################################
# Blackfin Systems: #
# #

3
MAKEALL
View File

@ -209,6 +209,8 @@ LIST_4xx=" \
MIP405T \
ML2 \
ml300 \
ml507 \
ml507_flash \
ocotea \
OCRTC \
ORSG \
@ -222,6 +224,7 @@ LIST_4xx=" \
PPChameleonEVB \
quad100hd \
rainier \
redwood \
sbc405 \
sc3 \
sequoia \

41
Makefile
View File

@ -24,7 +24,7 @@
VERSION = 1
PATCHLEVEL = 3
SUBLEVEL = 4
EXTRAVERSION = -rc2
EXTRAVERSION =
U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
VERSION_FILE = $(obj)include/version_autogenerated.h
@ -210,7 +210,7 @@ LIBS += cpu/ixp/npe/libnpe.a
endif
LIBS += lib_$(ARCH)/lib$(ARCH).a
LIBS += fs/cramfs/libcramfs.a fs/fat/libfat.a fs/fdos/libfdos.a fs/jffs2/libjffs2.a \
fs/reiserfs/libreiserfs.a fs/ext2/libext2fs.a
fs/reiserfs/libreiserfs.a fs/ext2/libext2fs.a fs/yaffs2/libyaffs2.a
LIBS += net/libnet.a
LIBS += disk/libdisk.a
LIBS += drivers/bios_emulator/libatibiosemu.a
@ -378,6 +378,7 @@ TAG_SUBDIRS += fs/cramfs
TAG_SUBDIRS += fs/fat
TAG_SUBDIRS += fs/fdos
TAG_SUBDIRS += fs/jffs2
TAG_SUBDIRS += fs/yaffs2
TAG_SUBDIRS += net
TAG_SUBDIRS += disk
TAG_SUBDIRS += common
@ -1348,6 +1349,17 @@ ML2_config: unconfig
ml300_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx ml300 xilinx
ml507_flash_config: unconfig
@mkdir -p $(obj)include $(obj)board/xilinx/ml507
@cp $(obj)board/xilinx/ml507/u-boot-rom.lds $(obj)board/xilinx/ml507/u-boot.lds
@echo "TEXT_BASE = 0xFE360000" > $(obj)board/xilinx/ml507/config.tmp
@$(MKCONFIG) $(@:_flash_config=) ppc ppc4xx ml507 xilinx
ml507_config: unconfig
@mkdir -p $(obj)include $(obj)board/xilinx/ml507
@cp $(obj)board/xilinx/ml507/u-boot-ram.lds $(obj)board/xilinx/ml507/u-boot.lds
@$(MKCONFIG) $(@:_config=) ppc ppc4xx ml507 xilinx
ocotea_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx ocotea amcc
@ -1409,6 +1421,9 @@ PPChameleonEVB_HI_33_config: unconfig
quad100hd_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx quad100hd
redwood_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx redwood amcc
sbc405_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx sbc405
@ -1996,8 +2011,11 @@ TASREG_config : unconfig
#########################################################################
MPC8313ERDB_33_config \
MPC8313ERDB_66_config: unconfig
MPC8313ERDB_66_config \
MPC8313ERDB_NAND_33_config \
MPC8313ERDB_NAND_66_config: unconfig
@mkdir -p $(obj)include
@mkdir -p $(obj)board/freescale/mpc8313erdb
@if [ "$(findstring _33_,$@)" ] ; then \
$(XECHO) -n "...33M ..." ; \
echo "#define CFG_33MHZ" >>$(obj)include/config.h ; \
@ -2005,6 +2023,11 @@ MPC8313ERDB_66_config: unconfig
if [ "$(findstring _66_,$@)" ] ; then \
$(XECHO) -n "...66M..." ; \
echo "#define CFG_66MHZ" >>$(obj)include/config.h ; \
fi ; \
if [ "$(findstring _NAND_,$@)" ] ; then \
$(XECHO) -n "...NAND..." ; \
echo "TEXT_BASE = 0x00100000" > $(obj)/board/freescale/mpc8313erdb/config.tmp ; \
echo "#define CONFIG_NAND_U_BOOT" >>$(obj)include/config.h ; \
fi ;
@$(MKCONFIG) -a MPC8313ERDB ppc mpc83xx mpc8313erdb freescale
@ -2354,13 +2377,13 @@ at91rm9200dk_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm920t at91rm9200dk atmel at91rm9200
at91sam9261ek_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm926ejs at91sam9261ek atmel at91sam9
@$(MKCONFIG) $(@:_config=) arm arm926ejs at91sam9261ek atmel at91
at91sam9263ek_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm926ejs at91sam9263ek atmel at91sam9
@$(MKCONFIG) $(@:_config=) arm arm926ejs at91sam9263ek atmel at91
at91sam9rlek_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm926ejs at91sam9rlek atmel at91sam9
@$(MKCONFIG) $(@:_config=) arm arm926ejs at91sam9rlek atmel at91
cmc_pu2_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm920t cmc_pu2 NULL at91rm9200
@ -2382,10 +2405,10 @@ mp2usb_config : unconfig
#########################################################################
at91cap9adk_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm926ejs at91cap9adk atmel at91sam9
@$(MKCONFIG) $(@:_config=) arm arm926ejs at91cap9adk atmel at91
at91sam9260ek_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm926ejs at91sam9260ek atmel at91sam9
@$(MKCONFIG) $(@:_config=) arm arm926ejs at91sam9260ek atmel at91
########################################################################
## ARM Integrator boards - see doc/README-integrator for more info.
@ -2672,7 +2695,7 @@ imx31_phycore_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm1136 imx31_phycore NULL mx31
mx31ads_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm1136 mx31ads NULL mx31
@$(MKCONFIG) $(@:_config=) arm arm1136 mx31ads freescale mx31
omap2420h4_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm1136 omap2420h4 NULL omap24xx

6
README
View File

@ -98,7 +98,7 @@ Where we come from:
- create ARMBoot project (http://sourceforge.net/projects/armboot)
- add other CPU families (starting with ARM)
- create U-Boot project (http://sourceforge.net/projects/u-boot)
- current project page: see http://www.denx.de/wiki/UBoot
- current project page: see http://www.denx.de/wiki/U-Boot
Names and Spelling:
@ -2064,7 +2064,7 @@ Configuration Settings:
Define if the flash driver uses extra elements in the
common flash structure for storing flash geometry.
- CFG_FLASH_CFI_DRIVER
- CONFIG_FLASH_CFI_DRIVER
This option also enables the building of the cfi_flash driver
in the drivers directory
@ -3903,7 +3903,7 @@ may be rejected, even when they contain important and valuable stuff.
Patches shall be sent to the u-boot-users mailing list.
Please see http://www.denx.de/wiki/UBoot/Patches for details.
Please see http://www.denx.de/wiki/U-Boot/Patches for details.
When you send a patch, please include the following information with
it:

2
board/ads5121/Makefile
View File

@ -27,7 +27,7 @@ $(shell mkdir -p $(OBJTREE)/board/freescale/common)
LIB = $(obj)lib$(BOARD).a
COBJS-y := $(BOARD).o iopin.o
COBJS-y := $(BOARD).o
COBJS-${CONFIG_FSL_DIU_FB} += ads5121_diu.o
COBJS-${CONFIG_FSL_DIU_FB} += ../freescale/common/fsl_diu_fb.o
COBJS-${CONFIG_FSL_DIU_FB} += ../freescale/common/fsl_logo_bmp.o

58
board/ads5121/ads5121.c
View File

@ -23,14 +23,12 @@
#include <common.h>
#include <mpc512x.h>
#include "iopin.h"
#include <asm/bitops.h>
#include <command.h>
#include <fdt_support.h>
#ifdef CONFIG_MISC_INIT_R
#include <i2c.h>
#endif
#include "iopin.h" /* for iopin_initialize() prototype */
/* Clocks in use */
#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \
@ -124,7 +122,7 @@ long int fixed_sdram (void)
u32 i;
/* Initialize IO Control */
im->io_ctrl.regs[MEM_IDX] = IOCTRL_MUX_DDR;
im->io_ctrl.regs[IOCTL_MEM/4] = IOCTRL_MUX_DDR;
/* Initialize DDR Local Window */
im->sysconf.ddrlaw.bar = CFG_DDR_BASE & 0xFFFFF000;
@ -237,6 +235,56 @@ int misc_init_r(void)
return 0;
}
static iopin_t ioregs_init[] = {
/* FUNC1=FEC_RX_DV Sets Next 3 to FEC pads */
{
IOCTL_SPDIF_TXCLK, 3, 0,
IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
},
/* Set highest Slew on 9 PATA pins */
{
IOCTL_PATA_CE1, 9, 1,
IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
},
/* FUNC1=FEC_COL Sets Next 15 to FEC pads */
{
IOCTL_PSC0_0, 15, 0,
IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
},
/* FUNC1=SPDIF_TXCLK */
{
IOCTL_LPC_CS1, 1, 0,
IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
},
/* FUNC2=SPDIF_TX and sets Next pin to SPDIF_RX */
{
IOCTL_I2C1_SCL, 2, 0,
IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
},
/* FUNC2=DIU CLK */
{
IOCTL_PSC6_0, 1, 0,
IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
},
/* FUNC2=DIU_HSYNC */
{
IOCTL_PSC6_1, 1, 0,
IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
},
/* FUNC2=DIUVSYNC Sets Next 26 to DIU Pads */
{
IOCTL_PSC6_4, 26, 0,
IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
}
};
int checkboard (void)
{
@ -246,7 +294,9 @@ int checkboard (void)
printf ("Board: ADS5121 rev. 0x%04x (CPLD rev. 0x%02x)\n",
brd_rev, cpld_rev);
/* initialize function mux & slew rate IO inter alia on IO Pins */
iopin_initialize();
iopin_initialize(ioregs_init, sizeof(ioregs_init) / sizeof(ioregs_init[0]));
return 0;
}

115
board/ads5121/iopin.c
View File

@ -1,115 +0,0 @@
/*
* (C) Copyright 2008
* Martha J Marx, Silicon Turnkey Express, mmarx@silicontkx.com
* mpc512x I/O pin/pad initialization for the ADS5121 board
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <linux/types.h>
#include "iopin.h"
/* IO pin fields */
#define IO_PIN_FMUX(v) ((v) << 7) /* pin function */
#define IO_PIN_HOLD(v) ((v) << 5) /* hold time, pci only */
#define IO_PIN_PUD(v) ((v) << 4) /* if PUE, 0=pull-down, 1=pull-up */
#define IO_PIN_PUE(v) ((v) << 3) /* pull up/down enable */
#define IO_PIN_ST(v) ((v) << 2) /* schmitt trigger */
#define IO_PIN_DS(v) ((v)) /* slew rate */
static struct iopin_t {
int p_offset; /* offset from IOCTL_MEM_OFFSET */
int nr_pins; /* number of pins to set this way */
int bit_or; /* or in the value instead of overwrite */
u_long val; /* value to write or or */
} ioregs_init[] = {
/* FUNC1=FEC_RX_DV Sets Next 3 to FEC pads */
{
IOCTL_SPDIF_TXCLK, 3, 0,
IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
},
/* Set highest Slew on 9 PATA pins */
{
IOCTL_PATA_CE1, 9, 1,
IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
},
/* FUNC1=FEC_COL Sets Next 15 to FEC pads */
{
IOCTL_PSC0_0, 15, 0,
IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
},
/* FUNC1=SPDIF_TXCLK */
{
IOCTL_LPC_CS1, 1, 0,
IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
},
/* FUNC2=SPDIF_TX and sets Next pin to SPDIF_RX */
{
IOCTL_I2C1_SCL, 2, 0,
IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
},
/* FUNC2=DIU CLK */
{
IOCTL_PSC6_0, 1, 0,
IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
},
/* FUNC2=DIU_HSYNC */
{
IOCTL_PSC6_1, 1, 0,
IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
},
/* FUNC2=DIUVSYNC Sets Next 26 to DIU Pads */
{
IOCTL_PSC6_4, 26, 0,
IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
}
};
void iopin_initialize(void)
{
short i, j, n, p;
u_long *reg;
immap_t *im = (immap_t *)CFG_IMMR;
reg = (u_long *)&(im->io_ctrl.regs[0]);
if (sizeof(ioregs_init) == 0)
return;
n = sizeof(ioregs_init) / sizeof(ioregs_init[0]);
for (i = 0; i < n; i++) {
for (p = 0, j = ioregs_init[i].p_offset / sizeof(u_long);
p < ioregs_init[i].nr_pins; p++, j++) {
if (ioregs_init[i].bit_or)
reg[j] |= ioregs_init[i].val;
else
reg[j] = ioregs_init[i].val;
}
}
return;
}

222
board/ads5121/iopin.h
View File

@ -1,222 +0,0 @@
/*
* (C) Copyright 2008
* Martha J Marx, Silicon Turnkey Express, mmarx@silicontkx.com
* mpc512x I/O pin/pad initialization for the ADS5121 board
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#define IOCTL_MEM 0x000
#define IOCTL_GP 0x004
#define IOCTL_LPC_CLK 0x008
#define IOCTL_LPC_OE 0x00C
#define IOCTL_LPC_RWB 0x010
#define IOCTL_LPC_ACK 0x014
#define IOCTL_LPC_CS0 0x018
#define IOCTL_NFC_CE0 0x01C
#define IOCTL_LPC_CS1 0x020
#define IOCTL_LPC_CS2 0x024
#define IOCTL_LPC_AX03 0x028
#define IOCTL_EMB_AX02 0x02C
#define IOCTL_EMB_AX01 0x030
#define IOCTL_EMB_AX00 0x034
#define IOCTL_EMB_AD31 0x038
#define IOCTL_EMB_AD30 0x03C
#define IOCTL_EMB_AD29 0x040
#define IOCTL_EMB_AD28 0x044
#define IOCTL_EMB_AD27 0x048
#define IOCTL_EMB_AD26 0x04C
#define IOCTL_EMB_AD25 0x050
#define IOCTL_EMB_AD24 0x054
#define IOCTL_EMB_AD23 0x058
#define IOCTL_EMB_AD22 0x05C
#define IOCTL_EMB_AD21 0x060
#define IOCTL_EMB_AD20 0x064
#define IOCTL_EMB_AD19 0x068
#define IOCTL_EMB_AD18 0x06C
#define IOCTL_EMB_AD17 0x070
#define IOCTL_EMB_AD16 0x074
#define IOCTL_EMB_AD15 0x078
#define IOCTL_EMB_AD14 0x07C
#define IOCTL_EMB_AD13 0x080
#define IOCTL_EMB_AD12 0x084
#define IOCTL_EMB_AD11 0x088
#define IOCTL_EMB_AD10 0x08C
#define IOCTL_EMB_AD09 0x090
#define IOCTL_EMB_AD08 0x094
#define IOCTL_EMB_AD07 0x098
#define IOCTL_EMB_AD06 0x09C
#define IOCTL_EMB_AD05 0x0A0
#define IOCTL_EMB_AD04 0x0A4
#define IOCTL_EMB_AD03 0x0A8
#define IOCTL_EMB_AD02 0x0AC
#define IOCTL_EMB_AD01 0x0B0
#define IOCTL_EMB_AD00 0x0B4
#define IOCTL_PATA_CE1 0x0B8
#define IOCTL_PATA_CE2 0x0BC
#define IOCTL_PATA_ISOLATE 0x0C0
#define IOCTL_PATA_IOR 0x0C4
#define IOCTL_PATA_IOW 0x0C8
#define IOCTL_PATA_IOCHRDY 0x0CC
#define IOCTL_PATA_INTRQ 0x0D0
#define IOCTL_PATA_DRQ 0x0D4
#define IOCTL_PATA_DACK 0x0D8
#define IOCTL_NFC_WP 0x0DC
#define IOCTL_NFC_RB 0x0E0
#define IOCTL_NFC_ALE 0x0E4
#define IOCTL_NFC_CLE 0x0E8
#define IOCTL_NFC_WE 0x0EC
#define IOCTL_NFC_RE 0x0F0
#define IOCTL_PCI_AD31 0x0F4
#define IOCTL_PCI_AD30 0x0F8
#define IOCTL_PCI_AD29 0x0FC
#define IOCTL_PCI_AD28 0x100
#define IOCTL_PCI_AD27 0x104
#define IOCTL_PCI_AD26 0x108
#define IOCTL_PCI_AD25 0x10C
#define IOCTL_PCI_AD24 0x110
#define IOCTL_PCI_AD23 0x114
#define IOCTL_PCI_AD22 0x118
#define IOCTL_PCI_AD21 0x11C
#define IOCTL_PCI_AD20 0x120
#define IOCTL_PCI_AD19 0x124
#define IOCTL_PCI_AD18 0x128
#define IOCTL_PCI_AD17 0x12C
#define IOCTL_PCI_AD16 0x130
#define IOCTL_PCI_AD15 0x134
#define IOCTL_PCI_AD14 0x138
#define IOCTL_PCI_AD13 0x13C
#define IOCTL_PCI_AD12 0x140
#define IOCTL_PCI_AD11 0x144
#define IOCTL_PCI_AD10 0x148
#define IOCTL_PCI_AD09 0x14C
#define IOCTL_PCI_AD08 0x150
#define IOCTL_PCI_AD07 0x154
#define IOCTL_PCI_AD06 0x158
#define IOCTL_PCI_AD05 0x15C
#define IOCTL_PCI_AD04 0x160
#define IOCTL_PCI_AD03 0x164
#define IOCTL_PCI_AD02 0x168
#define IOCTL_PCI_AD01 0x16C
#define IOCTL_PCI_AD00 0x170
#define IOCTL_PCI_CBE0 0x174
#define IOCTL_PCI_CBE1 0x178
#define IOCTL_PCI_CBE2 0x17C
#define IOCTL_PCI_CBE3 0x180
#define IOCTL_PCI_GNT2 0x184
#define IOCTL_PCI_REQ2 0x188
#define IOCTL_PCI_GNT1 0x18C
#define IOCTL_PCI_REQ1 0x190
#define IOCTL_PCI_GNT0 0x194
#define IOCTL_PCI_REQ0 0x198
#define IOCTL_PCI_INTA 0x19C
#define IOCTL_PCI_CLK 0x1A0
#define IOCTL_PCI_RST_OUT 0x1A4
#define IOCTL_PCI_FRAME 0x1A8
#define IOCTL_PCI_IDSEL 0x1AC
#define IOCTL_PCI_DEVSEL 0x1B0
#define IOCTL_PCI_IRDY 0x1B4
#define IOCTL_PCI_TRDY 0x1B8
#define IOCTL_PCI_STOP 0x1BC
#define IOCTL_PCI_PAR 0x1C0
#define IOCTL_PCI_PERR 0x1C4
#define IOCTL_PCI_SERR 0x1C8
#define IOCTL_SPDIF_TXCLK 0x1CC
#define IOCTL_SPDIF_TX 0x1D0
#define IOCTL_SPDIF_RX 0x1D4
#define IOCTL_I2C0_SCL 0x1D8
#define IOCTL_I2C0_SDA 0x1DC
#define IOCTL_I2C1_SCL 0x1E0
#define IOCTL_I2C1_SDA 0x1E4
#define IOCTL_I2C2_SCL 0x1E8
#define IOCTL_I2C2_SDA 0x1EC
#define IOCTL_IRQ0 0x1F0
#define IOCTL_IRQ1 0x1F4
#define IOCTL_CAN1_TX 0x1F8
#define IOCTL_CAN2_TX 0x1FC
#define IOCTL_J1850_TX 0x200
#define IOCTL_J1850_RX 0x204
#define IOCTL_PSC_MCLK_IN 0x208
#define IOCTL_PSC0_0 0x20C
#define IOCTL_PSC0_1 0x210
#define IOCTL_PSC0_2 0x214
#define IOCTL_PSC0_3 0x218
#define IOCTL_PSC0_4 0x21C
#define IOCTL_PSC1_0 0x220
#define IOCTL_PSC1_1 0x224
#define IOCTL_PSC1_2 0x228
#define IOCTL_PSC1_3 0x22C
#define IOCTL_PSC1_4 0x230
#define IOCTL_PSC2_0 0x234
#define IOCTL_PSC2_1 0x238
#define IOCTL_PSC2_2 0x23C
#define IOCTL_PSC2_3 0x240
#define IOCTL_PSC2_4 0x244
#define IOCTL_PSC3_0 0x248
#define IOCTL_PSC3_1 0x24C
#define IOCTL_PSC3_2 0x250
#define IOCTL_PSC3_3 0x254
#define IOCTL_PSC3_4 0x258
#define IOCTL_PSC4_0 0x25C
#define IOCTL_PSC4_1 0x260
#define IOCTL_PSC4_2 0x264
#define IOCTL_PSC4_3 0x268
#define IOCTL_PSC4_4 0x26C
#define IOCTL_PSC5_0 0x270
#define IOCTL_PSC5_1 0x274
#define IOCTL_PSC5_2 0x278
#define IOCTL_PSC5_3 0x27C
#define IOCTL_PSC5_4 0x280
#define IOCTL_PSC6_0 0x284
#define IOCTL_PSC6_1 0x288
#define IOCTL_PSC6_2 0x28C
#define IOCTL_PSC6_3 0x290
#define IOCTL_PSC6_4 0x294
#define IOCTL_PSC7_0 0x298
#define IOCTL_PSC7_1 0x29C
#define IOCTL_PSC7_2 0x2A0
#define IOCTL_PSC7_3 0x2A4
#define IOCTL_PSC7_4 0x2A8
#define IOCTL_PSC8_0 0x2AC
#define IOCTL_PSC8_1 0x2B0
#define IOCTL_PSC8_2 0x2B4
#define IOCTL_PSC8_3 0x2B8
#define IOCTL_PSC8_4 0x2BC
#define IOCTL_PSC9_0 0x2C0
#define IOCTL_PSC9_1 0x2C4
#define IOCTL_PSC9_2 0x2C8
#define IOCTL_PSC9_3 0x2CC
#define IOCTL_PSC9_4 0x2D0
#define IOCTL_PSC10_0 0x2D4
#define IOCTL_PSC10_1 0x2D8
#define IOCTL_PSC10_2 0x2DC
#define IOCTL_PSC10_3 0x2E0
#define IOCTL_PSC10_4 0x2E4
#define IOCTL_PSC11_0 0x2E8
#define IOCTL_PSC11_1 0x2EC
#define IOCTL_PSC11_2 0x2F0
#define IOCTL_PSC11_3 0x2F4
#define IOCTL_PSC11_4 0x2F8
#define IOCTL_HRESET 0x2FC
#define IOCTL_SRESET 0x300
#define IOCTL_CKSTP_OUT 0x304
#define IOCTL_USB2_VBUS_PWR_FAULT 0x308
#define IOCTL_USB2_VBUS_PWR_SELECT 0x30C
#define IOCTL_USB2_PHY_DRVV_BUS 0x310
extern void iopin_initialize(void);

72
board/amcc/katmai/katmai.c
View File

@ -349,7 +349,7 @@ int is_pci_host(struct pci_controller *hose)
return 1;
}
int katmai_pcie_card_present(int port)
static int katmai_pcie_card_present(int port)
{
u32 val;
@ -437,76 +437,6 @@ void pcie_setup_hoses(int busno)
}
#endif /* defined(CONFIG_PCI) */
int misc_init_f (void)
{
uint reg;
#if defined(CONFIG_STRESS)
uint i ;
uint disp;
#endif
/* minimal init for PCIe */
#if 0 /* test-only: test endpoint at some time, for now rootpoint only */
/* pci express 0 Endpoint Mode */
mfsdr(SDR0_PE0DLPSET, reg);
reg &= (~0x00400000);
mtsdr(SDR0_PE0DLPSET, reg);
#else
/* pci express 0 Rootpoint Mode */
mfsdr(SDR0_PE0DLPSET, reg);
reg |= 0x00400000;
mtsdr(SDR0_PE0DLPSET, reg);
#endif
/* pci express 1 Rootpoint Mode */
mfsdr(SDR0_PE1DLPSET, reg);
reg |= 0x00400000;
mtsdr(SDR0_PE1DLPSET, reg);
/* pci express 2 Rootpoint Mode */
mfsdr(SDR0_PE2DLPSET, reg);
reg |= 0x00400000;
mtsdr(SDR0_PE2DLPSET, reg);
#if defined(CONFIG_STRESS)
/*
* All this setting done by linux only needed by stress an charac. test
* procedure
* PCIe 1 Rootpoint PCIe2 Endpoint
* PCIe 0 FIR Pre-emphasis Filter Coefficients & Transmit Driver Power Level
*/
for (i=0,disp=0; i<8; i++,disp+=3) {
mfsdr(SDR0_PE0HSSSET1L0+disp, reg);
reg |= 0x33000000;
mtsdr(SDR0_PE0HSSSET1L0+disp, reg);
}
/*PCIe 1 FIR Pre-emphasis Filter Coefficients & Transmit Driver Power Level */
for (i=0,disp=0; i<4; i++,disp+=3) {
mfsdr(SDR0_PE1HSSSET1L0+disp, reg);
reg |= 0x33000000;
mtsdr(SDR0_PE1HSSSET1L0+disp, reg);
}
/*PCIE 2 FIR Pre-emphasis Filter Coefficients & Transmit Driver Power Level */
for (i=0,disp=0; i<4; i++,disp+=3) {
mfsdr(SDR0_PE2HSSSET1L0+disp, reg);
reg |= 0x33000000;
mtsdr(SDR0_PE2HSSSET1L0+disp, reg);
}
reg = 0x21242222;
mtsdr(SDR0_PE2UTLSET1, reg);
reg = 0x11000000;
mtsdr(SDR0_PE2UTLSET2, reg);
/* pci express 1 Endpoint Mode */
reg = 0x00004000;
mtsdr(SDR0_PE2DLPSET, reg);
mtsdr(SDR0_UART1, 0x2080005a); /* patch for TG */
#endif
return 0;
}
#ifdef CONFIG_POST
/*
* Returns 1 if keys pressed to start the power-on long-running tests

50
board/amcc/ocotea/ocotea.c
View File

@ -147,36 +147,48 @@ int board_early_init_f (void)
/*--------------------------------------------------------------------
* Setup the interrupt controller polarities, triggers, etc.
*-------------------------------------------------------------------*/
mtdcr (uic0sr, 0xffffffff); /* clear all */
mtdcr (uic0er, 0x00000000); /* disable all */
mtdcr (uic0cr, 0x00000009); /* SMI & UIC1 crit are critical */
mtdcr (uic0pr, 0xfffffe13); /* per ref-board manual */
mtdcr (uic0tr, 0x01c00008); /* per ref-board manual */
mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (uic0sr, 0xffffffff); /* clear all */
/*
* Because of the interrupt handling rework to handle 440GX interrupts
* with the common code, we needed to change names of the UIC registers.
* Here the new relationship:
*
* U-Boot name 440GX name
* -----------------------
* UIC0 UICB0
* UIC1 UIC0
* UIC2 UIC1
* UIC3 UIC2
*/
mtdcr (uic1sr, 0xffffffff); /* clear all */
mtdcr (uic1er, 0x00000000); /* disable all */
mtdcr (uic1cr, 0x00000000); /* all non-critical */
mtdcr (uic1pr, 0xffffe0ff); /* per ref-board manual */
mtdcr (uic1tr, 0x00ffc000); /* per ref-board manual */
mtdcr (uic1cr, 0x00000009); /* SMI & UIC1 crit are critical */
mtdcr (uic1pr, 0xfffffe13); /* per ref-board manual */
mtdcr (uic1tr, 0x01c00008); /* per ref-board manual */
mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (uic1sr, 0xffffffff); /* clear all */
mtdcr (uic2sr, 0xffffffff); /* clear all */
mtdcr (uic2er, 0x00000000); /* disable all */
mtdcr (uic2cr, 0x00000000); /* all non-critical */
mtdcr (uic2pr, 0xffffffff); /* per ref-board manual */
mtdcr (uic2tr, 0x00ff8c0f); /* per ref-board manual */
mtdcr (uic2pr, 0xffffe0ff); /* per ref-board manual */
mtdcr (uic2tr, 0x00ffc000); /* per ref-board manual */
mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (uic2sr, 0xffffffff); /* clear all */
mtdcr (uicb0sr, 0xfc000000); /* clear all */
mtdcr (uicb0er, 0x00000000); /* disable all */
mtdcr (uicb0cr, 0x00000000); /* all non-critical */
mtdcr (uicb0pr, 0xfc000000); /* */
mtdcr (uicb0tr, 0x00000000); /* */
mtdcr (uicb0vr, 0x00000001); /* */
mtdcr (uic3sr, 0xffffffff); /* clear all */
mtdcr (uic3er, 0x00000000); /* disable all */
mtdcr (uic3cr, 0x00000000); /* all non-critical */
mtdcr (uic3pr, 0xffffffff); /* per ref-board manual */
mtdcr (uic3tr, 0x00ff8c0f); /* per ref-board manual */
mtdcr (uic3vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (uic3sr, 0xffffffff); /* clear all */
mtdcr (uic0sr, 0xfc000000); /* clear all */
mtdcr (uic0er, 0x00000000); /* disable all */
mtdcr (uic0cr, 0x00000000); /* all non-critical */
mtdcr (uic0pr, 0xfc000000); /* */
mtdcr (uic0tr, 0x00000000); /* */
mtdcr (uic0vr, 0x00000001); /* */
mfsdr (sdr_mfr, mfr);
mfr &= ~SDR0_MFR_ECS_MASK;
/* mtsdr(sdr_mfr, mfr); */

50
board/amcc/redwood/Makefile Normal file
View File

@ -0,0 +1,50 @@
#
# (C) Copyright 2008
# Feng Kan, Applied Micro Circuits Corp., fkan@amcc.com.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o
SOBJS = init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend *~
#########################################################################
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

42
board/amcc/redwood/config.mk Normal file
View File

@ -0,0 +1,42 @@
#
# (C) Copyright 2008
# Feng Kan, Applied Micro Circuits Corp., fkan@amcc.com.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
# AMCC 460SX Reference Platform (redwood) board
#
ifeq ($(ramsym),1)
TEXT_BASE = 0x07FD0000
else
TEXT_BASE = 0xfffb0000
endif
PLATFORM_CPPFLAGS += -DCONFIG_440=1
ifeq ($(debug),1)
PLATFORM_CPPFLAGS += -DDEBUG
endif
ifeq ($(dbcr),1)
PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
endif

77
board/amcc/redwood/init.S Normal file
View File

@ -0,0 +1,77 @@
/*
* (C) Copyright 2008
* Feng Kan, Applied Micro Circuits Corp., fkan@amcc.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <ppc_asm.tmpl>
#include <config.h>
#include <asm-ppc/mmu.h>
/**************************************************************************
* TLB TABLE
*
* This table is used by the cpu boot code to setup the initial tlb
* entries. Rather than make broad assumptions in the cpu source tree,
* this table lets each board set things up however they like.
*
* Pointer to the table is returned in r1
*
*************************************************************************/
.section .bootpg,"ax"
.globl tlbtab
tlbtab:
tlbtab_start
/*
* BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
* speed up boot process. It is patched after relocation to enable SA_I
*/
tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_R|AC_W|AC_X|SA_G)
/*
* TLB entries for SDRAM are not needed on this platform.
* They are dynamically generated in the SPD DDR(2) detection
* routine.
*/
/* Although 512 KB, map 256k at a time */
tlbentry(CFG_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I)
tlbentry(CFG_ISRAM_BASE + 0x40000, SZ_256K, 0x00040000, 4, AC_R|AC_W|AC_X|SA_I)
tlbentry(CFG_OPER_FLASH, SZ_16M, 0xE7000000, 4,AC_R|AC_W|AC_X|SA_G|SA_I)
/*
* Peripheral base
*/
tlbentry(CFG_PERIPHERAL_BASE, SZ_16K, 0xEF600000, 4, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE0_XCFGBASE,SZ_16M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE1_XCFGBASE,SZ_16M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE2_XCFGBASE,SZ_16M, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE0_MEMBASE, SZ_256M, 0x00000000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE1_MEMBASE, SZ_256M, 0x00000000, 0xE, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE0_REGBASE, SZ_64K, 0x30000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE1_REGBASE, SZ_64K, 0x30010000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE2_REGBASE, SZ_64K, 0x30020000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbtab_end

456
board/amcc/redwood/redwood.c Normal file
View File

@ -0,0 +1,456 @@
/*
* This is the main board level file for the Redwood AMCC board.
*
* (C) Copyright 2008
* Feng Kan, Applied Micro Circuits Corp., fkan@amcc.com
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#include <common.h>
#include "redwood.h"
#include <ppc4xx.h>
#include <asm/processor.h>
#include <i2c.h>
#include <asm-ppc/io.h>
int compare_to_true(char *str);
char *remove_l_w_space(char *in_str);
char *remove_t_w_space(char *in_str);
int get_console_port(void);
static void early_init_EBC(void);
static int bootdevice_selected(void);
static void early_reinit_EBC(int);
static void early_init_UIC(void);
/*
* Define Boot devices
*/
#define BOOT_FROM_8BIT_SRAM 0x00
#define BOOT_FROM_16BIT_SRAM 0x01
#define BOOT_FROM_32BIT_SRAM 0x02
#define BOOT_FROM_8BIT_NAND 0x03
#define BOOT_FROM_16BIT_NOR 0x04
#define BOOT_DEVICE_UNKNOWN 0xff
/*
* EBC Devices Characteristics
* Peripheral Bank Access Parameters - EBC_BxAP
* Peripheral Bank Configuration Register - EBC_BxCR
*/
/*
* 8 bit width SRAM
* BU Value
* BxAP : 0x03800000 - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000
* B0CR : 0xff098000 - BAS = ff0 - 100 11 00 0000000000000
* B2CR : 0xe7098000 - BAS = e70 - 100 11 00 0000000000000
*/
#define EBC_BXAP_8BIT_SRAM \
EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(7) | \
EBC_BXAP_BCE_DISABLE | EBC_BXAP_BCT_2TRANS | \
EBC_BXAP_CSN_ENCODE(0) | EBC_BXAP_OEN_ENCODE(0) | \
EBC_BXAP_WBN_ENCODE(0) | EBC_BXAP_WBF_ENCODE(0) | \
EBC_BXAP_TH_ENCODE(0) | EBC_BXAP_RE_DISABLED | \
EBC_BXAP_SOR_DELAYED | EBC_BXAP_BEM_WRITEONLY | \
EBC_BXAP_PEN_DISABLED
#define EBC_BXAP_16BIT_SRAM EBC_BXAP_8BIT_SRAM
#define EBC_BXAP_32BIT_SRAM EBC_BXAP_8BIT_SRAM
/*
* NAND flash
* BU Value
* BxAP : 0x048ff240 - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000
* B0CR : 0xff09a000 - BAS = ff0 - 100 11 01 0000000000000
* B2CR : 0xe709a000 - BAS = e70 - 100 11 01 0000000000000
*/
#define EBC_BXAP_NAND \
EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(7) | \
EBC_BXAP_BCE_DISABLE | EBC_BXAP_BCT_2TRANS | \
EBC_BXAP_CSN_ENCODE(0) | EBC_BXAP_OEN_ENCODE(0) | \
EBC_BXAP_WBN_ENCODE(0) | EBC_BXAP_WBF_ENCODE(0) | \
EBC_BXAP_TH_ENCODE(0) | EBC_BXAP_RE_DISABLED | \
EBC_BXAP_SOR_DELAYED | EBC_BXAP_BEM_WRITEONLY | \
EBC_BXAP_PEN_DISABLED
/*
* NOR flash
* BU Value
* BxAP : 0x048ff240 - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000
* B0CR : 0xff09a000 - BAS = ff0 - 100 11 01 0000000000000
* B2CR : 0xe709a000 - BAS = e70 - 100 11 01 0000000000000
*/
#define EBC_BXAP_NOR \
EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(7) | \
EBC_BXAP_BCE_DISABLE | EBC_BXAP_BCT_2TRANS | \
EBC_BXAP_CSN_ENCODE(0) | EBC_BXAP_OEN_ENCODE(0) | \
EBC_BXAP_WBN_ENCODE(0) | EBC_BXAP_WBF_ENCODE(0) | \
EBC_BXAP_TH_ENCODE(0) | EBC_BXAP_RE_DISABLED | \
EBC_BXAP_SOR_DELAYED | EBC_BXAP_BEM_WRITEONLY | \
EBC_BXAP_PEN_DISABLED
/*
* FPGA
* BU value :
* B1AP = 0x05895240 - 0 00001011 0 00 10 01 01 01 001 0 0 1 0 00000
* B1CR = 0xe201a000 - BAS = e20 - 000 11 01 00000000000000
*/
#define EBC_BXAP_FPGA \
EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(11) | \
EBC_BXAP_BCE_DISABLE | EBC_BXAP_BCT_2TRANS | \
EBC_BXAP_CSN_ENCODE(10) | EBC_BXAP_OEN_ENCODE(1) | \
EBC_BXAP_WBN_ENCODE(1) | EBC_BXAP_WBF_ENCODE(1) | \
EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_RE_DISABLED | \
EBC_BXAP_SOR_DELAYED | EBC_BXAP_BEM_RW | \
EBC_BXAP_PEN_DISABLED
#define EBC_BXCR_8BIT_SRAM_CS0 \
EBC_BXCR_BAS_ENCODE(0xFFE00000) | EBC_BXCR_BS_1MB | \
EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT
#define EBC_BXCR_32BIT_SRAM_CS0 \
EBC_BXCR_BAS_ENCODE(0xFFC00000) | EBC_BXCR_BS_1MB | \
EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT
#define EBC_BXCR_NAND_CS0 \
EBC_BXCR_BAS_ENCODE(0xFF000000) | EBC_BXCR_BS_16MB | \
EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT
#define EBC_BXCR_16BIT_SRAM_CS0 \
EBC_BXCR_BAS_ENCODE(0xFFE00000) | EBC_BXCR_BS_2MB | \
EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT
#define EBC_BXCR_NOR_CS0 \
EBC_BXCR_BAS_ENCODE(0xFF000000) | EBC_BXCR_BS_16MB | \
EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT
#define EBC_BXCR_NOR_CS1 \
EBC_BXCR_BAS_ENCODE(0xE0000000) | EBC_BXCR_BS_128MB | \
EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT
#define EBC_BXCR_NAND_CS1 \
EBC_BXCR_BAS_ENCODE(0xE0000000) | EBC_BXCR_BS_128MB | \
EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT
#define EBC_BXCR_NAND_CS2 \
EBC_BXCR_BAS_ENCODE(0xC0000000) | EBC_BXCR_BS_128MB | \
EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT
#define EBC_BXCR_SRAM_CS2 \
EBC_BXCR_BAS_ENCODE(0xC0000000) | EBC_BXCR_BS_4MB | \
EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT
#define EBC_BXCR_LARGE_FLASH_CS2 \
EBC_BXCR_BAS_ENCODE(0xE7000000) | EBC_BXCR_BS_16MB | \
EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT
#define EBC_BXCR_FPGA_CS3 \
EBC_BXCR_BAS_ENCODE(0xE2000000) | EBC_BXCR_BS_1MB | \
EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT
/*****************************************************************************
* UBOOT initiated board specific function calls
****************************************************************************/
int board_early_init_f(void)
{
int computed_boot_device = BOOT_DEVICE_UNKNOWN;
/*
* Initialise EBC
*/
early_init_EBC();
/*
* Determine which boot device was selected
*/
computed_boot_device = bootdevice_selected();
/*
* Reinit EBC based on selected boot device
*/
early_reinit_EBC(computed_boot_device);
/*
* Setup for UIC on 460SX redwood board
*/
early_init_UIC();
return 0;
}
int checkboard(void)
{
char *s = getenv("serial#");
printf("Board: Redwood - AMCC 460SX Reference Board");
if (s != NULL) {
puts(", serial# ");
puts(s);
}
putc('\n');
return 0;
}
static void early_init_EBC(void)
{
/*
* Initialize EBC CONFIG -
* Keep the Default value, but the bit PDT which has to be set to 1 ?TBC
* default value :
* 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000
*/
mtebc(xbcfg, EBC_CFG_LE_UNLOCK |
EBC_CFG_PTD_ENABLE |
EBC_CFG_RTC_16PERCLK |
EBC_CFG_ATC_PREVIOUS |
EBC_CFG_DTC_PREVIOUS |
EBC_CFG_CTC_PREVIOUS |
EBC_CFG_OEO_PREVIOUS |
EBC_CFG_EMC_DEFAULT | EBC_CFG_PME_DISABLE | EBC_CFG_PR_16);
/*
* PART 1 : Initialize EBC Bank 3
* ==============================
* Bank1 is always associated to the EPLD.
* It has to be initialized prior to other banks settings computation
* since some board registers values may be needed to determine the
* boot type
*/
mtebc(pb1ap, EBC_BXAP_FPGA);
mtebc(pb1cr, EBC_BXCR_FPGA_CS3);
}
static int bootdevice_selected(void)
{
unsigned long sdr0_pinstp;
unsigned long bootstrap_settings;
int computed_boot_device = BOOT_DEVICE_UNKNOWN;
/*
* Determine which boot device was selected
* =================================================
*
* Read Pin Strap Register in PPC460SX
* Result can either be :
* - Boot strap = boot from EBC 8bits => Small Flash
* - Boot strap = boot from PCI
* - Boot strap = IIC
* In case of boot from IIC, read Serial Device Strap Register1
*
* Result can either be :
* - Boot from EBC - EBC Bus Width = 8bits => Small Flash
* - Boot from EBC - EBC Bus Width = 16bits => Large Flash or SRAM
* - Boot from PCI
*/
/* Read Pin Strap Register in PPC460SX */
mfsdr(SDR0_PINSTP, sdr0_pinstp);
bootstrap_settings = sdr0_pinstp & SDR0_PSTRP0_BOOTSTRAP_MASK;
switch (bootstrap_settings) {
case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0:
/*
* Boot from SRAM, 8bit width
*/
computed_boot_device = BOOT_FROM_8BIT_SRAM;
break;
case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1:
/*
* Boot from SRAM, 32bit width
*/
computed_boot_device = BOOT_FROM_32BIT_SRAM;
break;
case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2:
/*
* Boot from NAND, 8bit width
*/
computed_boot_device = BOOT_FROM_8BIT_NAND;
break;
case SDR0_PSTRP0_BOOTSTRAP_SETTINGS4:
/*
* Boot from SRAM, 16bit width
* Boot setting in IIC EEPROM 0x50
*/
computed_boot_device = BOOT_FROM_16BIT_SRAM;
break;
case SDR0_PSTRP0_BOOTSTRAP_SETTINGS5:
/*
* Boot from NOR, 16bit width
* Boot setting in IIC EEPROM 0x54
*/
computed_boot_device = BOOT_FROM_16BIT_NOR;
break;
default:
/* should not be */
computed_boot_device = BOOT_DEVICE_UNKNOWN;
break;
}
return computed_boot_device;
}
static void early_reinit_EBC(int computed_boot_device)
{
/*
* Compute EBC settings depending on selected boot device
* ======================================================
*
* Resulting EBC init will be among following configurations :
*
* - Boot from EBC 8bits => boot from Small Flash selected
* EBC-CS0 = Small Flash
* EBC-CS2 = Large Flash and SRAM
*
* - Boot from EBC 16bits => boot from Large Flash or SRAM
* EBC-CS0 = Large Flash or SRAM
* EBC-CS2 = Small Flash
*
* - Boot from PCI
* EBC-CS0 = not initialized to avoid address contention
* EBC-CS2 = same as boot from Small Flash selected
*/
unsigned long ebc0_cs0_bxap_value = 0, ebc0_cs0_bxcr_value = 0;
unsigned long ebc0_cs1_bxap_value = 0, ebc0_cs1_bxcr_value = 0;
unsigned long ebc0_cs2_bxap_value = 0, ebc0_cs2_bxcr_value = 0;
switch (computed_boot_device) {
/*-------------------------------------------------------------------*/
case BOOT_FROM_8BIT_SRAM:
/*-------------------------------------------------------------------*/
ebc0_cs0_bxap_value = EBC_BXAP_8BIT_SRAM;
ebc0_cs0_bxcr_value = EBC_BXCR_8BIT_SRAM_CS0;
ebc0_cs1_bxap_value = EBC_BXAP_NOR;
ebc0_cs1_bxcr_value = EBC_BXCR_NOR_CS1;
ebc0_cs2_bxap_value = EBC_BXAP_NAND;
ebc0_cs2_bxcr_value = EBC_BXCR_NAND_CS2;
break;
/*-------------------------------------------------------------------*/
case BOOT_FROM_16BIT_SRAM:
/*-------------------------------------------------------------------*/
ebc0_cs0_bxap_value = EBC_BXAP_16BIT_SRAM;
ebc0_cs0_bxcr_value = EBC_BXCR_16BIT_SRAM_CS0;
ebc0_cs1_bxap_value = EBC_BXAP_NOR;
ebc0_cs1_bxcr_value = EBC_BXCR_NOR_CS1;
ebc0_cs2_bxap_value = EBC_BXAP_NAND;
ebc0_cs2_bxcr_value = EBC_BXCR_NAND_CS2;
break;
/*-------------------------------------------------------------------*/
case BOOT_FROM_32BIT_SRAM:
/*-------------------------------------------------------------------*/
ebc0_cs0_bxap_value = EBC_BXAP_32BIT_SRAM;
ebc0_cs0_bxcr_value = EBC_BXCR_32BIT_SRAM_CS0;
ebc0_cs1_bxap_value = EBC_BXAP_NOR;
ebc0_cs1_bxcr_value = EBC_BXCR_NOR_CS1;
ebc0_cs2_bxap_value = EBC_BXAP_NAND;
ebc0_cs2_bxcr_value = EBC_BXCR_NAND_CS2;
break;
/*-------------------------------------------------------------------*/
case BOOT_FROM_16BIT_NOR:
/*-------------------------------------------------------------------*/
ebc0_cs0_bxap_value = EBC_BXAP_NOR;
ebc0_cs0_bxcr_value = EBC_BXCR_NOR_CS0;
ebc0_cs1_bxap_value = EBC_BXAP_NAND;
ebc0_cs1_bxcr_value = EBC_BXCR_NAND_CS1;
ebc0_cs2_bxap_value = EBC_BXAP_32BIT_SRAM;
ebc0_cs2_bxcr_value = EBC_BXCR_SRAM_CS2;
break;
/*-------------------------------------------------------------------*/
case BOOT_FROM_8BIT_NAND:
/*-------------------------------------------------------------------*/
ebc0_cs0_bxap_value = EBC_BXAP_NAND;
ebc0_cs0_bxcr_value = EBC_BXCR_NAND_CS0;
ebc0_cs1_bxap_value = EBC_BXAP_NOR;
ebc0_cs1_bxcr_value = EBC_BXCR_NOR_CS1;
ebc0_cs2_bxap_value = EBC_BXAP_32BIT_SRAM;
ebc0_cs2_bxcr_value = EBC_BXCR_SRAM_CS2;
break;
/*-------------------------------------------------------------------*/
default:
/*-------------------------------------------------------------------*/
/* BOOT_DEVICE_UNKNOWN */
break;
}
mtebc(pb0ap, ebc0_cs0_bxap_value);
mtebc(pb0cr, ebc0_cs0_bxcr_value);
mtebc(pb1ap, ebc0_cs1_bxap_value);
mtebc(pb1cr, ebc0_cs1_bxcr_value);
mtebc(pb2ap, ebc0_cs2_bxap_value);
mtebc(pb2cr, ebc0_cs2_bxcr_value);
}
static void early_init_UIC(void)
{
/*
* Initialise UIC registers. Clear all interrupts. Disable all
* interrupts.
* Set critical interrupt values. Set interrupt polarities. Set
* interrupt trigger levels. Make bit 0 High priority. Clear all
* interrupts again.
*/
mtdcr(uic3sr, 0xffffffff); /* Clear all interrupts */
mtdcr(uic3er, 0x00000000); /* disable all interrupts */
mtdcr(uic3cr, 0x00000000); /* Set Critical / Non Critical
* interrupts */
mtdcr(uic3pr, 0xffffffff); /* Set Interrupt Polarities */
mtdcr(uic3tr, 0x001fffff); /* Set Interrupt Trigger Levels */
mtdcr(uic3vr, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(uic3sr, 0xffffffff); /* clear all interrupts */
mtdcr(uic2sr, 0xffffffff); /* Clear all interrupts */
mtdcr(uic2er, 0x00000000); /* disable all interrupts */
mtdcr(uic2cr, 0x00000000); /* Set Critical / Non Critical
* interrupts */
mtdcr(uic2pr, 0xebebebff); /* Set Interrupt Polarities */
mtdcr(uic2tr, 0x74747400); /* Set Interrupt Trigger Levels */
mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(uic2sr, 0xffffffff); /* clear all interrupts */
mtdcr(uic1sr, 0xffffffff); /* Clear all interrupts */
mtdcr(uic1er, 0x00000000); /* disable all interrupts */
mtdcr(uic1cr, 0x00000000); /* Set Critical / Non Critical
* interrupts */
mtdcr(uic1pr, 0xffffffff); /* Set Interrupt Polarities */
mtdcr(uic1tr, 0x001fc0ff); /* Set Interrupt Trigger Levels */
mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(uic1sr, 0xffffffff); /* clear all interrupts */
mtdcr(uic0sr, 0xffffffff); /* Clear all interrupts */
mtdcr(uic0er, 0x00000000); /* disable all interrupts excepted
* cascade to be checked */
mtdcr(uic0cr, 0x00104001); /* Set Critical / Non Critical
* interrupts */
mtdcr(uic0pr, 0xffffffff); /* Set Interrupt Polarities */
mtdcr(uic0tr, 0x000f003c); /* Set Interrupt Trigger Levels */
mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(uic0sr, 0xffffffff); /* clear all interrupts */
}

50
board/amcc/redwood/redwood.h Normal file
View File

@ -0,0 +1,50 @@
/*
* (C) Copyright 2008
* Feng Kan, Applied Micro Circuit Corp., fkan@amcc.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __REDWOOD_H_
#define __REDWOOD_H_
#ifdef __cplusplus
extern "C" {
#endif
/*----------------------------------------------------------------------------+
| Defines
+----------------------------------------------------------------------------*/
/* Pin Straps Reg */
#define SDR0_PSTRP0 0x0040
#define SDR0_PSTRP0_BOOTSTRAP_MASK 0xE0000000 /* Strap Bits */
#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS0 0x00000000 /* Default strap settings 0 */
#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS1 0x20000000 /* Default strap settings 1 */
#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS2 0x40000000 /* Default strap settings 2 */
#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS3 0x60000000 /* Default strap settings 3 */
#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS4 0x80000000 /* Default strap settings 4 */
#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS5 0xA0000000 /* Default strap settings 5 */
#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS6 0xC0000000 /* Default strap settings 6 */
#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS7 0xE0000000 /* Default strap settings 7 */
#ifdef __cplusplus
}
#endif
#endif /* __REDWOOD_H_ */

147
board/amcc/redwood/u-boot.lds Normal file
View File

@ -0,0 +1,147 @@
/*
* (C) Copyright 2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
.resetvec 0xFFFFFFFC :
{
*(.resetvec)
} = 0xffff
.bootpg 0xFFFFF000 :
{
cpu/ppc4xx/start.o (.bootpg)
} = 0xffff
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/ppc4xx/start.o (.text)
board/amcc/redwood/init.o (.text)
/* . = env_offset;*/
/* common/environment.o(.text)*/
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
*(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
_end = . ;
PROVIDE (end = .);
}

10
board/amcc/sequoia/sequoia.c
View File

@ -25,12 +25,11 @@
#include <common.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <ppc440.h>
#include <ppc4xx.h>
#include <asm/gpio.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/bitops.h>
#include <asm/ppc4xx-intvec.h>
DECLARE_GLOBAL_DATA_PTR;
@ -93,6 +92,11 @@ int board_early_init_f(void)
#ifdef CONFIG_I2C_MULTI_BUS
sdr0_pfc1 |= ((sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL);
#endif
/* Two UARTs, so we need 4-pin mode. Also, we want CTS/RTS mode. */
sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_CTS_RTS;
sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_CTS_RTS;
mfsdr(SDR0_PFC2, sdr0_pfc2);
sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
SDR0_PFC2_SELECT_CONFIG_4;
@ -335,7 +339,7 @@ int checkboard(void)
*/
void sequoia_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
{
pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, VECNUM_EIR2);
pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, VECNUM_EIRQ2);
}
#endif

50
board/amcc/taishan/taishan.c
View File

@ -119,36 +119,48 @@ int board_early_init_f (void)
/*--------------------------------------------------------------------
* Setup the interrupt controller polarities, triggers, etc.
*-------------------------------------------------------------------*/
mtdcr (uic0sr, 0xffffffff); /* clear all */
mtdcr (uic0er, 0x00000000); /* disable all */
mtdcr (uic0cr, 0x00000009); /* SMI & UIC1 crit are critical */
mtdcr (uic0pr, 0xfffffe13); /* per ref-board manual */
mtdcr (uic0tr, 0x01c00008); /* per ref-board manual */
mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (uic0sr, 0xffffffff); /* clear all */
/*
* Because of the interrupt handling rework to handle 440GX interrupts
* with the common code, we needed to change names of the UIC registers.
* Here the new relationship:
*
* U-Boot name 440GX name
* -----------------------
* UIC0 UICB0
* UIC1 UIC0
* UIC2 UIC1
* UIC3 UIC2
*/
mtdcr (uic1sr, 0xffffffff); /* clear all */
mtdcr (uic1er, 0x00000000); /* disable all */
mtdcr (uic1cr, 0x00000000); /* all non-critical */
mtdcr (uic1pr, 0xffffe0ff); /* per ref-board manual */
mtdcr (uic1tr, 0x00ffc000); /* per ref-board manual */
mtdcr (uic1cr, 0x00000009); /* SMI & UIC1 crit are critical */
mtdcr (uic1pr, 0xfffffe13); /* per ref-board manual */
mtdcr (uic1tr, 0x01c00008); /* per ref-board manual */
mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (uic1sr, 0xffffffff); /* clear all */
mtdcr (uic2sr, 0xffffffff); /* clear all */
mtdcr (uic2er, 0x00000000); /* disable all */
mtdcr (uic2cr, 0x00000000); /* all non-critical */
mtdcr (uic2pr, 0xffffffff); /* per ref-board manual */
mtdcr (uic2tr, 0x00ff8c0f); /* per ref-board manual */
mtdcr (uic2pr, 0xffffe0ff); /* per ref-board manual */
mtdcr (uic2tr, 0x00ffc000); /* per ref-board manual */
mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (uic2sr, 0xffffffff); /* clear all */
mtdcr (uicb0sr, 0xfc000000); /* clear all */
mtdcr (uicb0er, 0x00000000); /* disable all */
mtdcr (uicb0cr, 0x00000000); /* all non-critical */
mtdcr (uicb0pr, 0xfc000000); /* */
mtdcr (uicb0tr, 0x00000000); /* */
mtdcr (uicb0vr, 0x00000001); /* */
mtdcr (uic3sr, 0xffffffff); /* clear all */
mtdcr (uic3er, 0x00000000); /* disable all */
mtdcr (uic3cr, 0x00000000); /* all non-critical */
mtdcr (uic3pr, 0xffffffff); /* per ref-board manual */
mtdcr (uic3tr, 0x00ff8c0f); /* per ref-board manual */
mtdcr (uic3vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (uic3sr, 0xffffffff); /* clear all */
mtdcr (uic0sr, 0xfc000000); /* clear all */
mtdcr (uic0er, 0x00000000); /* disable all */
mtdcr (uic0cr, 0x00000000); /* all non-critical */
mtdcr (uic0pr, 0xfc000000); /* */
mtdcr (uic0tr, 0x00000000); /* */
mtdcr (uic0vr, 0x00000001); /* */
/* Enable two GPIO 10~11 and TraceA signal */
mfsdr(sdr_pfc0,reg);

62
board/amcc/yucca/yucca.c
View File

@ -677,7 +677,7 @@ int is_pci_host(struct pci_controller *hose)
return 1;
}
int yucca_pcie_card_present(int port)
static int yucca_pcie_card_present(int port)
{
u16 reg;
@ -879,10 +879,6 @@ void pcie_setup_hoses(int busno)
int misc_init_f (void)
{
uint reg;
#if defined(CONFIG_STRESS)
uint i ;
uint disp;
#endif
out16(FPGA_REG10, (in16(FPGA_REG10) &
~(FPGA_REG10_AUTO_NEG_DIS|FPGA_REG10_RESET_ETH)) |
@ -897,67 +893,23 @@ int misc_init_f (void)
/* minimal init for PCIe */
/* pci express 0 Endpoint Mode */
mfsdr(SDR0_PE0DLPSET, reg);
mfsdr(SDRN_PESDR_DLPSET(0), reg);
reg &= (~0x00400000);
mtsdr(SDR0_PE0DLPSET, reg);
mtsdr(SDRN_PESDR_DLPSET(0), reg);
/* pci express 1 Rootpoint Mode */
mfsdr(SDR0_PE1DLPSET, reg);
mfsdr(SDRN_PESDR_DLPSET(1), reg);
reg |= 0x00400000;
mtsdr(SDR0_PE1DLPSET, reg);
mtsdr(SDRN_PESDR_DLPSET(1), reg);
/* pci express 2 Rootpoint Mode */
mfsdr(SDR0_PE2DLPSET, reg);
mfsdr(SDRN_PESDR_DLPSET(2), reg);
reg |= 0x00400000;
mtsdr(SDR0_PE2DLPSET, reg);
mtsdr(SDRN_PESDR_DLPSET(2), reg);
out16(FPGA_REG1C,(in16 (FPGA_REG1C) &
~FPGA_REG1C_PE0_ROOTPOINT &
~FPGA_REG1C_PE1_ENDPOINT &
~FPGA_REG1C_PE2_ENDPOINT));
#if defined(CONFIG_STRESS)
/*
* all this setting done by linux only needed by stress an charac. test
* procedure
* PCIe 1 Rootpoint PCIe2 Endpoint
* PCIe 0 FIR Pre-emphasis Filter Coefficients & Transmit Driver
* Power Level
*/
for (i = 0, disp = 0; i < 8; i++, disp += 3) {
mfsdr(SDR0_PE0HSSSET1L0 + disp, reg);
reg |= 0x33000000;
mtsdr(SDR0_PE0HSSSET1L0 + disp, reg);
}
/*
* PCIe 1 FIR Pre-emphasis Filter Coefficients & Transmit Driver
* Power Level
*/
for (i = 0, disp = 0; i < 4; i++, disp += 3) {
mfsdr(SDR0_PE1HSSSET1L0 + disp, reg);
reg |= 0x33000000;
mtsdr(SDR0_PE1HSSSET1L0 + disp, reg);
}
/*
* PCIE 2 FIR Pre-emphasis Filter Coefficients & Transmit Driver
* Power Level
*/
for (i = 0, disp = 0; i < 4; i++, disp += 3) {
mfsdr(SDR0_PE2HSSSET1L0 + disp, reg);
reg |= 0x33000000;
mtsdr(SDR0_PE2HSSSET1L0 + disp, reg);
}
reg = 0x21242222;
mtsdr(SDR0_PE2UTLSET1, reg);
reg = 0x11000000;
mtsdr(SDR0_PE2UTLSET2, reg);
/* pci express 1 Endpoint Mode */
reg = 0x00004000;
mtsdr(SDR0_PE2DLPSET, reg);
mtsdr(SDR0_UART1, 0x2080005a); /* patch for TG */
#endif
return 0;
}

43
board/bf537-stamp/nand.c
View File

@ -37,34 +37,29 @@
/*
* hardware specific access to control-lines
*/
static void bfin_hwcontrol(struct mtd_info *mtd, int cmd)
static void bfin_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
register struct nand_chip *this = mtd->priv;
u32 IO_ADDR_W = (u32) this->IO_ADDR_W;
switch (cmd) {
case NAND_CTL_SETCLE:
this->IO_ADDR_W = CFG_NAND_BASE + BFIN_NAND_CLE;
break;
case NAND_CTL_CLRCLE:
this->IO_ADDR_W = CFG_NAND_BASE;
break;
case NAND_CTL_SETALE:
this->IO_ADDR_W = CFG_NAND_BASE + BFIN_NAND_ALE;
break;
case NAND_CTL_CLRALE:
this->IO_ADDR_W = CFG_NAND_BASE;
break;
case NAND_CTL_SETNCE:
case NAND_CTL_CLRNCE:
break;
if (ctrl & NAND_CTRL_CHANGE) {
if( ctrl & NAND_CLE )
IO_ADDR_W = CFG_NAND_BASE + BFIN_NAND_CLE;
else
IO_ADDR_W = CFG_NAND_BASE;
if( ctrl & NAND_ALE )
IO_ADDR_W = CFG_NAND_BASE + BFIN_NAND_ALE;
else
IO_ADDR_W = CFG_NAND_BASE;
this->IO_ADDR_W = (void __iomem *) IO_ADDR_W;
}
this->IO_ADDR_R = this->IO_ADDR_W;
/* Drain the writebuffer */
SSYNC();
if (cmd != NAND_CMD_NONE)
writeb(cmd, this->IO_ADDR_W);
}
int bfin_device_ready(struct mtd_info *mtd)
@ -79,11 +74,11 @@ int bfin_device_ready(struct mtd_info *mtd)
* argument are board-specific (per include/linux/mtd/nand.h):
* - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
* - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
* - hwcontrol: hardwarespecific function for accesing control-lines
* - cmd_ctrl: hardwarespecific function for accesing control-lines
* - dev_ready: hardwarespecific function for accesing device ready/busy line
* - enable_hwecc?: function to enable (reset) hardware ecc generator. Must
* only be provided if a hardware ECC is available
* - eccmode: mode of ecc, see defines
* - ecc.mode: mode of ecc, see defines
* - chip_delay: chip dependent delay for transfering data from array to
* read regs (tR)
* - options: various chip options. They can partly be set to inform
@ -98,8 +93,8 @@ void board_nand_init(struct nand_chip *nand)
*PORT(CONFIG_NAND_GPIO_PORT, IO_DIR) &= ~BFIN_NAND_READY;
*PORT(CONFIG_NAND_GPIO_PORT, IO_INEN) |= BFIN_NAND_READY;
nand->hwcontrol = bfin_hwcontrol;
nand->eccmode = NAND_ECC_SOFT;
nand->cmd_ctrl = bfin_hwcontrol;
nand->ecc.mode = NAND_ECC_SOFT;
nand->dev_ready = bfin_device_ready;
nand->chip_delay = 30;
}

49
board/dave/PPChameleonEVB/nand.c
View File

@ -21,7 +21,7 @@
*/
#include <common.h>
#include <asm/io.h>
#if defined(CONFIG_CMD_NAND)
@ -31,31 +31,28 @@
* hardware specific access to control-lines
* function borrowed from Linux 2.6 (drivers/mtd/nand/ppchameleonevb.c)
*/
static void ppchameleonevb_hwcontrol(struct mtd_info *mtdinfo, int cmd)
static void ppchameleonevb_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
struct nand_chip *this = mtdinfo->priv;
struct nand_chip *this = mtd->priv;
ulong base = (ulong) this->IO_ADDR_W;
switch(cmd) {
case NAND_CTL_SETCLE:
MACRO_NAND_CTL_SETCLE((unsigned long)base);
break;
case NAND_CTL_CLRCLE:
MACRO_NAND_CTL_CLRCLE((unsigned long)base);
break;
case NAND_CTL_SETALE:
MACRO_NAND_CTL_SETALE((unsigned long)base);
break;
case NAND_CTL_CLRALE:
MACRO_NAND_CTL_CLRALE((unsigned long)base);
break;
case NAND_CTL_SETNCE:
MACRO_NAND_ENABLE_CE((unsigned long)base);
break;
case NAND_CTL_CLRNCE:
MACRO_NAND_DISABLE_CE((unsigned long)base);
break;
if (ctrl & NAND_CTRL_CHANGE) {
if ( ctrl & NAND_CLE )
MACRO_NAND_CTL_SETCLE((unsigned long)base);
else
MACRO_NAND_CTL_CLRCLE((unsigned long)base);
if ( ctrl & NAND_ALE )
MACRO_NAND_CTL_CLRCLE((unsigned long)base);
else
MACRO_NAND_CTL_CLRALE((unsigned long)base);
if ( ctrl & NAND_NCE )
MACRO_NAND_ENABLE_CE((unsigned long)base);
else
MACRO_NAND_DISABLE_CE((unsigned long)base);
}
if (cmd != NAND_CMD_NONE)
writeb(cmd, this->IO_ADDR_W);
}
@ -92,11 +89,11 @@ static int ppchameleonevb_device_ready(struct mtd_info *mtdinfo)
* argument are board-specific (per include/linux/mtd/nand.h):
* - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
* - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
* - hwcontrol: hardwarespecific function for accesing control-lines
* - cmd_ctrl: hardwarespecific function for accesing control-lines
* - dev_ready: hardwarespecific function for accesing device ready/busy line
* - enable_hwecc?: function to enable (reset) hardware ecc generator. Must
* only be provided if a hardware ECC is available
* - eccmode: mode of ecc, see defines
* - ecc.mode: mode of ecc, see defines
* - chip_delay: chip dependent delay for transfering data from array to
* read regs (tR)
* - options: various chip options. They can partly be set to inform
@ -108,9 +105,9 @@ static int ppchameleonevb_device_ready(struct mtd_info *mtdinfo)
int board_nand_init(struct nand_chip *nand)
{
nand->hwcontrol = ppchameleonevb_hwcontrol;
nand->cmd_ctrl = ppchameleonevb_hwcontrol;
nand->dev_ready = ppchameleonevb_device_ready;
nand->eccmode = NAND_ECC_SOFT;
nand->ecc.mode = NAND_ECC_SOFT;
nand->chip_delay = NAND_BIG_DELAY_US;
nand->options = NAND_SAMSUNG_LP_OPTIONS;
return 0;

43
board/delta/nand.c
View File

@ -23,7 +23,7 @@
#include <common.h>
#if defined(CONFIG_CMD_NAND)
#if !defined(CFG_NAND_LEGACY)
#if !defined(CONFIG_NAND_LEGACY)
#include <nand.h>
#include <asm/arch/pxa-regs.h>
@ -69,7 +69,7 @@ static struct nand_oobinfo delta_oob = {
/*
* not required for Monahans DFC
*/
static void dfc_hwcontrol(struct mtd_info *mtdinfo, int cmd)
static void dfc_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
return;
}
@ -110,30 +110,6 @@ static void dfc_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
}
/*
* These functions are quite problematic for the DFC. Luckily they are
* not used in the current nand code, except for nand_command, which
* we've defined our own anyway. The problem is, that we always need
* to write 4 bytes to the DFC Data Buffer, but in these functions we
* don't know if to buffer the bytes/half words until we've gathered 4
* bytes or if to send them straight away.
*
* Solution: Don't use these with Mona's DFC and complain loudly.
*/
static void dfc_write_word(struct mtd_info *mtd, u16 word)
{
printf("dfc_write_word: WARNING, this function does not work with the Monahans DFC!\n");
}
static void dfc_write_byte(struct mtd_info *mtd, u_char byte)
{
printf("dfc_write_byte: WARNING, this function does not work with the Monahans DFC!\n");
}
/* The original:
* static void dfc_read_buf(struct mtd_info *mtd, const u_char *buf, int len)
*
* Shouldn't this be "u_char * const buf" ?
*/
static void dfc_read_buf(struct mtd_info *mtd, u_char* const buf, int len)
{
int i=0, j;
@ -168,7 +144,7 @@ static void dfc_read_buf(struct mtd_info *mtd, u_char* const buf, int len)
*/
static u16 dfc_read_word(struct mtd_info *mtd)
{
printf("dfc_write_byte: UNIMPLEMENTED.\n");
printf("dfc_read_word: UNIMPLEMENTED.\n");
return 0;
}
@ -289,9 +265,10 @@ static void dfc_new_cmd(void)
/* this function is called after Programm and Erase Operations to
* check for success or failure */
static int dfc_wait(struct mtd_info *mtd, struct nand_chip *this, int state)
static int dfc_wait(struct mtd_info *mtd, struct nand_chip *this)
{
unsigned long ndsr=0, event=0;
int state = this->state;
if(state == FL_WRITING) {
event = NDSR_CS0_CMDD | NDSR_CS0_BBD;
@ -439,7 +416,7 @@ static void dfc_gpio_init(void)
* - dev_ready: hardwarespecific function for accesing device ready/busy line
* - enable_hwecc?: function to enable (reset) hardware ecc generator. Must
* only be provided if a hardware ECC is available
* - eccmode: mode of ecc, see defines
* - ecc.mode: mode of ecc, see defines
* - chip_delay: chip dependent delay for transfering data from array to
* read regs (tR)
* - options: various chip options. They can partly be set to inform
@ -561,20 +538,18 @@ int board_nand_init(struct nand_chip *nand)
/* wait(10); */
nand->hwcontrol = dfc_hwcontrol;
nand->cmd_ctrl = dfc_hwcontrol;
/* nand->dev_ready = dfc_device_ready; */
nand->eccmode = NAND_ECC_SOFT;
nand->ecc.mode = NAND_ECC_SOFT;
nand->options = NAND_BUSWIDTH_16;
nand->waitfunc = dfc_wait;
nand->read_byte = dfc_read_byte;
nand->write_byte = dfc_write_byte;
nand->read_word = dfc_read_word;
nand->write_word = dfc_write_word;
nand->read_buf = dfc_read_buf;
nand->write_buf = dfc_write_buf;
nand->cmdfunc = dfc_cmdfunc;
nand->autooob = &delta_oob;
/* nand->autooob = &delta_oob; */
nand->badblock_pattern = &delta_bbt_descr;
return 0;
}

12
board/esd/common/auto_update.c
View File

@ -27,7 +27,7 @@
#include <command.h>
#include <image.h>
#include <asm/byteorder.h>
#if defined(CFG_NAND_LEGACY)
#if defined(CONFIG_NAND_LEGACY)
#include <linux/mtd/nand_legacy.h>
#endif
#include <fat.h>
@ -58,7 +58,7 @@ extern int flash_sect_erase(ulong, ulong);
extern int flash_sect_protect (int, ulong, ulong);
extern int flash_write (char *, ulong, ulong);
#if defined(CONFIG_CMD_NAND) && defined(CFG_NAND_LEGACY)
#if defined(CONFIG_CMD_NAND) && defined(CONFIG_NAND_LEGACY)
/* references to names in cmd_nand.c */
#define NANDRW_READ 0x01
#define NANDRW_WRITE 0x00
@ -158,7 +158,7 @@ int au_do_update(int i, long sz)
int off, rc;
uint nbytes;
int k;
#if defined(CONFIG_CMD_NAND) && defined(CFG_NAND_LEGACY)
#if defined(CONFIG_CMD_NAND) && defined(CONFIG_NAND_LEGACY)
int total;
#endif
@ -241,7 +241,7 @@ int au_do_update(int i, long sz)
debug ("flash_sect_erase(%lx, %lx);\n", start, end);
flash_sect_erase (start, end);
} else {
#if defined(CONFIG_CMD_NAND) && defined(CFG_NAND_LEGACY)
#if defined(CONFIG_CMD_NAND) && defined(CONFIG_NAND_LEGACY)
printf ("Updating NAND FLASH with image %s\n",
au_image[i].name);
debug ("nand_legacy_erase(%lx, %lx);\n", start, end);
@ -273,7 +273,7 @@ int au_do_update(int i, long sz)
rc = flash_write ((char *)addr, start,
(nbytes + 1) & ~1);
} else {
#if defined(CONFIG_CMD_NAND) && defined(CFG_NAND_LEGACY)
#if defined(CONFIG_CMD_NAND) && defined(CONFIG_NAND_LEGACY)
debug ("nand_legacy_rw(%p, %lx, %x)\n",
addr, start, nbytes);
rc = nand_legacy_rw (nand_dev_desc,
@ -298,7 +298,7 @@ int au_do_update(int i, long sz)
rc = crc32 (0, (uchar *)(start + off),
image_get_data_size (hdr));
} else {
#if defined(CONFIG_CMD_NAND) && defined(CFG_NAND_LEGACY)
#if defined(CONFIG_CMD_NAND) && defined(CONFIG_NAND_LEGACY)
rc = nand_legacy_rw (nand_dev_desc,
NANDRW_READ | NANDRW_JFFS2 |
NANDRW_JFFS2_SKIP,

42
board/esd/common/esd405ep_nand.c
View File

@ -30,28 +30,26 @@
/*
* hardware specific access to control-lines
*/
static void esd405ep_nand_hwcontrol(struct mtd_info *mtdinfo, int cmd)
static void esd405ep_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
switch(cmd) {
case NAND_CTL_SETCLE:
out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_CLE);
break;
case NAND_CTL_CLRCLE:
out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_NAND_CLE);
break;
case NAND_CTL_SETALE:
out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_ALE);
break;
case NAND_CTL_CLRALE:
out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_NAND_ALE);
break;
case NAND_CTL_SETNCE:
out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_NAND_CE);
break;
case NAND_CTL_CLRNCE:
out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_CE);
break;
struct nand_chip *this = mtd->priv;
if (ctrl & NAND_CTRL_CHANGE) {
if ( ctrl & NAND_CLE )
out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_CLE);
else
out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_NAND_CLE);
if ( ctrl & NAND_ALE )
out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_ALE);
else
out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_NAND_ALE);
if ( ctrl & NAND_NCE )
out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_NAND_CE);
else
out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_CE);
}
if (cmd != NAND_CMD_NONE)
writeb(cmd, this->IO_ADDR_W);
}
@ -77,9 +75,9 @@ int board_nand_init(struct nand_chip *nand)
/*
* Initialize nand_chip structure
*/
nand->hwcontrol = esd405ep_nand_hwcontrol;
nand->cmd_ctrl = esd405ep_nand_hwcontrol;
nand->dev_ready = esd405ep_nand_device_ready;
nand->eccmode = NAND_ECC_SOFT;
nand->ecc.mode = NAND_ECC_SOFT;
nand->chip_delay = NAND_BIG_DELAY_US;
nand->options = NAND_SAMSUNG_LP_OPTIONS;
return 0;

42
board/freescale/m5329evb/nand.c
View File

@ -40,36 +40,26 @@ DECLARE_GLOBAL_DATA_PTR;
#define SET_ALE 0x08
#define CLR_ALE ~SET_ALE
static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd)
static void nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
struct nand_chip *this = mtdinfo->priv;
volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
/* volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; TODO: handle wp */
u32 nand_baseaddr = (u32) this->IO_ADDR_W;
switch (cmd) {
case NAND_CTL_SETNCE:
case NAND_CTL_CLRNCE:
break;
case NAND_CTL_SETCLE:
nand_baseaddr |= SET_CLE;
break;
case NAND_CTL_CLRCLE:
nand_baseaddr &= CLR_CLE;
break;
case NAND_CTL_SETALE:
nand_baseaddr |= SET_ALE;
break;
case NAND_CTL_CLRALE:
nand_baseaddr |= CLR_ALE;
break;
case NAND_CTL_SETWP:
fbcs->csmr2 |= FBCS_CSMR_WP;
break;
case NAND_CTL_CLRWP:
fbcs->csmr2 &= ~FBCS_CSMR_WP;
break;
if (ctrl & NAND_CTRL_CHANGE) {
if ( ctrl & NAND_CLE )
nand_baseaddr |= SET_CLE;
else
nand_baseaddr &= CLR_CLE;
if ( ctrl & NAND_ALE )
nand_baseaddr |= SET_ALE;
else
nand_baseaddr &= CLR_ALE;
}
this->IO_ADDR_W = (void __iomem *)(nand_baseaddr);
if (cmd != NAND_CMD_NONE)
writeb(cmd, this->IO_ADDR_W);
}
static void nand_write_byte(struct mtd_info *mtdinfo, u_char byte)
@ -103,8 +93,8 @@ int board_nand_init(struct nand_chip *nand)
gpio->podr_timer = 0;
nand->chip_delay = 50;
nand->eccmode = NAND_ECC_SOFT;
nand->hwcontrol = nand_hwcontrol;
nand->ecc.mode = NAND_ECC_SOFT;
nand->cmd_ctrl = nand_hwcontrol;
nand->read_byte = nand_read_byte;
nand->write_byte = nand_write_byte;
nand->dev_ready = nand_dev_ready;

6
board/freescale/mpc8313erdb/config.mk
View File

@ -1 +1,7 @@
ifndef NAND_SPL
sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
endif
ifndef TEXT_BASE
TEXT_BASE = 0xFE000000
endif

32
board/freescale/mpc8313erdb/mpc8313erdb.c
View File

@ -29,6 +29,8 @@
#include <pci.h>
#include <mpc83xx.h>
#include <vsc7385.h>
#include <ns16550.h>
#include <nand.h>
DECLARE_GLOBAL_DATA_PTR;
@ -50,6 +52,7 @@ int checkboard(void)
return 0;
}
#ifndef CONFIG_NAND_SPL
static struct pci_region pci_regions[] = {
{
bus_start: CFG_PCI1_MEM_BASE,
@ -128,3 +131,32 @@ void ft_board_setup(void *blob, bd_t *bd)
#endif
}
#endif
#else /* CONFIG_NAND_SPL */
void board_init_f(ulong bootflag)
{
board_early_init_f();
NS16550_init((NS16550_t)(CFG_IMMR + 0x4500),
CFG_NS16550_CLK / 16 / CONFIG_BAUDRATE);
puts("NAND boot... ");
init_timebase();
initdram(0);
relocate_code(CFG_NAND_U_BOOT_RELOC + 0x10000, (gd_t *)gd,
CFG_NAND_U_BOOT_RELOC);
}
void board_init_r(gd_t *gd, ulong dest_addr)
{
nand_boot();
}
void putc(char c)
{
if (gd->flags & GD_FLG_SILENT)
return;
if (c == '\n')
NS16550_putc((NS16550_t)(CFG_IMMR + 0x4500), '\r');
NS16550_putc((NS16550_t)(CFG_IMMR + 0x4500), c);
}
#endif

5
board/freescale/mpc8313erdb/sdram.c
View File

@ -58,8 +58,10 @@ static void resume_from_sleep(void)
*/
static long fixed_sdram(void)
{
volatile immap_t *im = (volatile immap_t *)CFG_IMMR;
u32 msize = CFG_DDR_SIZE * 1024 * 1024;
#ifndef CFG_RAMBOOT
volatile immap_t *im = (volatile immap_t *)CFG_IMMR;
u32 msize_log2 = __ilog2(msize);
im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE >> 12;
@ -100,6 +102,7 @@ static long fixed_sdram(void)
/* enable DDR controller */
im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
#endif
return msize;
}

16
board/freescale/mpc8540ads/u-boot.lds
View File

@ -26,6 +26,12 @@
OUTPUT_ARCH(powerpc)
/* Do we need any of these for elf?
__DYNAMIC = 0; */
PHDRS
{
text PT_LOAD;
bss PT_LOAD;
}
SECTIONS
{
/* Read-only sections, merged into text segment: */
@ -57,7 +63,7 @@ SECTIONS
*(.text)
*(.fixup)
*(.got1)
}
} :text
_etext = .;
PROVIDE (etext = .);
.rodata :
@ -66,7 +72,7 @@ SECTIONS
*(.rodata1)
*(.rodata.str1.4)
*(.eh_frame)
}
} :text
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
@ -118,12 +124,12 @@ SECTIONS
.bootpg ADDR(.text) + 0x7f000 :
{
cpu/mpc85xx/start.o (.bootpg)
} = 0xffff
} :text = 0xffff
.resetvec ADDR(.text) + 0x7fffc :
{
*(.resetvec)
} = 0xffff
} :text = 0xffff
. = ADDR(.text) + 0x80000;
@ -134,7 +140,7 @@ SECTIONS
*(.dynbss)
*(.bss)
*(COMMON)
}
} :bss
. = ALIGN(4);
_end = . ;

16
board/freescale/mpc8541cds/u-boot.lds
View File

@ -23,6 +23,12 @@
OUTPUT_ARCH(powerpc)
/* Do we need any of these for elf?
__DYNAMIC = 0; */
PHDRS
{
text PT_LOAD;
bss PT_LOAD;
}
SECTIONS
{
/* Read-only sections, merged into text segment: */
@ -54,7 +60,7 @@ SECTIONS
*(.text)
*(.fixup)
*(.got1)
}
} :text
_etext = .;
PROVIDE (etext = .);
.rodata :
@ -63,7 +69,7 @@ SECTIONS
*(.rodata1)
*(.rodata.str1.4)
*(.eh_frame)
}
} :text
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
@ -115,12 +121,12 @@ SECTIONS
.bootpg ADDR(.text) + 0x7f000 :
{
cpu/mpc85xx/start.o (.bootpg)
} = 0xffff
} :text = 0xffff
.resetvec ADDR(.text) + 0x7fffc :
{
*(.resetvec)
} = 0xffff
} :text = 0xffff
. = ADDR(.text) + 0x80000;
@ -131,7 +137,7 @@ SECTIONS
*(.dynbss)
*(.bss)
*(COMMON)
}
} :bss
. = ALIGN(4);
_end = . ;

16
board/freescale/mpc8544ds/u-boot.lds
View File

@ -23,6 +23,12 @@
OUTPUT_ARCH(powerpc)
/* Do we need any of these for elf?
__DYNAMIC = 0; */
PHDRS
{
text PT_LOAD;
bss PT_LOAD;
}
SECTIONS
{
/* Read-only sections, merged into text segment: */
@ -54,7 +60,7 @@ SECTIONS
*(.text)
*(.fixup)
*(.got1)
}
} :text
_etext = .;
PROVIDE (etext = .);
.rodata :
@ -63,7 +69,7 @@ SECTIONS
*(.rodata1)
*(.rodata.str1.4)
*(.eh_frame)
}
} :text
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
@ -115,12 +121,12 @@ SECTIONS
.bootpg ADDR(.text) + 0x7f000 :
{
cpu/mpc85xx/start.o (.bootpg)
} = 0xffff
} :text = 0xffff
.resetvec ADDR(.text) + 0x7fffc :
{
*(.resetvec)
} = 0xffff
} :text = 0xffff
. = ADDR(.text) + 0x80000;
@ -131,7 +137,7 @@ SECTIONS
*(.dynbss)
*(.bss)
*(COMMON)
}
} :bss
. = ALIGN(4);
_end = . ;

16
board/freescale/mpc8548cds/u-boot.lds
View File

@ -23,6 +23,12 @@
OUTPUT_ARCH(powerpc)
/* Do we need any of these for elf?
__DYNAMIC = 0; */
PHDRS
{
text PT_LOAD;
bss PT_LOAD;
}
SECTIONS
{
/* Read-only sections, merged into text segment: */
@ -54,7 +60,7 @@ SECTIONS
*(.text)
*(.fixup)
*(.got1)
}
} :text
_etext = .;
PROVIDE (etext = .);
.rodata :
@ -63,7 +69,7 @@ SECTIONS
*(.rodata1)
*(.rodata.str1.4)
*(.eh_frame)
}
} :text
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
@ -115,12 +121,12 @@ SECTIONS
.bootpg ADDR(.text) + 0x7f000 :
{
cpu/mpc85xx/start.o (.bootpg)
} = 0xffff
} :text = 0xffff
.resetvec ADDR(.text) + 0x7fffc :
{
*(.resetvec)
} = 0xffff
} :text = 0xffff
. = ADDR(.text) + 0x80000;
@ -131,7 +137,7 @@ SECTIONS
*(.dynbss)
*(.bss)
*(COMMON)
}
} :bss
. = ALIGN(4);
_end = . ;

16
board/freescale/mpc8555cds/u-boot.lds
View File

@ -23,6 +23,12 @@
OUTPUT_ARCH(powerpc)
/* Do we need any of these for elf?
__DYNAMIC = 0; */
PHDRS
{
text PT_LOAD;
bss PT_LOAD;
}
SECTIONS
{
/* Read-only sections, merged into text segment: */
@ -54,7 +60,7 @@ SECTIONS
*(.text)
*(.fixup)
*(.got1)
}
} :text
_etext = .;
PROVIDE (etext = .);
.rodata :
@ -63,7 +69,7 @@ SECTIONS
*(.rodata1)
*(.rodata.str1.4)
*(.eh_frame)
}
} :text
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
@ -115,12 +121,12 @@ SECTIONS
.bootpg ADDR(.text) + 0x7f000 :
{
cpu/mpc85xx/start.o (.bootpg)
} = 0xffff
} :text = 0xffff
.resetvec ADDR(.text) + 0x7fffc :
{
*(.resetvec)
} = 0xffff
} :text = 0xffff
. = ADDR(.text) + 0x80000;
@ -131,7 +137,7 @@ SECTIONS
*(.dynbss)
*(.bss)
*(COMMON)
}
} :bss
. = ALIGN(4);
_end = . ;

16
board/freescale/mpc8560ads/u-boot.lds
View File

@ -26,6 +26,12 @@
OUTPUT_ARCH(powerpc)
/* Do we need any of these for elf?
__DYNAMIC = 0; */
PHDRS
{
text PT_LOAD;
bss PT_LOAD;
}
SECTIONS
{
/* Read-only sections, merged into text segment: */
@ -57,7 +63,7 @@ SECTIONS
*(.text)
*(.fixup)
*(.got1)
}
} :text
_etext = .;
PROVIDE (etext = .);
.rodata :
@ -66,7 +72,7 @@ SECTIONS
*(.rodata1)
*(.rodata.str1.4)
*(.eh_frame)
}
} :text
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
@ -118,12 +124,12 @@ SECTIONS
.bootpg ADDR(.text) + 0x7f000 :
{
cpu/mpc85xx/start.o (.bootpg)
} = 0xffff
} :text = 0xffff
.resetvec ADDR(.text) + 0x7fffc :
{
*(.resetvec)
} = 0xffff
} :text = 0xffff
. = ADDR(.text) + 0x80000;
@ -134,7 +140,7 @@ SECTIONS
*(.dynbss)
*(.bss)
*(COMMON)
}
} :bss
. = ALIGN(4);
_end = . ;

16
board/freescale/mpc8568mds/u-boot.lds
View File

@ -23,6 +23,12 @@
OUTPUT_ARCH(powerpc)
/* Do we need any of these for elf?
__DYNAMIC = 0; */
PHDRS
{
text PT_LOAD;
bss PT_LOAD;
}
SECTIONS
{
/* Read-only sections, merged into text segment: */
@ -54,7 +60,7 @@ SECTIONS
*(.text)
*(.fixup)
*(.got1)
}
} :text
_etext = .;
PROVIDE (etext = .);
.rodata :
@ -63,7 +69,7 @@ SECTIONS
*(.rodata1)
*(.rodata.str1.4)
*(.eh_frame)
}
} :text
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
@ -115,12 +121,12 @@ SECTIONS
.bootpg ADDR(.text) + 0x7f000 :
{
cpu/mpc85xx/start.o (.bootpg)
} = 0xffff
} :text = 0xffff
.resetvec ADDR(.text) + 0x7fffc :
{
*(.resetvec)
} = 0xffff
} :text = 0xffff
. = ADDR(.text) + 0x80000;
@ -131,7 +137,7 @@ SECTIONS
*(.dynbss)
*(.bss)
*(COMMON)
}
} :bss
. = ALIGN(4);
_end = . ;

0
board/mx31ads/Makefile → board/freescale/mx31ads/Makefile
View File

0
board/mx31ads/config.mk → board/freescale/mx31ads/config.mk
View File

0
board/mx31ads/lowlevel_init.S → board/freescale/mx31ads/lowlevel_init.S
View File

16
board/mx31ads/mx31ads.c → board/freescale/mx31ads/mx31ads.c
View File

@ -55,16 +55,16 @@ int board_init (void)
mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
mx31_gpio_mux(MUX_RTS1__UART1_CTS_B);
mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
/* SPI2 */
mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_SS2);
mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_SCLK);
mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_SPI_RDY);
mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_MOSI);
mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_MISO);
mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_SS0);
mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_SS1);
mx31_gpio_mux(MUX_CSPI2_SS2__CSPI2_SS2_B);
mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK);
mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B);
mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI);
mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO);
mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B);
mx31_gpio_mux(MUX_CSPI2_SS1__CSPI2_SS1_B);
/* start SPI2 clock */
__REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 4);

10
board/mx31ads/u-boot.lds → board/freescale/mx31ads/u-boot.lds
View File

@ -37,11 +37,11 @@ SECTIONS
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/arm1136/start.o (.text)
board/mx31ads/libmx31ads.a (.text)
lib_arm/libarm.a (.text)
net/libnet.a (.text)
drivers/mtd/libmtd.a (.text)
cpu/arm1136/start.o (.text)
board/freescale/mx31ads/libmx31ads.a (.text)
lib_arm/libarm.a (.text)
net/libnet.a (.text)
drivers/mtd/libmtd.a (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/environment.o(.text)

4
board/icecube/flash.c
View File

@ -23,7 +23,7 @@
#include <common.h>
#ifndef CFG_FLASH_CFI_DRIVER
#ifndef CONFIG_FLASH_CFI_DRIVER
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
/* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it
@ -490,4 +490,4 @@ static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data)
return (res);
}
#endif /*CFG_FLASH_CFI_DRIVER*/
#endif /*CONFIG_FLASH_CFI_DRIVER*/

16
board/imx31_litekit/imx31_litekit.c
View File

@ -50,16 +50,16 @@ int board_init (void)
mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
mx31_gpio_mux(MUX_RTS1__UART1_CTS_B);
mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
/* SPI2 */
mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_SS2);
mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_SCLK);
mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_SPI_RDY);
mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_MOSI);
mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_MISO);
mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_SS0);
mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_SS1);
mx31_gpio_mux(MUX_CSPI2_SS2__CSPI2_SS2_B);
mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK);
mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B);
mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI);
mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO);
mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B);
mx31_gpio_mux(MUX_CSPI2_SS1__CSPI2_SS1_B);
/* start SPI2 clock */
__REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 4);

4
board/imx31_phycore/imx31_phycore.c
View File

@ -54,11 +54,11 @@ int board_init (void)
mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
mx31_gpio_mux(MUX_RTS1__UART1_CTS_B);
mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
/* setup pins for I2C2 (for EEPROM, RTC) */
mx31_gpio_mux(MUX_CSPI2_MOSI__I2C2_SCL);
mx31_gpio_mux(MUX_CSPI2_MISO__I2C2_SCL);
mx31_gpio_mux(MUX_CSPI2_MISO__I2C2_SDA);
gd->bd->bi_arch_number = 447; /* board id for linux */
gd->bd->bi_boot_params = (0x80000100); /* adress of boot parameters */

4
board/korat/korat.c
View File

@ -33,7 +33,7 @@
#include <asm/bitops.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/ppc4xx-intvec.h>
#include <asm/ppc4xx-uic.h>
#include <asm/processor.h>
DECLARE_GLOBAL_DATA_PTR;
@ -575,7 +575,7 @@ int checkboard(void)
*/
void korat_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
{
pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, VECNUM_EIR2);
pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, VECNUM_EIRQ2);
}
#endif

78
board/nc650/nand.c
View File

@ -22,7 +22,7 @@
*/
#include <common.h>
#include <asm/io.h>
#if defined(CONFIG_CMD_NAND)
@ -32,57 +32,49 @@
/*
* hardware specific access to control-lines
*/
static void nc650_hwcontrol(struct mtd_info *mtd, int cmd)
static void nc650_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
struct nand_chip *this = mtd->priv;
switch(cmd) {
case NAND_CTL_SETCLE:
this->IO_ADDR_W += 2;
break;
case NAND_CTL_CLRCLE:
this->IO_ADDR_W -= 2;
break;
case NAND_CTL_SETALE:
this->IO_ADDR_W += 1;
break;
case NAND_CTL_CLRALE:
this->IO_ADDR_W -= 1;
break;
case NAND_CTL_SETNCE:
case NAND_CTL_CLRNCE:
/* nop */
break;
if (ctrl & NAND_CTRL_CHANGE) {
if ( ctrl & NAND_CLE )
this->IO_ADDR_W += 2;
else
this->IO_ADDR_W -= 2;
if ( ctrl & NAND_ALE )
this->IO_ADDR_W += 1;
else
this->IO_ADDR_W -= 1;
}
if (cmd != NAND_CMD_NONE)
writeb(cmd, this->IO_ADDR_W);
}
#elif defined(CONFIG_IDS852_REV2)
/*
* hardware specific access to control-lines
*/
static void nc650_hwcontrol(struct mtd_info *mtd, int cmd)
static void nc650_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
struct nand_chip *this = mtd->priv;
switch(cmd) {
case NAND_CTL_SETCLE:
*(((volatile __u8 *) this->IO_ADDR_W) + 0xa) = 0;
break;
case NAND_CTL_CLRCLE:
*(((volatile __u8 *) this->IO_ADDR_W) + 0x8) = 0;
break;
case NAND_CTL_SETALE:
*(((volatile __u8 *) this->IO_ADDR_W) + 0x9) = 0;
break;
case NAND_CTL_CLRALE:
*(((volatile __u8 *) this->IO_ADDR_W) + 0x8) = 0;
break;
case NAND_CTL_SETNCE:
*(((volatile __u8 *) this->IO_ADDR_W) + 0x8) = 0;
break;
case NAND_CTL_CLRNCE:
*(((volatile __u8 *) this->IO_ADDR_W) + 0xc) = 0;
break;
if (ctrl & NAND_CTRL_CHANGE) {
if ( ctrl & NAND_CLE )
writeb(0, (volatile __u8 *) this->IO_ADDR_W + 0xa);
else
writeb(0, (volatile __u8 *) this->IO_ADDR_W) + 0x8);
if ( ctrl & NAND_ALE )
writeb(0, (volatile __u8 *) this->IO_ADDR_W) + 0x9);
else
writeb(0, (volatile __u8 *) this->IO_ADDR_W) + 0x8);
if ( ctrl & NAND_NCE )
writeb(0, (volatile __u8 *) this->IO_ADDR_W) + 0x8);
else
writeb(0, (volatile __u8 *) this->IO_ADDR_W) + 0xc);
}
if (cmd != NAND_CMD_NONE)
writeb(cmd, this->IO_ADDR_W);
}
#else
#error Unknown IDS852 module revision
@ -93,11 +85,11 @@ static void nc650_hwcontrol(struct mtd_info *mtd, int cmd)
* argument are board-specific (per include/linux/mtd/nand.h):
* - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
* - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
* - hwcontrol: hardwarespecific function for accesing control-lines
* - cmd_ctrl: hardwarespecific function for accesing control-lines
* - dev_ready: hardwarespecific function for accesing device ready/busy line
* - enable_hwecc?: function to enable (reset) hardware ecc generator. Must
* only be provided if a hardware ECC is available
* - eccmode: mode of ecc, see defines
* - eccm.ode: mode of ecc, see defines
* - chip_delay: chip dependent delay for transfering data from array to
* read regs (tR)
* - options: various chip options. They can partly be set to inform
@ -109,8 +101,8 @@ static void nc650_hwcontrol(struct mtd_info *mtd, int cmd)
int board_nand_init(struct nand_chip *nand)
{
nand->hwcontrol = nc650_hwcontrol;
nand->eccmode = NAND_ECC_SOFT;
nand->cmd_ctrl = nc650_hwcontrol;
nand->ecc.mode = NAND_ECC_SOFT;
nand->chip_delay = 12;
/* nand->options = NAND_SAMSUNG_LP_OPTIONS;*/
return 0;

20
board/netstar/nand.c
View File

@ -21,6 +21,7 @@
*/
#include <common.h>
#include <asm/io.h>
#if defined(CONFIG_CMD_NAND)
@ -32,24 +33,29 @@
#define MASK_CLE 0x02
#define MASK_ALE 0x04
static void netstar_nand_hwcontrol(struct mtd_info *mtd, int cmd)
static void netstar_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
struct nand_chip *this = mtd->priv;
ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);
switch (cmd) {
case NAND_CTL_SETCLE: IO_ADDR_W |= MASK_CLE; break;
case NAND_CTL_SETALE: IO_ADDR_W |= MASK_ALE; break;
if (ctrl & NAND_CTRL_CHANGE) {
if ( ctrl & NAND_CLE )
IO_ADDR_W |= MASK_CLE;
if ( ctrl & NAND_ALE )
IO_ADDR_W |= MASK_ALE;
}
this->IO_ADDR_W = (void *) IO_ADDR_W;
this->IO_ADDR_W = (void __iomem *) IO_ADDR_W;
if (cmd != NAND_CMD_NONE)
writeb(cmd, this->IO_ADDR_W);
}
int board_nand_init(struct nand_chip *nand)
{
nand->options = NAND_SAMSUNG_LP_OPTIONS;
nand->eccmode = NAND_ECC_SOFT;
nand->hwcontrol = netstar_nand_hwcontrol;
nand->ecc.mode = NAND_ECC_SOFT;
nand->cmd_ctrl = netstar_nand_hwcontrol;
nand->chip_delay = 400;
return 0;
}

2
board/netta/netta.c
View File

@ -555,7 +555,7 @@ int board_early_init_f(void)
return 0;
}
#if defined(CONFIG_CMD_NAND) && defined(CFG_NAND_LEGACY)
#if defined(CONFIG_CMD_NAND) && defined(CONFIG_NAND_LEGACY)
#include <linux/mtd/nand_legacy.h>

50
board/prodrive/alpr/alpr.c
View File

@ -48,36 +48,48 @@ int board_early_init_f (void)
/*--------------------------------------------------------------------
* Setup the interrupt controller polarities, triggers, etc.
*-------------------------------------------------------------------*/
mtdcr (uic0sr, 0xffffffff); /* clear all */
mtdcr (uic0er, 0x00000000); /* disable all */
mtdcr (uic0cr, 0x00000009); /* SMI & UIC1 crit are critical */
mtdcr (uic0pr, 0xfffffe03); /* per manual */
mtdcr (uic0tr, 0x01c00000); /* per manual */
mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (uic0sr, 0xffffffff); /* clear all */
/*
* Because of the interrupt handling rework to handle 440GX interrupts
* with the common code, we needed to change names of the UIC registers.
* Here the new relationship:
*
* U-Boot name 440GX name
* -----------------------
* UIC0 UICB0
* UIC1 UIC0
* UIC2 UIC1
* UIC3 UIC2
*/
mtdcr (uic1sr, 0xffffffff); /* clear all */
mtdcr (uic1er, 0x00000000); /* disable all */
mtdcr (uic1cr, 0x00000000); /* all non-critical */
mtdcr (uic1pr, 0xffffe0ff); /* per ref-board manual */
mtdcr (uic1tr, 0x00ffc000); /* per ref-board manual */
mtdcr (uic1cr, 0x00000009); /* SMI & UIC1 crit are critical */
mtdcr (uic1pr, 0xfffffe03); /* per manual */
mtdcr (uic1tr, 0x01c00000); /* per manual */
mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (uic1sr, 0xffffffff); /* clear all */
mtdcr (uic2sr, 0xffffffff); /* clear all */
mtdcr (uic2er, 0x00000000); /* disable all */
mtdcr (uic2cr, 0x00000000); /* all non-critical */
mtdcr (uic2pr, 0xffffffff); /* per ref-board manual */
mtdcr (uic2tr, 0x00ff8c0f); /* per ref-board manual */
mtdcr (uic2pr, 0xffffe0ff); /* per ref-board manual */
mtdcr (uic2tr, 0x00ffc000); /* per ref-board manual */
mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (uic2sr, 0xffffffff); /* clear all */
mtdcr (uicb0sr, 0xfc000000); /* clear all */
mtdcr (uicb0er, 0x00000000); /* disable all */
mtdcr (uicb0cr, 0x00000000); /* all non-critical */
mtdcr (uicb0pr, 0xfc000000); /* */
mtdcr (uicb0tr, 0x00000000); /* */
mtdcr (uicb0vr, 0x00000001); /* */
mtdcr (uic3sr, 0xffffffff); /* clear all */
mtdcr (uic3er, 0x00000000); /* disable all */
mtdcr (uic3cr, 0x00000000); /* all non-critical */
mtdcr (uic3pr, 0xffffffff); /* per ref-board manual */
mtdcr (uic3tr, 0x00ff8c0f); /* per ref-board manual */
mtdcr (uic3vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (uic3sr, 0xffffffff); /* clear all */
mtdcr (uic0sr, 0xfc000000); /* clear all */
mtdcr (uic0er, 0x00000000); /* disable all */
mtdcr (uic0cr, 0x00000000); /* all non-critical */
mtdcr (uic0pr, 0xfc000000); /* */
mtdcr (uic0tr, 0x00000000); /* */
mtdcr (uic0vr, 0x00000001); /* */
/* Setup shutdown/SSD empty interrupt as inputs */
out32(GPIO0_TCR, in32(GPIO0_TCR) & ~(CFG_GPIO_SHUTDOWN | CFG_GPIO_SSD_EMPTY));

57
board/prodrive/alpr/nand.c
View File

@ -56,43 +56,24 @@ static struct alpr_ndfc_regs *alpr_ndfc = NULL;
*
* There are 2 NAND devices on the board, a Hynix HY27US08561A (1 GByte).
*/
static void alpr_nand_hwcontrol(struct mtd_info *mtd, int cmd)
static void alpr_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
switch (cmd) {
case NAND_CTL_SETCLE:
hwctl |= 0x1;
break;
case NAND_CTL_CLRCLE:
hwctl &= ~0x1;
break;
case NAND_CTL_SETALE:
hwctl |= 0x2;
break;
case NAND_CTL_CLRALE:
hwctl &= ~0x2;
break;
case NAND_CTL_SETNCE:
break;
case NAND_CTL_CLRNCE:
writeb(0x00, &(alpr_ndfc->term));
break;
struct nand_chip *this = mtd->priv;
if (ctrl & NAND_CTRL_CHANGE) {
if ( ctrl & NAND_CLE )
hwctl |= 0x1;
else
hwctl &= ~0x1;
if ( ctrl & NAND_ALE )
hwctl |= 0x2;
else
hwctl &= ~0x2;
if ( (ctrl & NAND_NCE) != NAND_NCE)
writeb(0x00, &(alpr_ndfc->term));
}
}
static void alpr_nand_write_byte(struct mtd_info *mtd, u_char byte)
{
struct nand_chip *nand = mtd->priv;
if (hwctl & 0x1)
/*
* IO_ADDR_W used as CMD[i] reg to support multiple NAND
* chips.
*/
writeb(byte, nand->IO_ADDR_W);
else if (hwctl & 0x2) {
writeb(byte, &(alpr_ndfc->addr_wait));
} else
writeb(byte, &(alpr_ndfc->data));
if (cmd != NAND_CMD_NONE)
writeb(cmd, this->IO_ADDR_W);
}
static u_char alpr_nand_read_byte(struct mtd_info *mtd)
@ -158,12 +139,10 @@ int board_nand_init(struct nand_chip *nand)
{
alpr_ndfc = (struct alpr_ndfc_regs *)CFG_NAND_BASE;
nand->eccmode = NAND_ECC_SOFT;
nand->ecc.mode = NAND_ECC_SOFT;
/* Reference hardware control function */
nand->hwcontrol = alpr_nand_hwcontrol;
/* Set command delay time */
nand->write_byte = alpr_nand_write_byte;
nand->cmd_ctrl = alpr_nand_hwcontrol;
nand->read_byte = alpr_nand_read_byte;
nand->write_buf = alpr_nand_write_buf;
nand->read_buf = alpr_nand_read_buf;

4
board/prodrive/pdnb3/flash.c
View File

@ -24,7 +24,7 @@
#include <common.h>
#include <asm/arch/ixp425.h>
#if !defined(CFG_FLASH_CFI_DRIVER)
#if !defined(CONFIG_FLASH_CFI_DRIVER)
/*
* include common flash code (for esd boards)
@ -86,4 +86,4 @@ unsigned long flash_init(void)
return size;
}
#endif /* CFG_FLASH_CFI_DRIVER */
#endif /* CONFIG_FLASH_CFI_DRIVER */

51
board/prodrive/pdnb3/nand.c
View File

@ -52,40 +52,26 @@ static struct pdnb3_ndfc_regs *pdnb3_ndfc;
*
* There is one NAND devices on the board, a Hynix HY27US08561A (32 MByte).
*/
static void pdnb3_nand_hwcontrol(struct mtd_info *mtd, int cmd)
static void pdnb3_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
switch (cmd) {
case NAND_CTL_SETCLE:
hwctl |= 0x1;
break;
case NAND_CTL_CLRCLE:
hwctl &= ~0x1;
break;
struct nand_chip *this = mtd->priv;
case NAND_CTL_SETALE:
hwctl |= 0x2;
break;
case NAND_CTL_CLRALE:
hwctl &= ~0x2;
break;
case NAND_CTL_SETNCE:
break;
case NAND_CTL_CLRNCE:
writeb(0x00, &(pdnb3_ndfc->term));
break;
if (ctrl & NAND_CTRL_CHANGE) {
if ( ctrl & NAND_CLE )
hwctl |= 0x1;
else
hwctl &= ~0x1;
if ( ctrl & NAND_ALE )
hwctl |= 0x2;
else
hwctl &= ~0x2;
if ( (ctrl & NAND_NCE) != NAND_NCE)
writeb(0x00, &(pdnb3_ndfc->term));
}
if (cmd != NAND_CMD_NONE)
writeb(cmd, this->IO_ADDR_W);
}
static void pdnb3_nand_write_byte(struct mtd_info *mtd, u_char byte)
{
if (hwctl & 0x1)
writeb(byte, &(pdnb3_ndfc->cmd));
else if (hwctl & 0x2)
writeb(byte, &(pdnb3_ndfc->addr));
else
writeb(byte, &(pdnb3_ndfc->data));
}
static u_char pdnb3_nand_read_byte(struct mtd_info *mtd)
{
@ -152,16 +138,13 @@ int board_nand_init(struct nand_chip *nand)
{
pdnb3_ndfc = (struct pdnb3_ndfc_regs *)CFG_NAND_BASE;
nand->eccmode = NAND_ECC_SOFT;
nand->ecc.mode = NAND_ECC_SOFT;
/* Set address of NAND IO lines (Using Linear Data Access Region) */
nand->IO_ADDR_R = (void __iomem *) ((ulong) pdnb3_ndfc + 0x4);
nand->IO_ADDR_W = (void __iomem *) ((ulong) pdnb3_ndfc + 0x4);
/* Reference hardware control function */
nand->hwcontrol = pdnb3_nand_hwcontrol;
/* Set command delay time */
nand->hwcontrol = pdnb3_nand_hwcontrol;
nand->write_byte = pdnb3_nand_write_byte;
nand->cmd_ctrl = pdnb3_nand_hwcontrol;
nand->read_byte = pdnb3_nand_read_byte;
nand->write_buf = pdnb3_nand_write_buf;
nand->read_buf = pdnb3_nand_read_buf;

50
board/sandburst/karef/karef.c
View File

@ -195,36 +195,48 @@ int board_early_init_f (void)
/*--------------------------------------------------------------------+
* Setup the interrupt controller polarities, triggers, etc.
+-------------------------------------------------------------------*/
mtdcr (uic0sr, 0xffffffff); /* clear all */
mtdcr (uic0er, 0x00000000); /* disable all */
mtdcr (uic0cr, 0x00000000); /* all non- critical */
mtdcr (uic0pr, 0xfffffe03); /* polarity */
mtdcr (uic0tr, 0x01c00000); /* trigger edge vs level */
mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (uic0sr, 0xffffffff); /* clear all */
/*
* Because of the interrupt handling rework to handle 440GX interrupts
* with the common code, we needed to change names of the UIC registers.
* Here the new relationship:
*
* U-Boot name 440GX name
* -----------------------
* UIC0 UICB0
* UIC1 UIC0
* UIC2 UIC1
* UIC3 UIC2
*/
mtdcr (uic1sr, 0xffffffff); /* clear all */
mtdcr (uic1er, 0x00000000); /* disable all */
mtdcr (uic1cr, 0x00000000); /* all non-critical */
mtdcr (uic1pr, 0xffffc8ff); /* polarity */
mtdcr (uic1tr, 0x00ff0000); /* trigger edge vs level */
mtdcr (uic1cr, 0x00000000); /* all non- critical */
mtdcr (uic1pr, 0xfffffe03); /* polarity */
mtdcr (uic1tr, 0x01c00000); /* trigger edge vs level */
mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (uic1sr, 0xffffffff); /* clear all */
mtdcr (uic2sr, 0xffffffff); /* clear all */
mtdcr (uic2er, 0x00000000); /* disable all */
mtdcr (uic2cr, 0x00000000); /* all non-critical */
mtdcr (uic2pr, 0xffff83ff); /* polarity */
mtdcr (uic2tr, 0x00ff8c0f); /* trigger edge vs level */
mtdcr (uic2pr, 0xffffc8ff); /* polarity */
mtdcr (uic2tr, 0x00ff0000); /* trigger edge vs level */
mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (uic2sr, 0xffffffff); /* clear all */
mtdcr (uicb0sr, 0xfc000000); /* clear all */
mtdcr (uicb0er, 0x00000000); /* disable all */
mtdcr (uicb0cr, 0x00000000); /* all non-critical */
mtdcr (uicb0pr, 0xfc000000);
mtdcr (uicb0tr, 0x00000000);
mtdcr (uicb0vr, 0x00000001);
mtdcr (uic3sr, 0xffffffff); /* clear all */
mtdcr (uic3er, 0x00000000); /* disable all */
mtdcr (uic3cr, 0x00000000); /* all non-critical */
mtdcr (uic3pr, 0xffff83ff); /* polarity */
mtdcr (uic3tr, 0x00ff8c0f); /* trigger edge vs level */
mtdcr (uic3vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (uic3sr, 0xffffffff); /* clear all */
mtdcr (uic0sr, 0xfc000000); /* clear all */
mtdcr (uic0er, 0x00000000); /* disable all */
mtdcr (uic0cr, 0x00000000); /* all non-critical */
mtdcr (uic0pr, 0xfc000000);
mtdcr (uic0tr, 0x00000000);
mtdcr (uic0vr, 0x00000001);
fpga_init();

50
board/sandburst/metrobox/metrobox.c
View File

@ -185,36 +185,48 @@ int board_early_init_f (void)
/*--------------------------------------------------------------------+
* Setup the interrupt controller polarities, triggers, etc.
+-------------------------------------------------------------------*/
mtdcr (uic0sr, 0xffffffff); /* clear all */
mtdcr (uic0er, 0x00000000); /* disable all */
mtdcr (uic0cr, 0x00000000); /* all non- critical */
mtdcr (uic0pr, 0xfffffe03); /* polarity */
mtdcr (uic0tr, 0x01c00000); /* trigger edge vs level */
mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (uic0sr, 0xffffffff); /* clear all */
/*
* Because of the interrupt handling rework to handle 440GX interrupts
* with the common code, we needed to change names of the UIC registers.
* Here the new relationship:
*
* U-Boot name 440GX name
* -----------------------
* UIC0 UICB0
* UIC1 UIC0
* UIC2 UIC1
* UIC3 UIC2
*/
mtdcr (uic1sr, 0xffffffff); /* clear all */
mtdcr (uic1er, 0x00000000); /* disable all */
mtdcr (uic1cr, 0x00000000); /* all non-critical */
mtdcr (uic1pr, 0xffffc8ff); /* polarity */
mtdcr (uic1tr, 0x00ff0000); /* trigger edge vs level */
mtdcr (uic1cr, 0x00000000); /* all non- critical */
mtdcr (uic1pr, 0xfffffe03); /* polarity */
mtdcr (uic1tr, 0x01c00000); /* trigger edge vs level */
mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (uic1sr, 0xffffffff); /* clear all */
mtdcr (uic2sr, 0xffffffff); /* clear all */
mtdcr (uic2er, 0x00000000); /* disable all */
mtdcr (uic2cr, 0x00000000); /* all non-critical */
mtdcr (uic2pr, 0xffff83ff); /* polarity */
mtdcr (uic2tr, 0x00ff8c0f); /* trigger edge vs level */
mtdcr (uic2pr, 0xffffc8ff); /* polarity */
mtdcr (uic2tr, 0x00ff0000); /* trigger edge vs level */
mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (uic2sr, 0xffffffff); /* clear all */
mtdcr (uicb0sr, 0xfc000000); /* clear all */
mtdcr (uicb0er, 0x00000000); /* disable all */
mtdcr (uicb0cr, 0x00000000); /* all non-critical */
mtdcr (uicb0pr, 0xfc000000);
mtdcr (uicb0tr, 0x00000000);
mtdcr (uicb0vr, 0x00000001);
mtdcr (uic3sr, 0xffffffff); /* clear all */
mtdcr (uic3er, 0x00000000); /* disable all */
mtdcr (uic3cr, 0x00000000); /* all non-critical */
mtdcr (uic3pr, 0xffff83ff); /* polarity */
mtdcr (uic3tr, 0x00ff8c0f); /* trigger edge vs level */
mtdcr (uic3vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (uic3sr, 0xffffffff); /* clear all */
mtdcr (uic0sr, 0xfc000000); /* clear all */
mtdcr (uic0er, 0x00000000); /* disable all */
mtdcr (uic0cr, 0x00000000); /* all non-critical */
mtdcr (uic0pr, 0xfc000000);
mtdcr (uic0tr, 0x00000000);
mtdcr (uic0vr, 0x00000001);
fpga_init();

44
board/sc3/sc3nand.c
View File

@ -39,30 +39,26 @@
static void *sc3_io_base;
static void *sc3_control_base = (void *)0xEF600700;
static void sc3_nand_hwcontrol(struct mtd_info *mtd, int cmd)
static void sc3_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
switch (cmd) {
case NAND_CTL_SETCLE:
set_bit (SC3_NAND_CLE, sc3_control_base);
break;
case NAND_CTL_CLRCLE:
clear_bit (SC3_NAND_CLE, sc3_control_base);
break;
case NAND_CTL_SETALE:
set_bit (SC3_NAND_ALE, sc3_control_base);
break;
case NAND_CTL_CLRALE:
clear_bit (SC3_NAND_ALE, sc3_control_base);
break;
case NAND_CTL_SETNCE:
set_bit (SC3_NAND_CE, sc3_control_base);
break;
case NAND_CTL_CLRNCE:
clear_bit (SC3_NAND_CE, sc3_control_base);
break;
struct nand_chip *this = mtd->priv;
if (ctrl & NAND_CTRL_CHANGE) {
if ( ctrl & NAND_CLE )
set_bit (SC3_NAND_CLE, sc3_control_base);
else
clear_bit (SC3_NAND_CLE, sc3_control_base);
if ( ctrl & NAND_ALE )
set_bit (SC3_NAND_ALE, sc3_control_base);
else
clear_bit (SC3_NAND_ALE, sc3_control_base);
if ( ctrl & NAND_NCE )
set_bit (SC3_NAND_CE, sc3_control_base);
else
clear_bit (SC3_NAND_CE, sc3_control_base);
}
if (cmd != NAND_CMD_NONE)
writeb(cmd, this->IO_ADDR_W);
}
static int sc3_nand_dev_ready(struct mtd_info *mtd)
@ -79,14 +75,14 @@ static void sc3_select_chip(struct mtd_info *mtd, int chip)
int board_nand_init(struct nand_chip *nand)
{
nand->eccmode = NAND_ECC_SOFT;
nand->ecc.mode = NAND_ECC_SOFT;
sc3_io_base = (void *) CFG_NAND_BASE;
/* Set address of NAND IO lines (Using Linear Data Access Region) */
nand->IO_ADDR_R = (void __iomem *) sc3_io_base;
nand->IO_ADDR_W = (void __iomem *) sc3_io_base;
/* Reference hardware control function */
nand->hwcontrol = sc3_nand_hwcontrol;
nand->cmd_ctrl = sc3_nand_hwcontrol;
nand->dev_ready = sc3_nand_dev_ready;
nand->select_chip = sc3_select_chip;
return 0;

32
board/tqc/tqm8272/tqm8272.c
View File

@ -1068,24 +1068,22 @@ int update_flash_size (int flash_size)
static u8 hwctl = 0;
static void upmnand_hwcontrol(struct mtd_info *mtdinfo, int cmd)
static void upmnand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
switch (cmd) {
case NAND_CTL_SETCLE:
hwctl |= 0x1;
break;
case NAND_CTL_CLRCLE:
hwctl &= ~0x1;
break;
struct nand_chip *this = mtd->priv;
case NAND_CTL_SETALE:
hwctl |= 0x2;
break;
case NAND_CTL_CLRALE:
hwctl &= ~0x2;
break;
if (ctrl & NAND_CTRL_CHANGE) {
if ( ctrl & NAND_CLE )
hwctl |= 0x1;
else
hwctl &= ~0x1;
if ( ctrl & NAND_ALE )
hwctl |= 0x2;
else
hwctl &= ~0x2;
}
if (cmd != NAND_CMD_NONE)
writeb(cmd, this->IO_ADDR_W);
}
static void upmnand_write_byte(struct mtd_info *mtdinfo, u_char byte)
@ -1188,9 +1186,9 @@ int board_nand_init(struct nand_chip *nand)
memctl->memc_br3 = CFG_NAND_BR;
memctl->memc_mbmr = (MxMR_OP_NORM);
nand->eccmode = NAND_ECC_SOFT;
nand->ecc.mode = NAND_ECC_SOFT;
nand->hwcontrol = upmnand_hwcontrol;
nand->cmd_ctrl = upmnand_hwcontrol;
nand->read_byte = upmnand_read_byte;
nand->write_byte = upmnand_write_byte;
nand->dev_ready = tqm8272_dev_ready;

4
board/tqc/tqm8xx/flash.c
View File

@ -33,7 +33,7 @@
DECLARE_GLOBAL_DATA_PTR;
#if !defined(CFG_FLASH_CFI_DRIVER) /* do not use if CFI driver is configured */
#if !defined(CONFIG_FLASH_CFI_DRIVER) /* do not use if CFI driver is configured */
#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) \
&& !defined(CONFIG_TQM885D)
@ -831,4 +831,4 @@ static int write_word (flash_info_t *info, ulong dest, ulong data)
/*-----------------------------------------------------------------------
*/
#endif /* !defined(CFG_FLASH_CFI_DRIVER) */
#endif /* !defined(CONFIG_FLASH_CFI_DRIVER) */

58
board/xilinx/ml507/Makefile Normal file
View File

@ -0,0 +1,58 @@
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
ifneq ($(OBJTREE),$(SRCTREE))
endif
INCS :=
CFLAGS += $(INCS)
HOST_CFLAGS += $(INCS)
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o
SOBJS = init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $^
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

27
board/xilinx/ml507/config.mk Normal file
View File

@ -0,0 +1,27 @@
#
# (C) Copyright 2000
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
ifndef TEXT_BASE
TEXT_BASE = 0x04000000
endif

53
board/xilinx/ml507/init.S Normal file
View File

@ -0,0 +1,53 @@
/*
* (C) Copyright 2008
* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
* This work has been supported by: QTechnology http://qtec.com/
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <ppc_asm.tmpl>
#include <config.h>
#include <asm-ppc/mmu.h>
.section .bootpg,"ax"
.globl tlbtab
tlbtab:
tlbtab_start
/* SDRAM */
tlbentry(XPAR_DDR2_SDRAM_MEM_BASEADDR, SZ_256M, CFG_SDRAM_BASE, 0,
AC_R | AC_W | AC_X | SA_G | SA_I)
/* UART */
tlbentry(XPAR_UARTLITE_0_BASEADDR, SZ_64K, XPAR_UARTLITE_0_BASEADDR, 0,
AC_R | AC_W | SA_G | SA_I)
/* PIC */
tlbentry(XPAR_INTC_0_BASEADDR, SZ_64K, XPAR_INTC_0_BASEADDR, 0,
AC_R | AC_W | SA_G | SA_I)
#ifdef XPAR_IIC_EEPROM_BASEADDR
/* I2C */
tlbentry(XPAR_IIC_EEPROM_BASEADDR, SZ_64K, XPAR_IIC_EEPROM_BASEADDR, 0,
AC_R | AC_W | SA_G | SA_I)
#endif
#ifdef XPAR_LLTEMAC_0_BASEADDR
/* Net */
tlbentry(XPAR_LLTEMAC_0_BASEADDR, SZ_64K, XPAR_LLTEMAC_0_BASEADDR, 0,
AC_R | AC_W | SA_G | SA_I)
#endif
#ifdef XPAR_FLASH_MEM0_BASEADDR
/*Flash*/
tlbentry(XPAR_FLASH_MEM0_BASEADDR, SZ_256M, XPAR_FLASH_MEM0_BASEADDR, 0,
AC_R | AC_W | AC_X | SA_G | SA_I)
#endif
tlbtab_end

47
board/xilinx/ml507/ml507.c Normal file
View File

@ -0,0 +1,47 @@
/*
* (C) Copyright 2008
* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
* This work has been supported by: QTechnology http://qtec.com/
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <config.h>
#include <common.h>
#include <asm/processor.h>
int board_pre_init(void)
{
return 0;
}
int checkboard(void)
{
puts("ML507 Board\n");
return 0;
}
phys_size_t initdram(int board_type)
{
return get_ram_size(XPAR_DDR2_SDRAM_MEM_BASEADDR,
CFG_SDRAM_SIZE_MB * 1024 * 1024);
}
void get_sys_info(sys_info_t * sysInfo)
{
sysInfo->freqProcessor = XPAR_CORE_CLOCK_FREQ_HZ;
sysInfo->freqPLB = XPAR_PLB_CLOCK_FREQ_HZ;
sysInfo->freqPCI = 0;
return;
}

134
board/xilinx/ml507/u-boot-ram.lds Normal file
View File

@ -0,0 +1,134 @@
/*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
ENTRY(_start_440)
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
*(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss (NOLOAD) :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
ppcenv_assert = ASSERT(. < 0xFFFFB000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified.");
_end = . ;
PROVIDE (end = .);
}

144
board/xilinx/ml507/u-boot-rom.lds Normal file
View File

@ -0,0 +1,144 @@
/*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
ENTRY(_start_440)
SECTIONS
{
.resetvec 0xFFFFFFFC :
{
*(.resetvec)
} = 0xffff
.bootpg 0xFFFFF000 :
{
cpu/ppc4xx/start.o (.bootpg)
} = 0xffff
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
*(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss (NOLOAD) :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
ppcenv_assert = ASSERT(. < 0xFFFFB000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified.");
_end = . ;
PROVIDE (end = .);
}

35
board/xilinx/ml507/xparameters.h Normal file
View File

@ -0,0 +1,35 @@
/*
* (C) Copyright 2008
* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
* This work has been supported by: QTechnology http://qtec.com/
* based on xparameters-ml507.h by Xilinx
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef XPARAMETER_H
#define XPARAMETER_H
#define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000
#define XPAR_IIC_EEPROM_BASEADDR 0x81600000
#define XPAR_INTC_0_BASEADDR 0x81800000
#define XPAR_LLTEMAC_0_BASEADDR 0x81C00000
#define XPAR_UARTLITE_0_BASEADDR 0x84000000
#define XPAR_FLASH_MEM0_BASEADDR 0xFE000000
#define XPAR_PLB_CLOCK_FREQ_HZ 100000000
#define XPAR_CORE_CLOCK_FREQ_HZ 400000000
#define XPAR_INTC_MAX_NUM_INTR_INPUTS 13
#define XPAR_UARTLITE_0_BAUDRATE 9600
#endif

50
board/xpedite1k/xpedite1k.c
View File

@ -59,36 +59,48 @@ int board_early_init_f(void)
/*--------------------------------------------------------------------
* Setup the interrupt controller polarities, triggers, etc.
*-------------------------------------------------------------------*/
mtdcr (uic0sr, 0xffffffff); /* clear all */
mtdcr (uic0er, 0x00000000); /* disable all */
mtdcr (uic0cr, 0x00000003); /* SMI & UIC1 crit are critical */
mtdcr (uic0pr, 0xfffffe00); /* per ref-board manual */
mtdcr (uic0tr, 0x01c00000); /* per ref-board manual */
mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (uic0sr, 0xffffffff); /* clear all */
/*
* Because of the interrupt handling rework to handle 440GX interrupts
* with the common code, we needed to change names of the UIC registers.
* Here the new relationship:
*
* U-Boot name 440GX name
* -----------------------
* UIC0 UICB0
* UIC1 UIC0
* UIC2 UIC1
* UIC3 UIC2
*/
mtdcr (uic1sr, 0xffffffff); /* clear all */
mtdcr (uic1er, 0x00000000); /* disable all */
mtdcr (uic1cr, 0x00000000); /* all non-critical */
mtdcr (uic1pr, 0xffffc0ff); /* per ref-board manual */
mtdcr (uic1tr, 0x00ff8000); /* per ref-board manual */
mtdcr (uic1cr, 0x00000003); /* SMI & UIC1 crit are critical */
mtdcr (uic1pr, 0xfffffe00); /* per ref-board manual */
mtdcr (uic1tr, 0x01c00000); /* per ref-board manual */
mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (uic1sr, 0xffffffff); /* clear all */
mtdcr (uic2sr, 0xffffffff); /* clear all */
mtdcr (uic2er, 0x00000000); /* disable all */
mtdcr (uic2cr, 0x00000000); /* all non-critical */
mtdcr (uic2pr, 0xffffffff); /* per ref-board manual */
mtdcr (uic2tr, 0x00ff8c0f); /* per ref-board manual */
mtdcr (uic2pr, 0xffffc0ff); /* per ref-board manual */
mtdcr (uic2tr, 0x00ff8000); /* per ref-board manual */
mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (uic2sr, 0xffffffff); /* clear all */
mtdcr (uicb0sr, 0xfc000000); /* clear all */
mtdcr (uicb0er, 0x00000000); /* disable all */
mtdcr (uicb0cr, 0x00000000); /* all non-critical */
mtdcr (uicb0pr, 0xfc000000); /* */
mtdcr (uicb0tr, 0x00000000); /* */
mtdcr (uicb0vr, 0x00000001); /* */
mtdcr (uic3sr, 0xffffffff); /* clear all */
mtdcr (uic3er, 0x00000000); /* disable all */
mtdcr (uic3cr, 0x00000000); /* all non-critical */
mtdcr (uic3pr, 0xffffffff); /* per ref-board manual */
mtdcr (uic3tr, 0x00ff8c0f); /* per ref-board manual */
mtdcr (uic3vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (uic3sr, 0xffffffff); /* clear all */
mtdcr (uic0sr, 0xfc000000); /* clear all */
mtdcr (uic0er, 0x00000000); /* disable all */
mtdcr (uic0cr, 0x00000000); /* all non-critical */
mtdcr (uic0pr, 0xfc000000); /* */
mtdcr (uic0tr, 0x00000000); /* */
mtdcr (uic0vr, 0x00000001); /* */
LED0_ON();

39
board/zylonite/nand.c
View File

@ -69,7 +69,7 @@ static struct nand_oobinfo delta_oob = {
/*
* not required for Monahans DFC
*/
static void dfc_hwcontrol(struct mtd_info *mtdinfo, int cmd)
static void dfc_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
return;
}
@ -110,25 +110,6 @@ static void dfc_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
}
/*
* These functions are quite problematic for the DFC. Luckily they are
* not used in the current nand code, except for nand_command, which
* we've defined our own anyway. The problem is, that we always need
* to write 4 bytes to the DFC Data Buffer, but in these functions we
* don't know if to buffer the bytes/half words until we've gathered 4
* bytes or if to send them straight away.
*
* Solution: Don't use these with Mona's DFC and complain loudly.
*/
static void dfc_write_word(struct mtd_info *mtd, u16 word)
{
printf("dfc_write_word: WARNING, this function does not work with the Monahans DFC!\n");
}
static void dfc_write_byte(struct mtd_info *mtd, u_char byte)
{
printf("dfc_write_byte: WARNING, this function does not work with the Monahans DFC!\n");
}
/* The original:
* static void dfc_read_buf(struct mtd_info *mtd, const u_char *buf, int len)
*
@ -168,7 +149,7 @@ static void dfc_read_buf(struct mtd_info *mtd, u_char* const buf, int len)
*/
static u16 dfc_read_word(struct mtd_info *mtd)
{
printf("dfc_write_byte: UNIMPLEMENTED.\n");
printf("dfc_read_word: UNIMPLEMENTED.\n");
return 0;
}
@ -289,9 +270,10 @@ static void dfc_new_cmd(void)
/* this function is called after Programm and Erase Operations to
* check for success or failure */
static int dfc_wait(struct mtd_info *mtd, struct nand_chip *this, int state)
static int dfc_wait(struct mtd_info *mtd, struct nand_chip *this)
{
unsigned long ndsr=0, event=0;
int state = this->state;
if(state == FL_WRITING) {
event = NDSR_CS0_CMDD | NDSR_CS0_BBD;
@ -435,11 +417,11 @@ static void dfc_gpio_init(void)
* argument are board-specific (per include/linux/mtd/nand_new.h):
* - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
* - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
* - hwcontrol: hardwarespecific function for accesing control-lines
* - cmd_ctrl: hardwarespecific function for accesing control-lines
* - dev_ready: hardwarespecific function for accesing device ready/busy line
* - enable_hwecc?: function to enable (reset) hardware ecc generator. Must
* only be provided if a hardware ECC is available
* - eccmode: mode of ecc, see defines
* - ecc.mode: mode of ecc, see defines
* - chip_delay: chip dependent delay for transfering data from array to
* read regs (tR)
* - options: various chip options. They can partly be set to inform
@ -560,21 +542,18 @@ int board_nand_init(struct nand_chip *nand)
/* wait 10 us due to cmd buffer clear reset */
/* wait(10); */
nand->hwcontrol = dfc_hwcontrol;
nand->cmd_ctrl = dfc_hwcontrol;
/* nand->dev_ready = dfc_device_ready; */
nand->eccmode = NAND_ECC_SOFT;
nand->ecc.mode = NAND_ECC_SOFT;
nand->options = NAND_BUSWIDTH_16;
nand->waitfunc = dfc_wait;
nand->read_byte = dfc_read_byte;
nand->write_byte = dfc_write_byte;
nand->read_word = dfc_read_word;
nand->write_word = dfc_write_word;
nand->read_buf = dfc_read_buf;
nand->write_buf = dfc_write_buf;
nand->cmdfunc = dfc_cmdfunc;
nand->autooob = &delta_oob;
/* nand->autooob = &delta_oob; */
nand->badblock_pattern = &delta_bbt_descr;
return 0;
}

4
common/ACEX1K.c
View File

@ -28,8 +28,6 @@
#include <common.h> /* core U-Boot definitions */
#include <ACEX1K.h> /* ACEX device family */
#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ALTERA) && defined(CONFIG_FPGA_ACEX1K)
/* Define FPGA_DEBUG to get debug printf's */
#ifdef FPGA_DEBUG
#define PRINTF(fmt,args...) printf (fmt ,##args)
@ -362,5 +360,3 @@ static int ACEX1K_ps_reloc (Altera_desc * desc, ulong reloc_offset)
return ret_val;
}
#endif /* CONFIG_FPGA && CONFIG_FPGA_ALTERA && CONFIG_FPGA_ACEX1K */

43
common/Makefile
View File

@ -28,9 +28,7 @@ LIB = $(obj)libcommon.a
AOBJS =
COBJS-y += main.o
COBJS-y += ACEX1K.o
COBJS-y += altera.o
COBJS-y += bedbug.o
COBJS-$(CONFIG_CMD_BEDBUG) += bedbug.o
COBJS-y += circbuf.o
COBJS-$(CONFIG_CMD_AMBAPP) += cmd_ambapp.o
COBJS-y += cmd_autoscript.o
@ -64,7 +62,18 @@ COBJS-$(CONFIG_OF_LIBFDT) += cmd_fdt.o fdt_support.o
COBJS-$(CONFIG_CMD_FDOS) += cmd_fdos.o
COBJS-$(CONFIG_CMD_FLASH) += cmd_flash.o
ifdef CONFIG_FPGA
COBJS-y += fpga.o
COBJS-$(CONFIG_CMD_FPGA) += cmd_fpga.o
COBJS-$(CONFIG_FPGA_SPARTAN2) += spartan2.o
COBJS-$(CONFIG_FPGA_SPARTAN3) += spartan3.o
COBJS-$(CONFIG_FPGA_VIRTEX2) += virtex2.o
COBJS-$(CONFIG_FPGA_XILINX) += xilinx.o
ifdef CONFIG_FPGA_ALTERA
COBJS-y += altera.o
COBJS-$(CONFIG_FPGA_ACEX1K) += ACEX1K.o
COBJS-$(CONFIG_FPGA_CYCLON2) += cyclon2.o
COBJS-$(CONFIG_FPGA_STRATIX_II) += stratixII.o
endif
endif
COBJS-$(CONFIG_CMD_I2C) += cmd_i2c.o
COBJS-$(CONFIG_CMD_IDE) += cmd_ide.o
@ -80,7 +89,7 @@ COBJS-$(CONFIG_CMD_MMC) += cmd_mmc.o
COBJS-y += cmd_nand.o
COBJS-$(CONFIG_CMD_NET) += cmd_net.o
COBJS-y += cmd_nvedit.o
COBJS-y += cmd_onenand.o
COBJS-$(CONFIG_CMD_ONENAND) += cmd_onenand.o
COBJS-$(CONFIG_CMD_OTP) += cmd_otp.o
ifdef CONFIG_PCI
COBJS-$(CONFIG_CMD_PCI) += cmd_pci.o
@ -98,14 +107,13 @@ COBJS-$(CONFIG_CMD_TERMINAL) += cmd_terminal.o
COBJS-$(CONFIG_CMD_UNIVERSE) += cmd_universe.o
COBJS-$(CONFIG_CMD_USB) += cmd_usb.o
COBJS-$(CONFIG_CMD_XIMG) += cmd_ximg.o
COBJS-$(CONFIG_YAFFS2) += cmd_yaffs2.o
COBJS-y += cmd_vfd.o
COBJS-y += command.o
COBJS-y += console.o
COBJS-y += cyclon2.o
COBJS-y += stratixII.o
COBJS-y += devices.o
COBJS-y += dlmalloc.o
COBJS-y += docecc.o
COBJS-$(CONFIG_CMD_DOC) += docecc.o
COBJS-y += environment.o
COBJS-y += env_common.o
COBJS-y += env_nand.o
@ -118,26 +126,23 @@ COBJS-y += env_nvram.o
COBJS-y += env_nowhere.o
COBJS-y += exports.o
COBJS-y += flash.o
COBJS-y += fpga.o
COBJS-y += hush.o
COBJS-y += kgdb.o
COBJS-y += lcd.o
COBJS-$(CONFIG_LCD) += lcd.o
COBJS-y += lists.o
COBJS-y += lynxkdi.o
COBJS-$(CONFIG_LYNXKDI) += lynxkdi.o
COBJS-y += memsize.o
COBJS-y += miiphybb.o
COBJS-$(CONFIG_BITBANGMII) += miiphybb.o
COBJS-y += miiphyutil.o
COBJS-y += s_record.o
COBJS-y += serial.o
COBJS-y += soft_i2c.o
COBJS-y += soft_spi.o
COBJS-y += spartan2.o
COBJS-y += spartan3.o
COBJS-$(CONFIG_SOFT_I2C) += soft_i2c.o
COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o
ifdef CONFIG_CMD_USB
COBJS-y += usb.o
COBJS-y += usb_kbd.o
COBJS-y += usb_storage.o
COBJS-y += virtex2.o
COBJS-y += xilinx.o
COBJS-$(CONFIG_USB_STORAGE) += usb_storage.o
endif
COBJS-$(CONFIG_USB_KEYBOARD) += usb_kbd.o
COBJS-y += crc16.o
COBJS-y += xyzModem.o
COBJS-y += cmd_mac.o

4
common/altera.c
View File

@ -41,8 +41,6 @@
#define PRINTF(fmt,args...)
#endif
#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ALTERA)
/* Local Static Functions */
static int altera_validate (Altera_desc * desc, const char *fn);
@ -283,5 +281,3 @@ static int altera_validate (Altera_desc * desc, const char *fn)
}
/* ------------------------------------------------------------------------- */
#endif /* CONFIG_FPGA & CONFIG_FPGA_ALTERA */

4
common/bedbug.c
View File

@ -2,8 +2,6 @@
#include <common.h>
#if defined(CONFIG_CMD_BEDBUG)
#include <linux/ctype.h>
#include <bedbug/bedbug.h>
#include <bedbug/ppc.h>
@ -1252,5 +1250,3 @@ int find_next_address (unsigned char *nextaddr, int step_over,
* warranties of merchantability and fitness for a particular
* purpose.
*/
#endif

6
common/cmd_bootm.c
View File

@ -138,7 +138,6 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
memset ((void *)&images, 0, sizeof (images));
images.verify = getenv_yesno ("verify");
images.autostart = getenv_yesno ("autostart");
images.lmb = &lmb;
lmb_init(&lmb);
@ -362,10 +361,9 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
show_boot_progress (-9);
#ifdef DEBUG
puts ("\n## Control returned to monitor - resetting...\n");
if (images.autostart)
do_reset (cmdtp, flag, argc, argv);
do_reset (cmdtp, flag, argc, argv);
#endif
if (!images.autostart && iflag)
if (iflag)
enable_interrupts();
return 1;

9
common/cmd_doc.c
View File

@ -14,6 +14,12 @@
#include <linux/mtd/nftl.h>
#include <linux/mtd/doc2000.h>
/*
* ! BROKEN !
*
* TODO: must be implemented and tested by someone with HW
*/
#if 0
#ifdef CFG_DOC_SUPPORT_2000
#define DoC_is_2000(doc) (doc->ChipID == DOC_ChipID_Doc2k)
#else
@ -1629,3 +1635,6 @@ void doc_probe(unsigned long physadr)
puts ("No DiskOnChip found\n");
}
}
#else
void doc_probe(unsigned long physadr) {}
#endif

12
common/cmd_jffs2.c
View File

@ -96,12 +96,12 @@
#include <cramfs/cramfs_fs.h>
#if defined(CONFIG_CMD_NAND)
#ifdef CFG_NAND_LEGACY
#ifdef CONFIG_NAND_LEGACY
#include <linux/mtd/nand_legacy.h>
#else /* !CFG_NAND_LEGACY */
#else /* !CONFIG_NAND_LEGACY */
#include <linux/mtd/nand.h>
#include <nand.h>
#endif /* !CFG_NAND_LEGACY */
#endif /* !CONFIG_NAND_LEGACY */
#endif
/* enable/disable debugging messages */
#define DEBUG_JFFS
@ -476,7 +476,7 @@ static int part_del(struct mtd_device *dev, struct part_info *part)
}
}
#ifdef CFG_NAND_LEGACY
#ifdef CONFIG_NAND_LEGACY
jffs2_free_cache(part);
#endif
list_del(&part->link);
@ -505,7 +505,7 @@ static void part_delall(struct list_head *head)
list_for_each_safe(entry, n, head) {
part_tmp = list_entry(entry, struct part_info, link);
#ifdef CFG_NAND_LEGACY
#ifdef CONFIG_NAND_LEGACY
jffs2_free_cache(part_tmp);
#endif
list_del(entry);
@ -741,7 +741,7 @@ static int device_validate(u8 type, u8 num, u32 *size)
} else if (type == MTD_DEV_TYPE_NAND) {
#if defined(CONFIG_JFFS2_NAND) && defined(CONFIG_CMD_NAND)
if (num < CFG_MAX_NAND_DEVICE) {
#ifndef CFG_NAND_LEGACY
#ifndef CONFIG_NAND_LEGACY
*size = nand_info[num].size;
#else
extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];

15
common/cmd_load.c
View File

@ -424,7 +424,6 @@ write_record (char *buf)
#define untochar(x) ((int) (((x) - SPACE) & 0xff))
extern int os_data_count;
extern int os_data_header[8];
static void set_kerm_bin_mode(unsigned long *);
static int k_recv(void);
@ -631,11 +630,6 @@ void send_nack (int n)
}
/* os_data_* takes an OS Open image and puts it into memory, and
puts the boot header in an array named os_data_header
if image is binary, no header is stored in os_data_header.
*/
void (*os_data_init) (void);
void (*os_data_char) (char new_char);
static int os_data_state, os_data_state_saved;
@ -643,25 +637,28 @@ int os_data_count;
static int os_data_count_saved;
static char *os_data_addr, *os_data_addr_saved;
static char *bin_start_address;
int os_data_header[8];
static void bin_data_init (void)
{
os_data_state = 0;
os_data_count = 0;
os_data_addr = bin_start_address;
}
static void os_data_save (void)
{
os_data_state_saved = os_data_state;
os_data_count_saved = os_data_count;
os_data_addr_saved = os_data_addr;
}
static void os_data_restore (void)
{
os_data_state = os_data_state_saved;
os_data_count = os_data_count_saved;
os_data_addr = os_data_addr_saved;
}
static void bin_data_char (char new_char)
{
switch (os_data_state) {
@ -671,6 +668,7 @@ static void bin_data_char (char new_char)
break;
}
}
static void set_kerm_bin_mode (unsigned long *addr)
{
bin_start_address = (char *) addr;
@ -686,16 +684,19 @@ void k_data_init (void)
k_data_escape = 0;
os_data_init ();
}
void k_data_save (void)
{
k_data_escape_saved = k_data_escape;
os_data_save ();
}
void k_data_restore (void)
{
k_data_escape = k_data_escape_saved;
os_data_restore ();
}
void k_data_char (char new_char)
{
if (k_data_escape) {

4
common/cmd_mp.c
View File

@ -34,9 +34,9 @@ cpu_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
cpuid = simple_strtoul(argv[1], NULL, 10);
if (cpuid >= CONFIG_NR_CPUS) {
if (cpuid >= CONFIG_NUM_CPUS) {
printf ("Core num: %lu is out of range[0..%d]\n",
cpuid, CONFIG_NR_CPUS - 1);
cpuid, CONFIG_NUM_CPUS - 1);
return 1;
}

259
common/cmd_nand.c
View File

@ -11,13 +11,14 @@
#include <common.h>
#ifndef CFG_NAND_LEGACY
#ifndef CONFIG_NAND_LEGACY
/*
*
* New NAND support
*
*/
#include <common.h>
#include <linux/mtd/mtd.h>
#if defined(CONFIG_CMD_NAND)
@ -34,48 +35,58 @@
int mtdparts_init(void);
int id_parse(const char *id, const char **ret_id, u8 *dev_type, u8 *dev_num);
int find_dev_and_part(const char *id, struct mtd_device **dev,
u8 *part_num, struct part_info **part);
u8 *part_num, struct part_info **part);
#endif
static int nand_dump_oob(nand_info_t *nand, ulong off)
{
return 0;
}
static int nand_dump(nand_info_t *nand, ulong off)
static int nand_dump(nand_info_t *nand, ulong off, int only_oob)
{
int i;
u_char *buf, *p;
u_char *datbuf, *oobbuf, *p;
buf = malloc(nand->oobblock + nand->oobsize);
if (!buf) {
datbuf = malloc(nand->writesize + nand->oobsize);
oobbuf = malloc(nand->oobsize);
if (!datbuf || !oobbuf) {
puts("No memory for page buffer\n");
return 1;
}
off &= ~(nand->oobblock - 1);
i = nand_read_raw(nand, buf, off, nand->oobblock, nand->oobsize);
off &= ~(nand->writesize - 1);
loff_t addr = (loff_t) off;
struct mtd_oob_ops ops;
memset(&ops, 0, sizeof(ops));
ops.datbuf = datbuf;
ops.oobbuf = oobbuf; /* must exist, but oob data will be appended to ops.datbuf */
ops.len = nand->writesize;
ops.ooblen = nand->oobsize;
ops.mode = MTD_OOB_RAW;
i = nand->read_oob(nand, addr, &ops);
if (i < 0) {
printf("Error (%d) reading page %08lx\n", i, off);
free(buf);
free(datbuf);
free(oobbuf);
return 1;
}
printf("Page %08lx dump:\n", off);
i = nand->oobblock >> 4; p = buf;
i = nand->writesize >> 4;
p = datbuf;
while (i--) {
printf( "\t%02x %02x %02x %02x %02x %02x %02x %02x"
" %02x %02x %02x %02x %02x %02x %02x %02x\n",
p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7],
p[8], p[9], p[10], p[11], p[12], p[13], p[14], p[15]);
if (!only_oob)
printf("\t%02x %02x %02x %02x %02x %02x %02x %02x"
" %02x %02x %02x %02x %02x %02x %02x %02x\n",
p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7],
p[8], p[9], p[10], p[11], p[12], p[13], p[14],
p[15]);
p += 16;
}
puts("OOB:\n");
i = nand->oobsize >> 3;
while (i--) {
printf( "\t%02x %02x %02x %02x %02x %02x %02x %02x\n",
p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7]);
printf("\t%02x %02x %02x %02x %02x %02x %02x %02x\n",
p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7]);
p += 8;
}
free(buf);
free(datbuf);
free(oobbuf);
return 0;
}
@ -155,7 +166,7 @@ out:
int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
int i, dev, ret;
int i, dev, ret = 0;
ulong addr, off;
size_t size;
char *cmd, *s;
@ -182,8 +193,8 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
for (i = 0; i < CFG_MAX_NAND_DEVICE; i++) {
if (nand_info[i].name)
printf("Device %d: %s, sector size %u KiB\n",
i, nand_info[i].name,
nand_info[i].erasesize >> 10);
i, nand_info[i].name,
nand_info[i].erasesize >> 10);
}
return 0;
}
@ -196,7 +207,7 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
puts("\nno devices available\n");
else
printf("\nDevice %d: %s\n", nand_curr_device,
nand_info[nand_curr_device].name);
nand_info[nand_curr_device].name);
return 0;
}
dev = (int)simple_strtoul(argv[2], NULL, 10);
@ -299,15 +310,14 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
off = (int)simple_strtoul(argv[2], NULL, 16);
if (s != NULL && strcmp(s, ".oob") == 0)
ret = nand_dump_oob(nand, off);
ret = nand_dump(nand, off, 1);
else
ret = nand_dump(nand, off);
ret = nand_dump(nand, off, 0);
return ret == 0 ? 1 : 0;
}
/* read write */
if (strncmp(cmd, "read", 4) == 0 || strncmp(cmd, "write", 5) == 0) {
int read;
@ -322,43 +332,29 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
return 1;
s = strchr(cmd, '.');
if (s != NULL &&
(!strcmp(s, ".jffs2") || !strcmp(s, ".e") || !strcmp(s, ".i"))) {
if (read) {
/* read */
nand_read_options_t opts;
memset(&opts, 0, sizeof(opts));
opts.buffer = (u_char*) addr;
opts.length = size;
opts.offset = off;
opts.quiet = quiet;
ret = nand_read_opts(nand, &opts);
} else {
/* write */
nand_write_options_t opts;
memset(&opts, 0, sizeof(opts));
opts.buffer = (u_char*) addr;
opts.length = size;
opts.offset = off;
/* opts.forcejffs2 = 1; */
opts.pad = 1;
opts.blockalign = 1;
opts.quiet = quiet;
ret = nand_write_opts(nand, &opts);
}
if (!s || !strcmp(s, ".jffs2") ||
!strcmp(s, ".e") || !strcmp(s, ".i")) {
if (read)
ret = nand_read_skip_bad(nand, off, &size,
(u_char *)addr);
else
ret = nand_write_skip_bad(nand, off, &size,
(u_char *)addr);
} else if (s != NULL && !strcmp(s, ".oob")) {
/* read out-of-band data */
/* out-of-band data */
mtd_oob_ops_t ops = {
.oobbuf = (u8 *)addr,
.ooblen = size,
.mode = MTD_OOB_RAW
};
if (read)
ret = nand->read_oob(nand, off, size, &size,
(u_char *) addr);
ret = nand->read_oob(nand, off, &ops);
else
ret = nand->write_oob(nand, off, size, &size,
(u_char *) addr);
ret = nand->write_oob(nand, off, &ops);
} else {
if (read)
ret = nand_read(nand, off, &size, (u_char *)addr);
else
ret = nand_write(nand, off, &size, (u_char *)addr);
printf("Unknown nand command suffix '%s'.\n", s);
return 1;
}
printf(" %d bytes %s: %s\n", size,
@ -381,6 +377,7 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
}
return 1;
}
if (strcmp(cmd, "biterr") == 0) {
/* todo */
return 1;
@ -395,7 +392,12 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
if (!strcmp("status", argv[2]))
status = 1;
}
/*
* ! BROKEN !
*
* TODO: must be implemented and tested by someone with HW
*/
#if 0
if (status) {
ulong block_start = 0;
ulong off;
@ -406,28 +408,28 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
nand_chip->cmdfunc (nand, NAND_CMD_STATUS, -1, -1);
printf("device is %swrite protected\n",
(nand_chip->read_byte(nand) & 0x80 ?
"NOT " : "" ) );
"NOT " : ""));
for (off = 0; off < nand->size; off += nand->oobblock) {
for (off = 0; off < nand->size; off += nand->writesize) {
int s = nand_get_lock_status(nand, off);
/* print message only if status has changed
* or at end of chip
*/
if (off == nand->size - nand->oobblock
if (off == nand->size - nand->writesize
|| (s != last_status && off != 0)) {
printf("%08lx - %08lx: %8lu pages %s%s%s\n",
printf("%08lx - %08lx: %8d pages %s%s%s\n",
block_start,
off-1,
(off-block_start)/nand->oobblock,
(off-block_start)/nand->writesize,
((last_status & NAND_LOCK_STATUS_TIGHT) ? "TIGHT " : ""),
((last_status & NAND_LOCK_STATUS_LOCK) ? "LOCK " : ""),
((last_status & NAND_LOCK_STATUS_UNLOCK) ? "UNLOCK " : ""));
}
last_status = s;
}
}
} else {
if (!nand_lock(nand, tight)) {
puts("NAND flash successfully locked\n");
@ -436,6 +438,7 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
return 1;
}
}
#endif
return 0;
}
@ -443,6 +446,12 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
if (arg_off_size(argc - 2, argv + 2, nand, &off, &size) < 0)
return 1;
/*
* ! BROKEN !
*
* TODO: must be implemented and tested by someone with HW
*/
#if 0
if (!nand_unlock(nand, off, size)) {
puts("NAND flash successfully unlocked\n");
} else {
@ -450,6 +459,7 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
"write and erase will probably fail\n");
return 1;
}
#endif
return 0;
}
@ -459,54 +469,47 @@ usage:
}
U_BOOT_CMD(nand, 5, 1, do_nand,
"nand - NAND sub-system\n",
"info - show available NAND devices\n"
"nand device [dev] - show or set current device\n"
"nand read[.jffs2] - addr off|partition size\n"
"nand write[.jffs2] - addr off|partition size - read/write `size' bytes starting\n"
" at offset `off' to/from memory address `addr'\n"
"nand erase [clean] [off size] - erase `size' bytes from\n"
" offset `off' (entire device if not specified)\n"
"nand bad - show bad blocks\n"
"nand dump[.oob] off - dump page\n"
"nand scrub - really clean NAND erasing bad blocks (UNSAFE)\n"
"nand markbad off - mark bad block at offset (UNSAFE)\n"
"nand biterr off - make a bit error at offset (UNSAFE)\n"
"nand lock [tight] [status] - bring nand to lock state or display locked pages\n"
"nand unlock [offset] [size] - unlock section\n");
"nand - NAND sub-system\n",
"info - show available NAND devices\n"
"nand device [dev] - show or set current device\n"
"nand read - addr off|partition size\n"
"nand write - addr off|partition size\n"
" read/write 'size' bytes starting at offset 'off'\n"
" to/from memory address 'addr', skipping bad blocks.\n"
"nand erase [clean] [off size] - erase 'size' bytes from\n"
" offset 'off' (entire device if not specified)\n"
"nand bad - show bad blocks\n"
"nand dump[.oob] off - dump page\n"
"nand scrub - really clean NAND erasing bad blocks (UNSAFE)\n"
"nand markbad off - mark bad block at offset (UNSAFE)\n"
"nand biterr off - make a bit error at offset (UNSAFE)\n"
"nand lock [tight] [status]\n"
" bring nand to lock state or display locked pages\n"
"nand unlock [offset] [size] - unlock section\n");
static int nand_load_image(cmd_tbl_t *cmdtp, nand_info_t *nand,
ulong offset, ulong addr, char *cmd)
ulong offset, ulong addr, char *cmd)
{
int r;
char *ep, *s;
size_t cnt;
image_header_t *hdr;
int jffs2 = 0;
#if defined(CONFIG_FIT)
const void *fit_hdr = NULL;
#endif
s = strchr(cmd, '.');
if (s != NULL &&
(!strcmp(s, ".jffs2") || !strcmp(s, ".e") || !strcmp(s, ".i")))
jffs2 = 1;
(strcmp(s, ".jffs2") && !strcmp(s, ".e") && !strcmp(s, ".i"))) {
printf("Unknown nand load suffix '%s'\n", s);
show_boot_progress(-53);
return 1;
}
printf("\nLoading from %s, offset 0x%lx\n", nand->name, offset);
cnt = nand->oobblock;
if (jffs2) {
nand_read_options_t opts;
memset(&opts, 0, sizeof(opts));
opts.buffer = (u_char*) addr;
opts.length = cnt;
opts.offset = offset;
opts.quiet = 1;
r = nand_read_opts(nand, &opts);
} else {
r = nand_read(nand, offset, &cnt, (u_char *) addr);
}
cnt = nand->writesize;
r = nand_read(nand, offset, &cnt, (u_char *) addr);
if (r) {
puts("** Read error\n");
show_boot_progress (-56);
@ -536,19 +539,10 @@ static int nand_load_image(cmd_tbl_t *cmdtp, nand_info_t *nand,
puts ("** Unknown image type\n");
return 1;
}
show_boot_progress (57);
if (jffs2) {
nand_read_options_t opts;
memset(&opts, 0, sizeof(opts));
opts.buffer = (u_char*) addr;
opts.length = cnt;
opts.offset = offset;
opts.quiet = 1;
r = nand_read_opts(nand, &opts);
} else {
r = nand_read(nand, offset, &cnt, (u_char *) addr);
}
/* FIXME: skip bad blocks */
r = nand_read(nand, offset, &cnt, (u_char *) addr);
if (r) {
puts("** Read error\n");
show_boot_progress (-58);
@ -614,7 +608,7 @@ int do_nandboot(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
else
addr = CFG_LOAD_ADDR;
return nand_load_image(cmdtp, &nand_info[dev->id->num],
part->offset, addr, argv[0]);
part->offset, addr, argv[0]);
}
}
#endif
@ -669,11 +663,11 @@ usage:
U_BOOT_CMD(nboot, 4, 1, do_nandboot,
"nboot - boot from NAND device\n",
"[.jffs2] [partition] | [[[loadAddr] dev] offset]\n");
"[partition] | [[[loadAddr] dev] offset]\n");
#endif
#else /* CFG_NAND_LEGACY */
#else /* CONFIG_NAND_LEGACY */
/*
*
* Legacy NAND support - to be phased out
@ -726,10 +720,10 @@ void archflashwp(void *archdata, int wp);
#define CONFIG_MTD_NAND_ECC_JFFS2
/* bits for nand_legacy_rw() `cmd'; or together as needed */
#define NANDRW_READ 0x01
#define NANDRW_WRITE 0x00
#define NANDRW_JFFS2 0x02
#define NANDRW_JFFS2_SKIP 0x04
#define NANDRW_READ 0x01
#define NANDRW_WRITE 0x00
#define NANDRW_JFFS2 0x02
#define NANDRW_JFFS2_SKIP 0x04
/*
* Imports from nand_legacy.c
@ -839,11 +833,11 @@ int do_nand (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
if (strncmp (argv[1], "read", 4) == 0 ||
strncmp (argv[1], "write", 5) == 0) {
ulong addr = simple_strtoul (argv[2], NULL, 16);
off_t off = simple_strtoul (argv[3], NULL, 16);
size_t size = simple_strtoul (argv[4], NULL, 16);
int cmd = (strncmp (argv[1], "read", 4) == 0) ?
NANDRW_READ : NANDRW_WRITE;
ulong addr = simple_strtoul (argv[2], NULL, 16);
off_t off = simple_strtoul (argv[3], NULL, 16);
size_t size = simple_strtoul (argv[4], NULL, 16);
int cmd = (strncmp (argv[1], "read", 4) == 0) ?
NANDRW_READ : NANDRW_WRITE;
size_t total;
int ret;
char *cmdtail = strchr (argv[1], '.');
@ -892,8 +886,7 @@ int do_nand (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
ret = nand_legacy_rw (nand_dev_desc + curr_device,
cmd, off, size,
&total,
(u_char *) addr);
&total, (u_char *) addr);
printf (" %d bytes %s: %s\n", total,
(cmd & NANDRW_READ) ? "read" : "written",
@ -1000,11 +993,11 @@ int do_nandboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
show_boot_progress (55);
printf ("\nLoading from device %d: %s at 0x%lx (offset 0x%lx)\n",
dev, nand_dev_desc[dev].name, nand_dev_desc[dev].IO_ADDR,
offset);
dev, nand_dev_desc[dev].name, nand_dev_desc[dev].IO_ADDR,
offset);
if (nand_legacy_rw (nand_dev_desc + dev, NANDRW_READ, offset,
SECTORSIZE, NULL, (u_char *)addr)) {
SECTORSIZE, NULL, (u_char *)addr)) {
printf ("** Read error on %d\n", dev);
show_boot_progress (-56);
return 1;
@ -1035,8 +1028,8 @@ int do_nandboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
show_boot_progress (57);
if (nand_legacy_rw (nand_dev_desc + dev, NANDRW_READ,
offset + SECTORSIZE, cnt, NULL,
(u_char *)(addr+SECTORSIZE))) {
offset + SECTORSIZE, cnt, NULL,
(u_char *)(addr+SECTORSIZE))) {
printf ("** Read error on %d\n", dev);
show_boot_progress (-58);
return 1;
@ -1084,4 +1077,4 @@ U_BOOT_CMD(
#endif
#endif /* CFG_NAND_LEGACY */
#endif /* CONFIG_NAND_LEGACY */

12
common/cmd_onenand.c
View File

@ -12,8 +12,6 @@
#include <common.h>
#include <command.h>
#ifdef CONFIG_CMD_ONENAND
#include <linux/mtd/compat.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/onenand.h>
@ -38,7 +36,7 @@ int do_onenand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
onenand_init();
return 0;
}
onenand_print_device_info(onenand_chip.device_id, 1);
printf("%s\n", onenand_mtd.name);
return 0;
default:
@ -58,8 +56,6 @@ int do_onenand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
} else {
start = simple_strtoul(argv[2], NULL, 10);
end = simple_strtoul(argv[3], NULL, 10);
start -= (unsigned long)onenand_chip.base;
end -= (unsigned long)onenand_chip.base;
start >>= onenand_chip.erase_shift;
end >>= onenand_chip.erase_shift;
@ -92,8 +88,6 @@ int do_onenand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
size_t retlen = 0;
int oob = strncmp(argv[1], "read.oob", 8) ? 0 : 1;
ofs -= (unsigned long)onenand_chip.base;
if (oob)
onenand_read_oob(&onenand_mtd, ofs, len,
&retlen, (u_char *) addr);
@ -111,8 +105,6 @@ int do_onenand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
size_t len = simple_strtoul(argv[4], NULL, 16);
size_t retlen = 0;
ofs -= (unsigned long)onenand_chip.base;
onenand_write(&onenand_mtd, ofs, len, &retlen,
(u_char *) addr);
printf("Done\n");
@ -165,5 +157,3 @@ U_BOOT_CMD(
"onenand block[.oob] addr block [page] [len] - "
"read data with (block [, page]) to addr"
);
#endif /* CONFIG_CMD_ONENAND */

5
common/cmd_reginfo.c
View File

@ -93,11 +93,10 @@ int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
#elif defined (CONFIG_405GP)
printf ("\n405GP registers; MSR=%08x\n",mfmsr());
printf ("\nUniversal Interrupt Controller Regs\n"
"uicsr uicsrs uicer uiccr uicpr uictr uicmsr uicvr uicvcr"
"uicsr uicer uiccr uicpr uictr uicmsr uicvr uicvcr"
"\n"
"%08x %08x %08x %08x %08x %08x %08x %08x %08x\n",
"%08x %08x %08x %08x %08x %08x %08x %08x\n",
mfdcr(uicsr),
mfdcr(uicsrs),
mfdcr(uicer),
mfdcr(uiccr),
mfdcr(uicpr),

215
common/cmd_yaffs2.c Normal file
View File

@ -0,0 +1,215 @@
#include <common.h>
#include <config.h>
#include <command.h>
#ifdef YAFFS2_DEBUG
#define PRINTF(fmt,args...) printf (fmt ,##args)
#else
#define PRINTF(fmt,args...)
#endif
extern void cmd_yaffs_mount(char *mp);
extern void cmd_yaffs_umount(char *mp);
extern void cmd_yaffs_read_file(char *fn);
extern void cmd_yaffs_write_file(char *fn,char bval,int sizeOfFile);
extern void cmd_yaffs_ls(const char *mountpt, int longlist);
extern void cmd_yaffs_mwrite_file(char *fn, char *addr, int size);
extern void cmd_yaffs_mread_file(char *fn, char *addr);
extern void cmd_yaffs_mkdir(const char *dir);
extern void cmd_yaffs_rmdir(const char *dir);
extern void cmd_yaffs_rm(const char *path);
extern void cmd_yaffs_mv(const char *oldPath, const char *newPath);
extern int yaffs_DumpDevStruct(const char *path);
int do_ymount (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
char *mtpoint = argv[1];
cmd_yaffs_mount(mtpoint);
return(0);
}
int do_yumount (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
char *mtpoint = argv[1];
cmd_yaffs_umount(mtpoint);
return(0);
}
int do_yls (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
char *dirname = argv[argc-1];
cmd_yaffs_ls(dirname, (argc>2)?1:0);
return(0);
}
int do_yrd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
char *filename = argv[1];
printf ("Reading file %s ", filename);
cmd_yaffs_read_file(filename);
printf ("done\n");
return(0);
}
int do_ywr (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
char *filename = argv[1];
ulong value = simple_strtoul(argv[2], NULL, 16);
ulong numValues = simple_strtoul(argv[3], NULL, 16);
printf ("Writing value (%x) %x times to %s... ", value, numValues, filename);
cmd_yaffs_write_file(filename,value,numValues);
printf ("done\n");
return(0);
}
int do_yrdm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
char *filename = argv[1];
ulong addr = simple_strtoul(argv[2], NULL, 16);
cmd_yaffs_mread_file(filename, (char *)addr);
return(0);
}
int do_ywrm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
char *filename = argv[1];
ulong addr = simple_strtoul(argv[2], NULL, 16);
ulong size = simple_strtoul(argv[3], NULL, 16);
cmd_yaffs_mwrite_file(filename, (char *)addr, size);
return(0);
}
int do_ymkdir (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
char *dirname = argv[1];
cmd_yaffs_mkdir(dirname);
return(0);
}
int do_yrmdir (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
char *dirname = argv[1];
cmd_yaffs_rmdir(dirname);
return(0);
}
int do_yrm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
char *path = argv[1];
cmd_yaffs_rm(path);
return(0);
}
int do_ymv (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
char *oldPath = argv[1];
char *newPath = argv[2];
cmd_yaffs_mv(newPath, oldPath);
return(0);
}
int do_ydump (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
char *dirname = argv[1];
if (yaffs_DumpDevStruct(dirname) != 0)
printf("yaffs_DumpDevStruct returning error when dumping path: , %s\n", dirname);
return 0;
}
U_BOOT_CMD(
ymount, 3, 0, do_ymount,
"ymount\t- mount yaffs\n",
"\n"
);
U_BOOT_CMD(
yumount, 3, 0, do_yumount,
"yumount\t- unmount yaffs\n",
"\n"
);
U_BOOT_CMD(
yls, 4, 0, do_yls,
"yls\t- yaffs ls\n",
"[-l] name\n"
);
U_BOOT_CMD(
yrd, 2, 0, do_yrd,
"yrd\t- read file from yaffs\n",
"filename\n"
);
U_BOOT_CMD(
ywr, 4, 0, do_ywr,
"ywr\t- write file to yaffs\n",
"filename value num_vlues\n"
);
U_BOOT_CMD(
yrdm, 3, 0, do_yrdm,
"yrdm\t- read file to memory from yaffs\n",
"filename offset\n"
);
U_BOOT_CMD(
ywrm, 4, 0, do_ywrm,
"ywrm\t- write file from memory to yaffs\n",
"filename offset size\n"
);
U_BOOT_CMD(
ymkdir, 2, 0, do_ymkdir,
"ymkdir\t- YAFFS mkdir\n",
"dirname\n"
);
U_BOOT_CMD(
yrmdir, 2, 0, do_yrmdir,
"yrmdir\t- YAFFS rmdir\n",
"dirname\n"
);
U_BOOT_CMD(
yrm, 2, 0, do_yrm,
"yrm\t- YAFFS rm\n",
"path\n"
);
U_BOOT_CMD(
ymv, 4, 0, do_ymv,
"ymv\t- YAFFS mv\n",
"oldPath newPath\n"
);
U_BOOT_CMD(
ydump, 2, 0, do_ydump,
"ydump\t- YAFFS device struct\n",
"dirname\n"
);

4
common/cyclon2.c
View File

@ -27,8 +27,6 @@
#include <altera.h>
#include <ACEX1K.h> /* ACEX device family */
#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ALTERA) && defined(CONFIG_FPGA_CYCLON2)
/* Define FPGA_DEBUG to get debug printf's */
#ifdef FPGA_DEBUG
#define PRINTF(fmt,args...) printf (fmt ,##args)
@ -301,5 +299,3 @@ static int CYC2_ps_reloc (Altera_desc * desc, ulong reloc_offset)
return ret_val;
}
#endif /* CONFIG_FPGA && CONFIG_FPGA_ALTERA && CONFIG_FPGA_CYCLON2 */

4
common/docecc.c
View File

@ -31,8 +31,6 @@
#undef ECC_DEBUG
#undef PSYCHO_DEBUG
#if defined(CONFIG_CMD_DOC)
#include <linux/mtd/doc2000.h>
/* need to undef it (from asm/termbits.h) */
@ -513,5 +511,3 @@ int doc_decode_ecc(unsigned char sector[SECTOR_SIZE], unsigned char ecc1[6])
free(Index_of);
return nb_errors;
}
#endif

18
common/env_nand.c
View File

@ -159,22 +159,23 @@ int writeenv(size_t offset, u_char *buf)
{
size_t end = offset + CFG_ENV_RANGE;
size_t amount_saved = 0;
size_t blocksize;
size_t blocksize, len;
u_char *char_ptr;
blocksize = nand_info[0].erasesize;
len = min(blocksize, CFG_ENV_SIZE);
while (amount_saved < CFG_ENV_SIZE && offset < end) {
if (nand_block_isbad(&nand_info[0], offset)) {
offset += blocksize;
} else {
char_ptr = &buf[amount_saved];
if (nand_write(&nand_info[0], offset, &blocksize,
if (nand_write(&nand_info[0], offset, &len,
char_ptr))
return 1;
offset += blocksize;
amount_saved += blocksize;
amount_saved += len;
}
}
if (amount_saved != CFG_ENV_SIZE)
@ -261,21 +262,22 @@ int readenv (size_t offset, u_char * buf)
{
size_t end = offset + CFG_ENV_RANGE;
size_t amount_loaded = 0;
size_t blocksize;
size_t blocksize, len;
u_char *char_ptr;
blocksize = nand_info[0].erasesize;
len = min(blocksize, CFG_ENV_SIZE);
while (amount_loaded < CFG_ENV_SIZE && offset < end) {
if (nand_block_isbad(&nand_info[0], offset)) {
offset += blocksize;
} else {
char_ptr = &buf[amount_loaded];
if (nand_read(&nand_info[0], offset, &blocksize, char_ptr))
if (nand_read(&nand_info[0], offset, &len, char_ptr))
return 1;
offset += blocksize;
amount_loaded += blocksize;
amount_loaded += len;
}
}
if (amount_loaded != CFG_ENV_SIZE)
@ -345,12 +347,10 @@ void env_relocate_spec (void)
void env_relocate_spec (void)
{
#if !defined(ENV_IS_EMBEDDED)
size_t total;
int ret;
total = CFG_ENV_SIZE;
ret = readenv(CFG_ENV_OFFSET, (u_char *) env_ptr);
if (ret || total != CFG_ENV_SIZE)
if (ret)
return use_default();
if (crc32(0, env_ptr->data, ENV_SIZE) != env_ptr->crc)

3
common/env_onenand.c
View File

@ -66,7 +66,6 @@ void env_relocate_spec(void)
size_t retlen;
env_addr = CFG_ENV_ADDR;
env_addr -= (unsigned long) onenand_chip.base;
/* Check OneNAND exist */
if (onenand_mtd.oobblock)
@ -101,7 +100,6 @@ int saveenv(void)
instr.len = CFG_ENV_SIZE;
instr.addr = env_addr;
instr.addr -= (unsigned long)onenand_chip.base;
if (onenand_erase(&onenand_mtd, &instr)) {
printf("OneNAND: erase failed at 0x%08lx\n", env_addr);
return 1;
@ -111,7 +109,6 @@ int saveenv(void)
env_ptr->crc =
crc32(0, env_ptr->data, ONENAND_ENV_SIZE(onenand_mtd));
env_addr -= (unsigned long)onenand_chip.base;
if (onenand_write(&onenand_mtd, env_addr, onenand_mtd.oobblock, &retlen,
(u_char *) env_ptr)) {
printf("OneNAND: write failed at 0x%08x\n", instr.addr);

4
common/fpga.c
View File

@ -29,8 +29,6 @@
#include <xilinx.h> /* xilinx specific definitions */
#include <altera.h> /* altera specific definitions */
#if defined(CONFIG_FPGA)
#if 0
#define FPGA_DEBUG /* define FPGA_DEBUG to get debug messages */
#endif
@ -335,5 +333,3 @@ int fpga_info( int devnum )
}
/* ------------------------------------------------------------------------- */
#endif /* CONFIG_FPGA */

3
common/image.c
View File

@ -189,7 +189,6 @@ int image_check_dcrc (image_header_t *hdr)
return (dcrc == image_get_dcrc (hdr));
}
/**
* image_multi_count - get component (sub-image) count
* @hdr: pointer to the header of the multi component image
@ -833,7 +832,7 @@ int boot_get_ramdisk (int argc, char *argv[], bootm_headers_t *images,
rd_noffset = fit_conf_get_ramdisk_node (fit_hdr, cfg_noffset);
if (rd_noffset < 0) {
debug ("* ramdisk: no ramdisk in config\n");
return 1;
return 0;
}
}
#endif

6
common/lcd.c
View File

@ -55,8 +55,6 @@
#include <nand.h>
#endif
#ifdef CONFIG_LCD
/************************************************************************/
/* ** FONT DATA */
/************************************************************************/
@ -793,7 +791,7 @@ static void *lcd_logo (void)
sprintf (info, "%s (%s - %s) ", U_BOOT_VERSION, __DATE__, __TIME__);
lcd_drawchars (LCD_INFO_X, LCD_INFO_Y, (uchar *)info, strlen(info));
sprintf (info, "(C) 2004 DENX Software Engineering");
sprintf (info, "(C) 2008 DENX Software Engineering GmbH");
lcd_drawchars (LCD_INFO_X, LCD_INFO_Y + VIDEO_FONT_HEIGHT,
(uchar *)info, strlen(info));
@ -867,5 +865,3 @@ static void *lcd_logo (void)
/************************************************************************/
/************************************************************************/
#endif /* CONFIG_LCD */

3
common/lynxkdi.c
View File

@ -17,7 +17,6 @@
#include <asm/processor.h>
#include <image.h>
#if defined(CONFIG_LYNXKDI)
#include <lynxkdi.h>
DECLARE_GLOBAL_DATA_PTR;
@ -66,5 +65,3 @@ void lynxkdi_boot (image_header_t *hdr)
#else
#error "Lynx KDI support not implemented for configured CPU"
#endif
#endif /* CONFIG_LYNXKDI */

5
common/miiphybb.c
View File

@ -30,9 +30,6 @@
#include <ioports.h>
#include <ppc_asm.tmpl>
#ifdef CONFIG_BITBANGMII
/*****************************************************************************
*
* Utility to send the preamble, address, and register (common to read
@ -236,5 +233,3 @@ int bb_miiphy_write (char *devname, unsigned char addr,
return 0;
}
#endif /* CONFIG_BITBANGMII */

5
common/soft_i2c.c
View File

@ -41,8 +41,6 @@
#endif
#include <i2c.h>
#if defined(CONFIG_SOFT_I2C)
/* #define DEBUG_I2C */
#ifdef DEBUG_I2C
@ -423,6 +421,3 @@ void i2c_reg_write(uchar i2c_addr, uchar reg, uchar val)
{
i2c_write(i2c_addr, reg, 1, &val, 1);
}
#endif /* CONFIG_SOFT_I2C */

4
common/soft_spi.c
View File

@ -27,8 +27,6 @@
#include <common.h>
#include <spi.h>
#if defined(CONFIG_SOFT_SPI)
#include <malloc.h>
/*-----------------------------------------------------------------------
@ -193,5 +191,3 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
return(0);
}
#endif /* CONFIG_SOFT_SPI */

4
common/spartan2.c
View File

@ -25,8 +25,6 @@
#include <common.h> /* core U-Boot definitions */
#include <spartan2.h> /* Spartan-II device family */
#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_SPARTAN2)
/* Define FPGA_DEBUG to get debug printf's */
#ifdef FPGA_DEBUG
#define PRINTF(fmt,args...) printf (fmt ,##args)
@ -663,5 +661,3 @@ static int Spartan2_ss_reloc (Xilinx_desc * desc, ulong reloc_offset)
return ret_val;
}
#endif

4
common/spartan3.c
View File

@ -30,8 +30,6 @@
#include <common.h> /* core U-Boot definitions */
#include <spartan3.h> /* Spartan-II device family */
#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_SPARTAN3)
/* Define FPGA_DEBUG to get debug printf's */
#ifdef FPGA_DEBUG
#define PRINTF(fmt,args...) printf (fmt ,##args)
@ -668,5 +666,3 @@ static int Spartan3_ss_reloc (Xilinx_desc * desc, ulong reloc_offset)
return ret_val;
}
#endif

4
common/stratixII.c
View File

@ -25,8 +25,6 @@
#include <common.h> /* core U-Boot definitions */
#include <altera.h>
#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ALTERA) && defined(CONFIG_FPGA_STRATIX_II)
int StratixII_ps_fpp_load (Altera_desc * desc, void *buf, size_t bsize,
int isSerial, int isSecure);
int StratixII_ps_fpp_dump (Altera_desc * desc, void *buf, size_t bsize);
@ -231,5 +229,3 @@ int StratixII_ps_fpp_load (Altera_desc * desc, void *buf, size_t bsize,
return FPGA_SUCCESS;
}
#endif /* defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ALTERA) && defined(CONFIG_FPGA_STRATIX_II) */

4
common/usb.c
View File

@ -50,8 +50,6 @@
#include <linux/ctype.h>
#include <asm/byteorder.h>
#if defined(CONFIG_CMD_USB)
#include <usb.h>
#ifdef CONFIG_4xx
#include <asm/4xx_pci.h>
@ -1247,6 +1245,4 @@ int usb_hub_probe(struct usb_device *dev, int ifnum)
return ret;
}
#endif
/* EOF */

5
common/usb_kbd.c
View File

@ -28,8 +28,6 @@
#include <devices.h>
#include <asm/byteorder.h>
#ifdef CONFIG_USB_KEYBOARD
#include <usb.h>
#undef USB_KBD_DEBUG
@ -746,7 +744,4 @@ static int usb_kbd_get_hid_desc(struct usb_device *dev)
}
#endif
#endif /* CONFIG_USB_KEYBOARD */

7
common/usb_storage.c
View File

@ -55,13 +55,9 @@
#include <asm/byteorder.h>
#include <asm/processor.h>
#if defined(CONFIG_CMD_USB)
#include <part.h>
#include <usb.h>
#ifdef CONFIG_USB_STORAGE
#undef USB_STOR_DEBUG
#undef BBB_COMDAT_TRACE
#undef BBB_XPORT_TRACE
@ -1242,6 +1238,3 @@ int usb_stor_get_info(struct usb_device *dev,struct us_data *ss,block_dev_desc_t
USB_STOR_PRINTF("partype: %d\n",dev_desc->part_type);
return 1;
}
#endif /* CONFIG_USB_STORAGE */
#endif

3
common/virtex2.c
View File

@ -31,8 +31,6 @@
#include <common.h>
#include <virtex2.h>
#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_VIRTEX2)
#if 0
#define FPGA_DEBUG
#endif
@ -552,6 +550,5 @@ static int Virtex2_ss_reloc (Xilinx_desc * desc, ulong reloc_offset)
}
return ret_val;
}
#endif
/* vim: set ts=4 tw=78: */

4
common/xilinx.c
View File

@ -32,8 +32,6 @@
#include <spartan2.h>
#include <spartan3.h>
#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_XILINX)
#if 0
#define FPGA_DEBUG
#endif
@ -307,5 +305,3 @@ static int xilinx_validate (Xilinx_desc * desc, char *fn)
return ret_val;
}
#endif /* CONFIG_FPGA && CONFIG_FPGA_XILINX */

4
cpu/arm1136/mx31/generic.c
View File

@ -81,12 +81,12 @@ void mx31_gpio_mux(unsigned long mode)
{
unsigned long reg, shift, tmp;
reg = IOMUXC_BASE + (mode & 0xfc);
reg = IOMUXC_BASE + (mode & 0x1fc);
shift = (~mode & 0x3) * 8;
tmp = __REG(reg);
tmp &= ~(0xff << shift);
tmp |= ((mode >> 8) & 0xff) << shift;
tmp |= ((mode >> IOMUX_MODE_POS) & 0xff) << shift;
__REG(reg) = tmp;
}

Some files were not shown because too many files have changed in this diff Show More