ppc4xx: Update PMC440 board support
This patch brings PMC440 board support up to date: - fix GPIO configuration - add misc_init_f() - use better values for usbact variable - fix USB 2.0 phy reset sequence - shrink BAR2 to save PCI address space - add FDT support Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com> Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Matthias Fuchs
Stefan Roese
parent
75183b1a7f
commit
be27079890
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@ -1,5 +1,5 @@
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/*
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* (C) Copyright 2007-2008
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* (Cg) Copyright 2007-2008
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* Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com.
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* Based on board/amcc/sequoia/sequoia.c
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*
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@ -45,9 +45,11 @@
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DECLARE_GLOBAL_DATA_PTR;
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extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
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extern void __ft_board_setup(void *blob, bd_t *bd);
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ulong flash_get_size(ulong base, int banknum);
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int pci_is_66mhz(void);
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int is_monarch(void);
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int bootstrap_eeprom_read(unsigned dev_addr, unsigned offset,
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uchar *buffer, unsigned cnt);
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@ -107,9 +109,9 @@ int board_early_init_f(void)
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*/
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out32(GPIO0_OR, 0x40000002);
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out32(GPIO0_TCR, 0x4c90011f);
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out32(GPIO0_OSRL, 0x28011400);
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out32(GPIO0_OSRL, 0x28051400);
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out32(GPIO0_OSRH, 0x55005000);
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out32(GPIO0_TSRL, 0x08011400);
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out32(GPIO0_TSRL, 0x08051400);
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out32(GPIO0_TSRH, 0x55005000);
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out32(GPIO0_ISR1L, 0x54000000);
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out32(GPIO0_ISR1H, 0x00000000);
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@ -196,6 +198,23 @@ int board_early_init_f(void)
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return 0;
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}
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#if defined(CONFIG_MISC_INIT_F)
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int misc_init_f(void)
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{
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struct pci_controller hose;
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hose.first_busno = 0;
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hose.last_busno = 0;
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hose.region_count = 0;
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if (getenv("pciearly") && (!is_monarch())) {
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printf("PCI: early target init\n");
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pci_setup_indirect(&hose, PCIX0_CFGADR, PCIX0_CFGDATA);
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pci_target_init(&hose);
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}
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return 0;
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}
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#endif
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/*
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* misc_init_r.
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*/
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@ -207,6 +226,7 @@ int misc_init_r(void)
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unsigned long usb2d0cr = 0;
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unsigned long usb2phy0cr, usb2h0cr = 0;
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unsigned long sdr0_pfc1;
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unsigned long sdr0_srst0, sdr0_srst1;
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char *act = getenv("usbact");
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/*
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@ -256,7 +276,7 @@ int misc_init_r(void)
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/*
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* USB suff...
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*/
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if ((act == NULL || strcmp(act, "hostdev") == 0) &&
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if ((act == NULL || strcmp(act, "host") == 0) &&
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!(in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)){
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/* SDR Setting */
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mfsdr(SDR0_PFC1, sdr0_pfc1);
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@ -290,12 +310,46 @@ int misc_init_r(void)
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mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
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mtsdr(SDR0_USB2H0CR, usb2h0cr);
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/* clear resets */
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/*
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* Take USB out of reset:
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* -Initial status = all cores are in reset
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* -deassert reset to OPB1, P4OPB0, OPB2, PLB42OPB1 OPB2PLB40 cores
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* -wait 1 ms
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* -deassert reset to PHY
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* -wait 1 ms
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* -deassert reset to HOST
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* -wait 4 ms
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* -deassert all other resets
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*/
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mfsdr(SDR0_SRST1, sdr0_srst1);
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sdr0_srst1 &= ~(SDR0_SRST1_OPBA1 | \
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SDR0_SRST1_P4OPB0 | \
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SDR0_SRST1_OPBA2 | \
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SDR0_SRST1_PLB42OPB1 | \
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SDR0_SRST1_OPB2PLB40);
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mtsdr(SDR0_SRST1, sdr0_srst1);
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udelay(1000);
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mfsdr(SDR0_SRST1, sdr0_srst1);
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sdr0_srst1 &= ~SDR0_SRST1_USB20PHY;
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mtsdr(SDR0_SRST1, sdr0_srst1);
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udelay(1000);
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mfsdr(SDR0_SRST0, sdr0_srst0);
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sdr0_srst0 &= ~SDR0_SRST0_USB2H;
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mtsdr(SDR0_SRST0, sdr0_srst0);
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udelay(4000);
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/* finally all the other resets */
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mtsdr(SDR0_SRST1, 0x00000000);
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udelay(1000);
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mtsdr(SDR0_SRST0, 0x00000000);
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if (!(in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)) {
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/* enable power on USB socket */
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out_be32((void*)GPIO1_OR,
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in_be32((void*)GPIO1_OR) & ~GPIO1_USB_PWR_N);
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}
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printf("USB: Host\n");
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} else if ((strcmp(act, "dev") == 0) ||
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@ -547,14 +601,14 @@ void pci_target_init(struct pci_controller *hose)
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out32r(PCIX0_PTM2MS, simple_strtoul(ptmms_str, NULL, 16));
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out32r(PCIX0_PTM2LA, simple_strtoul(ptmla_str, NULL, 16));
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} else {
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/* BAR2: default: 16 MB FPGA + registers */
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out32r(PCIX0_PTM2MS, 0xff000001); /* Memory Size/Attribute */
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/* BAR2: default: 4MB FPGA */
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out32r(PCIX0_PTM2MS, 0xffc00001); /* Memory Size/Attribute */
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out32r(PCIX0_PTM2LA, 0xef000000); /* Local Addr. Reg */
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}
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if (is_monarch()) {
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/* BAR2: map FPGA registers behind system memory at 1GB */
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pci_write_config_dword(0, PCI_BASE_ADDRESS_2, 0x40000008);
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pci_hose_write_config_dword(hose, 0, PCI_BASE_ADDRESS_2, 0x40000008);
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}
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/*
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@ -562,8 +616,8 @@ void pci_target_init(struct pci_controller *hose)
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*/
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/* Program the board's vendor id */
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pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
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CONFIG_SYS_PCI_SUBSYS_VENDORID);
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pci_hose_write_config_word(hose, 0, PCI_SUBSYSTEM_VENDOR_ID,
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CONFIG_SYS_PCI_SUBSYS_VENDORID);
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/* disabled for PMC405 backward compatibility */
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/* Configure command register as bus master */
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@ -571,19 +625,19 @@ void pci_target_init(struct pci_controller *hose)
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/* 240nS PCI clock */
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pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
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pci_hose_write_config_word(hose, 0, PCI_LATENCY_TIMER, 1);
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/* No error reporting */
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pci_write_config_word(0, PCI_ERREN, 0);
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pci_hose_write_config_word(hose, 0, PCI_ERREN, 0);
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pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
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if (!is_monarch()) {
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/* Program the board's subsystem id/classcode */
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pci_write_config_word(0, PCI_SUBSYSTEM_ID,
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CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH);
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pci_write_config_word(0, PCI_CLASS_SUB_CODE,
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CONFIG_SYS_PCI_CLASSCODE_NONMONARCH);
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pci_hose_write_config_word(hose, 0, PCI_SUBSYSTEM_ID,
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CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH);
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pci_hose_write_config_word(hose, 0, PCI_CLASS_SUB_CODE,
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CONFIG_SYS_PCI_CLASSCODE_NONMONARCH);
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/* PCI configuration done: release ERREADY */
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out_be32((void*)GPIO1_OR,
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@ -592,11 +646,14 @@ void pci_target_init(struct pci_controller *hose)
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in_be32((void*)GPIO1_TCR) | GPIO1_PPC_EREADY);
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} else {
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/* Program the board's subsystem id/classcode */
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pci_write_config_word(0, PCI_SUBSYSTEM_ID,
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CONFIG_SYS_PCI_SUBSYS_ID_MONARCH);
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pci_write_config_word(0, PCI_CLASS_SUB_CODE,
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CONFIG_SYS_PCI_CLASSCODE_MONARCH);
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pci_hose_write_config_word(hose, 0, PCI_SUBSYSTEM_ID,
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CONFIG_SYS_PCI_SUBSYS_ID_MONARCH);
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pci_hose_write_config_word(hose, 0, PCI_CLASS_SUB_CODE,
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CONFIG_SYS_PCI_CLASSCODE_MONARCH);
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}
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/* enable host configuration */
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pci_hose_write_config_dword(hose, 0, PCI_BRDGOPT2, 0x00000101);
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}
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#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
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@ -626,6 +683,12 @@ static void wait_for_pci_ready(void)
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{
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int i;
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char *s = getenv("pcidelay");
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/*
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* We have our own handling of the pcidelay variable.
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* Using CONFIG_PCI_BOOTDELAY enables pausing for host
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* and adapter devices. For adapter devices we do not
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* want this.
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*/
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if (s) {
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int ms = simple_strtoul(s, NULL, 10);
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printf("PCI: Waiting for %d ms\n", ms);
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@ -851,7 +914,7 @@ int usb_board_init(void)
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char *act = getenv("usbact");
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int i;
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if ((act == NULL || strcmp(act, "hostdev") == 0) &&
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if ((act == NULL || strcmp(act, "host") == 0) &&
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!(in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT))
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/* enable power on USB socket */
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out_be32((void*)GPIO1_OR,
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@ -876,3 +939,24 @@ int usb_board_init_fail(void)
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return 0;
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}
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#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT) */
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#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
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void ft_board_setup(void *blob, bd_t *bd)
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{
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int rc;
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__ft_board_setup(blob, bd);
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/*
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* Disable PCI in non-monarch mode.
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*/
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if (!is_monarch()) {
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rc = fdt_find_and_setprop(blob, "/plb/pci@1ec000000", "status",
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"disabled", sizeof("disabled"), 1);
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if (rc) {
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printf("Unable to update property status in PCI node, err=%s\n",
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fdt_strerror(rc));
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}
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}
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}
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#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
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