From 205a0988d8fd778c60746c34c2f17dbd2b7cd0d2 Mon Sep 17 00:00:00 2001 From: Prafulla Wadaskar Date: Mon, 29 Jun 2009 15:25:18 +0530 Subject: [PATCH 01/12] nand: Add Marvell Kirkwood NAND driver This patch adds a NAND driver for the Marvell Kirkwood SoC's Signed-off-by: Prafulla Wadaskar Acked-by: Scott Wood --- drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/kirkwood_nand.c | 82 ++++++++++++++++++++++++++++++++ 2 files changed, 83 insertions(+) create mode 100644 drivers/mtd/nand/kirkwood_nand.c diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index 71dd5b9b8..d4d394853 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -40,6 +40,7 @@ COBJS-$(CONFIG_DRIVER_NAND_BFIN) += bfin_nand.o COBJS-$(CONFIG_NAND_DAVINCI) += davinci_nand.o COBJS-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_nand.o COBJS-$(CONFIG_NAND_FSL_UPM) += fsl_upm.o +COBJS-$(CONFIG_NAND_KIRKWOOD) += kirkwood_nand.o COBJS-$(CONFIG_NAND_MPC5121_NFC) += mpc5121_nfc.o COBJS-$(CONFIG_NAND_NOMADIK) += nomadik.o COBJS-$(CONFIG_NAND_S3C2410) += s3c2410_nand.c diff --git a/drivers/mtd/nand/kirkwood_nand.c b/drivers/mtd/nand/kirkwood_nand.c new file mode 100644 index 000000000..376378ed3 --- /dev/null +++ b/drivers/mtd/nand/kirkwood_nand.c @@ -0,0 +1,82 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor + * Written-by: Prafulla Wadaskar + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +/* NAND Flash Soc registers */ +struct kwnandf_registers { + u32 rd_params; /* 0x10418 */ + u32 wr_param; /* 0x1041c */ + u8 pad[0x10470 - 0x1041c - 4]; + u32 ctrl; /* 0x10470 */ +}; + +static struct kwnandf_registers *nf_reg = + (struct kwnandf_registers *)KW_NANDF_BASE; + +/* + * hardware specific access to control-lines/bits + */ +#define NAND_ACTCEBOOT_BIT 0x02 + +static void kw_nand_hwcontrol(struct mtd_info *mtd, int cmd, + unsigned int ctrl) +{ + struct nand_chip *nc = mtd->priv; + u32 offs; + + if (cmd == NAND_CMD_NONE) + return; + + if (ctrl & NAND_CLE) + offs = (1 << 0); /* Commands with A[1:0] == 01 */ + else if (ctrl & NAND_ALE) + offs = (1 << 1); /* Addresses with A[1:0] == 10 */ + else + return; + + writeb(cmd, nc->IO_ADDR_W + offs); +} + +void kw_nand_select_chip(struct mtd_info *mtd, int chip) +{ + u32 data; + + data = readl(&nf_reg->ctrl); + data |= NAND_ACTCEBOOT_BIT; + writel(data, &nf_reg->ctrl); +} + +int board_nand_init(struct nand_chip *nand) +{ + nand->options = NAND_COPYBACK | NAND_CACHEPRG | NAND_NO_PADDING; + nand->ecc.mode = NAND_ECC_SOFT; + nand->cmd_ctrl = kw_nand_hwcontrol; + nand->chip_delay = 30; + nand->select_chip = kw_nand_select_chip; + return 0; +} From b996165f5a1623a055c03b22d64d6d5da81835d0 Mon Sep 17 00:00:00 2001 From: Prafulla Wadaskar Date: Mon, 6 Jul 2009 15:50:47 +0530 Subject: [PATCH 02/12] arm: Kirkwood: bugfix: UART1 bar correction Signed-off-by: Prafulla Wadaskar --- include/asm-arm/arch-kirkwood/kirkwood.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/asm-arm/arch-kirkwood/kirkwood.h b/include/asm-arm/arch-kirkwood/kirkwood.h index 52dafc22c..47679dd44 100644 --- a/include/asm-arm/arch-kirkwood/kirkwood.h +++ b/include/asm-arm/arch-kirkwood/kirkwood.h @@ -45,7 +45,7 @@ #define KW_REG_UNDOC_0x1478 (KW_REGISTER(0x1478)) #define KW_UART0_BASE (KW_REGISTER(0x12000)) -#define KW_UART1_BASE (KW_REGISTER(0x13000)) +#define KW_UART1_BASE (KW_REGISTER(0x12100)) #define KW_MPP_BASE (KW_REGISTER(0x10000)) #define KW_GPIO0_BASE (KW_REGISTER(0x10100)) #define KW_GPIO1_BASE (KW_REGISTER(0x10140)) From 67c97c346b27c586a7263564f7afff6d1f8d8d0a Mon Sep 17 00:00:00 2001 From: Grazvydas Ignotas Date: Wed, 8 Jul 2009 00:29:58 +0300 Subject: [PATCH 03/12] OMAP3 pandora: pin mux cleanup Remove configuration of not unused pins, effectively leaving them in safe mode. --- board/omap3/pandora/pandora.h | 25 ------------------------- 1 file changed, 25 deletions(-) diff --git a/board/omap3/pandora/pandora.h b/board/omap3/pandora/pandora.h index 8f0838c0a..3d04b2ad1 100644 --- a/board/omap3/pandora/pandora.h +++ b/board/omap3/pandora/pandora.h @@ -107,15 +107,6 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\ MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\ MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\ - MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\ - MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/\ - MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0))\ - MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M1))\ - MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M1))\ - MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0))\ - MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0))\ MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\ MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\ MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\ @@ -254,16 +245,10 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(CAM_WEN), (IEN | PTU | DIS | M4)) /*GPIO_167*/\ /* - nIRQ_NUB2*/\ /*Various other stuff*/\ - MUX_VAL(CP(CAM_VS), (IEN | PTU | DIS | M4)) /*GPIO_95*/\ - /* - nTOUCH_BUSY*/\ MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | DIS | M4)) /*GPIO_163*/\ /* - nOC_USB5*/\ - MUX_VAL(CP(MCBSP1_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_162*/\ - /* - START_ADC*/\ MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | DIS | M4)) /*GPIO_22*/\ /* - MSECURE*/\ - MUX_VAL(CP(CAM_STROBE), (IEN | PTU | DIS | M4)) /*GPIO_126*/\ - /* - HP_DETECT*/\ /*External Resets and Enables*/\ MUX_VAL(CP(ETK_D0_ES2), (IDIS | PTD | DIS | M4)) /*GPIO_14*/\ /* - nHDPHN_SHUTDOWN*/\ @@ -277,14 +262,6 @@ const omap3_sysinfo sysinfo = { /* - RESET_NUBS*/\ MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTU | EN | M4)) /*GPIO_164*/\ /* - EN_USB_5V*/\ - /*Unused*/\ - MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M0)) /*HDQ_SIO - NC*/\ - MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) /*CSI2_DX0 - NC*/\ - MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) /*CSI2_DY0 - NC*/\ - MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) /*CSI2_DX1 - NC*/\ - MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) /*CSI2_DY1 - NC*/\ - MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) /*I2C2_SCL - NC*/\ - MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) /*I2C2_SDA - NC*/\ /*HS USB OTG Port (connects to HSUSB0)*/\ MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\ MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) /*HSUSB0_STP*/\ @@ -338,8 +315,6 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\ MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4)) /*GPIO_8*/\ MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE*/\ - MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M4)) /*SYS_CLKOUT1 - NC*/\ - MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTD | DIS | M4)) /*SYS_CLKOUT2 - NC*/\ /*JTAG*/\ MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) /*JTAG_nTRST*/\ MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /*JTAG_TCK*/\ From 5ff78122f229946862a3f67a2f50a329e8e1bcf5 Mon Sep 17 00:00:00 2001 From: Grazvydas Ignotas Date: Wed, 8 Jul 2009 00:29:59 +0300 Subject: [PATCH 04/12] OMAP3 pandora: setup pin mux for pins used on rev3 boards Setup pin mux for GPIO pins connected on rev3 or later boards. Also change NUB2 IRQ pin. This should not affect older boards because they don't have any nubs (analog controllers) attached to them. --- board/omap3/pandora/pandora.h | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/board/omap3/pandora/pandora.h b/board/omap3/pandora/pandora.h index 3d04b2ad1..1bd3d30c6 100644 --- a/board/omap3/pandora/pandora.h +++ b/board/omap3/pandora/pandora.h @@ -242,13 +242,15 @@ const omap3_sysinfo sysinfo = { /* - WIFI_IRQ*/\ MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M4)) /*GPIO_161*/\ /* - nIRQ_NUB1*/\ - MUX_VAL(CP(CAM_WEN), (IEN | PTU | DIS | M4)) /*GPIO_167*/\ + MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTU | DIS | M4)) /*GPIO_162*/\ /* - nIRQ_NUB2*/\ /*Various other stuff*/\ MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | DIS | M4)) /*GPIO_163*/\ /* - nOC_USB5*/\ MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | DIS | M4)) /*GPIO_22*/\ /* - MSECURE*/\ + MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M4)) /*GPIO_115*/\ + /* - POP_OVERHEAT*/\ /*External Resets and Enables*/\ MUX_VAL(CP(ETK_D0_ES2), (IDIS | PTD | DIS | M4)) /*GPIO_14*/\ /* - nHDPHN_SHUTDOWN*/\ @@ -262,6 +264,13 @@ const omap3_sysinfo sysinfo = { /* - RESET_NUBS*/\ MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTU | EN | M4)) /*GPIO_164*/\ /* - EN_USB_5V*/\ + /*Spare GPIOs*/\ + MUX_VAL(CP(GPMC_NCS7), (IEN | PTD | EN | M4)) /*GPIO_58*/\ + MUX_VAL(CP(GPMC_WAIT2), (IEN | PTD | EN | M4)) /*GPIO_64*/\ + MUX_VAL(CP(GPMC_WAIT3), (IEN | PTD | EN | M4)) /*GPIO_65*/\ + MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M4)) /*GPIO_95*/\ + MUX_VAL(CP(CAM_WEN), (IEN | PTD | EN | M4)) /*GPIO_167*/\ + MUX_VAL(CP(HDQ_SIO), (IEN | PTD | EN | M4)) /*GPIO_170*/\ /*HS USB OTG Port (connects to HSUSB0)*/\ MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\ MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) /*HSUSB0_STP*/\ From 8672c288703f3c51c829851c8fe6608c7869faaa Mon Sep 17 00:00:00 2001 From: Grazvydas Ignotas Date: Wed, 8 Jul 2009 00:30:00 +0300 Subject: [PATCH 05/12] OMAP3 pandora: setup pulls for various GPIOs Set pullups or pulldowns for GPIOs which need them. Disable them for others, which have external pulls. Also make disabled pull setting consistent (some pins had type set to "up" even if pull type selection was disabled). --- board/omap3/pandora/pandora.h | 50 +++++++++++++++++------------------ 1 file changed, 25 insertions(+), 25 deletions(-) diff --git a/board/omap3/pandora/pandora.h b/board/omap3/pandora/pandora.h index 1bd3d30c6..dfaf32f67 100644 --- a/board/omap3/pandora/pandora.h +++ b/board/omap3/pandora/pandora.h @@ -145,26 +145,26 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\ MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\ /*GPIO based game buttons*/\ - MUX_VAL(CP(CAM_XCLKA), (IEN | PTU | DIS | M4)) /*GPIO_96 - LEFT*/\ - MUX_VAL(CP(CAM_PCLK), (IEN | PTU | DIS | M4)) /*GPIO_97 - L2*/\ - MUX_VAL(CP(CAM_FLD), (IEN | PTU | DIS | M4)) /*GPIO_98 - RIGHT*/\ - MUX_VAL(CP(CAM_D0), (IEN | PTU | DIS | M4)) /*GPIO_99 - MENU*/\ - MUX_VAL(CP(CAM_D1), (IEN | PTU | DIS | M4)) /*GPIO_100 - START*/\ - MUX_VAL(CP(CAM_D2), (IEN | PTU | DIS | M4)) /*GPIO_101 - Y*/\ - MUX_VAL(CP(CAM_D3), (IEN | PTU | DIS | M4)) /*GPIO_102 - L1*/\ - MUX_VAL(CP(CAM_D4), (IEN | PTU | DIS | M4)) /*GPIO_103 - DOWN*/\ - MUX_VAL(CP(CAM_D5), (IEN | PTU | DIS | M4)) /*GPIO_104 - SELECT*/\ - MUX_VAL(CP(CAM_D6), (IEN | PTU | DIS | M4)) /*GPIO_105 - R1*/\ - MUX_VAL(CP(CAM_D7), (IEN | PTU | DIS | M4)) /*GPIO_106 - B*/\ - MUX_VAL(CP(CAM_D8), (IEN | PTU | DIS | M4)) /*GPIO_107 - R2*/\ - MUX_VAL(CP(CAM_D10), (IEN | PTU | DIS | M4)) /*GPIO_109 - X*/\ - MUX_VAL(CP(CAM_D11), (IEN | PTU | DIS | M4)) /*GPIO_110 - UP*/\ - MUX_VAL(CP(CAM_XCLKB), (IEN | PTU | DIS | M4)) /*GPIO_111 - A*/\ + MUX_VAL(CP(CAM_XCLKA), (IEN | PTD | DIS | M4)) /*GPIO_96 - LEFT*/\ + MUX_VAL(CP(CAM_PCLK), (IEN | PTD | DIS | M4)) /*GPIO_97 - L2*/\ + MUX_VAL(CP(CAM_FLD), (IEN | PTD | DIS | M4)) /*GPIO_98 - RIGHT*/\ + MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M4)) /*GPIO_99 - MENU*/\ + MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M4)) /*GPIO_100 - START*/\ + MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M4)) /*GPIO_101 - Y*/\ + MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M4)) /*GPIO_102 - L1*/\ + MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M4)) /*GPIO_103 - DOWN*/\ + MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M4)) /*GPIO_104 - SELECT*/\ + MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M4)) /*GPIO_105 - R1*/\ + MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M4)) /*GPIO_106 - B*/\ + MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M4)) /*GPIO_107 - R2*/\ + MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M4)) /*GPIO_109 - X*/\ + MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M4)) /*GPIO_110 - UP*/\ + MUX_VAL(CP(CAM_XCLKB), (IEN | PTD | DIS | M4)) /*GPIO_111 - A*/\ /*Audio Interface To External DAC (Headphone, Speakers)*/\ MUX_VAL(CP(MCBSP2_FSX), (IDIS | PTD | DIS | M0)) /*McBSP2_FSX*/\ MUX_VAL(CP(MCBSP2_CLKX), (IDIS | PTD | DIS | M0)) /*McBSP2_CLKX*/\ MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\ - MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) /*McBSP_CLKS*/\ + MUX_VAL(CP(MCBSP_CLKS), (IEN | PTD | DIS | M0)) /*McBSP_CLKS*/\ MUX_VAL(CP(MCBSP2_DR), (IDIS | PTD | DIS | M4)) /*GPIO_118*/\ /* - nPOWERDOWN_DAC*/\ /*Expansion card 1*/\ @@ -210,13 +210,13 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(MCBSP4_DX), (IDIS | PTD | DIS | M0)) /*McBSP4_DX*/\ MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M0)) /*McBSP4_FSX*/\ /*GPIO definitions for muxed pins on AV connector*/\ - MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M4)) /*GPIO_144,*/\ + MUX_VAL(CP(UART2_CTS), (IEN | PTD | EN | M4)) /*GPIO_144,*/\ /*UART2_CTS*/\ - MUX_VAL(CP(UART2_RTS), (IEN | PTU | DIS | M4)) /*GPIO_145,*/\ + MUX_VAL(CP(UART2_RTS), (IEN | PTD | EN | M4)) /*GPIO_145,*/\ /*UART2_RTS*/\ - MUX_VAL(CP(UART2_TX), (IEN | PTU | EN | M4)) /*GPIO_146,*/\ + MUX_VAL(CP(UART2_TX), (IEN | PTD | EN | M4)) /*GPIO_146,*/\ /*UART2_TX*/\ - MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M4)) /*GPIO_147,*/\ + MUX_VAL(CP(UART2_RX), (IEN | PTD | EN | M4)) /*GPIO_147,*/\ /*UART2_RX*/\ /*Serial Interface (Peripheral boot, Linux console, on AV connector)*/\ MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /*UART3_RX*/\ @@ -231,18 +231,18 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(MCBSP1_DR), (IDIS | PTD | DIS | M4)) /*GPIO_159*/\ /* - LED_WIFI*/\ /*Switches*/\ - MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | DIS | M4)) /*GPIO_176*/\ + MUX_VAL(CP(MCSPI1_CS2), (IEN | PTD | DIS | M4)) /*GPIO_176*/\ /* - nHOLD_SWITCH*/\ - MUX_VAL(CP(CAM_D9), (IEN | PTU | DIS | M4)) /*GPIO_108*/\ + MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M4)) /*GPIO_108*/\ /* - nLID_SWITCH*/\ /*External IRQs*/\ - MUX_VAL(CP(CAM_HS), (IEN | PTU | DIS | M4)) /*GPIO_94*/\ + MUX_VAL(CP(CAM_HS), (IEN | PTD | DIS | M4)) /*GPIO_94*/\ /* - nTOUCH_IRQ*/\ MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | DIS | M4)) /*GPIO_21*/\ /* - WIFI_IRQ*/\ MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M4)) /*GPIO_161*/\ /* - nIRQ_NUB1*/\ - MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTU | DIS | M4)) /*GPIO_162*/\ + MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M4)) /*GPIO_162*/\ /* - nIRQ_NUB2*/\ /*Various other stuff*/\ MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | DIS | M4)) /*GPIO_163*/\ @@ -262,7 +262,7 @@ const omap3_sysinfo sysinfo = { /* - nLCD_RESET*/\ MUX_VAL(CP(MCBSP1_CLKR), (IDIS | PTD | DIS | M4)) /*GPIO_156*/\ /* - RESET_NUBS*/\ - MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTU | EN | M4)) /*GPIO_164*/\ + MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M4)) /*GPIO_164*/\ /* - EN_USB_5V*/\ /*Spare GPIOs*/\ MUX_VAL(CP(GPMC_NCS7), (IEN | PTD | EN | M4)) /*GPIO_58*/\ From b016000a95514c08cab50e1cba00b019c0801bc4 Mon Sep 17 00:00:00 2001 From: Grazvydas Ignotas Date: Wed, 8 Jul 2009 00:30:01 +0300 Subject: [PATCH 06/12] OMAP3 pandora: Fix CKE1 MUX setting to allow self-refresh Pandora is using both SDRC CSes. The MUX setting is needed for the second CS clock signal to allow the 2 RAM parts to be put in self-refresh correctly. Based on similar patch for beagle and overo by Jean Pihet and Steve Sakoman. --- board/omap3/pandora/pandora.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/omap3/pandora/pandora.h b/board/omap3/pandora/pandora.h index dfaf32f67..f06ee5be4 100644 --- a/board/omap3/pandora/pandora.h +++ b/board/omap3/pandora/pandora.h @@ -396,6 +396,6 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_mbusflag*/\ MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_sbusflag*/\ MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\ - MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)) /*sdrc_cke1*/ + MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /*sdrc_cke1*/ #endif From bd876be46f28b5fc2896537f6d01353f332789f7 Mon Sep 17 00:00:00 2001 From: Daniel Mack Date: Tue, 23 Jun 2009 17:30:04 +0200 Subject: [PATCH 07/12] pxa: add clock for system bus 2 arbiter This clock is needed for systems using the USB2 device unit or the 2d graphics accelerator. Signed-off-by: Daniel Mack --- include/asm-arm/arch-pxa/pxa-regs.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h index 5a0885aef..1f81e1187 100644 --- a/include/asm-arm/arch-pxa/pxa-regs.h +++ b/include/asm-arm/arch-pxa/pxa-regs.h @@ -1952,6 +1952,7 @@ typedef void (*ExcpHndlr) (void) ; #define CKENA_2_USBHOST (1 << 2) /* USB Host Unit Clock Enable */ #define CKENA_1_LCD (1 << 1) /* LCD Unit Clock Enable */ +#define CKENB_9_SYSBUS2 (1 << 9) /* System bus 2 */ #define CKENB_8_1WIRE ((1 << 8) + 32) /* One Wire Interface Unit Clock Enable */ #define CKENB_7_GPIO ((1 << 7) + 32) /* GPIO Clock Enable */ #define CKENB_6_IRQ ((1 << 6) + 32) /* Interrupt Controller Clock Enable */ From c33c5990cec7ced9ef1ef148debbca34adafa12b Mon Sep 17 00:00:00 2001 From: Daniel Mack Date: Tue, 23 Jun 2009 17:30:05 +0200 Subject: [PATCH 08/12] pxa: fix CKEN_B register bits The current defition for CKEN_B register bits is nonsense. Adding 32 to the shifted value is equal to '| (1 << 5)', and this bit is marked 'reserved' in the PXA docs. Signed-off-by: Daniel Mack --- include/asm-arm/arch-pxa/pxa-regs.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h index 1f81e1187..2a723dcea 100644 --- a/include/asm-arm/arch-pxa/pxa-regs.h +++ b/include/asm-arm/arch-pxa/pxa-regs.h @@ -1953,12 +1953,12 @@ typedef void (*ExcpHndlr) (void) ; #define CKENA_1_LCD (1 << 1) /* LCD Unit Clock Enable */ #define CKENB_9_SYSBUS2 (1 << 9) /* System bus 2 */ -#define CKENB_8_1WIRE ((1 << 8) + 32) /* One Wire Interface Unit Clock Enable */ -#define CKENB_7_GPIO ((1 << 7) + 32) /* GPIO Clock Enable */ -#define CKENB_6_IRQ ((1 << 6) + 32) /* Interrupt Controller Clock Enable */ -#define CKENB_4_I2C ((1 << 4) + 32) /* I2C Unit Clock Enable */ -#define CKENB_1_PWM1 ((1 << 1) + 32) /* PWM2 & PWM3 Clock Enable */ -#define CKENB_0_PWM0 ((1 << 0) + 32) /* PWM0 & PWM1 Clock Enable */ +#define CKENB_8_1WIRE (1 << 8) /* One Wire Interface Unit Clock Enable */ +#define CKENB_7_GPIO (1 << 7) /* GPIO Clock Enable */ +#define CKENB_6_IRQ (1 << 6) /* Interrupt Controller Clock Enable */ +#define CKENB_4_I2C (1 << 4) /* I2C Unit Clock Enable */ +#define CKENB_1_PWM1 (1 << 1) /* PWM2 & PWM3 Clock Enable */ +#define CKENB_0_PWM0 (1 << 0) /* PWM0 & PWM1 Clock Enable */ #else /* if defined CONFIG_CPU_MONAHANS */ From 22ee647380c42f44528f99b7c1b423725e542102 Mon Sep 17 00:00:00 2001 From: Sedji Gaouaou Date: Thu, 9 Jul 2009 10:16:29 +0200 Subject: [PATCH 09/12] at91: Introduction of at91sam9g45 SOC. AT91sam9g45 series is an ARM 926ej-s SOC family clocked at 400/133MHz. It embeds USB high speed host and device, LCD, DDR2 RAM, and a full set of peripherals. The first board that embeds at91sam9g45 chip is the AT91SAM9G45-EKES. On the board you can find 2 USART, USB high speed, a 480*272 LG lcd, ethernet, gpio/joystick/buttons. Signed-off-by: Sedji Gaouaou --- MAINTAINERS | 3 + MAKEALL | 37 +- Makefile | 25 ++ board/atmel/at91sam9m10g45ek/Makefile | 55 +++ .../atmel/at91sam9m10g45ek/at91sam9m10g45ek.c | 334 ++++++++++++++++++ board/atmel/at91sam9m10g45ek/config.mk | 1 + board/atmel/at91sam9m10g45ek/led.c | 41 +++ cpu/arm926ejs/at91/Makefile | 2 + cpu/arm926ejs/at91/at91sam9m10g45_devices.c | 175 +++++++++ cpu/arm926ejs/at91/clock.c | 12 +- doc/README.at91 | 20 ++ drivers/net/macb.c | 6 +- include/asm-arm/arch-at91/at91_pmc.h | 1 + include/asm-arm/arch-at91/at91sam9_matrix.h | 2 + include/asm-arm/arch-at91/at91sam9g45.h | 139 ++++++++ .../asm-arm/arch-at91/at91sam9g45_matrix.h | 153 ++++++++ include/asm-arm/arch-at91/clk.h | 5 + include/asm-arm/arch-at91/hardware.h | 6 + include/asm-arm/arch-at91/memory-map.h | 1 + include/configs/at91sam9m10g45ek.h | 225 ++++++++++++ 20 files changed, 1221 insertions(+), 22 deletions(-) create mode 100644 board/atmel/at91sam9m10g45ek/Makefile create mode 100644 board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c create mode 100644 board/atmel/at91sam9m10g45ek/config.mk create mode 100644 board/atmel/at91sam9m10g45ek/led.c create mode 100644 cpu/arm926ejs/at91/at91sam9m10g45_devices.c create mode 100644 include/asm-arm/arch-at91/at91sam9g45.h create mode 100644 include/asm-arm/arch-at91/at91sam9g45_matrix.h create mode 100644 include/configs/at91sam9m10g45ek.h diff --git a/MAINTAINERS b/MAINTAINERS index 705bac5a7..5a8f12c23 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -547,6 +547,9 @@ Daniel Gorsulowski meesc ARM926EJS (AT91SAM9263 SoC) +Sedji Gaouaou + at91sam9m10g45ek ARM926EJS (AT91SAM9G45 SoC) + Marius Gröger impa7 ARM720T (EP7211) diff --git a/MAKEALL b/MAKEALL index 41f144553..03ef5b45c 100755 --- a/MAKEALL +++ b/MAKEALL @@ -578,24 +578,25 @@ LIST_ARM_CORTEX_A8=" \ ## AT91 Systems ######################################################################### -LIST_at91=" \ - afeb9260 \ - at91cap9adk \ - at91rm9200dk \ - at91rm9200ek \ - at91sam9260ek \ - at91sam9261ek \ - at91sam9263ek \ - at91sam9g20ek \ - at91sam9rlek \ - cmc_pu2 \ - csb637 \ - kb9202 \ - meesc \ - mp2usb \ - m501sk \ - pm9261 \ - pm9263 \ +LIST_at91=" \ + afeb9260 \ + at91cap9adk \ + at91rm9200dk \ + at91rm9200ek \ + at91sam9260ek \ + at91sam9261ek \ + at91sam9263ek \ + at91sam9m10g45ek \ + at91sam9g20ek \ + at91sam9rlek \ + cmc_pu2 \ + csb637 \ + kb9202 \ + meesc \ + mp2usb \ + m501sk \ + pm9261 \ + pm9263 \ " ######################################################################### diff --git a/Makefile b/Makefile index 2a0644024..55a9648d7 100644 --- a/Makefile +++ b/Makefile @@ -2800,6 +2800,31 @@ meesc_config : unconfig pm9261_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm926ejs pm9261 ronetix at91 +at91sam9m10g45ek_nandflash_config \ +at91sam9m10g45ek_dataflash_config \ +at91sam9m10g45ek_dataflash_cs0_config \ +at91sam9m10g45ek_config \ +at91sam9g45ekes_nandflash_config \ +at91sam9g45ekes_dataflash_config \ +at91sam9g45ekes_dataflash_cs0_config \ +at91sam9g45ekes_config : unconfig + @mkdir -p $(obj)include + @if [ "$(findstring 9m10,$@)" ] ; then \ + echo "#define CONFIG_AT91SAM9M10G45EK 1" >>$(obj)include/config.h ; \ + $(XECHO) "... 9M10G45 Variant" ; \ + else \ + echo "#define CONFIG_AT91SAM9G45EKES 1" >>$(obj)include/config.h ; \ + fi; + + @if [ "$(findstring _nandflash,$@)" ] ; then \ + echo "#define CONFIG_SYS_USE_NANDFLASH 1" >>$(obj)include/config.h ; \ + $(XECHO) "... with environment variable in NAND FLASH" ; \ + else \ + echo "#define CONFIG_ATMEL_SPI 1" >>$(obj)include/config.h ; \ + $(XECHO) "... with environment variable in SPI DATAFLASH CS0" ; \ + fi; + @$(MKCONFIG) -a at91sam9m10g45ek arm arm926ejs at91sam9m10g45ek atmel at91 + pm9263_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm926ejs pm9263 ronetix at91 diff --git a/board/atmel/at91sam9m10g45ek/Makefile b/board/atmel/at91sam9m10g45ek/Makefile new file mode 100644 index 000000000..4caf1e416 --- /dev/null +++ b/board/atmel/at91sam9m10g45ek/Makefile @@ -0,0 +1,55 @@ +# +# (C) Copyright 2003-2008 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2008 +# Stelian Pop +# Lead Tech Design +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y += at91sam9m10g45ek.o +COBJS-y += led.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c new file mode 100644 index 000000000..45a14a95f --- /dev/null +++ b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c @@ -0,0 +1,334 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop + * Lead Tech Design + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) +#include +#endif +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* ------------------------------------------------------------------------- */ +/* + * Miscelaneous platform dependent initialisations + */ + +#ifdef CONFIG_CMD_NAND +static void at91sam9m10g45ek_nand_hw_init(void) +{ + unsigned long csa; + + /* Enable CS3 */ + csa = at91_sys_read(AT91_MATRIX_EBICSA); + at91_sys_write(AT91_MATRIX_EBICSA, + csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA); + + /* Configure SMC CS3 for NAND/SmartMedia */ + at91_sys_write(AT91_SMC_SETUP(3), + AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) | + AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0)); + at91_sys_write(AT91_SMC_PULSE(3), + AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(3) | + AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(2)); + at91_sys_write(AT91_SMC_CYCLE(3), + AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(4)); + at91_sys_write(AT91_SMC_MODE(3), + AT91_SMC_READMODE | AT91_SMC_WRITEMODE | + AT91_SMC_EXNWMODE_DISABLE | +#ifdef CONFIG_SYS_NAND_DBW_16 + AT91_SMC_DBW_16 | +#else /* CONFIG_SYS_NAND_DBW_8 */ + AT91_SMC_DBW_8 | +#endif + AT91_SMC_TDF_(3)); + + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_PIOC); + + /* Configure RDY/BSY */ + at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); + + /* Enable NandFlash */ + at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); +} +#endif + +#ifdef CONFIG_MACB +static void at91sam9m10g45ek_macb_hw_init(void) +{ + unsigned long rstc; + + /* Enable clock */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_EMAC); + + /* + * Disable pull-up on: + * RXDV (PA15) => PHY normal mode (not Test mode) + * ERX0 (PA12) => PHY ADDR0 + * ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0 + * + * PHY has internal pull-down + */ + writel(pin_to_mask(AT91_PIN_PA15) | + pin_to_mask(AT91_PIN_PA12) | + pin_to_mask(AT91_PIN_PA13), + pin_to_controller(AT91_PIN_PA0) + PIO_PUDR); + + rstc = at91_sys_read(AT91_RSTC_MR); + + /* Need to reset PHY -> 500ms reset */ + at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | + (AT91_RSTC_ERSTL & (0x0D << 8)) | + AT91_RSTC_URSTEN); + + at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST); + + /* Wait for end hardware reset */ + while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL)); + + /* Restore NRST value */ + at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | + (rstc) | + AT91_RSTC_URSTEN); + + /* Re-enable pull-up */ + writel(pin_to_mask(AT91_PIN_PA15) | + pin_to_mask(AT91_PIN_PA12) | + pin_to_mask(AT91_PIN_PA13), + pin_to_controller(AT91_PIN_PA0) + PIO_PUER); + + at91_macb_hw_init(); +} +#endif + +#ifdef CONFIG_LCD + +vidinfo_t panel_info = { + vl_col: 480, + vl_row: 272, + vl_clk: 9000000, + vl_sync: ATMEL_LCDC_INVLINE_NORMAL | + ATMEL_LCDC_INVFRAME_NORMAL, + vl_bpix: 3, + vl_tft: 1, + vl_hsync_len: 45, + vl_left_margin: 1, + vl_right_margin:1, + vl_vsync_len: 1, + vl_upper_margin:40, + vl_lower_margin:1, + mmio: AT91SAM9G45_LCDC_BASE, +}; + + +void lcd_enable(void) +{ + at91_set_A_periph(AT91_PIN_PE6, 1); /* power up */ +} + +void lcd_disable(void) +{ + at91_set_A_periph(AT91_PIN_PE6, 0); /* power down */ +} + +static void at91sam9m10g45ek_lcd_hw_init(void) +{ + at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */ + at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */ + at91_set_A_periph(AT91_PIN_PE3, 0); /* LCDVSYNC */ + at91_set_A_periph(AT91_PIN_PE4, 0); /* LCDHSYNC */ + at91_set_A_periph(AT91_PIN_PE5, 0); /* LCDDOTCK */ + + at91_set_A_periph(AT91_PIN_PE7, 0); /* LCDD0 */ + at91_set_A_periph(AT91_PIN_PE8, 0); /* LCDD1 */ + at91_set_A_periph(AT91_PIN_PE9, 0); /* LCDD2 */ + at91_set_A_periph(AT91_PIN_PE10, 0); /* LCDD3 */ + at91_set_A_periph(AT91_PIN_PE11, 0); /* LCDD4 */ + at91_set_A_periph(AT91_PIN_PE12, 0); /* LCDD5 */ + at91_set_A_periph(AT91_PIN_PE13, 0); /* LCDD6 */ + at91_set_A_periph(AT91_PIN_PE14, 0); /* LCDD7 */ + at91_set_A_periph(AT91_PIN_PE15, 0); /* LCDD8 */ + at91_set_A_periph(AT91_PIN_PE16, 0); /* LCDD9 */ + at91_set_A_periph(AT91_PIN_PE17, 0); /* LCDD10 */ + at91_set_A_periph(AT91_PIN_PE18, 0); /* LCDD11 */ + at91_set_A_periph(AT91_PIN_PE19, 0); /* LCDD12 */ + at91_set_B_periph(AT91_PIN_PE20, 0); /* LCDD13 */ + at91_set_A_periph(AT91_PIN_PE21, 0); /* LCDD14 */ + at91_set_A_periph(AT91_PIN_PE22, 0); /* LCDD15 */ + at91_set_A_periph(AT91_PIN_PE23, 0); /* LCDD16 */ + at91_set_A_periph(AT91_PIN_PE24, 0); /* LCDD17 */ + at91_set_A_periph(AT91_PIN_PE25, 0); /* LCDD18 */ + at91_set_A_periph(AT91_PIN_PE26, 0); /* LCDD19 */ + at91_set_A_periph(AT91_PIN_PE27, 0); /* LCDD20 */ + at91_set_B_periph(AT91_PIN_PE28, 0); /* LCDD21 */ + at91_set_A_periph(AT91_PIN_PE29, 0); /* LCDD22 */ + at91_set_A_periph(AT91_PIN_PE30, 0); /* LCDD23 */ + + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_LCDC); + + gd->fb_base = CONFIG_AT91SAM9G45_LCD_BASE; +} + +#ifdef CONFIG_LCD_INFO +#include +#include + +void lcd_show_board_info(void) +{ + ulong dram_size, nand_size; + int i; + char temp[32]; + + lcd_printf ("%s\n", U_BOOT_VERSION); + lcd_printf ("(C) 2008 ATMEL Corp\n"); + lcd_printf ("at91support@atmel.com\n"); + lcd_printf ("%s CPU at %s MHz\n", + AT91_CPU_NAME, + strmhz(temp, get_cpu_clk_rate())); + + dram_size = 0; + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) + dram_size += gd->bd->bi_dram[i].size; + nand_size = 0; + for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) + nand_size += nand_info[i].size; + lcd_printf (" %ld MB SDRAM, %ld MB NAND\n", + dram_size >> 20, + nand_size >> 20 ); +} +#endif /* CONFIG_LCD_INFO */ +#endif + +int board_init(void) +{ + /* Enable Ctrlc */ + console_init_f(); + + /* arch number of AT91SAM9M10G45EK-Board */ +#ifdef CONFIG_AT91SAM9M10G45EK + gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9M10G45EK; +#elif defined CONFIG_AT91SAM9G45EKES + gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G45EKES; +#endif + /* adress of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + at91_serial_hw_init(); +#ifdef CONFIG_CMD_NAND + at91sam9m10g45ek_nand_hw_init(); +#endif +#ifdef CONFIG_HAS_DATAFLASH + at91_spi0_hw_init(1 << 0); +#endif +#ifdef CONFIG_ATMEL_SPI + at91_spi0_hw_init(1 << 4); +#endif + +#ifdef CONFIG_MACB + at91sam9m10g45ek_macb_hw_init(); +#endif + +#ifdef CONFIG_LCD + at91sam9m10g45ek_lcd_hw_init(); +#endif + return 0; +} + +int dram_init(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM; + gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; + return 0; +} + +#ifdef CONFIG_RESET_PHY_R +void reset_phy(void) +{ +#ifdef CONFIG_MACB + /* + * Initialize ethernet HW addr prior to starting Linux, + * needed for nfsroot + */ + eth_init(gd->bd); +#endif +} +#endif + +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_MACB + rc = macb_eth_initialize(0, (void *)AT91SAM9G45_BASE_EMAC, 0x00); +#endif + return rc; +} + +/* SPI chip select control */ +#ifdef CONFIG_ATMEL_SPI +#include + +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return bus == 0 && cs < 2; +} + +void spi_cs_activate(struct spi_slave *slave) +{ + switch(slave->cs) { + case 1: + at91_set_gpio_output(AT91_PIN_PB18, 0); + break; + case 0: + default: + at91_set_gpio_output(AT91_PIN_PB3, 0); + break; + } +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + switch(slave->cs) { + case 1: + at91_set_gpio_output(AT91_PIN_PB18, 1); + break; + case 0: + default: + at91_set_gpio_output(AT91_PIN_PB3, 1); + break; + } +} +#endif /* CONFIG_ATMEL_SPI */ diff --git a/board/atmel/at91sam9m10g45ek/config.mk b/board/atmel/at91sam9m10g45ek/config.mk new file mode 100644 index 000000000..7fe9d0313 --- /dev/null +++ b/board/atmel/at91sam9m10g45ek/config.mk @@ -0,0 +1 @@ +TEXT_BASE = 0x73f00000 diff --git a/board/atmel/at91sam9m10g45ek/led.c b/board/atmel/at91sam9m10g45ek/led.c new file mode 100644 index 000000000..ff59a2d5d --- /dev/null +++ b/board/atmel/at91sam9m10g45ek/led.c @@ -0,0 +1,41 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop + * Lead Tech Design + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +void coloured_LED_init(void) +{ + /* Enable clock */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_PIODE); + + at91_set_gpio_output(CONFIG_RED_LED, 1); + at91_set_gpio_output(CONFIG_GREEN_LED, 1); + + at91_set_gpio_value(CONFIG_RED_LED, 0); + at91_set_gpio_value(CONFIG_GREEN_LED, 1); +} diff --git a/cpu/arm926ejs/at91/Makefile b/cpu/arm926ejs/at91/Makefile index 3da89f4fb..69051c1cd 100644 --- a/cpu/arm926ejs/at91/Makefile +++ b/cpu/arm926ejs/at91/Makefile @@ -31,6 +31,8 @@ COBJS-$(CONFIG_AT91SAM9G20) += at91sam9260_devices.o COBJS-$(CONFIG_AT91SAM9261) += at91sam9261_devices.o COBJS-$(CONFIG_AT91SAM9263) += at91sam9263_devices.o COBJS-$(CONFIG_AT91SAM9RL) += at91sam9rl_devices.o +COBJS-$(CONFIG_AT91SAM9M10G45) += at91sam9m10g45_devices.o +COBJS-$(CONFIG_AT91SAM9G45) += at91sam9m10g45_devices.o COBJS-$(CONFIG_AT91_LED) += led.o COBJS-y += clock.o COBJS-y += cpu.o diff --git a/cpu/arm926ejs/at91/at91sam9m10g45_devices.c b/cpu/arm926ejs/at91/at91sam9m10g45_devices.c new file mode 100644 index 000000000..98d90f251 --- /dev/null +++ b/cpu/arm926ejs/at91/at91sam9m10g45_devices.c @@ -0,0 +1,175 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop + * Lead Tech Design + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +void at91_serial0_hw_init(void) +{ + at91_set_A_periph(AT91_PIN_PB19, 1); /* TXD0 */ + at91_set_A_periph(AT91_PIN_PB18, 0); /* RXD0 */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_US0); +} + +void at91_serial1_hw_init(void) +{ + at91_set_A_periph(AT91_PIN_PB4, 1); /* TXD1 */ + at91_set_A_periph(AT91_PIN_PB5, 0); /* RXD1 */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_US1); +} + +void at91_serial2_hw_init(void) +{ + at91_set_A_periph(AT91_PIN_PD6, 1); /* TXD2 */ + at91_set_A_periph(AT91_PIN_PD7, 0); /* RXD2 */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_US2); +} + +void at91_serial3_hw_init(void) +{ + at91_set_A_periph(AT91_PIN_PB12, 0); /* DRXD */ + at91_set_A_periph(AT91_PIN_PB13, 1); /* DTXD */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);; +} + +void at91_serial_hw_init(void) +{ +#ifdef CONFIG_USART0 + at91_serial0_hw_init(); +#endif + +#ifdef CONFIG_USART1 + at91_serial1_hw_init(); +#endif + +#ifdef CONFIG_USART2 + at91_serial2_hw_init(); +#endif + +#ifdef CONFIG_USART3 /* DBGU */ + at91_serial3_hw_init(); +#endif +} + +#ifdef CONFIG_ATMEL_SPI +void at91_spi0_hw_init(unsigned long cs_mask) +{ + at91_set_A_periph(AT91_PIN_PB0, 0); /* SPI0_MISO */ + at91_set_A_periph(AT91_PIN_PB1, 0); /* SPI0_MOSI */ + at91_set_A_periph(AT91_PIN_PB2, 0); /* SPI0_SPCK */ + + /* Enable clock */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_SPI0); + + if (cs_mask & (1 << 0)) { + at91_set_A_periph(AT91_PIN_PB3, 0); + } + if (cs_mask & (1 << 1)) { + at91_set_B_periph(AT91_PIN_PB18, 0); + } + if (cs_mask & (1 << 2)) { + at91_set_B_periph(AT91_PIN_PB19, 0); + } + if (cs_mask & (1 << 3)) { + at91_set_B_periph(AT91_PIN_PD27, 0); + } + if (cs_mask & (1 << 4)) { + at91_set_gpio_output(AT91_PIN_PB3, 0); + } + if (cs_mask & (1 << 5)) { + at91_set_gpio_output(AT91_PIN_PB18, 0); + } + if (cs_mask & (1 << 6)) { + at91_set_gpio_output(AT91_PIN_PB19, 0); + } + if (cs_mask & (1 << 7)) { + at91_set_gpio_output(AT91_PIN_PD27, 0); + } +} + +void at91_spi1_hw_init(unsigned long cs_mask) +{ + at91_set_A_periph(AT91_PIN_PB14, 0); /* SPI1_MISO */ + at91_set_A_periph(AT91_PIN_PB15, 0); /* SPI1_MOSI */ + at91_set_A_periph(AT91_PIN_PB16, 0); /* SPI1_SPCK */ + + /* Enable clock */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_SPI1); + + if (cs_mask & (1 << 0)) { + at91_set_A_periph(AT91_PIN_PB17, 0); + } + if (cs_mask & (1 << 1)) { + at91_set_B_periph(AT91_PIN_PD28, 0); + } + if (cs_mask & (1 << 2)) { + at91_set_A_periph(AT91_PIN_PD18, 0); + } + if (cs_mask & (1 << 3)) { + at91_set_A_periph(AT91_PIN_PD19, 0); + } + if (cs_mask & (1 << 4)) { + at91_set_gpio_output(AT91_PIN_PB17, 0); + } + if (cs_mask & (1 << 5)) { + at91_set_gpio_output(AT91_PIN_PD28, 0); + } + if (cs_mask & (1 << 6)) { + at91_set_gpio_output(AT91_PIN_PD18, 0); + } + if (cs_mask & (1 << 7)) { + at91_set_gpio_output(AT91_PIN_PD19, 0); + } + +} +#endif + +#ifdef CONFIG_MACB +void at91_macb_hw_init(void) +{ + at91_set_A_periph(AT91_PIN_PA17, 0); /* ETXCK_EREFCK */ + at91_set_A_periph(AT91_PIN_PA15, 0); /* ERXDV */ + at91_set_A_periph(AT91_PIN_PA12, 0); /* ERX0 */ + at91_set_A_periph(AT91_PIN_PA13, 0); /* ERX1 */ + at91_set_A_periph(AT91_PIN_PA16, 0); /* ERXER */ + at91_set_A_periph(AT91_PIN_PA14, 0); /* ETXEN */ + at91_set_A_periph(AT91_PIN_PA10, 0); /* ETX0 */ + at91_set_A_periph(AT91_PIN_PA11, 0); /* ETX1 */ + at91_set_A_periph(AT91_PIN_PA19, 0); /* EMDIO */ + at91_set_A_periph(AT91_PIN_PA18, 0); /* EMDC */ +#ifndef CONFIG_RMII + at91_set_B_periph(AT91_PIN_PA29, 0); /* ECRS */ + at91_set_B_periph(AT91_PIN_PA30, 0); /* ECOL */ + at91_set_B_periph(AT91_PIN_PA8, 0); /* ERX2 */ + at91_set_B_periph(AT91_PIN_PA9, 0); /* ERX3 */ + at91_set_B_periph(AT91_PIN_PA28, 0); /* ERXCK */ + at91_set_B_periph(AT91_PIN_PA6, 0); /* ETX2 */ + at91_set_B_periph(AT91_PIN_PA7, 0); /* ETX3 */ + at91_set_B_periph(AT91_PIN_PA27, 0); /* ETXER */ +#endif +} +#endif diff --git a/cpu/arm926ejs/at91/clock.c b/cpu/arm926ejs/at91/clock.c index 9f03468b6..574f48824 100644 --- a/cpu/arm926ejs/at91/clock.c +++ b/cpu/arm926ejs/at91/clock.c @@ -183,15 +183,23 @@ int at91_clock_init(unsigned long main_clock) * For now, assume this parentage won't change. */ mckr = at91_sys_read(AT91_PMC_MCKR); +#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) + /* plla divisor by 2 */ + plla_rate_hz /= (1 << ((mckr & 1 << 12) >> 12)); +#endif freq = mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_CSS); + freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2)); /* prescale */ #if defined(CONFIG_AT91RM9200) mck_rate_hz = freq / (1 + ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */ #elif defined(CONFIG_AT91SAM9G20) mck_rate_hz = (mckr & AT91_PMC_MDIV) ? - freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq; /* mdiv ; (x >> 7) = ((x >> 8) * 2) */ + freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq; /* mdiv ; (x >> 7) = ((x >> 8) * 2) */ if (mckr & AT91_PMC_PDIV) - freq /= 2; /* processor clock division */ + freq /= 2; /* processor clock division */ +#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) + mck_rate_hz = (mckr & AT91_PMC_MDIV) == AT91SAM9_PMC_MDIV_3 ? + freq / 3 : freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */ #else mck_rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */ #endif diff --git a/doc/README.at91 b/doc/README.at91 index 4a2c56bd9..269d0729a 100644 --- a/doc/README.at91 +++ b/doc/README.at91 @@ -74,6 +74,26 @@ Environment variables make at91sam9263ek_norflash_boot_config - boot from nor falsh +------------------------------------------------------------------------------ +AT91SAM9M10G45EK +------------------------------------------------------------------------------ + +Memory map + 0x20000000 - 23FFFFFF SDRAM (64 MB) + 0xC0000000 - Cxxxxxxx Atmel Dataflash card (J12) + +Environment variables + + U-Boot environment variables can be stored at different places: + - Dataflash on SPI chip select 0 (dataflash card) + - Nand flash. + + You can choose your storage location at config step (here for at91sam9m10g45ek) : + make at91sam9m10g45ek_config - use data flash (spi cs0) (default) + make at91sam9m10g45ek_nandflash_config - use nand flash + make at91sam9m10g45ek_dataflash_cs0_config - use data flash (spi cs0) + + ------------------------------------------------------------------------------ AT91SAM9RLEK ------------------------------------------------------------------------------ diff --git a/drivers/net/macb.c b/drivers/net/macb.c index 6de0a0441..c1843539f 100644 --- a/drivers/net/macb.c +++ b/drivers/net/macb.c @@ -447,14 +447,16 @@ static int macb_init(struct eth_device *netdev, bd_t *bd) /* choose RMII or MII mode. This depends on the board */ #ifdef CONFIG_RMII #if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \ - defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G20) + defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G20) || \ + defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) macb_writel(macb, USRIO, MACB_BIT(RMII) | MACB_BIT(CLKEN)); #else macb_writel(macb, USRIO, 0); #endif #else #if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \ - defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G20) + defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G20) || \ + defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) macb_writel(macb, USRIO, MACB_BIT(CLKEN)); #else macb_writel(macb, USRIO, MACB_BIT(MII)); diff --git a/include/asm-arm/arch-at91/at91_pmc.h b/include/asm-arm/arch-at91/at91_pmc.h index a82955c1b..9fe94c7e4 100644 --- a/include/asm-arm/arch-at91/at91_pmc.h +++ b/include/asm-arm/arch-at91/at91_pmc.h @@ -89,6 +89,7 @@ #define AT91SAM9_PMC_MDIV_1 (0 << 8) /* [SAM9,CAP9 only] */ #define AT91SAM9_PMC_MDIV_2 (1 << 8) #define AT91SAM9_PMC_MDIV_4 (2 << 8) +#define AT91SAM9_PMC_MDIV_3 (3 << 8) /* [some SAM9 only] */ #define AT91SAM9_PMC_MDIV_6 (3 << 8) #define AT91_PMC_PDIV (1 << 12) /* Processor Clock Division [some SAM9 only] */ #define AT91_PMC_PDIV_1 (0 << 12) diff --git a/include/asm-arm/arch-at91/at91sam9_matrix.h b/include/asm-arm/arch-at91/at91sam9_matrix.h index 913f37479..6d97189d2 100644 --- a/include/asm-arm/arch-at91/at91sam9_matrix.h +++ b/include/asm-arm/arch-at91/at91sam9_matrix.h @@ -21,6 +21,8 @@ #include #elif defined(CONFIG_AT91CAP9) #include +#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) +#include #else #error "Unsupported AT91SAM9/CAP9 processor" #endif diff --git a/include/asm-arm/arch-at91/at91sam9g45.h b/include/asm-arm/arch-at91/at91sam9g45.h new file mode 100644 index 000000000..0feed9c28 --- /dev/null +++ b/include/asm-arm/arch-at91/at91sam9g45.h @@ -0,0 +1,139 @@ +/* + * Chip-specific header file for the AT91SAM9M1x family + * + * Copyright (C) 2008 Atmel Corporation. + * + * Common definitions. + * Based on AT91SAM9G45 preliminary datasheet. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91SAM9G45_H +#define AT91SAM9G45_H + +/* + * Peripheral identifiers/interrupts. + */ +#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ +#define AT91_ID_SYS 1 /* System Controller Interrupt */ +#define AT91SAM9G45_ID_PIOA 2 /* Parallel I/O Controller A */ +#define AT91SAM9G45_ID_PIOB 3 /* Parallel I/O Controller B */ +#define AT91SAM9G45_ID_PIOC 4 /* Parallel I/O Controller C */ +#define AT91SAM9G45_ID_PIODE 5 /* Parallel I/O Controller D and E */ +#define AT91SAM9G45_ID_TRNG 6 /* True Random Number Generator */ +#define AT91SAM9G45_ID_US0 7 /* USART 0 */ +#define AT91SAM9G45_ID_US1 8 /* USART 1 */ +#define AT91SAM9G45_ID_US2 9 /* USART 2 */ +#define AT91SAM9G45_ID_US3 10 /* USART 3 */ +#define AT91SAM9G45_ID_MCI0 11 /* High Speed Multimedia Card Interface 0 */ +#define AT91SAM9G45_ID_TWI0 12 /* Two-Wire Interface 0 */ +#define AT91SAM9G45_ID_TWI1 13 /* Two-Wire Interface 1 */ +#define AT91SAM9G45_ID_SPI0 14 /* Serial Peripheral Interface 0 */ +#define AT91SAM9G45_ID_SPI1 15 /* Serial Peripheral Interface 1 */ +#define AT91SAM9G45_ID_SSC0 16 /* Synchronous Serial Controller 0 */ +#define AT91SAM9G45_ID_SSC1 17 /* Synchronous Serial Controller 1 */ +#define AT91SAM9G45_ID_TCB 18 /* Timer Counter 0, 1, 2, 3, 4 and 5 */ +#define AT91SAM9G45_ID_PWMC 19 /* Pulse Width Modulation Controller */ +#define AT91SAM9G45_ID_TSC 20 /* Touch Screen ADC Controller */ +#define AT91SAM9G45_ID_DMA 21 /* DMA Controller */ +#define AT91SAM9G45_ID_UHPHS 22 /* USB Host High Speed */ +#define AT91SAM9G45_ID_LCDC 23 /* LCD Controller */ +#define AT91SAM9G45_ID_AC97C 24 /* AC97 Controller */ +#define AT91SAM9G45_ID_EMAC 25 /* Ethernet MAC */ +#define AT91SAM9G45_ID_ISI 26 /* Image Sensor Interface */ +#define AT91SAM9G45_ID_UDPHS 27 /* USB Device High Speed */ +#define AT91SAM9G45_ID_AESTDESSHA 28 /* AES + T-DES + SHA */ +#define AT91SAM9G45_ID_MCI1 29 /* High Speed Multimedia Card Interface 1 */ +#define AT91SAM9G45_ID_VDEC 30 /* Video Decoder */ +#define AT91SAM9G45_ID_IRQ0 31 /* Advanced Interrupt Controller */ + +/* + * User Peripheral physical base addresses. + */ +#define AT91SAM9G45_BASE_UDPHS 0xfff78000 +#define AT91SAM9G45_BASE_TC0 0xfff7c000 +#define AT91SAM9G45_BASE_TC1 0xfff7c040 +#define AT91SAM9G45_BASE_TC2 0xfff7c080 +#define AT91SAM9G45_BASE_MCI0 0xfff80000 +#define AT91SAM9G45_BASE_TWI0 0xfff84000 +#define AT91SAM9G45_BASE_TWI1 0xfff88000 +#define AT91SAM9G45_BASE_US0 0xfff8c000 +#define AT91SAM9G45_BASE_US1 0xfff90000 +#define AT91SAM9G45_BASE_US2 0xfff94000 +#define AT91SAM9G45_BASE_US3 0xfff98000 +#define AT91SAM9G45_BASE_SSC0 0xfff9c000 +#define AT91SAM9G45_BASE_SSC1 0xfffa0000 +#define AT91SAM9G45_BASE_SPI0 0xfffa4000 +#define AT91SAM9G45_BASE_SPI1 0xfffa8000 +#define AT91SAM9G45_BASE_AC97C 0xfffac000 +#define AT91SAM9G45_BASE_TSC 0xfffb0000 +#define AT91SAM9G45_BASE_ISI 0xfffb4000 +#define AT91SAM9G45_BASE_PWMC 0xfffb8000 +#define AT91SAM9G45_BASE_EMAC 0xfffbc000 +#define AT91SAM9G45_BASE_AES 0xfffc0000 +#define AT91SAM9G45_BASE_TDES 0xfffc4000 +#define AT91SAM9G45_BASE_SHA 0xfffc8000 +#define AT91SAM9G45_BASE_TRNG 0xfffcc000 +#define AT91SAM9G45_BASE_MCI1 0xfffd0000 +#define AT91SAM9G45_BASE_TC3 0xfffd4000 +#define AT91SAM9G45_BASE_TC4 0xfffd4040 +#define AT91SAM9G45_BASE_TC5 0xfffd4080 +#define AT91_BASE_SYS 0xffffe200 + +/* + * System Peripherals (offset from AT91_BASE_SYS) + */ +#define AT91_ECC (0xffffe200 - AT91_BASE_SYS) +#define AT91_DDRSDRC1 (0xffffe400 - AT91_BASE_SYS) +#define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS) +#define AT91_SMC (0xffffe800 - AT91_BASE_SYS) +#define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS) +#define AT91_DMA (0xffffec00 - AT91_BASE_SYS) +#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS) +#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) +#define AT91_PIOA (0xfffff200 - AT91_BASE_SYS) +#define AT91_PIOB (0xfffff400 - AT91_BASE_SYS) +#define AT91_PIOC (0xfffff600 - AT91_BASE_SYS) +#define AT91_PIOD (0xfffff800 - AT91_BASE_SYS) +#define AT91_PIOE (0xfffffa00 - AT91_BASE_SYS) +#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) +#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) +#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) +#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) +#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) +#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) +#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) +#define AT91_RTC (0xfffffdb0 - AT91_BASE_SYS) + +#define AT91_USART0 AT91SAM9G45_BASE_US0 +#define AT91_USART1 AT91SAM9G45_BASE_US1 +#define AT91_USART2 AT91SAM9G45_BASE_US2 +#define AT91_USART3 AT91SAM9G45_BASE_US3 + +/* + * Internal Memory. + */ +#define AT91SAM9G45_SRAM_BASE 0x00300000 /* Internal SRAM base address */ +#define AT91SAM9G45_SRAM_SIZE SZ_64K /* Internal SRAM size (64Kb) */ + +#define AT91SAM9G45_ROM_BASE 0x00400000 /* Internal ROM base address */ +#define AT91SAM9G45_ROM_SIZE SZ_64K /* Internal ROM size (64Kb) */ + +#define AT91SAM9G45_LCDC_BASE 0x00500000 /* LCD Controller */ +#define AT91SAM9G45_UDPHS_FIFO 0x00600000 /* USB Device HS controller */ +#define AT91SAM9G45_HCI_BASE 0x00700000 /* USB Host controller (OHCI) */ +#define AT91SAM9G45_EHCI_BASE 0x00800000 /* USB Host controller (EHCI) */ +#define AT91SAM9G45_VDEC_BASE 0x00900000 /* Video Decoder Controller */ + +#define CONFIG_DRAM_BASE AT91_CHIPSELECT_6 + +/* + * Cpu Name + */ +#define AT91_CPU_NAME "AT91SAM9G45" + +#endif diff --git a/include/asm-arm/arch-at91/at91sam9g45_matrix.h b/include/asm-arm/arch-at91/at91sam9g45_matrix.h new file mode 100644 index 000000000..1620e1baf --- /dev/null +++ b/include/asm-arm/arch-at91/at91sam9g45_matrix.h @@ -0,0 +1,153 @@ +/* + * Matrix-centric header file for the AT91SAM9M1x family + * + * Copyright (C) 2008 Atmel Corporation. + * + * Memory Controllers (MATRIX, EBI) - System peripherals registers. + * Based on AT91SAM9G45 preliminary datasheet. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91SAM9G45_MATRIX_H +#define AT91SAM9G45_MATRIX_H + +#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */ +#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */ +#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */ +#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */ +#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */ +#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */ +#define AT91_MATRIX_MCFG6 (AT91_MATRIX + 0x18) /* Master Configuration Register 6 */ +#define AT91_MATRIX_MCFG7 (AT91_MATRIX + 0x1C) /* Master Configuration Register 7 */ +#define AT91_MATRIX_MCFG8 (AT91_MATRIX + 0x20) /* Master Configuration Register 8 */ +#define AT91_MATRIX_MCFG9 (AT91_MATRIX + 0x24) /* Master Configuration Register 9 */ +#define AT91_MATRIX_MCFG10 (AT91_MATRIX + 0x28) /* Master Configuration Register 10 */ +#define AT91_MATRIX_MCFG11 (AT91_MATRIX + 0x2C) /* Master Configuration Register 11 */ +#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ +#define AT91_MATRIX_ULBT_INFINITE (0 << 0) +#define AT91_MATRIX_ULBT_SINGLE (1 << 0) +#define AT91_MATRIX_ULBT_FOUR (2 << 0) +#define AT91_MATRIX_ULBT_EIGHT (3 << 0) +#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) +#define AT91_MATRIX_ULBT_THIRTYTWO (5 << 0) +#define AT91_MATRIX_ULBT_SIXTYFOUR (6 << 0) +#define AT91_MATRIX_ULBT_128 (7 << 0) + +#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */ +#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */ +#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */ +#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */ +#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */ +#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */ +#define AT91_MATRIX_SCFG6 (AT91_MATRIX + 0x58) /* Slave Configuration Register 6 */ +#define AT91_MATRIX_SCFG7 (AT91_MATRIX + 0x5C) /* Slave Configuration Register 7 */ +#define AT91_MATRIX_SLOT_CYCLE (0x1ff << 0) /* Maximum Number of Allowed Cycles for a Burst */ +#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ +#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) +#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) +#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) +#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */ + +#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */ +#define AT91_MATRIX_PRBS0 (AT91_MATRIX + 0x84) /* Priority Register B for Slave 0 */ +#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */ +#define AT91_MATRIX_PRBS1 (AT91_MATRIX + 0x8C) /* Priority Register B for Slave 1 */ +#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */ +#define AT91_MATRIX_PRBS2 (AT91_MATRIX + 0x94) /* Priority Register B for Slave 2 */ +#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */ +#define AT91_MATRIX_PRBS3 (AT91_MATRIX + 0x9C) /* Priority Register B for Slave 3 */ +#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */ +#define AT91_MATRIX_PRBS4 (AT91_MATRIX + 0xA4) /* Priority Register B for Slave 4 */ +#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */ +#define AT91_MATRIX_PRBS5 (AT91_MATRIX + 0xAC) /* Priority Register B for Slave 5 */ +#define AT91_MATRIX_PRAS6 (AT91_MATRIX + 0xB0) /* Priority Register A for Slave 6 */ +#define AT91_MATRIX_PRBS6 (AT91_MATRIX + 0xB4) /* Priority Register B for Slave 6 */ +#define AT91_MATRIX_PRAS7 (AT91_MATRIX + 0xB8) /* Priority Register A for Slave 7 */ +#define AT91_MATRIX_PRBS7 (AT91_MATRIX + 0xBC) /* Priority Register B for Slave 7 */ +#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ +#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ +#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ +#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */ +#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ +#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */ +#define AT91_MATRIX_M6PR (3 << 24) /* Master 6 Priority */ +#define AT91_MATRIX_M7PR (3 << 28) /* Master 7 Priority */ +#define AT91_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */ +#define AT91_MATRIX_M9PR (3 << 4) /* Master 9 Priority (in Register B) */ +#define AT91_MATRIX_M10PR (3 << 8) /* Master 10 Priority (in Register B) */ +#define AT91_MATRIX_M11PR (3 << 12) /* Master 11 Priority (in Register B) */ + +#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */ +#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ +#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ +#define AT91_MATRIX_RCB2 (1 << 2) +#define AT91_MATRIX_RCB3 (1 << 3) +#define AT91_MATRIX_RCB4 (1 << 4) +#define AT91_MATRIX_RCB5 (1 << 5) +#define AT91_MATRIX_RCB6 (1 << 6) +#define AT91_MATRIX_RCB7 (1 << 7) +#define AT91_MATRIX_RCB8 (1 << 8) +#define AT91_MATRIX_RCB9 (1 << 9) +#define AT91_MATRIX_RCB10 (1 << 10) +#define AT91_MATRIX_RCB11 (1 << 11) + +#define AT91_MATRIX_TCMR (AT91_MATRIX + 0x110) /* TCM Configuration Register */ +#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */ +#define AT91_MATRIX_ITCM_0 (0 << 0) +#define AT91_MATRIX_ITCM_32 (6 << 0) +#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */ +#define AT91_MATRIX_DTCM_0 (0 << 4) +#define AT91_MATRIX_DTCM_32 (6 << 4) +#define AT91_MATRIX_DTCM_64 (7 << 4) +#define AT91_MATRIX_TCM_NWS (0x1 << 11) /* Wait state TCM register */ +#define AT91_MATRIX_TCM_NO_WS (0x0 << 11) +#define AT91_MATRIX_TCM_ONE_WS (0x1 << 11) + +#define AT91_MATRIX_VIDEO (AT91_MATRIX + 0x118) /* Video Mode Configuration Register */ +#define AT91C_VDEC_SEL (0x1 << 0) /* Video Mode Selection */ +#define AT91C_VDEC_SEL_OFF (0 << 0) +#define AT91C_VDEC_SEL_ON (1 << 0) + +#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x128) /* EBI Chip Select Assignment Register */ +#define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */ +#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1) +#define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1) +#define AT91_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */ +#define AT91_MATRIX_EBI_CS3A_SMC (0 << 3) +#define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA (1 << 3) +#define AT91_MATRIX_EBI_CS4A (1 << 4) /* Chip Select 4 Assignment */ +#define AT91_MATRIX_EBI_CS4A_SMC (0 << 4) +#define AT91_MATRIX_EBI_CS4A_SMC_CF0 (1 << 4) +#define AT91_MATRIX_EBI_CS5A (1 << 5) /* Chip Select 5 Assignment */ +#define AT91_MATRIX_EBI_CS5A_SMC (0 << 5) +#define AT91_MATRIX_EBI_CS5A_SMC_CF1 (1 << 5) +#define AT91_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ +#define AT91_MATRIX_EBI_DBPU_ON (0 << 8) +#define AT91_MATRIX_EBI_DBPU_OFF (1 << 8) +#define AT91_MATRIX_EBI_VDDIOMSEL (1 << 16) /* Memory voltage selection */ +#define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16) +#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16) +#define AT91_MATRIX_EBI_EBI_IOSR (1 << 17) /* EBI I/O slew rate selection */ +#define AT91_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17) +#define AT91_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17) +#define AT91_MATRIX_EBI_DDR_IOSR (1 << 18) /* DDR2 dedicated port I/O slew rate selection */ +#define AT91_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18) +#define AT91_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18) + +#define AT91_MATRIX_WPMR (AT91_MATRIX + 0x1E4) /* Write Protect Mode Register */ +#define AT91_MATRIX_WPMR_WPEN (1 << 0) /* Write Protect ENable */ +#define AT91_MATRIX_WPMR_WP_WPDIS (0 << 0) +#define AT91_MATRIX_WPMR_WP_WPEN (1 << 0) +#define AT91_MATRIX_WPMR_WPKEY (0xFFFFFF << 8) /* Write Protect KEY */ + +#define AT91_MATRIX_WPSR (AT91_MATRIX + 0x1E8) /* Write Protect Status Register */ +#define AT91_MATRIX_WPSR_WPVS (1 << 0) /* Write Protect Violation Status */ +#define AT91_MATRIX_WPSR_NO_WPV (0 << 0) +#define AT91_MATRIX_WPSR_WPV (1 << 0) +#define AT91_MATRIX_WPSR_WPVSRC (0xFFFF << 8) /* Write Protect Violation Source */ + +#endif diff --git a/include/asm-arm/arch-at91/clk.h b/include/asm-arm/arch-at91/clk.h index 6aaf82eae..f642dd995 100644 --- a/include/asm-arm/arch-at91/clk.h +++ b/include/asm-arm/arch-at91/clk.h @@ -49,6 +49,11 @@ static inline unsigned long get_lcdc_clk_rate(unsigned int dev_id) return get_mck_clk_rate(); } +static inline unsigned long get_spi_clk_rate(unsigned int dev_id) +{ + return get_mck_clk_rate(); +} + static inline unsigned long get_twi_clk_rate(unsigned int dev_id) { return get_mck_clk_rate(); diff --git a/include/asm-arm/arch-at91/hardware.h b/include/asm-arm/arch-at91/hardware.h index 870410645..c42709efc 100644 --- a/include/asm-arm/arch-at91/hardware.h +++ b/include/asm-arm/arch-at91/hardware.h @@ -37,6 +37,12 @@ #include #define AT91_BASE_SPI AT91SAM9RL_BASE_SPI #define AT91_ID_UHP AT91SAM9RL_ID_UHP +#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) +#include +#define AT91_BASE_EMAC AT91SAM9G45_BASE_EMAC +#define AT91_BASE_SPI AT91SAM9G45_BASE_SPI0 +#define AT91_ID_UHP AT91SAM9G45_ID_UHPHS +#define AT91_PMC_UHP AT91SAM926x_PMC_UHP #elif defined(CONFIG_AT91CAP9) #include #define AT91_BASE_SPI AT91CAP9_BASE_SPI0 diff --git a/include/asm-arm/arch-at91/memory-map.h b/include/asm-arm/arch-at91/memory-map.h index 8015dad6a..f605f37fd 100644 --- a/include/asm-arm/arch-at91/memory-map.h +++ b/include/asm-arm/arch-at91/memory-map.h @@ -30,5 +30,6 @@ #define USART1_BASE AT91_USART1 #define USART2_BASE AT91_USART2 #define USART3_BASE (AT91_BASE_SYS + AT91_DBGU) +#define SPI0_BASE AT91_BASE_SPI #endif /* __ASM_ARM_ARCH_MEMORYMAP_H__ */ diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h new file mode 100644 index 000000000..572c45bfb --- /dev/null +++ b/include/configs/at91sam9m10g45ek.h @@ -0,0 +1,225 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop + * Lead Tech Design + * + * Configuation settings for the AT91SAM9M10G45EK board(and AT91SAM9G45EKES). + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* ARM asynchronous clock */ +#define AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ +#ifdef CONFIG_AT91SAM9M10G45EK +#define CONFIG_AT91SAM9M10G45 1 /* It's an Atmel AT91SAM9M10G45 SoC*/ +#else +#define CONFIG_AT91SAM9G45 1 /* It's an Atmel AT91SAM9G45 SoC*/ +#endif +#define CONFIG_ARCH_CPU_INIT +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_RELOCATE_UBOOT + +/* + * Hardware drivers + */ +#define CONFIG_ATMEL_USART 1 +#undef CONFIG_USART0 +#undef CONFIG_USART1 +#undef CONFIG_USART2 +#define CONFIG_USART3 1 /* USART 3 is DBGU */ + +/* LCD */ +#define CONFIG_LCD 1 +#define LCD_BPP LCD_COLOR8 +#define CONFIG_LCD_LOGO 1 +#undef LCD_TEST_PATTERN +#define CONFIG_LCD_INFO 1 +#define CONFIG_LCD_INFO_BELOW_LOGO 1 +#define CONFIG_SYS_WHITE_ON_BLACK 1 +#define CONFIG_ATMEL_LCD 1 +#define CONFIG_ATMEL_LCD_RGB565 1 +#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 +/* board specific(not enough SRAM) */ +#define CONFIG_AT91SAM9G45_LCD_BASE 0x73E00000 + +/* LED */ +#define CONFIG_AT91_LED +#define CONFIG_RED_LED AT91_PIN_PD31 /* this is the user1 led */ +#define CONFIG_GREEN_LED AT91_PIN_PD0 /* this is the user2 led */ + +#define CONFIG_BOOTDELAY 3 + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE 1 +#define CONFIG_BOOTP_BOOTPATH 1 +#define CONFIG_BOOTP_GATEWAY 1 +#define CONFIG_BOOTP_HOSTNAME 1 + +/* + * Command line configuration. + */ +#include +#undef CONFIG_CMD_BDI +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_IMI +#undef CONFIG_CMD_IMLS +#undef CONFIG_CMD_AUTOSCRIPT +#undef CONFIG_CMD_LOADS + +#define CONFIG_CMD_PING 1 +#define CONFIG_CMD_DHCP 1 +#define CONFIG_CMD_NAND 1 +#define CONFIG_CMD_USB 1 + +/* SDRAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM 0x70000000 +#define PHYS_SDRAM_SIZE 0x08000000 /* 128 megs */ + +/* DataFlash */ +#ifdef CONFIG_ATMEL_SPI +#define CONFIG_CMD_SF +#define CONFIG_CMD_SPI +#define CONFIG_SPI_FLASH 1 +#define CONFIG_SPI_FLASH_ATMEL 1 +#define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 +#endif + +/* NOR flash, if populated */ +#ifndef CONFIG_CMD_NAND +#define CONFIG_SYS_NO_FLASH 1 +#else +#define CONFIG_SYS_FLASH_CFI 1 +#define CONFIG_FLASH_CFI_DRIVER 1 +#define PHYS_FLASH_1 0x10000000 +#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CONFIG_SYS_MAX_FLASH_SECT 256 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#endif + +/* NAND flash */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_NAND_MAX_CHIPS 1 +#define CONFIG_NAND_ATMEL +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_DBW_8 1 +/* our ALE is AD21 */ +#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +/* our CLE is AD22 */ +#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 +#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC8 +#endif + +/* Ethernet */ +#define CONFIG_MACB 1 +#define CONFIG_RMII 1 +#define CONFIG_NET_MULTI 1 +#define CONFIG_NET_RETRY_COUNT 20 +#define CONFIG_RESET_PHY_R 1 + +/* USB */ +#define CONFIG_USB_ATMEL +#define CONFIG_USB_OHCI_NEW 1 +#define CONFIG_DOS_PARTITION 1 +#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 +#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00700000 /* AT91SAM9G45_UHP_OHCI_BASE */ +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9g45" +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 +#define CONFIG_USB_STORAGE 1 + +#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ + +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM +#define CONFIG_SYS_MEMTEST_END 0x23e00000 + +#ifdef CONFIG_SYS_USE_DATAFLASH + +/* bootstrap + u-boot + env + linux in dataflash on CS0 */ +#define CONFIG_ENV_IS_IN_SPI_FLASH 1 +#define CONFIG_SYS_MONITOR_BASE (0xC0000000 + 0x8400) +#define CONFIG_ENV_OFFSET 0x4200 +#define CONFIG_ENV_ADDR (0xC0000000 + CONFIG_ENV_OFFSET) +#define CONFIG_ENV_SIZE 0x4200 +#define CONFIG_ENV_SECT_SIZE 0x10000 +#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm" +#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ + "root=/dev/mtdblock0 " \ + "mtdparts=at91_nand:-(root) "\ + "rw rootfstype=jffs2" + +#else /* CONFIG_SYS_USE_NANDFLASH */ + +/* bootstrap + u-boot + env + linux in nandflash */ +#define CONFIG_ENV_IS_IN_NAND 1 +#define CONFIG_ENV_OFFSET 0x60000 +#define CONFIG_ENV_OFFSET_REDUND 0x80000 +#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ +#define CONFIG_BOOTCOMMAND "nand read 0x72000000 0x200000 0x200000; bootm" +#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ + "root=/dev/mtdblock5 " \ + "mtdparts=at91_nand:128k(bootstrap)ro, \ + 256k(uboot)ro,128k(env1)ro,128k(env2)ro, \ + 2M(linux),-(root) " \ + "rw rootfstype=jffs2" + +#endif + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } + +#define CONFIG_SYS_PROMPT "U-Boot> " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_LONGHELP 1 +#define CONFIG_CMDLINE_EDITING 1 +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +#define ROUND(A, B) (((A) + (B)) & ~((B) - 1)) +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */ + +#define CONFIG_STACKSIZE (32*1024) /* regular stack */ + +#ifdef CONFIG_USE_IRQ +#error CONFIG_USE_IRQ not supported +#endif + +#endif From 5ccc2d99d61c81805348b0cd9f79731b271f7daf Mon Sep 17 00:00:00 2001 From: Sedji Gaouaou Date: Thu, 25 Jun 2009 17:04:15 +0200 Subject: [PATCH 10/12] at91: Introduction of at91sam9g10 SOC. AT91sam9g10 is an ARM 926ej-s SOC. It is an evolution of the at91sam9261 with a faster clock speed: 266/133MHz. Signed-off-by: Sedji Gaouaou --- MAINTAINERS | 1 + MAKEALL | 3 +- Makefile | 14 +++++++-- board/atmel/at91sam9261ek/at91sam9261ek.c | 36 +++++++++++++++++++++++ cpu/arm926ejs/at91/Makefile | 1 + doc/README.at91 | 2 +- include/asm-arm/arch-at91/hardware.h | 2 +- include/configs/at91sam9261ek.h | 13 +++++++- 8 files changed, 66 insertions(+), 6 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 5a8f12c23..6fc2901d3 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -548,6 +548,7 @@ Daniel Gorsulowski meesc ARM926EJS (AT91SAM9263 SoC) Sedji Gaouaou + at91sam9g10ek ARM926EJS (AT91SAM9G10 SoC) at91sam9m10g45ek ARM926EJS (AT91SAM9G45 SoC) Marius Gröger diff --git a/MAKEALL b/MAKEALL index 03ef5b45c..3c15f9c3c 100755 --- a/MAKEALL +++ b/MAKEALL @@ -586,8 +586,9 @@ LIST_at91=" \ at91sam9260ek \ at91sam9261ek \ at91sam9263ek \ - at91sam9m10g45ek \ + at91sam9g10ek \ at91sam9g20ek \ + at91sam9m10g45ek \ at91sam9rlek \ cmc_pu2 \ csb637 \ diff --git a/Makefile b/Makefile index 55a9648d7..3e71a088a 100644 --- a/Makefile +++ b/Makefile @@ -2743,12 +2743,22 @@ at91sam9xeek_config : unconfig at91sam9261ek_nandflash_config \ at91sam9261ek_dataflash_cs0_config \ at91sam9261ek_dataflash_cs3_config \ -at91sam9261ek_config : unconfig +at91sam9261ek_config \ +at91sam9g10ek_nandflash_config \ +at91sam9g10ek_dataflash_cs0_config \ +at91sam9g10ek_dataflash_cs3_config \ +at91sam9g10ek_config : unconfig @mkdir -p $(obj)include + @if [ "$(findstring 9g10,$@)" ] ; then \ + echo "#define CONFIG_AT91SAM9G10EK 1" >>$(obj)include/config.h ; \ + $(XECHO) "... 9G10 Variant" ; \ + else \ + echo "#define CONFIG_AT91SAM9261EK 1" >>$(obj)include/config.h ; \ + fi; @if [ "$(findstring _nandflash,$@)" ] ; then \ echo "#define CONFIG_SYS_USE_NANDFLASH 1" >>$(obj)include/config.h ; \ $(XECHO) "... with environment variable in NAND FLASH" ; \ - elif [ "$(findstring dataflash_cs3,$@)" ] ; then \ + elif [ "$(findstring dataflash_cs0,$@)" ] ; then \ echo "#define CONFIG_SYS_USE_DATAFLASH_CS3 1" >>$(obj)include/config.h ; \ $(XECHO) "... with environment variable in SPI DATAFLASH CS3" ; \ else \ diff --git a/board/atmel/at91sam9261ek/at91sam9261ek.c b/board/atmel/at91sam9261ek/at91sam9261ek.c index 0817e6015..2f6b599a6 100644 --- a/board/atmel/at91sam9261ek/at91sam9261ek.c +++ b/board/atmel/at91sam9261ek/at91sam9261ek.c @@ -57,6 +57,16 @@ static void at91sam9261ek_nand_hw_init(void) csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA); /* Configure SMC CS3 for NAND/SmartMedia */ +#ifdef CONFIG_AT91SAM9G10EK + at91_sys_write(AT91_SMC_SETUP(3), + AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(0) | + AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(0)); + at91_sys_write(AT91_SMC_PULSE(3), + AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(7) | + AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(7)); + at91_sys_write(AT91_SMC_CYCLE(3), + AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(7)); +#else at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) | AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0)); @@ -65,6 +75,7 @@ static void at91sam9261ek_nand_hw_init(void) AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3)); at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5)); +#endif at91_sys_write(AT91_SMC_MODE(3), AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | @@ -92,6 +103,21 @@ static void at91sam9261ek_nand_hw_init(void) static void at91sam9261ek_dm9000_hw_init(void) { /* Configure SMC CS2 for DM9000 */ +#ifdef CONFIG_AT91SAM9G10EK + at91_sys_write(AT91_SMC_SETUP(2), + AT91_SMC_NWESETUP_(3) | AT91_SMC_NCS_WRSETUP_(0) | + AT91_SMC_NRDSETUP_(3) | AT91_SMC_NCS_RDSETUP_(0)); + at91_sys_write(AT91_SMC_PULSE(2), + AT91_SMC_NWEPULSE_(6) | AT91_SMC_NCS_WRPULSE_(8) | + AT91_SMC_NRDPULSE_(6) | AT91_SMC_NCS_RDPULSE_(8)); + at91_sys_write(AT91_SMC_CYCLE(2), + AT91_SMC_NWECYCLE_(20) | AT91_SMC_NRDCYCLE_(20)); + at91_sys_write(AT91_SMC_MODE(2), + AT91_SMC_READMODE | AT91_SMC_WRITEMODE | + AT91_SMC_EXNWMODE_DISABLE | + AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16 | + AT91_SMC_TDF_(1)); +#else at91_sys_write(AT91_SMC_SETUP(2), AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(0) | AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(0)); @@ -105,6 +131,7 @@ static void at91sam9261ek_dm9000_hw_init(void) AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16 | AT91_SMC_TDF_(1)); +#endif /* Configure Reset signal as output */ at91_set_gpio_output(AT91_PIN_PC10, 0); @@ -169,7 +196,11 @@ static void at91sam9261ek_lcd_hw_init(void) at91_sys_write(AT91_PMC_SCER, AT91_PMC_HCK1); +#ifdef CONFIG_AT91SAM9G10EK + gd->fb_base = CONFIG_AT91SAM9G10_LCD_BASE; +#else gd->fb_base = AT91SAM9261_SRAM_BASE; +#endif } #ifdef CONFIG_LCD_INFO @@ -207,8 +238,13 @@ int board_init(void) /* Enable Ctrlc */ console_init_f(); +#ifdef CONFIG_AT91SAM9G10EK + /* arch number of AT91SAM9G10EK-Board */ + gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G10EK; +#else /* arch number of AT91SAM9261EK-Board */ gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9261EK; +#endif /* adress of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; diff --git a/cpu/arm926ejs/at91/Makefile b/cpu/arm926ejs/at91/Makefile index 69051c1cd..4f467be91 100644 --- a/cpu/arm926ejs/at91/Makefile +++ b/cpu/arm926ejs/at91/Makefile @@ -29,6 +29,7 @@ COBJS-$(CONFIG_AT91CAP9) += at91cap9_devices.o COBJS-$(CONFIG_AT91SAM9260) += at91sam9260_devices.o COBJS-$(CONFIG_AT91SAM9G20) += at91sam9260_devices.o COBJS-$(CONFIG_AT91SAM9261) += at91sam9261_devices.o +COBJS-$(CONFIG_AT91SAM9G10) += at91sam9261_devices.o COBJS-$(CONFIG_AT91SAM9263) += at91sam9263_devices.o COBJS-$(CONFIG_AT91SAM9RL) += at91sam9rl_devices.o COBJS-$(CONFIG_AT91SAM9M10G45) += at91sam9m10g45_devices.o diff --git a/doc/README.at91 b/doc/README.at91 index 269d0729a..84b5595a9 100644 --- a/doc/README.at91 +++ b/doc/README.at91 @@ -27,7 +27,7 @@ Environment variables ------------------------------------------------------------------------------ -AT91SAM9261EK +AT91SAM9261EK, AT91SAM9G10EK ------------------------------------------------------------------------------ Memory map diff --git a/include/asm-arm/arch-at91/hardware.h b/include/asm-arm/arch-at91/hardware.h index c42709efc..de06a1004 100644 --- a/include/asm-arm/arch-at91/hardware.h +++ b/include/asm-arm/arch-at91/hardware.h @@ -23,7 +23,7 @@ #define AT91_BASE_SPI AT91SAM9260_BASE_SPI0 #define AT91_ID_UHP AT91SAM9260_ID_UHP #define AT91_PMC_UHP AT91SAM926x_PMC_UHP -#elif defined(CONFIG_AT91SAM9261) +#elif defined(CONFIG_AT91SAM9261) || defined(CONFIG_AT91SAM9G10) #include #define AT91_BASE_SPI AT91SAM9261_BASE_SPI0 #define AT91_ID_UHP AT91SAM9261_ID_UHP diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h index 83e05b343..6d240230d 100644 --- a/include/configs/at91sam9261ek.h +++ b/include/configs/at91sam9261ek.h @@ -32,8 +32,11 @@ #define CONFIG_SYS_HZ 1000 #define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ +#ifdef CONFIG_AT91SAM9G10EK +#define CONFIG_AT91SAM9G10 1 /* It's an Atmel AT91SAM9G10 SoC*/ +#else #define CONFIG_AT91SAM9261 1 /* It's an Atmel AT91SAM9261 SoC*/ -#define CONFIG_AT91SAM9261EK 1 /* on an AT91SAM9261EK Board */ +#endif #define CONFIG_ARCH_CPU_INIT #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ @@ -62,7 +65,11 @@ #define CONFIG_LCD_INFO_BELOW_LOGO 1 #define CONFIG_SYS_WHITE_ON_BLACK 1 #define CONFIG_ATMEL_LCD 1 +#ifdef CONFIG_AT91SAM9261EK #define CONFIG_ATMEL_LCD_BGR555 1 +#else +#define CONFIG_AT91SAM9G10_LCD_BASE 0x23E00000 /* LCD is no more in SRAM */ +#endif #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 /* LED */ @@ -147,7 +154,11 @@ #define CONFIG_DOS_PARTITION 1 #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9261_UHP_BASE */ +#ifdef CONFIG_AT91SAM9G10EK +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9g10" +#else #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9261" +#endif #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 #define CONFIG_USB_STORAGE 1 #define CONFIG_CMD_FAT 1 From d6e8ed832b25d5db4fdd3fb91e73028e494dcd6e Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Sat, 2 May 2009 11:53:49 +0200 Subject: [PATCH 11/12] versatile: specify the board type on the prompt Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD Signed-off-by: Peter Pearse Cc: Catalin Marinas --- include/configs/versatile.h | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/include/configs/versatile.h b/include/configs/versatile.h index 300271f9d..a53f80afb 100644 --- a/include/configs/versatile.h +++ b/include/configs/versatile.h @@ -39,6 +39,10 @@ #define CONFIG_VERSATILE 1 /* in Versatile Platform Board */ #define CONFIG_ARCH_VERSATILE 1 /* Specifically, a Versatile */ +#ifndef CONFIG_ARCH_VERSATILE_AB /* AB */ +#define CONFIG_ARCH_VERSATILE_PB /* Versatile PB is default */ +#endif + #define CONFIG_SYS_MEMTEST_START 0x100000 #define CONFIG_SYS_MEMTEST_END 0x10000000 #define CONFIG_SYS_HZ (1000000 / 256) @@ -101,7 +105,6 @@ /* * Command line configuration. */ - #define CONFIG_CMD_BDI #define CONFIG_CMD_DHCP #define CONFIG_CMD_FLASH @@ -132,8 +135,13 @@ * Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "Versatile # " /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +/* Monitor Command Prompt */ +#ifdef CONFIG_ARCH_VERSATILE_AB +# define CONFIG_SYS_PROMPT "VersatileAB # " +#else +# define CONFIG_SYS_PROMPT "VersatilePB # " +#endif /* Print Buffer Size */ #define CONFIG_SYS_PBSIZE \ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) From 986922714ffd21ad39f48522d285fffc7aed56b1 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Sat, 2 May 2009 11:53:50 +0200 Subject: [PATCH 12/12] versatile: update config and merge to cfi flash driver Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD Signed-off-by: Peter Pearse Cc: Catalin Marinas --- board/armltd/versatile/Makefile | 2 +- board/armltd/versatile/flash.c | 514 -------------------------------- include/configs/versatile.h | 65 +++- 3 files changed, 51 insertions(+), 530 deletions(-) delete mode 100644 board/armltd/versatile/flash.c diff --git a/board/armltd/versatile/Makefile b/board/armltd/versatile/Makefile index 044a42989..80a2c7e21 100644 --- a/board/armltd/versatile/Makefile +++ b/board/armltd/versatile/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := versatile.o flash.o +COBJS := versatile.o SOBJS := lowlevel_init.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/board/armltd/versatile/flash.c b/board/armltd/versatile/flash.c deleted file mode 100644 index 3bdc895ec..000000000 --- a/board/armltd/versatile/flash.c +++ /dev/null @@ -1,514 +0,0 @@ -/* - * (C) Copyright 2001 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2001-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2003 - * Texas Instruments, - * Kshitij Gupta - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 256 KB sectors (x2) */ -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* Board support for 1 or 2 flash devices */ -#define FLASH_PORT_WIDTH32 -#undef FLASH_PORT_WIDTH16 - -#ifdef FLASH_PORT_WIDTH16 -#define FLASH_PORT_WIDTH ushort -#define FLASH_PORT_WIDTHV vu_short -#define SWAP(x) __swab16(x) -#else -#define FLASH_PORT_WIDTH ulong -#define FLASH_PORT_WIDTHV vu_long -#define SWAP(x) __swab32(x) -#endif - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -#define mb() __asm__ __volatile__ ("" : : : "memory") - - -/* Flash Organization Structure */ -typedef struct OrgDef { - unsigned int sector_number; - unsigned int sector_size; -} OrgDef; - - -/* Flash Organizations */ -OrgDef OrgIntel_28F256K3[] = { - {256, 128 * 1024}, /* 256 * 128kBytes sectors */ -}; - - -/*----------------------------------------------------------------------- - * Functions - */ -unsigned long flash_init (void); -static ulong flash_get_size (FPW * addr, flash_info_t * info); -static int write_data (flash_info_t * info, ulong dest, FPW data); -static void flash_get_offsets (ulong base, flash_info_t * info); -void inline spin_wheel (void); -void flash_print_info (flash_info_t * info); -void flash_unprotect_sectors (FPWV * addr); -int flash_erase (flash_info_t * info, int s_first, int s_last); -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt); - -/*----------------------------------------------------------------------- - */ - -static void flash_vpp(int on) -{ - unsigned int tmp; - - tmp = *(unsigned int *)(VERSATILE_FLASHCTRL); - - if (on) - tmp |= VERSATILE_FLASHPROG_FLVPPEN; - else - tmp &= ~VERSATILE_FLASHPROG_FLVPPEN; - - *(unsigned int *)(VERSATILE_FLASHCTRL) = tmp; -} - -unsigned long flash_init (void) -{ - int i; - ulong size = 0; - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - switch (i) { - case 0: - flash_vpp(1); - flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]); - flash_get_offsets (PHYS_FLASH_1, &flash_info[i]); - flash_vpp(0); - break; - default: - panic ("configured too many flash banks!\n"); - break; - } - size += flash_info[i].size; - } - - /* Protect monitor and environment sectors - */ - flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]); - - return size; -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t * info) -{ - int i; - OrgDef *pOrgDef; - - pOrgDef = OrgIntel_28F256K3; - if (info->flash_id == FLASH_UNKNOWN) { - return; - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - for (i = 0; i < info->sector_count; i++) { - if (i > 255) { - info->start[i] = base + (i * 0x8000); - info->protect[i] = 0; - } else { - info->start[i] = base + - (i * PHYS_FLASH_SECT_SIZE); - info->protect[i] = 0; - } - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: - printf ("INTEL "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F256L18T: - printf ("FLASH 28F256L18T\n"); - break; - case FLASH_28F256K3: - printf ("FLASH 28F256K3\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - return; -} - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (FPW * addr, flash_info_t * info) -{ - volatile FPW value; - - /* Write auto select command: read Manufacturer ID */ - addr[0x5555] = (FPW) 0x00AA00AA; - addr[0x2AAA] = (FPW) 0x00550055; - addr[0x5555] = (FPW) 0x00900090; - - mb (); - value = addr[0]; - switch (value) { - - case (FPW) INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - return (0); /* no or unknown flash */ - } - - mb (); - value = addr[1]; /* device ID */ - switch (value) { - - case (FPW) (INTEL_ID_28F256L18T): - info->flash_id += FLASH_28F256L18T; - info->sector_count = 259; - info->size = 0x02000000; - break; /* => 32 MB */ - - case (FPW)(INTEL_ID_28F256K3): - info->flash_id += FLASH_28F256K3; - info->sector_count = 256; - info->size = 0x02000000; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - break; - } - - if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); - info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; - } - - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - - return (info->size); -} - - -/* unprotects a sector for write and erase - * on some intel parts, this unprotects the entire chip, but it - * wont hurt to call this additional times per sector... - */ -void flash_unprotect_sectors (FPWV * addr) -{ -#define PD_FINTEL_WSMS_READY_MASK 0x0080 - - *addr = (FPW) 0x00500050; /* clear status register */ - - /* this sends the clear lock bit command */ - *addr = (FPW) 0x00600060; - *addr = (FPW) 0x00D000D0; -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong type, start, last; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - type = (info->flash_id & FLASH_VENDMASK); - if ((type != FLASH_MAN_INTEL)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - flash_vpp(1); - - start = get_timer (0); - last = start; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - FPWV *addr = (FPWV *) (info->start[sect]); - FPW status; - - printf ("Erasing sector %2d ... ", sect); - - flash_unprotect_sectors (addr); - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); - - *addr = (FPW) 0x00500050;/* clear status register */ - *addr = (FPW) 0x00200020;/* erase setup */ - *addr = (FPW) 0x00D000D0;/* erase confirm */ - - while (((status = - *addr) & (FPW) 0x00800080) != - (FPW) 0x00800080) { - if (get_timer_masked () > - CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - /* suspend erase */ - *addr = (FPW) 0x00B000B0; - /* reset to read mode */ - *addr = (FPW) 0x00FF00FF; - rcode = 1; - break; - } - } - - /* clear status register cmd. */ - *addr = (FPW) 0x00500050; - *addr = (FPW) 0x00FF00FF;/* resest to read mode */ - printf (" done\n"); - } - } - - flash_vpp(0); - - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp; - FPW data; - int count, i, l, rc, port_width; - - if (info->flash_id == FLASH_UNKNOWN) { - return 4; - } -/* get lower word aligned address */ -#ifdef FLASH_PORT_WIDTH16 - wp = (addr & ~1); - port_width = 2; -#else - wp = (addr & ~3); - port_width = 4; -#endif - - flash_vpp(1); - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < port_width && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_data (info, wp, SWAP (data))) != 0) { - flash_vpp(0); - return (rc); - } - wp += port_width; - } - - /* - * handle word aligned part - */ - count = 0; - while (cnt >= port_width) { - data = 0; - for (i = 0; i < port_width; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_data (info, wp, SWAP (data))) != 0) { - flash_vpp(0); - return (rc); - } - wp += port_width; - cnt -= port_width; - if (count++ > 0x800) { - spin_wheel (); - count = 0; - } - } - - if (cnt == 0) { - flash_vpp(0); - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - rc = write_data (info, wp, SWAP (data)); - - flash_vpp(0); - - return rc; -} - -/*----------------------------------------------------------------------- - * Write a word or halfword to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_data (flash_info_t * info, ulong dest, FPW data) -{ - FPWV *addr = (FPWV *) dest; - ulong status; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - printf ("not erased at %08lx (%lx)\n", (ulong) addr, (ulong) *addr); - return (2); - } - - flash_vpp(1); - - flash_unprotect_sectors (addr); - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - *addr = (FPW) 0x00400040; /* write setup */ - *addr = data; - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); - - /* wait while polling the status register */ - while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) { - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - flash_vpp(0); - return (1); - } - } - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - flash_vpp(0); - return (0); -} - -void inline spin_wheel (void) -{ - static int p = 0; - static char w[] = "\\/-"; - - printf ("\010%c", w[p]); - (++p == 3) ? (p = 0) : 0; -} diff --git a/include/configs/versatile.h b/include/configs/versatile.h index a53f80afb..a9b70cc36 100644 --- a/include/configs/versatile.h +++ b/include/configs/versatile.h @@ -167,13 +167,20 @@ #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ #define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ #define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ - -#define CONFIG_SYS_FLASH_BASE 0x34000000 +#define PHYS_FLASH_SIZE 0x04000000 /* 64MB */ /*----------------------------------------------------------------------- * FLASH and environment organization */ - +/* + * Use the CFI flash driver for ease of use + */ +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_ENV_IS_IN_FLASH 1 +/* + * System control register + */ #define VERSATILE_SYS_BASE 0x10000000 #define VERSATILE_SYS_FLASH_OFFSET 0x4C #define VERSATILE_FLASHCTRL \ @@ -181,19 +188,47 @@ /* Enable writing to flash */ #define VERSATILE_FLASHPROG_FLVPPEN (1 << 0) -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define PHYS_FLASH_SIZE 0x34000000 /* 64MB */ /* timeout values are in ticks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (20 * CONFIG_SYS_HZ) /* Erase Timeout */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (20 * CONFIG_SYS_HZ) /* Write Timeout */ -#define CONFIG_SYS_MAX_FLASH_SECT (256) +#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Erase Timeout */ +#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Write Timeout */ -#define PHYS_FLASH_1 (CONFIG_SYS_FLASH_BASE) +/* + * Note that CONFIG_SYS_MAX_FLASH_SECT allows for a parameter block + * i.e. + * the bottom "sector" (bottom boot), or top "sector" + * (top boot), is a seperate erase region divided into + * 4 (equal) smaller sectors. This, notionally, allows + * quicker erase/rewrire of the most frequently changed + * area...... + * CONFIG_SYS_MAX_FLASH_SECT is padded up to a multiple of 4 + */ -#define CONFIG_ENV_IS_IN_FLASH 1 /* env in flash */ -#define CONFIG_ENV_SECT_SIZE 0x00020000 /* 256 KB sectors (x2) */ -#define CONFIG_ENV_SIZE 0x10000 /* Size of Environment */ -#define CONFIG_ENV_OFFSET 0x01f00000 /* environment starts */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) +#ifdef CONFIG_ARCH_VERSATILE_AB +#define FLASH_SECTOR_SIZE 0x00020000 /* 128 KB sectors */ +#define CONFIG_ENV_SECT_SIZE (2 * FLASH_SECTOR_SIZE) +#define CONFIG_SYS_MAX_FLASH_SECT (520) +#endif -#endif /* __CONFIG_H */ +#ifdef CONFIG_ARCH_VERSATILE_PB /* Versatile PB is default */ +#define FLASH_SECTOR_SIZE 0x00040000 /* 256 KB sectors */ +#define CONFIG_ENV_SECT_SIZE FLASH_SECTOR_SIZE +#define CONFIG_SYS_MAX_FLASH_SECT (260) +#endif + +#define CONFIG_SYS_FLASH_BASE 0x34000000 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 + +#define CONFIG_SYS_MONITOR_LEN (4 * CONFIG_ENV_SECT_SIZE) + +/* The ARM Boot Monitor is shipped in the lowest sector of flash */ + +#define FLASH_TOP (CONFIG_SYS_FLASH_BASE + PHYS_FLASH_SIZE) +#define CONFIG_ENV_SIZE 8192 +#define CONFIG_ENV_ADDR (FLASH_TOP - CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) +#define CONFIG_SYS_MONITOR_BASE (CONFIG_ENV_ADDR - CONFIG_SYS_MONITOR_LEN) + +#define CONFIG_SYS_FLASH_PROTECTION /* The devices have real protection */ +#define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */ + +#endif /* __CONFIG_H */