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Code cleanup

This commit is contained in:
Wolfgang Denk 2006-07-21 11:56:05 +02:00
parent 87a5c73d66
commit b9365a26a1
14 changed files with 130 additions and 132 deletions
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8
CHANGELOG
View File

@ -2,6 +2,8 @@
Changes since U-Boot 1.1.4:
======================================================================
* Code cleanup
* Update NetStar board
Patch by Ladislav Michl, 03 Nov 2005
@ -10,13 +12,13 @@ Changes since U-Boot 1.1.4:
* Enable initrd ATAG for xm250 board.
Patch by Josef Wagner, 05 Sep 2005
* Add readline cmdline-editing extension
Patch by JinHua Luo, 01 Sep 2005
* Add support for friendly-arm SBC-2410X board
Patch by JinHua Luo, 01 Sep 2005
* Fix multi-part image support on i386 platform.
Patch by David Updegraff, 19 Aug 2005

6
README
View File

@ -306,7 +306,7 @@ The following options need to be configured:
CONFIG_ARMADILLO, CONFIG_AT91RM9200DK, CONFIG_CERF250,
CONFIG_CSB637, CONFIG_DELTA, CONFIG_DNP1110,
CONFIG_EP7312, CONFIG_H2_OMAP1610, CONFIG_HHP_CRADLE,
CONFIG_EP7312, CONFIG_H2_OMAP1610, CONFIG_HHP_CRADLE,
CONFIG_IMPA7, CONFIG_INNOVATOROMAP1510, CONFIG_INNOVATOROMAP1610,
CONFIG_KB9202, CONFIG_LART, CONFIG_LPD7A400,
CONFIG_LUBBOCK, CONFIG_OSK_OMAP5912, CONFIG_OMAP2420H4,
@ -1493,8 +1493,8 @@ The following options need to be configured:
- Commandline Editing and History:
CONFIG_CMDLINE_EDITING
Enable editiong and History functions for interactive
commandline input operations
Enable editiong and History functions for interactive
commandline input operations
- Default Environment:
CONFIG_EXTRA_ENV_SETTINGS

8
board/MAI/bios_emulator/scitech/src/pm/win32/event.c
View File

@ -147,14 +147,14 @@ void _EVT_pumpMessages(void)
if (EVT.oldMove != -1) {
EVT.evtq[EVT.oldMove].where_x = evt.where_x;/* Modify existing one */
EVT.evtq[EVT.oldMove].where_y = evt.where_y;
/* EVT.evtq[EVT.oldMove].relative_x += mickeyX; // TODO! */
/* EVT.evtq[EVT.oldMove].relative_y += mickeyY; // TODO! */
/* EVT.evtq[EVT.oldMove].relative_x += mickeyX; / / TODO! */
/* EVT.evtq[EVT.oldMove].relative_y += mickeyY; / / TODO! */
evt.what = 0;
}
else {
EVT.oldMove = EVT.freeHead; /* Save id of this move event */
/* evt.relative_x = mickeyX; // TODO! */
/* evt.relative_y = mickeyY; // TODO! */
/* evt.relative_x = mickeyX; / / TODO! */
/* evt.relative_y = mickeyY; / / TODO! */
}
}
else

2
board/netstar/crcek.S
View File

@ -113,7 +113,7 @@ locking:
ldr r0, MPU_CLKM_BASE @ base of CLOCK unit
mov r1, #(1 << 10) @ disable idle mode do not check
@ nWAKEUP pin, other remain active
strh r1, [r0, #0x04]
strh r1, [r0, #0x04]
ldr r1, EN_CLK_VAL
strh r1, [r0, #0x08]
mov r1, #0x003f @ FLASH.RP not enabled in idle and

1
board/netstar/eeprom.c
View File

@ -213,4 +213,3 @@ int eeprom(int argc, char *argv[])
return 0;
}

5
board/netstar/nand.c
View File

@ -57,11 +57,10 @@ static int netstar_nand_ready(struct mtd_info *mtd)
void board_nand_init(struct nand_chip *nand)
{
nand->options = NAND_SAMSUNG_LP_OPTIONS;
nand->options = NAND_SAMSUNG_LP_OPTIONS;
nand->eccmode = NAND_ECC_SOFT;
nand->hwcontrol = netstar_nand_hwcontrol;
nand->hwcontrol = netstar_nand_hwcontrol;
/* nand->dev_ready = netstar_nand_ready; */
nand->chip_delay = 18;
}
#endif

1
board/netstar/netstar.c
View File

@ -59,4 +59,3 @@ int board_late_init(void)
{
return 0;
}

20
board/netstar/setup.S
View File

@ -58,10 +58,10 @@ VAL_EMIFF_SDRAM_CONFIG: .word ((0 << 0) | (0 << 1) | (3 << 2) | (0xf << 4) | (0
VAL_EMIFF_SDRAM_CONFIG: .word ((0 << 0) | (0 << 1) | (3 << 2) | (0xd << 4) | (0x246 << 8) | (0 << 24) | (0 << 26) | (0 << 27))
#endif
VAL_EMIFF_SDRAM_CONFIG2: .word 0x00000003
VAL_EMIFF_SDRAM_CONFIG2: .word 0x00000003
VAL_EMIFF_MRS: .word 0x00000037
/*
/*
* GPIO04 - Green LED (Red LED is connected to LED Pulse Generator)
* GPIO07 - LAN91C111 reset
*/
@ -106,7 +106,7 @@ MUX_CONFIG_OFFSETS:
.align 1
.byte 0x00 @ FUNC_MUX_CTRL_0
.byte 0x04 @ FUNC_MUX_CTRL_1
.byte 0x08 @ FUNC_MUX_CTRL_2
.byte 0x08 @ FUNC_MUX_CTRL_2
.byte 0x10 @ FUNC_MUX_CTRL_3
.byte 0x14 @ FUNC_MUX_CTRL_4
.byte 0x18 @ FUNC_MUX_CTRL_5
@ -180,7 +180,7 @@ locking:
ldr r0, OMAP5910_MPU_CLKM_BASE @ base of CLOCK unit
mov r1, #(1 << 10) @ disable idle mode do not check
@ nWAKEUP pin, other remain active
strh r1, [r0, #0x04]
strh r1, [r0, #0x04]
ldr r1, _OMAP5910_ARM_EN_CLK
strh r1, [r0, #0x08]
mov r1, #0x003f @ FLASH.RP not enabled in idle and
@ -190,7 +190,7 @@ locking:
ldr r0, MUX_CONFIG_BASE
adr r1, MUX_CONFIG_VALUES
adr r2, MUX_CONFIG_OFFSETS
next_mux_cfg:
next_mux_cfg:
ldrb r3, [r2], #1
ldr r4, [r1], #4
cmp r3, #0xff
@ -237,15 +237,15 @@ next_mux_cfg:
strh r1, [r0, #0x34]
/* Setup clock divisors */
ldr r0, OMAP5910_ULPD_PWR_MNG_BASE @ base of ULDPL DPLL1 register
ldr r0, OMAP5910_ULPD_PWR_MNG_BASE @ base of ULDPL DPLL1 register
mov r1, #0x0010 @ set PLL_ENABLE
orr r1, r1, #0x2000 @ set IOB to new locking
strh r1, [r0] @ write
orr r1, r1, #0x2000 @ set IOB to new locking
strh r1, [r0] @ write
ulocking:
ldrh r1, [r0] @ get DPLL value
tst r1, #1
tst r1, #1
beq ulocking @ while LOCK not set
/* EMIF init */
@ -254,7 +254,7 @@ ulocking:
bic r1, r1, #0x0c @ pwr down disabled, flash WP
orr r1, r1, #0x01
str r1, [r0, #0x0c]
ldr r1, VAL_EMIFS_CS0_CONFIG
str r1, [r0, #0x10] @ EMIFS_CS0_CONFIG
ldr r1, VAL_EMIFS_CS1_CONFIG

1
board/ppmc7xx/config.mk
View File

@ -22,7 +22,6 @@
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
TEXT_BASE = 0xFFF00000
TEXT_END = 0xFFF40000

130
board/sbc2410x/lowlevel_init.S
View File

@ -43,82 +43,82 @@
#define BWSCON 0x48000000
/* BWSCON */
#define DW8 (0x0)
#define DW16 (0x1)
#define DW32 (0x2)
#define WAIT (0x1<<2)
#define UBLB (0x1<<3)
#define DW8 (0x0)
#define DW16 (0x1)
#define DW32 (0x2)
#define WAIT (0x1<<2)
#define UBLB (0x1<<3)
#define B1_BWSCON (DW16)
#define B2_BWSCON (DW16)
#define B3_BWSCON (DW16 + WAIT + UBLB)
#define B4_BWSCON (DW16)
#define B5_BWSCON (DW16)
#define B6_BWSCON (DW32)
#define B7_BWSCON (DW32)
#define B1_BWSCON (DW16)
#define B2_BWSCON (DW16)
#define B3_BWSCON (DW16 + WAIT + UBLB)
#define B4_BWSCON (DW16)
#define B5_BWSCON (DW16)
#define B6_BWSCON (DW32)
#define B7_BWSCON (DW32)
#define B0_Tacs 0x0
#define B0_Tcos 0x0
#define B0_Tacc 0x7
#define B0_Tcoh 0x0
#define B0_Tah 0x0
#define B0_Tacp 0x0
#define B0_PMC 0x0
#define B0_Tacs 0x0
#define B0_Tcos 0x0
#define B0_Tacc 0x7
#define B0_Tcoh 0x0
#define B0_Tah 0x0
#define B0_Tacp 0x0
#define B0_PMC 0x0
#define B1_Tacs 0x0
#define B1_Tcos 0x0
#define B1_Tacc 0x7
#define B1_Tcoh 0x0
#define B1_Tah 0x0
#define B1_Tacp 0x0
#define B1_PMC 0x0
#define B1_Tacs 0x0
#define B1_Tcos 0x0
#define B1_Tacc 0x7
#define B1_Tcoh 0x0
#define B1_Tah 0x0
#define B1_Tacp 0x0
#define B1_PMC 0x0
#define B2_Tacs 0x0
#define B2_Tcos 0x0
#define B2_Tacc 0x7
#define B2_Tcoh 0x0
#define B2_Tah 0x0
#define B2_Tacp 0x0
#define B2_PMC 0x0
#define B2_Tacs 0x0
#define B2_Tcos 0x0
#define B2_Tacc 0x7
#define B2_Tcoh 0x0
#define B2_Tah 0x0
#define B2_Tacp 0x0
#define B2_PMC 0x0
#define B3_Tacs 0xc
#define B3_Tcos 0x7
#define B3_Tacc 0xf
#define B3_Tcoh 0x1
#define B3_Tah 0x0
#define B3_Tacp 0x0
#define B3_PMC 0x0
#define B3_Tacs 0xc
#define B3_Tcos 0x7
#define B3_Tacc 0xf
#define B3_Tcoh 0x1
#define B3_Tah 0x0
#define B3_Tacp 0x0
#define B3_PMC 0x0
#define B4_Tacs 0x0
#define B4_Tcos 0x0
#define B4_Tacc 0x7
#define B4_Tcoh 0x0
#define B4_Tah 0x0
#define B4_Tacp 0x0
#define B4_PMC 0x0
#define B4_Tacs 0x0
#define B4_Tcos 0x0
#define B4_Tacc 0x7
#define B4_Tcoh 0x0
#define B4_Tah 0x0
#define B4_Tacp 0x0
#define B4_PMC 0x0
#define B5_Tacs 0xc
#define B5_Tcos 0x7
#define B5_Tacc 0xf
#define B5_Tcoh 0x1
#define B5_Tah 0x0
#define B5_Tacp 0x0
#define B5_PMC 0x0
#define B5_Tacs 0xc
#define B5_Tcos 0x7
#define B5_Tacc 0xf
#define B5_Tcoh 0x1
#define B5_Tah 0x0
#define B5_Tacp 0x0
#define B5_PMC 0x0
#define B6_MT 0x3 /* SDRAM */
#define B6_Trcd 0x1
#define B6_SCAN 0x1 /* 9bit */
#define B6_MT 0x3 /* SDRAM */
#define B6_Trcd 0x1
#define B6_SCAN 0x1 /* 9bit */
#define B7_MT 0x3 /* SDRAM */
#define B7_Trcd 0x1 /* 3clk */
#define B7_SCAN 0x1 /* 9bit */
#define B7_MT 0x3 /* SDRAM */
#define B7_Trcd 0x1 /* 3clk */
#define B7_SCAN 0x1 /* 9bit */
/* REFRESH parameter */
#define REFEN 0x1 /* Refresh enable */
#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */
#define Trp 0x0 /* 2clk */
#define Trc 0x3 /* 7clk */
#define Tchr 0x2 /* 3clk */
#define REFEN 0x1 /* Refresh enable */
#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */
#define Trp 0x0 /* 2clk */
#define Trc 0x3 /* 7clk */
#define Tchr 0x2 /* 3clk */
#define REFCNT 0x0459
/**************************************/

2
common/crc16.c
View File

@ -101,7 +101,7 @@ cyg_crc16(unsigned char *buf, int len)
cksum = 0;
for (i = 0; i < len; i++) {
cksum = crc16_tab[((cksum>>8) ^ *buf++) & 0xFF] ^ (cksum << 8);
cksum = crc16_tab[((cksum>>8) ^ *buf++) & 0xFF] ^ (cksum << 8);
}
return cksum;
}

2
cpu/ppc4xx/serial.c
View File

@ -1,5 +1,5 @@
/*
* (C) Copyright 2000
* (C) Copyright 2000-2006
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this

2
include/configs/sbc2410x.h
View File

@ -95,7 +95,7 @@
CFG_CMD_REGINFO | \
CFG_CMD_DATE | \
CFG_CMD_PING | \
CFG_CMD_DHCP | \
CFG_CMD_DHCP | \
CFG_CMD_ELF)
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */

74
include/linux/mtd/nand.h
View File

@ -2,7 +2,7 @@
* linux/include/linux/mtd/nand.h
*
* Copyright (c) 2000 David Woodhouse <dwmw2@mvhi.com>
* Steven J. Hill <sjhill@realitydiluted.com>
* Steven J. Hill <sjhill@realitydiluted.com>
* Thomas Gleixner <tglx@linutronix.de>
*
* $Id: nand.h,v 1.68 2004/11/12 10:40:37 gleixner Exp $
@ -15,15 +15,15 @@
* Contains standard defines and IDs for NAND flash devices
*
* Changelog:
* 01-31-2000 DMW Created
* 09-18-2000 SJH Moved structure out of the Disk-On-Chip drivers
* 01-31-2000 DMW Created
* 09-18-2000 SJH Moved structure out of the Disk-On-Chip drivers
* so it can be used by other NAND flash device
* drivers. I also changed the copyright since none
* of the original contents of this file are specific
* to DoC devices. David can whack me with a baseball
* bat later if I did something naughty.
* 10-11-2000 SJH Added private NAND flash structure for driver
* 10-24-2000 SJH Added prototype for 'nand_scan' function
* 10-11-2000 SJH Added private NAND flash structure for driver
* 10-24-2000 SJH Added prototype for 'nand_scan' function
* 10-29-2001 TG changed nand_chip structure to support
* hardwarespecific function for accessing control lines
* 02-21-2002 TG added support for different read/write adress and
@ -36,7 +36,7 @@
* CONFIG_MTD_NAND_ECC_JFFS2 is not set
* 08-10-2002 TG extensions to nand_chip structure to support HW-ECC
*
* 08-29-2002 tglx nand_chip structure: data_poi for selecting
* 08-29-2002 tglx nand_chip structure: data_poi for selecting
* internal / fs-driver buffer
* support for 6byte/512byte hardware ECC
* read_ecc, write_ecc extended for different oob-layout
@ -45,8 +45,8 @@
* 11-25-2002 tglx Added Manufacturer code FUJITSU, NATIONAL
* Split manufacturer and device ID structures
*
* 02-08-2004 tglx added option field to nand structure for chip anomalities
* 05-25-2004 tglx added bad block table support, ST-MICRO manufacturer id
* 02-08-2004 tglx added option field to nand structure for chip anomalities
* 05-25-2004 tglx added bad block table support, ST-MICRO manufacturer id
* update of nand_chip structure description
*/
#ifndef __LINUX_MTD_NAND_H
@ -75,7 +75,7 @@ extern int nand_read_raw (struct mtd_info *mtd, uint8_t *buf, loff_t from, size_
* Constants for hardware specific CLE/ALE/NCE function
*/
/* Select the chip by setting nCE to low */
#define NAND_CTL_SETNCE 1
#define NAND_CTL_SETNCE 1
/* Deselect the chip by setting nCE to high */
#define NAND_CTL_CLRNCE 2
/* Select the command latch by setting CLE to high */
@ -215,7 +215,7 @@ struct nand_chip;
#if 0
/**
* struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independend devices
* @lock: protection lock
* @lock: protection lock
* @active: the mtd device which holds the controller currently
*/
struct nand_hw_control {
@ -244,20 +244,20 @@ struct nand_hw_control {
* is read from the chip status register
* @cmdfunc: [REPLACEABLE] hardwarespecific function for writing commands to the chip
* @waitfunc: [REPLACEABLE] hardwarespecific function for wait on ready
* @calculate_ecc: [REPLACEABLE] function for ecc calculation or readback from ecc hardware
* @calculate_ecc: [REPLACEABLE] function for ecc calculation or readback from ecc hardware
* @correct_data: [REPLACEABLE] function for ecc correction, matching to ecc generator (sw/hw)
* @enable_hwecc: [BOARDSPECIFIC] function to enable (reset) hardware ecc generator. Must only
* be provided if a hardware ECC is available
* @erase_cmd: [INTERN] erase command write function, selectable due to AND support
* @scan_bbt: [REPLACEABLE] function to scan bad block table
* @eccmode: [BOARDSPECIFIC] mode of ecc, see defines
* @eccsize: [INTERN] databytes used per ecc-calculation
* @eccbytes: [INTERN] number of ecc bytes per ecc-calculation step
* @eccsize: [INTERN] databytes used per ecc-calculation
* @eccbytes: [INTERN] number of ecc bytes per ecc-calculation step
* @eccsteps: [INTERN] number of ecc calculation steps per page
* @chip_delay: [BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR)
* @chip_lock: [INTERN] spinlock used to protect access to this structure and the chip
* @wq: [INTERN] wait queue to sleep on if a NAND operation is in progress
* @state: [INTERN] the current state of the NAND device
* @state: [INTERN] the current state of the NAND device
* @page_shift: [INTERN] number of address bits in a page (column address bits)
* @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock
* @bbt_erase_shift: [INTERN] number of address bits in a bbt entry
@ -284,7 +284,7 @@ struct nand_hw_control {
struct nand_chip {
void __iomem *IO_ADDR_R;
void __iomem *IO_ADDR_W;
void __iomem *IO_ADDR_W;
u_char (*read_byte)(struct mtd_info *mtd);
void (*write_byte)(struct mtd_info *mtd, u_char byte);
@ -297,12 +297,12 @@ struct nand_chip {
void (*select_chip)(struct mtd_info *mtd, int chip);
int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip);
int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
void (*hwcontrol)(struct mtd_info *mtd, int cmd);
int (*dev_ready)(struct mtd_info *mtd);
void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, int page_addr);
int (*waitfunc)(struct mtd_info *mtd, struct nand_chip *this, int state);
void (*hwcontrol)(struct mtd_info *mtd, int cmd);
int (*dev_ready)(struct mtd_info *mtd);
void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, int page_addr);
int (*waitfunc)(struct mtd_info *mtd, struct nand_chip *this, int state);
int (*calculate_ecc)(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code);
int (*correct_data)(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc);
int (*correct_data)(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc);
void (*enable_hwecc)(struct mtd_info *mtd, int mode);
void (*erase_cmd)(struct mtd_info *mtd, int page);
int (*scan_bbt)(struct mtd_info *mtd);
@ -310,17 +310,17 @@ struct nand_chip {
int eccsize;
int eccbytes;
int eccsteps;
int chip_delay;
int chip_delay;
#if 0
spinlock_t chip_lock;
wait_queue_head_t wq;
nand_state_t state;
nand_state_t state;
#endif
int page_shift;
int page_shift;
int phys_erase_shift;
int bbt_erase_shift;
int chip_shift;
u_char *data_buf;
u_char *data_buf;
u_char *oob_buf;
int oobdirty;
u_char *data_poi;
@ -335,7 +335,7 @@ struct nand_chip {
struct nand_bbt_descr *bbt_td;
struct nand_bbt_descr *bbt_md;
struct nand_bbt_descr *badblock_pattern;
struct nand_hw_control *controller;
struct nand_hw_control *controller;
void *priv;
};
@ -352,14 +352,14 @@ struct nand_chip {
/**
* struct nand_flash_dev - NAND Flash Device ID Structure
*
* @name: Identify the device type
* @id: device ID code
* @pagesize: Pagesize in bytes. Either 256 or 512 or 0
* @name: Identify the device type
* @id: device ID code
* @pagesize: Pagesize in bytes. Either 256 or 512 or 0
* If the pagesize is 0, then the real pagesize
* and the eraseize are determined from the
* extended id bytes in the chip
* @erasesize: Size of an erase block in the flash device.
* @chipsize: Total chipsize in Mega Bytes
* @erasesize: Size of an erase block in the flash device.
* @chipsize: Total chipsize in Mega Bytes
* @options: Bitfield to store chip relevant options
*/
struct nand_flash_dev {
@ -374,7 +374,7 @@ struct nand_flash_dev {
/**
* struct nand_manufacturers - NAND Flash Manufacturer ID Structure
* @name: Manufacturer name
* @id: manufacturer ID code of device.
* @id: manufacturer ID code of device.
*/
struct nand_manufacturers {
int id;
@ -398,7 +398,7 @@ extern struct nand_manufacturers nand_manuf_ids[];
* blocks is reserved at the end of the device where the tables are
* written.
* @reserved_block_code: if non-0, this pattern denotes a reserved (rather than
* bad) block in the stored bbt
* bad) block in the stored bbt
* @pattern: pattern to identify bad block table or factory marked good /
* bad blocks, can be NULL, if len = 0
*
@ -412,11 +412,11 @@ struct nand_bbt_descr {
int pages[NAND_MAX_CHIPS];
int offs;
int veroffs;
uint8_t version[NAND_MAX_CHIPS];
uint8_t version[NAND_MAX_CHIPS];
int len;
int maxblocks;
int maxblocks;
int reserved_block_code;
uint8_t *pattern;
uint8_t *pattern;
};
/* Options for the bad block table descriptors */
@ -428,7 +428,7 @@ struct nand_bbt_descr {
#define NAND_BBT_4BIT 0x00000004
#define NAND_BBT_8BIT 0x00000008
/* The bad block table is in the last good block of the device */
#define NAND_BBT_LASTBLOCK 0x00000010
#define NAND_BBT_LASTBLOCK 0x00000010
/* The bbt is at the given page, else we must scan for the bbt */
#define NAND_BBT_ABSPAGE 0x00000020
/* The bbt is at the given page, else we must scan for the bbt */
@ -451,7 +451,7 @@ struct nand_bbt_descr {
#define NAND_BBT_SCAN2NDPAGE 0x00004000
/* The maximum number of blocks to scan for a bbt */
#define NAND_BBT_SCAN_MAXBLOCKS 4
#define NAND_BBT_SCAN_MAXBLOCKS 4
extern int nand_scan_bbt (struct mtd_info *mtd, struct nand_bbt_descr *bd);
extern int nand_update_bbt (struct mtd_info *mtd, loff_t offs);