Add Sandburst Metrobox and Sandburst Karef board support packages.
Second serial port on 440GX now defined as a system device. Add 'Short Etch' code for Cicada PHY within 440gx_enet.c Patch by Travis B. Sawyer, 12 Jul 2005 Check return value of malloc in 440gx_enet.c Patch by Travis B. Sawyer, 18 Jul 2005
This commit is contained in:
Stefan Roese
parent
2893ecbf3e
commit
b79316f2a2
12
CHANGELOG
12
CHANGELOG
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@ -1,3 +1,15 @@
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======================================================================
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Changes for U-Boot 1.1.4:
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======================================================================
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* Check return value of malloc in 440gx_enet.c
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Patch by Travis B. Sawyer, 18 Jul 2005
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* Add Sandburst Metrobox and Sandburst Karef board support packages.
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Second serial port on 440GX now defined as a system device.
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Add 'Short Etch' code for Cicada PHY within 440gx_enet.c
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Patch by Travis B. Sawyer, 12 Jul 2005
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======================================================================
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Changes for U-Boot 1.1.3:
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======================================================================
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@ -277,6 +277,8 @@ Yusdi Santoso <yusdi_santoso@adaptec.com>
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Travis Sawyer (travis.sawyer@sandburst.com>
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KAREF PPC440GX
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METROBOX PPC440GX
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XPEDITE1K PPC440GX
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Peter De Schrijver <p2@mind.be>
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12
MAKEALL
12
MAKEALL
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@ -65,12 +65,12 @@ LIST_4xx=" \
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CPCI440 CPCIISER4 CRAYL1 csb272 \
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csb472 DASA_SIM DP405 DU405 \
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ebony ERIC EXBITGEN HUB405 \
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JSE MIP405 MIP405T ML2 \
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ml300 ocotea OCRTC ORSG \
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PCI405 PIP405 PLU405 PMC405 \
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PPChameleonEVB VOH405 W7OLMC W7OLMG \
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walnut WUH405 XPEDITE1K yellowstone \
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yosemite \
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JSE KAREF METROBOX MIP405 \
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MIP405T ML2 ml300 ocotea \
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OCRTC ORSG PCI405 PIP405 \
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PLU405 PMC405 PPChameleonEVB VOH405 \
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W7OLMC W7OLMG walnut WUH405 \
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XPEDITE1K yellowstone yosemite \
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"
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#########################################################################
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6
Makefile
6
Makefile
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@ -794,6 +794,12 @@ HUB405_config: unconfig
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JSE_config: unconfig
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@./mkconfig $(@:_config=) ppc ppc4xx jse
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KAREF_config: unconfig
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@./mkconfig $(@:_config=) ppc ppc4xx karef sandburst
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METROBOX_config: unconfig
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@./mkconfig $(@:_config=) ppc ppc4xx metrobox sandburst
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MIP405_config: unconfig
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@./mkconfig $(@:_config=) ppc ppc4xx mip405 mpl
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@ -0,0 +1,512 @@
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/*
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* (C) Copyright 2002-2005
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
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* Add support for Am29F016D and dynamic switch setting.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* Ported from Ebony flash support
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* Travis B. Sawyer
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* Sandburst Corporation
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*/
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#include <common.h>
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#include <ppc4xx.h>
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#include <asm/processor.h>
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#undef DEBUG
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#ifdef DEBUG
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#define DEBUGF(x...) printf(x)
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#else
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#define DEBUGF(x...)
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#endif /* DEBUG */
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flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
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static unsigned long flash_addr_table[8][CFG_MAX_FLASH_BANKS] = {
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{0xfff80000} /* Boot Flash */
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};
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/*-----------------------------------------------------------------------
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* Functions
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*/
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static ulong flash_get_size (vu_long *addr, flash_info_t *info);
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static int write_word (flash_info_t *info, ulong dest, ulong data);
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#define ADDR0 0x5555
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#define ADDR1 0x2aaa
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#define FLASH_WORD_SIZE unsigned char
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/*-----------------------------------------------------------------------
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*/
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unsigned long flash_init (void)
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{
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unsigned long total_b = 0;
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unsigned long size_b[CFG_MAX_FLASH_BANKS];
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unsigned short index = 0;
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int i;
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DEBUGF("\n");
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DEBUGF("FLASH: Index: %d\n", index);
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/* Init: no FLASHes known */
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for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
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flash_info[i].flash_id = FLASH_UNKNOWN;
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flash_info[i].sector_count = -1;
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flash_info[i].size = 0;
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/* check whether the address is 0 */
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if (flash_addr_table[index][i] == 0) {
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continue;
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}
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/* call flash_get_size() to initialize sector address */
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size_b[i] = flash_get_size(
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(vu_long *)flash_addr_table[index][i], &flash_info[i]);
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flash_info[i].size = size_b[i];
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if (flash_info[i].flash_id == FLASH_UNKNOWN) {
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printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
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i, size_b[i], size_b[i]<<20);
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flash_info[i].sector_count = -1;
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flash_info[i].size = 0;
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}
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total_b += flash_info[i].size;
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}
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return total_b;
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}
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/*-----------------------------------------------------------------------
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*/
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void flash_print_info (flash_info_t *info)
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{
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int i;
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int k;
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int size;
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int erased;
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volatile unsigned long *flash;
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if (info->flash_id == FLASH_UNKNOWN) {
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printf ("missing or unknown FLASH type\n");
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return;
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}
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switch (info->flash_id & FLASH_VENDMASK) {
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case FLASH_MAN_AMD: printf ("AMD "); break;
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default: printf ("Unknown Vendor "); break;
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}
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switch (info->flash_id & FLASH_TYPEMASK) {
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case FLASH_AM040: printf ("AM29F040 (512 Kbit, uniform sector size)\n");
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break;
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default: printf ("Unknown Chip Type\n");
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break;
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}
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printf (" Size: %ld KB in %d Sectors\n",
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info->size >> 10, info->sector_count);
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printf (" Sector Start Addresses:");
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for (i=0; i<info->sector_count; ++i) {
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/*
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* Check if whole sector is erased
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*/
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if (i != (info->sector_count-1))
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size = info->start[i+1] - info->start[i];
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else
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size = info->start[0] + info->size - info->start[i];
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erased = 1;
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flash = (volatile unsigned long *)info->start[i];
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size = size >> 2; /* divide by 4 for longword access */
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for (k=0; k<size; k++)
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{
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if (*flash++ != 0xffffffff)
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{
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erased = 0;
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break;
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}
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}
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if ((i % 5) == 0)
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printf ("\n ");
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printf (" %08lX%s%s",
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info->start[i],
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erased ? " E" : " ",
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info->protect[i] ? "RO " : " "
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);
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}
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printf ("\n");
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return;
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}
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/*-----------------------------------------------------------------------
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*/
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/*-----------------------------------------------------------------------
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*/
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/*
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* The following code cannot be run from FLASH!
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*/
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static ulong flash_get_size (vu_long *addr, flash_info_t *info)
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{
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short i;
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FLASH_WORD_SIZE value;
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ulong base = (ulong)addr;
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volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr;
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DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr );
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/* Write auto select command: read Manufacturer ID */
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udelay(10000);
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addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
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udelay(1000);
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addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
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udelay(1000);
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addr2[ADDR0] = (FLASH_WORD_SIZE)0x00900090;
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udelay(1000);
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value = addr2[0];
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DEBUGF("FLASH MANUFACT: %x\n", value);
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switch (value) {
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case (FLASH_WORD_SIZE)AMD_MANUFACT:
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info->flash_id = FLASH_MAN_AMD;
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break;
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default:
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info->flash_id = FLASH_UNKNOWN;
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info->sector_count = 0;
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info->size = 0;
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return (0); /* no or unknown flash */
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}
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value = addr2[1]; /* device ID */
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DEBUGF("\nFLASH DEVICEID: %x\n", value);
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switch (value) {
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case (FLASH_WORD_SIZE)AMD_ID_LV040B:
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info->flash_id += FLASH_AM040;
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info->sector_count = 8;
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info->size = 0x00080000; /* => 512 kb */
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break;
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default:
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info->flash_id = FLASH_UNKNOWN;
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return (0); /* => no or unknown flash */
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}
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/* set up sector start address table */
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if (info->flash_id == FLASH_AM040) {
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for (i = 0; i < info->sector_count; i++)
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info->start[i] = base + (i * 0x00010000);
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} else {
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if (info->flash_id & FLASH_BTYPE) {
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/* set sector offsets for bottom boot block type */
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info->start[0] = base + 0x00000000;
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info->start[1] = base + 0x00004000;
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info->start[2] = base + 0x00006000;
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info->start[3] = base + 0x00008000;
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for (i = 4; i < info->sector_count; i++) {
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info->start[i] = base + (i * 0x00010000) - 0x00030000;
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}
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} else {
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/* set sector offsets for top boot block type */
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i = info->sector_count - 1;
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info->start[i--] = base + info->size - 0x00004000;
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info->start[i--] = base + info->size - 0x00006000;
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info->start[i--] = base + info->size - 0x00008000;
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for (; i >= 0; i--) {
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info->start[i] = base + i * 0x00010000;
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}
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}
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}
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/* check for protected sectors */
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for (i = 0; i < info->sector_count; i++) {
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/* read sector protection at sector address, (A7 .. A0) = 0x02 */
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/* D0 = 1 if protected */
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addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]);
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if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
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info->protect[i] = 0;
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else
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info->protect[i] = addr2[2] & 1;
|
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}
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|
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/* reset to return to reading data */
|
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addr2[0] = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */
|
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|
||||
/*
|
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* Prevent writes to uninitialized FLASH.
|
||||
*/
|
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if (info->flash_id != FLASH_UNKNOWN) {
|
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addr2 = (FLASH_WORD_SIZE *)info->start[0];
|
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*addr2 = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
|
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}
|
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|
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return (info->size);
|
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}
|
||||
|
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int wait_for_DQ7(flash_info_t *info, int sect)
|
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{
|
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ulong start, now, last;
|
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volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[sect]);
|
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|
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start = get_timer (0);
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last = start;
|
||||
while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) {
|
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if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
|
||||
printf ("Timeout\n");
|
||||
return -1;
|
||||
}
|
||||
/* show that we're waiting */
|
||||
if ((now - last) > 1000) { /* every second */
|
||||
putc ('.');
|
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last = now;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
int flash_erase (flash_info_t *info, int s_first, int s_last)
|
||||
{
|
||||
volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]);
|
||||
volatile FLASH_WORD_SIZE *addr2;
|
||||
int flag, prot, sect, l_sect;
|
||||
int i;
|
||||
|
||||
if ((s_first < 0) || (s_first > s_last)) {
|
||||
if (info->flash_id == FLASH_UNKNOWN) {
|
||||
printf ("- missing\n");
|
||||
} else {
|
||||
printf ("- no sectors to erase\n");
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
if (info->flash_id == FLASH_UNKNOWN) {
|
||||
printf ("Can't erase unknown flash type - aborted\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
prot = 0;
|
||||
for (sect=s_first; sect<=s_last; ++sect) {
|
||||
if (info->protect[sect]) {
|
||||
prot++;
|
||||
}
|
||||
}
|
||||
|
||||
if (prot) {
|
||||
printf ("- Warning: %d protected sectors will not be erased!\n",
|
||||
prot);
|
||||
} else {
|
||||
printf ("\n");
|
||||
}
|
||||
|
||||
l_sect = -1;
|
||||
|
||||
/* Disable interrupts which might cause a timeout here */
|
||||
flag = disable_interrupts();
|
||||
|
||||
/* Start erase on unprotected sectors */
|
||||
for (sect = s_first; sect<=s_last; sect++) {
|
||||
if (info->protect[sect] == 0) { /* not protected */
|
||||
addr2 = (FLASH_WORD_SIZE *)(info->start[sect]);
|
||||
DEBUGF("Erasing sector %p\n", addr2);
|
||||
|
||||
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
|
||||
addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
|
||||
addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
|
||||
addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080;
|
||||
addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
|
||||
addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
|
||||
addr2[0] = (FLASH_WORD_SIZE)0x00500050; /* block erase */
|
||||
for (i=0; i<50; i++)
|
||||
udelay(1000); /* wait 1 ms */
|
||||
} else {
|
||||
addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
|
||||
addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
|
||||
addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080;
|
||||
addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
|
||||
addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
|
||||
addr2[0] = (FLASH_WORD_SIZE)0x00300030; /* sector erase */
|
||||
}
|
||||
l_sect = sect;
|
||||
/*
|
||||
* Wait for each sector to complete, it's more
|
||||
* reliable. According to AMD Spec, you must
|
||||
* issue all erase commands within a specified
|
||||
* timeout. This has been seen to fail, especially
|
||||
* if printf()s are included (for debug)!!
|
||||
*/
|
||||
wait_for_DQ7(info, sect);
|
||||
}
|
||||
}
|
||||
|
||||
/* re-enable interrupts if necessary */
|
||||
if (flag)
|
||||
enable_interrupts();
|
||||
|
||||
/* wait at least 80us - let's wait 1 ms */
|
||||
udelay (1000);
|
||||
|
||||
/* reset to read mode */
|
||||
addr = (FLASH_WORD_SIZE *)info->start[0];
|
||||
addr[0] = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
|
||||
|
||||
printf (" done\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Copy memory to flash, returns:
|
||||
* 0 - OK
|
||||
* 1 - write timeout
|
||||
* 2 - Flash not erased
|
||||
*/
|
||||
|
||||
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
|
||||
{
|
||||
ulong cp, wp, data;
|
||||
int i, l, rc;
|
||||
|
||||
wp = (addr & ~3); /* get lower word aligned address */
|
||||
|
||||
/*
|
||||
* handle unaligned start bytes
|
||||
*/
|
||||
if ((l = addr - wp) != 0) {
|
||||
data = 0;
|
||||
for (i=0, cp=wp; i<l; ++i, ++cp) {
|
||||
data = (data << 8) | (*(uchar *)cp);
|
||||
}
|
||||
for (; i<4 && cnt>0; ++i) {
|
||||
data = (data << 8) | *src++;
|
||||
--cnt;
|
||||
++cp;
|
||||
}
|
||||
for (; cnt==0 && i<4; ++i, ++cp) {
|
||||
data = (data << 8) | (*(uchar *)cp);
|
||||
}
|
||||
|
||||
if ((rc = write_word(info, wp, data)) != 0) {
|
||||
return (rc);
|
||||
}
|
||||
wp += 4;
|
||||
}
|
||||
|
||||
/*
|
||||
* handle word aligned part
|
||||
*/
|
||||
while (cnt >= 4) {
|
||||
data = 0;
|
||||
for (i=0; i<4; ++i) {
|
||||
data = (data << 8) | *src++;
|
||||
}
|
||||
if ((rc = write_word(info, wp, data)) != 0) {
|
||||
return (rc);
|
||||
}
|
||||
wp += 4;
|
||||
cnt -= 4;
|
||||
}
|
||||
|
||||
if (cnt == 0) {
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*
|
||||
* handle unaligned tail bytes
|
||||
*/
|
||||
data = 0;
|
||||
for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
|
||||
data = (data << 8) | *src++;
|
||||
--cnt;
|
||||
}
|
||||
for (; i<4; ++i, ++cp) {
|
||||
data = (data << 8) | (*(uchar *)cp);
|
||||
}
|
||||
|
||||
return (write_word(info, wp, data));
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Write a word to Flash, returns:
|
||||
* 0 - OK
|
||||
* 1 - write timeout
|
||||
* 2 - Flash not erased
|
||||
*/
|
||||
static int write_word (flash_info_t * info, ulong dest, ulong data)
|
||||
{
|
||||
volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) (info->start[0]);
|
||||
volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest;
|
||||
volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data;
|
||||
ulong start;
|
||||
int i;
|
||||
|
||||
/* Check if Flash is (sufficiently) erased */
|
||||
if ((*((volatile FLASH_WORD_SIZE *) dest) &
|
||||
(FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) {
|
||||
return (2);
|
||||
}
|
||||
|
||||
for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) {
|
||||
int flag;
|
||||
|
||||
/* Disable interrupts which might cause a timeout here */
|
||||
flag = disable_interrupts ();
|
||||
|
||||
addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
|
||||
addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
|
||||
addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00A000A0;
|
||||
|
||||
dest2[i] = data2[i];
|
||||
|
||||
/* re-enable interrupts if necessary */
|
||||
if (flag)
|
||||
enable_interrupts ();
|
||||
|
||||
/* data polling for D7 */
|
||||
start = get_timer (0);
|
||||
while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) !=
|
||||
(data2[i] & (FLASH_WORD_SIZE) 0x00800080)) {
|
||||
|
||||
if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
|
||||
return (1);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
|
@ -0,0 +1,515 @@
|
|||
/*
|
||||
* Copyright (C) 2005 Sandburst Corporation
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* Ported from cpu/ppc4xx/i2c.c by AS HARNOIS by
|
||||
* Travis B. Sawyer
|
||||
* Sandburst Corporation.
|
||||
*/
|
||||
#include <common.h>
|
||||
#include <ppc4xx.h>
|
||||
#if defined(CONFIG_440)
|
||||
# include <440_i2c.h>
|
||||
#else
|
||||
# include <405gp_i2c.h>
|
||||
#endif
|
||||
#include <i2c.h>
|
||||
#include <440_i2c.h>
|
||||
#include <command.h>
|
||||
#include "ppc440gx_i2c.h"
|
||||
|
||||
#ifdef CONFIG_I2C_BUS1
|
||||
|
||||
|
||||
|
||||
#define IIC_OK 0
|
||||
#define IIC_NOK 1
|
||||
#define IIC_NOK_LA 2 /* Lost arbitration */
|
||||
#define IIC_NOK_ICT 3 /* Incomplete transfer */
|
||||
#define IIC_NOK_XFRA 4 /* Transfer aborted */
|
||||
#define IIC_NOK_DATA 5 /* No data in buffer */
|
||||
#define IIC_NOK_TOUT 6 /* Transfer timeout */
|
||||
|
||||
#define IIC_TIMEOUT 1 /* 1 second */
|
||||
#if defined(CFG_I2C_NOPROBES)
|
||||
static uchar i2c_no_probes[] = CFG_I2C_NOPROBES;
|
||||
#endif
|
||||
|
||||
static void _i2c_bus1_reset (void)
|
||||
{
|
||||
int i, status;
|
||||
|
||||
/* Reset status register */
|
||||
/* write 1 in SCMP and IRQA to clear these fields */
|
||||
out8 (IIC_STS1, 0x0A);
|
||||
|
||||
/* write 1 in IRQP IRQD LA ICT XFRA to clear these fields */
|
||||
out8 (IIC_EXTSTS1, 0x8F);
|
||||
__asm__ volatile ("eieio");
|
||||
|
||||
/*
|
||||
* Get current state, reset bus
|
||||
* only if no transfers are pending.
|
||||
*/
|
||||
i = 10;
|
||||
do {
|
||||
/* Get status */
|
||||
status = in8 (IIC_STS1);
|
||||
udelay (500); /* 500us */
|
||||
i--;
|
||||
} while ((status & IIC_STS_PT) && (i > 0));
|
||||
/* Soft reset controller */
|
||||
status = in8 (IIC_XTCNTLSS1);
|
||||
out8 (IIC_XTCNTLSS1, (status | IIC_XTCNTLSS_SRST));
|
||||
__asm__ volatile ("eieio");
|
||||
|
||||
/* make sure where in initial state, data hi, clock hi */
|
||||
out8 (IIC_DIRECTCNTL1, 0xC);
|
||||
for (i = 0; i < 10; i++) {
|
||||
if ((in8 (IIC_DIRECTCNTL1) & 0x3) != 0x3) {
|
||||
/* clock until we get to known state */
|
||||
out8 (IIC_DIRECTCNTL1, 0x8); /* clock lo */
|
||||
udelay (100); /* 100us */
|
||||
out8 (IIC_DIRECTCNTL1, 0xC); /* clock hi */
|
||||
udelay (100); /* 100us */
|
||||
} else {
|
||||
break;
|
||||
}
|
||||
}
|
||||
/* send start condition */
|
||||
out8 (IIC_DIRECTCNTL1, 0x4);
|
||||
udelay (1000); /* 1ms */
|
||||
/* send stop condition */
|
||||
out8 (IIC_DIRECTCNTL1, 0xC);
|
||||
udelay (1000); /* 1ms */
|
||||
/* Unreset controller */
|
||||
out8 (IIC_XTCNTLSS1, (status & ~IIC_XTCNTLSS_SRST));
|
||||
udelay (1000); /* 1ms */
|
||||
}
|
||||
|
||||
void i2c1_init (int speed, int slaveadd)
|
||||
{
|
||||
sys_info_t sysInfo;
|
||||
unsigned long freqOPB;
|
||||
int val, divisor;
|
||||
|
||||
#ifdef CFG_I2C_INIT_BOARD
|
||||
/* call board specific i2c bus reset routine before accessing the */
|
||||
/* environment, which might be in a chip on that bus. For details */
|
||||
/* about this problem see doc/I2C_Edge_Conditions. */
|
||||
i2c_init_board();
|
||||
#endif
|
||||
|
||||
/* Handle possible failed I2C state */
|
||||
/* FIXME: put this into i2c_init_board()? */
|
||||
_i2c_bus1_reset ();
|
||||
|
||||
/* clear lo master address */
|
||||
out8 (IIC_LMADR1, 0);
|
||||
|
||||
/* clear hi master address */
|
||||
out8 (IIC_HMADR1, 0);
|
||||
|
||||
/* clear lo slave address */
|
||||
out8 (IIC_LSADR1, 0);
|
||||
|
||||
/* clear hi slave address */
|
||||
out8 (IIC_HSADR1, 0);
|
||||
|
||||
/* Clock divide Register */
|
||||
/* get OPB frequency */
|
||||
get_sys_info (&sysInfo);
|
||||
freqOPB = sysInfo.freqPLB / sysInfo.pllOpbDiv;
|
||||
/* set divisor according to freqOPB */
|
||||
divisor = (freqOPB - 1) / 10000000;
|
||||
if (divisor == 0)
|
||||
divisor = 1;
|
||||
out8 (IIC_CLKDIV1, divisor);
|
||||
|
||||
/* no interrupts */
|
||||
out8 (IIC_INTRMSK1, 0);
|
||||
|
||||
/* clear transfer count */
|
||||
out8 (IIC_XFRCNT1, 0);
|
||||
|
||||
/* clear extended control & stat */
|
||||
/* write 1 in SRC SRS SWC SWS to clear these fields */
|
||||
out8 (IIC_XTCNTLSS1, 0xF0);
|
||||
|
||||
/* Mode Control Register
|
||||
Flush Slave/Master data buffer */
|
||||
out8 (IIC_MDCNTL1, IIC_MDCNTL_FSDB | IIC_MDCNTL_FMDB);
|
||||
__asm__ volatile ("eieio");
|
||||
|
||||
|
||||
val = in8(IIC_MDCNTL1);
|
||||
__asm__ volatile ("eieio");
|
||||
|
||||
/* Ignore General Call, slave transfers are ignored,
|
||||
disable interrupts, exit unknown bus state, enable hold
|
||||
SCL
|
||||
100kHz normaly or FastMode for 400kHz and above
|
||||
*/
|
||||
|
||||
val |= IIC_MDCNTL_EUBS|IIC_MDCNTL_HSCL;
|
||||
if( speed >= 400000 ){
|
||||
val |= IIC_MDCNTL_FSM;
|
||||
}
|
||||
out8 (IIC_MDCNTL1, val);
|
||||
|
||||
/* clear control reg */
|
||||
out8 (IIC_CNTL1, 0x00);
|
||||
__asm__ volatile ("eieio");
|
||||
|
||||
}
|
||||
|
||||
/*
|
||||
This code tries to use the features of the 405GP i2c
|
||||
controller. It will transfer up to 4 bytes in one pass
|
||||
on the loop. It only does out8(lbz) to the buffer when it
|
||||
is possible to do out16(lhz) transfers.
|
||||
|
||||
cmd_type is 0 for write 1 for read.
|
||||
|
||||
addr_len can take any value from 0-255, it is only limited
|
||||
by the char, we could make it larger if needed. If it is
|
||||
0 we skip the address write cycle.
|
||||
|
||||
Typical case is a Write of an addr followd by a Read. The
|
||||
IBM FAQ does not cover this. On the last byte of the write
|
||||
we don't set the creg CHT bit, and on the first bytes of the
|
||||
read we set the RPST bit.
|
||||
|
||||
It does not support address only transfers, there must be
|
||||
a data part. If you want to write the address yourself, put
|
||||
it in the data pointer.
|
||||
|
||||
It does not support transfer to/from address 0.
|
||||
|
||||
It does not check XFRCNT.
|
||||
*/
|
||||
static
|
||||
int i2c_transfer1(unsigned char cmd_type,
|
||||
unsigned char chip,
|
||||
unsigned char addr[],
|
||||
unsigned char addr_len,
|
||||
unsigned char data[],
|
||||
unsigned short data_len )
|
||||
{
|
||||
unsigned char* ptr;
|
||||
int reading;
|
||||
int tran,cnt;
|
||||
int result;
|
||||
int status;
|
||||
int i;
|
||||
uchar creg;
|
||||
|
||||
if( data == 0 || data_len == 0 ){
|
||||
/*Don't support data transfer of no length or to address 0*/
|
||||
printf( "i2c_transfer: bad call\n" );
|
||||
return IIC_NOK;
|
||||
}
|
||||
if( addr && addr_len ){
|
||||
ptr = addr;
|
||||
cnt = addr_len;
|
||||
reading = 0;
|
||||
}else{
|
||||
ptr = data;
|
||||
cnt = data_len;
|
||||
reading = cmd_type;
|
||||
}
|
||||
|
||||
/*Clear Stop Complete Bit*/
|
||||
out8(IIC_STS1,IIC_STS_SCMP);
|
||||
/* Check init */
|
||||
i=10;
|
||||
do {
|
||||
/* Get status */
|
||||
status = in8(IIC_STS1);
|
||||
__asm__ volatile("eieio");
|
||||
i--;
|
||||
} while ((status & IIC_STS_PT) && (i>0));
|
||||
|
||||
if (status & IIC_STS_PT) {
|
||||
result = IIC_NOK_TOUT;
|
||||
return(result);
|
||||
}
|
||||
/*flush the Master/Slave Databuffers*/
|
||||
out8(IIC_MDCNTL1, ((in8(IIC_MDCNTL1))|IIC_MDCNTL_FMDB|IIC_MDCNTL_FSDB));
|
||||
/*need to wait 4 OPB clocks? code below should take that long*/
|
||||
|
||||
/* 7-bit adressing */
|
||||
out8(IIC_HMADR1,0);
|
||||
out8(IIC_LMADR1, chip);
|
||||
__asm__ volatile("eieio");
|
||||
|
||||
tran = 0;
|
||||
result = IIC_OK;
|
||||
creg = 0;
|
||||
|
||||
while ( tran != cnt && (result == IIC_OK)) {
|
||||
int bc,j;
|
||||
|
||||
/* Control register =
|
||||
Normal transfer, 7-bits adressing, Transfer up to bc bytes, Normal start,
|
||||
Transfer is a sequence of transfers
|
||||
*/
|
||||
creg |= IIC_CNTL_PT;
|
||||
|
||||
bc = (cnt - tran) > 4 ? 4 :
|
||||
cnt - tran;
|
||||
creg |= (bc-1)<<4;
|
||||
/* if the real cmd type is write continue trans*/
|
||||
if ( (!cmd_type && (ptr == addr)) || ((tran+bc) != cnt) )
|
||||
creg |= IIC_CNTL_CHT;
|
||||
|
||||
if (reading)
|
||||
creg |= IIC_CNTL_READ;
|
||||
else {
|
||||
for(j=0; j<bc; j++) {
|
||||
/* Set buffer */
|
||||
out8(IIC_MDBUF1,ptr[tran+j]);
|
||||
__asm__ volatile("eieio");
|
||||
}
|
||||
}
|
||||
out8(IIC_CNTL1, creg );
|
||||
__asm__ volatile("eieio");
|
||||
|
||||
/* Transfer is in progress
|
||||
we have to wait for upto 5 bytes of data
|
||||
1 byte chip address+r/w bit then bc bytes
|
||||
of data.
|
||||
udelay(10) is 1 bit time at 100khz
|
||||
Doubled for slop. 20 is too small.
|
||||
*/
|
||||
i=2*5*8;
|
||||
do {
|
||||
/* Get status */
|
||||
status = in8(IIC_STS1);
|
||||
__asm__ volatile("eieio");
|
||||
udelay (10);
|
||||
i--;
|
||||
} while ((status & IIC_STS_PT) && !(status & IIC_STS_ERR)
|
||||
&& (i>0));
|
||||
|
||||
if (status & IIC_STS_ERR) {
|
||||
result = IIC_NOK;
|
||||
status = in8 (IIC_EXTSTS1);
|
||||
/* Lost arbitration? */
|
||||
if (status & IIC_EXTSTS_LA)
|
||||
result = IIC_NOK_LA;
|
||||
/* Incomplete transfer? */
|
||||
if (status & IIC_EXTSTS_ICT)
|
||||
result = IIC_NOK_ICT;
|
||||
/* Transfer aborted? */
|
||||
if (status & IIC_EXTSTS_XFRA)
|
||||
result = IIC_NOK_XFRA;
|
||||
} else if ( status & IIC_STS_PT) {
|
||||
result = IIC_NOK_TOUT;
|
||||
}
|
||||
/* Command is reading => get buffer */
|
||||
if ((reading) && (result == IIC_OK)) {
|
||||
/* Are there data in buffer */
|
||||
if (status & IIC_STS_MDBS) {
|
||||
/*
|
||||
even if we have data we have to wait 4OPB clocks
|
||||
for it to hit the front of the FIFO, after that
|
||||
we can just read. We should check XFCNT here and
|
||||
if the FIFO is full there is no need to wait.
|
||||
*/
|
||||
udelay (1);
|
||||
for(j=0;j<bc;j++) {
|
||||
ptr[tran+j] = in8(IIC_MDBUF1);
|
||||
__asm__ volatile("eieio");
|
||||
}
|
||||
} else
|
||||
result = IIC_NOK_DATA;
|
||||
}
|
||||
creg = 0;
|
||||
tran+=bc;
|
||||
if( ptr == addr && tran == cnt ) {
|
||||
ptr = data;
|
||||
cnt = data_len;
|
||||
tran = 0;
|
||||
reading = cmd_type;
|
||||
if( reading )
|
||||
creg = IIC_CNTL_RPST;
|
||||
}
|
||||
}
|
||||
return (result);
|
||||
}
|
||||
|
||||
int i2c_probe1 (uchar chip)
|
||||
{
|
||||
uchar buf[1];
|
||||
|
||||
buf[0] = 0;
|
||||
|
||||
/*
|
||||
* What is needed is to send the chip address and verify that the
|
||||
* address was <ACK>ed (i.e. there was a chip at that address which
|
||||
* drove the data line low).
|
||||
*/
|
||||
return(i2c_transfer1 (1, chip << 1, 0,0, buf, 1) != 0);
|
||||
}
|
||||
|
||||
|
||||
int i2c_read1 (uchar chip, uint addr, int alen, uchar * buffer, int len)
|
||||
{
|
||||
uchar xaddr[4];
|
||||
int ret;
|
||||
|
||||
if ( alen > 4 ) {
|
||||
printf ("I2C read: addr len %d not supported\n", alen);
|
||||
return 1;
|
||||
}
|
||||
|
||||
if ( alen > 0 ) {
|
||||
xaddr[0] = (addr >> 24) & 0xFF;
|
||||
xaddr[1] = (addr >> 16) & 0xFF;
|
||||
xaddr[2] = (addr >> 8) & 0xFF;
|
||||
xaddr[3] = addr & 0xFF;
|
||||
}
|
||||
|
||||
|
||||
#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
|
||||
/*
|
||||
* EEPROM chips that implement "address overflow" are ones
|
||||
* like Catalyst 24WC04/08/16 which has 9/10/11 bits of
|
||||
* address and the extra bits end up in the "chip address"
|
||||
* bit slots. This makes a 24WC08 (1Kbyte) chip look like
|
||||
* four 256 byte chips.
|
||||
*
|
||||
* Note that we consider the length of the address field to
|
||||
* still be one byte because the extra address bits are
|
||||
* hidden in the chip address.
|
||||
*/
|
||||
if( alen > 0 )
|
||||
chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
|
||||
#endif
|
||||
if( (ret = i2c_transfer1( 1, chip<<1, &xaddr[4-alen], alen, buffer, len )) != 0) {
|
||||
printf( "I2c read: failed %d\n", ret);
|
||||
return 1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
int i2c_write1 (uchar chip, uint addr, int alen, uchar * buffer, int len)
|
||||
{
|
||||
uchar xaddr[4];
|
||||
|
||||
if ( alen > 4 ) {
|
||||
printf ("I2C write: addr len %d not supported\n", alen);
|
||||
return 1;
|
||||
|
||||
}
|
||||
if ( alen > 0 ) {
|
||||
xaddr[0] = (addr >> 24) & 0xFF;
|
||||
xaddr[1] = (addr >> 16) & 0xFF;
|
||||
xaddr[2] = (addr >> 8) & 0xFF;
|
||||
xaddr[3] = addr & 0xFF;
|
||||
}
|
||||
|
||||
#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
|
||||
/*
|
||||
* EEPROM chips that implement "address overflow" are ones
|
||||
* like Catalyst 24WC04/08/16 which has 9/10/11 bits of
|
||||
* address and the extra bits end up in the "chip address"
|
||||
* bit slots. This makes a 24WC08 (1Kbyte) chip look like
|
||||
* four 256 byte chips.
|
||||
*
|
||||
* Note that we consider the length of the address field to
|
||||
* still be one byte because the extra address bits are
|
||||
* hidden in the chip address.
|
||||
*/
|
||||
if( alen > 0 )
|
||||
chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
|
||||
#endif
|
||||
|
||||
return (i2c_transfer1( 0, chip<<1, &xaddr[4-alen], alen, buffer, len ) != 0);
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Read a register
|
||||
*/
|
||||
uchar i2c_reg_read1(uchar i2c_addr, uchar reg)
|
||||
{
|
||||
char buf;
|
||||
|
||||
i2c_read1(i2c_addr, reg, 1, &buf, 1);
|
||||
|
||||
return(buf);
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Write a register
|
||||
*/
|
||||
void i2c_reg_write1(uchar i2c_addr, uchar reg, uchar val)
|
||||
{
|
||||
i2c_write1(i2c_addr, reg, 1, &val, 1);
|
||||
}
|
||||
|
||||
|
||||
int do_i2c1_probe(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
int j;
|
||||
#if defined(CFG_I2C_NOPROBES)
|
||||
int k, skip;
|
||||
#endif
|
||||
|
||||
puts ("Valid chip addresses:");
|
||||
for(j = 0; j < 128; j++) {
|
||||
#if defined(CFG_I2C_NOPROBES)
|
||||
skip = 0;
|
||||
for (k = 0; k < sizeof(i2c_no_probes); k++){
|
||||
if (j == i2c_no_probes[k]){
|
||||
skip = 1;
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (skip)
|
||||
continue;
|
||||
#endif
|
||||
if(i2c_probe1(j) == 0) {
|
||||
printf(" %02X", j);
|
||||
}
|
||||
}
|
||||
putc ('\n');
|
||||
|
||||
#if defined(CFG_I2C_NOPROBES)
|
||||
puts ("Excluded chip addresses:");
|
||||
for( k = 0; k < sizeof(i2c_no_probes); k++ )
|
||||
printf(" %02X", i2c_no_probes[k] );
|
||||
putc ('\n');
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
U_BOOT_CMD(
|
||||
iprobe1, 1, 1, do_i2c1_probe,
|
||||
"iprobe1 - probe to discover valid I2C chip addresses\n",
|
||||
"\n -discover valid I2C chip addresses\n"
|
||||
);
|
||||
|
||||
#endif
|
||||
|
||||
|
|
@ -0,0 +1,67 @@
|
|||
/*
|
||||
* Copyright (C) 2005 Sandburst Corporation
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* Ported from i2c driver for ppc4xx by AS HARNOIS by
|
||||
* Travis B. Sawyer
|
||||
* Sandburst Corporation
|
||||
*/
|
||||
#include <common.h>
|
||||
#include <ppc4xx.h>
|
||||
#if defined(CONFIG_440)
|
||||
# include <440_i2c.h>
|
||||
#else
|
||||
# include <405gp_i2c.h>
|
||||
#endif
|
||||
#include <i2c.h>
|
||||
|
||||
|
||||
#ifdef CONFIG_HARD_I2C
|
||||
|
||||
|
||||
|
||||
#define I2C_BUS1_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x00000500)
|
||||
#define I2C_REGISTERS_BUS1_BASE_ADDRESS I2C_BUS1_BASE_ADDR
|
||||
#define IIC_MDBUF1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICMDBUF)
|
||||
#define IIC_SDBUF1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICSDBUF)
|
||||
#define IIC_LMADR1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICLMADR)
|
||||
#define IIC_HMADR1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICHMADR)
|
||||
#define IIC_CNTL1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICCNTL)
|
||||
#define IIC_MDCNTL1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICMDCNTL)
|
||||
#define IIC_STS1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICSTS)
|
||||
#define IIC_EXTSTS1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICEXTSTS)
|
||||
#define IIC_LSADR1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICLSADR)
|
||||
#define IIC_HSADR1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICHSADR)
|
||||
#define IIC_CLKDIV1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICCLKDIV)
|
||||
#define IIC_INTRMSK1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICINTRMSK)
|
||||
#define IIC_XFRCNT1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICXFRCNT)
|
||||
#define IIC_XTCNTLSS1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICXTCNTLSS)
|
||||
#define IIC_DIRECTCNTL1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICDIRECTCNTL)
|
||||
|
||||
void i2c1_init (int speed, int slaveadd);
|
||||
int i2c_probe1 (uchar chip);
|
||||
int i2c_read1 (uchar chip, uint addr, int alen, uchar * buffer, int len);
|
||||
int i2c_write1 (uchar chip, uint addr, int alen, uchar * buffer, int len);
|
||||
uchar i2c_reg_read1(uchar i2c_addr, uchar reg);
|
||||
void i2c_reg_write1(uchar i2c_addr, uchar reg, uchar val);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,451 @@
|
|||
/*
|
||||
* Copyright (C) 2005 Sandburst Corporation
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
#include <config.h>
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/io.h>
|
||||
#include <spd_sdram.h>
|
||||
#include <i2c.h>
|
||||
#include "ppc440gx_i2c.h"
|
||||
#include "sb_common.h"
|
||||
|
||||
long int fixed_sdram (void);
|
||||
|
||||
/*************************************************************************
|
||||
* metrobox_get_master
|
||||
*
|
||||
* PRI_N - active low signal. If the GPIO pin is low we are the master
|
||||
*
|
||||
************************************************************************/
|
||||
int sbcommon_get_master(void)
|
||||
{
|
||||
ppc440_gpio_regs_t *gpio_regs;
|
||||
|
||||
gpio_regs = (ppc440_gpio_regs_t *)CFG_GPIO_BASE;
|
||||
|
||||
if (gpio_regs->in & SBCOMMON_GPIO_PRI_N) {
|
||||
return 0;
|
||||
}
|
||||
else {
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
||||
/*************************************************************************
|
||||
* metrobox_secondary_present
|
||||
*
|
||||
* Figure out if secondary/slave board is present
|
||||
*
|
||||
************************************************************************/
|
||||
int sbcommon_secondary_present(void)
|
||||
{
|
||||
ppc440_gpio_regs_t *gpio_regs;
|
||||
|
||||
gpio_regs = (ppc440_gpio_regs_t *)CFG_GPIO_BASE;
|
||||
|
||||
if (gpio_regs->in & SBCOMMON_GPIO_SEC_PRES)
|
||||
return 0;
|
||||
else
|
||||
return 1;
|
||||
}
|
||||
|
||||
/*************************************************************************
|
||||
* sbcommon_get_serial_number
|
||||
*
|
||||
* Retrieve the board serial number via the mac address in eeprom
|
||||
*
|
||||
************************************************************************/
|
||||
unsigned short sbcommon_get_serial_number(void)
|
||||
{
|
||||
unsigned char buff[0x100];
|
||||
unsigned short sernum;
|
||||
|
||||
/* Get the board serial number from eeprom */
|
||||
/* Initialize I2C */
|
||||
i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
|
||||
|
||||
/* Read 256 bytes in EEPROM */
|
||||
i2c_read (0x50, 0, 1, buff, 0x100);
|
||||
|
||||
memcpy(&sernum, &buff[0xF4], 2);
|
||||
sernum /= 32;
|
||||
|
||||
return (sernum);
|
||||
}
|
||||
|
||||
/*************************************************************************
|
||||
* sbcommon_fans
|
||||
*
|
||||
* Spin up fans 2 & 3 to get some air moving. OS will take care
|
||||
* of the rest. This is mostly a precaution...
|
||||
*
|
||||
* Assumes i2c bus 1 is ready.
|
||||
*
|
||||
************************************************************************/
|
||||
void sbcommon_fans(void)
|
||||
{
|
||||
/*
|
||||
* Attempt to turn on 2 of the fans...
|
||||
* Need to go through the bridge
|
||||
*/
|
||||
puts ("FANS: ");
|
||||
|
||||
/* select fan4 through the bridge */
|
||||
i2c_reg_write1(0x73, /* addr */
|
||||
0x00, /* reg */
|
||||
0x08); /* val = bus 4 */
|
||||
|
||||
/* Turn on FAN 4 */
|
||||
i2c_reg_write1(0x2e,
|
||||
1,
|
||||
0x80);
|
||||
|
||||
i2c_reg_write1(0x2e,
|
||||
0,
|
||||
0x19);
|
||||
|
||||
/* Deselect bus 4 on the bridge */
|
||||
i2c_reg_write1(0x73,
|
||||
0x00,
|
||||
0x00);
|
||||
|
||||
/* select fan3 through the bridge */
|
||||
i2c_reg_write1(0x73, /* addr */
|
||||
0x00, /* reg */
|
||||
0x04); /* val = bus 3 */
|
||||
|
||||
/* Turn on FAN 3 */
|
||||
i2c_reg_write1(0x2e,
|
||||
1,
|
||||
0x80);
|
||||
|
||||
i2c_reg_write1(0x2e,
|
||||
0,
|
||||
0x19);
|
||||
|
||||
/* Deselect bus 3 on the bridge */
|
||||
i2c_reg_write1(0x73,
|
||||
0x00,
|
||||
0x00);
|
||||
|
||||
/* select fan2 through the bridge */
|
||||
i2c_reg_write1(0x73, /* addr */
|
||||
0x00, /* reg */
|
||||
0x02); /* val = bus 4 */
|
||||
|
||||
/* Turn on FAN 2 */
|
||||
i2c_reg_write1(0x2e,
|
||||
1,
|
||||
0x80);
|
||||
|
||||
i2c_reg_write1(0x2e,
|
||||
0,
|
||||
0x19);
|
||||
|
||||
/* Deselect bus 2 on the bridge */
|
||||
i2c_reg_write1(0x73,
|
||||
0x00,
|
||||
0x00);
|
||||
|
||||
/* select fan1 through the bridge */
|
||||
i2c_reg_write1(0x73, /* addr */
|
||||
0x00, /* reg */
|
||||
0x01); /* val = bus 0 */
|
||||
|
||||
/* Turn on FAN 1 */
|
||||
i2c_reg_write1(0x2e,
|
||||
1,
|
||||
0x80);
|
||||
|
||||
i2c_reg_write1(0x2e,
|
||||
0,
|
||||
0x19);
|
||||
|
||||
/* Deselect bus 1 on the bridge */
|
||||
i2c_reg_write1(0x73,
|
||||
0x00,
|
||||
0x00);
|
||||
|
||||
puts ("on\n");
|
||||
|
||||
return;
|
||||
|
||||
}
|
||||
|
||||
/*************************************************************************
|
||||
* initdram
|
||||
*
|
||||
* Initialize sdram
|
||||
*
|
||||
************************************************************************/
|
||||
long int initdram (int board_type)
|
||||
{
|
||||
long dram_size = 0;
|
||||
|
||||
#if defined(CONFIG_SPD_EEPROM)
|
||||
dram_size = spd_sdram (0);
|
||||
#else
|
||||
dram_size = fixed_sdram ();
|
||||
#endif
|
||||
return dram_size;
|
||||
}
|
||||
|
||||
|
||||
/*************************************************************************
|
||||
* testdram
|
||||
*
|
||||
*
|
||||
************************************************************************/
|
||||
#if defined(CFG_DRAM_TEST)
|
||||
int testdram (void)
|
||||
{
|
||||
uint *pstart = (uint *) CFG_MEMTEST_START;
|
||||
uint *pend = (uint *) CFG_MEMTEST_END;
|
||||
uint *p;
|
||||
|
||||
printf("Testing SDRAM: ");
|
||||
for (p = pstart; p < pend; p++)
|
||||
*p = 0xaaaaaaaa;
|
||||
|
||||
for (p = pstart; p < pend; p++) {
|
||||
if (*p != 0xaaaaaaaa) {
|
||||
printf ("SDRAM test fails at: %08x\n", (uint) p);
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
||||
for (p = pstart; p < pend; p++)
|
||||
*p = 0x55555555;
|
||||
|
||||
for (p = pstart; p < pend; p++) {
|
||||
if (*p != 0x55555555) {
|
||||
printf ("SDRAM test fails at: %08x\n", (uint) p);
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
||||
printf("OK\n");
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if !defined(CONFIG_SPD_EEPROM)
|
||||
/*************************************************************************
|
||||
* fixed sdram init -- doesn't use serial presence detect.
|
||||
*
|
||||
* Assumes: 128 MB, non-ECC, non-registered
|
||||
* PLB @ 133 MHz
|
||||
*
|
||||
************************************************************************/
|
||||
long int fixed_sdram (void)
|
||||
{
|
||||
uint reg;
|
||||
|
||||
/*--------------------------------------------------------------------
|
||||
* Setup some default
|
||||
*------------------------------------------------------------------*/
|
||||
mtsdram (mem_uabba, 0x00000000); /* ubba=0 (default) */
|
||||
mtsdram (mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
|
||||
mtsdram (mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
|
||||
mtsdram (mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */
|
||||
mtsdram (mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
|
||||
|
||||
/*--------------------------------------------------------------------
|
||||
* Setup for board-specific specific mem
|
||||
*------------------------------------------------------------------*/
|
||||
/*
|
||||
* Following for CAS Latency = 2.5 @ 133 MHz PLB
|
||||
*/
|
||||
mtsdram (mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
|
||||
mtsdram (mem_tr0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */
|
||||
/* RA=10 RD=3 */
|
||||
mtsdram (mem_tr1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */
|
||||
mtsdram (mem_rtr, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */
|
||||
mtsdram (mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
|
||||
udelay (400); /* Delay 200 usecs (min) */
|
||||
|
||||
/*--------------------------------------------------------------------
|
||||
* Enable the controller, then wait for DCEN to complete
|
||||
*------------------------------------------------------------------*/
|
||||
mtsdram (mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */
|
||||
for (;;) {
|
||||
mfsdram (mem_mcsts, reg);
|
||||
if (reg & 0x80000000)
|
||||
break;
|
||||
}
|
||||
|
||||
return (128 * 1024 * 1024); /* 128 MB */
|
||||
}
|
||||
#endif /* !defined(CONFIG_SPD_EEPROM) */
|
||||
|
||||
|
||||
/*************************************************************************
|
||||
* pci_pre_init
|
||||
*
|
||||
* This routine is called just prior to registering the hose and gives
|
||||
* the board the opportunity to check things. Returning a value of zero
|
||||
* indicates that things are bad & PCI initialization should be aborted.
|
||||
*
|
||||
* Different boards may wish to customize the pci controller structure
|
||||
* (add regions, override default access routines, etc) or perform
|
||||
* certain pre-initialization actions.
|
||||
*
|
||||
************************************************************************/
|
||||
#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
|
||||
int pci_pre_init(struct pci_controller * hose )
|
||||
{
|
||||
unsigned long strap;
|
||||
|
||||
/*--------------------------------------------------------------------------+
|
||||
* The metrobox is always configured as the host & requires the
|
||||
* PCI arbiter to be enabled.
|
||||
*--------------------------------------------------------------------------*/
|
||||
mfsdr(sdr_sdstp1, strap);
|
||||
if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){
|
||||
printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
|
||||
return 0;
|
||||
}
|
||||
|
||||
return 1;
|
||||
}
|
||||
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
|
||||
|
||||
/*************************************************************************
|
||||
* pci_target_init
|
||||
*
|
||||
* The bootstrap configuration provides default settings for the pci
|
||||
* inbound map (PIM). But the bootstrap config choices are limited and
|
||||
* may not be sufficient for a given board.
|
||||
*
|
||||
************************************************************************/
|
||||
#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
|
||||
void pci_target_init(struct pci_controller * hose )
|
||||
{
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
/*--------------------------------------------------------------------------+
|
||||
* Disable everything
|
||||
*--------------------------------------------------------------------------*/
|
||||
out32r( PCIX0_PIM0SA, 0 ); /* disable */
|
||||
out32r( PCIX0_PIM1SA, 0 ); /* disable */
|
||||
out32r( PCIX0_PIM2SA, 0 ); /* disable */
|
||||
out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
|
||||
|
||||
/*--------------------------------------------------------------------------+
|
||||
* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
|
||||
* options to not support sizes such as 128/256 MB.
|
||||
*--------------------------------------------------------------------------*/
|
||||
out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
|
||||
out32r( PCIX0_PIM0LAH, 0 );
|
||||
out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
|
||||
|
||||
out32r( PCIX0_BAR0, 0 );
|
||||
|
||||
/*--------------------------------------------------------------------------+
|
||||
* Program the board's subsystem id/vendor id
|
||||
*--------------------------------------------------------------------------*/
|
||||
out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
|
||||
out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
|
||||
|
||||
out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
|
||||
}
|
||||
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
|
||||
|
||||
|
||||
/*************************************************************************
|
||||
* is_pci_host
|
||||
*
|
||||
*
|
||||
************************************************************************/
|
||||
#if defined(CONFIG_PCI)
|
||||
int is_pci_host(struct pci_controller *hose)
|
||||
{
|
||||
/* The metrobox is always configured as host. */
|
||||
return(1);
|
||||
}
|
||||
#endif /* defined(CONFIG_PCI) */
|
||||
|
||||
/*************************************************************************
|
||||
* board_get_enetaddr
|
||||
*
|
||||
* Get the ethernet MAC address for the management ethernet from the
|
||||
* strap EEPROM. Note that is the BASE address for the range of
|
||||
* external ethernet MACs on the board. The base + 31 is the actual
|
||||
* mgmt mac address.
|
||||
*
|
||||
************************************************************************/
|
||||
static int macaddr_idx = 0;
|
||||
|
||||
void board_get_enetaddr (uchar * enet)
|
||||
{
|
||||
int i;
|
||||
unsigned short tmp;
|
||||
unsigned char buff[0x100], *cp;
|
||||
|
||||
if (0 == macaddr_idx) {
|
||||
|
||||
/* Initialize I2C */
|
||||
i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
|
||||
|
||||
/* Read 256 bytes in EEPROM */
|
||||
i2c_read (0x50, 0, 1, buff, 0x100);
|
||||
|
||||
cp = &buff[0xF0];
|
||||
|
||||
for (i = 0; i < 6; i++,cp++)
|
||||
enet[i] = *cp;
|
||||
|
||||
memcpy(&tmp, &enet[4], 2);
|
||||
tmp += 31;
|
||||
memcpy(&enet[4], &tmp, 2);
|
||||
|
||||
macaddr_idx++;
|
||||
} else {
|
||||
enet[0] = 0x02;
|
||||
enet[1] = 0x00;
|
||||
enet[2] = 0x00;
|
||||
enet[3] = 0x00;
|
||||
enet[4] = 0x00;
|
||||
if (1 == sbcommon_get_master() ) {
|
||||
/* Master/Primary card */
|
||||
enet[5] = 0x01;
|
||||
} else {
|
||||
/* Slave/Secondary card */
|
||||
enet [5] = 0x02;
|
||||
}
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_POST
|
||||
/*
|
||||
* Returns 1 if keys pressed to start the power-on long-running tests
|
||||
* Called from board_init_f().
|
||||
*/
|
||||
int post_hotkeys_pressed(void)
|
||||
{
|
||||
|
||||
return (ctrlc());
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,83 @@
|
|||
#ifndef __SBCOMMON_H__
|
||||
#define __SBCOMMON_H__
|
||||
/*
|
||||
* Copyright (C) 2005 Sandburst Corporation
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
#include <config.h>
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/io.h>
|
||||
#include <spd_sdram.h>
|
||||
#include <i2c.h>
|
||||
#include "ppc440gx_i2c.h"
|
||||
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* GPIO Settings
|
||||
*/
|
||||
/* Chassis settings */
|
||||
#define SBCOMMON_GPIO_PRI_N 0x00001000 /* 0 = Chassis Master, 1 = Slave */
|
||||
#define SBCOMMON_GPIO_SEC_PRES 0x00000800 /* 1 = Other board present */
|
||||
|
||||
/* Debug LEDs */
|
||||
#define SBCOMMON_GPIO_DBGLED_0 0x00000400
|
||||
#define SBCOMMON_GPIO_DBGLED_1 0x00000200
|
||||
#define SBCOMMON_GPIO_DBGLED_2 0x00100000
|
||||
#define SBCOMMON_GPIO_DBGLED_3 0x00000100
|
||||
|
||||
#define SBCOMMON_GPIO_DBGLEDS (SBCOMMON_GPIO_DBGLED_0 | \
|
||||
SBCOMMON_GPIO_DBGLED_1 | \
|
||||
SBCOMMON_GPIO_DBGLED_2 | \
|
||||
SBCOMMON_GPIO_DBGLED_3)
|
||||
|
||||
#define SBCOMMON_GPIO_SYS_FAULT 0x00000080
|
||||
#define SBCOMMON_GPIO_SYS_OTEMP 0x00000040
|
||||
#define SBCOMMON_GPIO_SYS_STATUS 0x00000020
|
||||
|
||||
#define SBCOMMON_GPIO_SYS_LEDS (SBCOMMON_GPIO_SYS_STATUS)
|
||||
|
||||
#define SBCOMMON_GPIO_LEDS (SBCOMMON_GPIO_DBGLED_0 | \
|
||||
SBCOMMON_GPIO_DBGLED_1 | \
|
||||
SBCOMMON_GPIO_DBGLED_2 | \
|
||||
SBCOMMON_GPIO_DBGLED_3 | \
|
||||
SBCOMMON_GPIO_SYS_STATUS)
|
||||
|
||||
typedef struct ppc440_gpio_regs {
|
||||
volatile unsigned long out;
|
||||
volatile unsigned long tri_state;
|
||||
volatile unsigned long dummy[4];
|
||||
volatile unsigned long open_drain;
|
||||
volatile unsigned long in;
|
||||
} __attribute__((packed)) ppc440_gpio_regs_t;
|
||||
|
||||
|
||||
|
||||
|
||||
int sbcommon_get_master(void);
|
||||
int sbcommon_secondary_present(void);
|
||||
unsigned short sbcommon_get_serial_number(void);
|
||||
void sbcommon_fans(void);
|
||||
|
||||
|
||||
#endif /* __SBCOMMON_H__ */
|
||||
|
|
@ -0,0 +1,59 @@
|
|||
#
|
||||
# (C) Copyright 2005
|
||||
# Sandburst Corporation
|
||||
# Travis B. Sawyer
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
# TBS: add for debugging purposes
|
||||
BUILDUSER := $(shell whoami)
|
||||
FORCEBUILD := $(shell rm -f $(LIB) $(BOARD).o)
|
||||
|
||||
CFLAGS += -DBUILDUSER='"$(BUILDUSER)"'
|
||||
# TBS: end debugging
|
||||
|
||||
|
||||
LIB = lib$(BOARD).a
|
||||
|
||||
OBJS = $(BOARD).o ../common/flash.o ../common/ppc440gx_i2c.o \
|
||||
../common/sb_common.o
|
||||
|
||||
SOBJS = init.o
|
||||
|
||||
|
||||
$(LIB): $(OBJS) $(SOBJS)
|
||||
$(AR) crv $@ $(OBJS)
|
||||
|
||||
clean:
|
||||
rm -f $(SOBJS) $(OBJS)
|
||||
|
||||
distclean: clean
|
||||
rm -f $(LIB) core *.bak .depend *~
|
||||
|
||||
#########################################################################
|
||||
|
||||
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
|
||||
$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
|
||||
|
||||
sinclude .depend
|
||||
|
||||
#########################################################################
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
#
|
||||
# (C) Copyright 2005
|
||||
# Sandburst Corporation
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
#
|
||||
# Sandburst Corporation Metrobox Reference Design
|
||||
# Travis B. Sawyer
|
||||
#
|
||||
|
||||
ifeq ($(ramsym),1)
|
||||
TEXT_BASE = 0x07FD0000
|
||||
else
|
||||
TEXT_BASE = 0xFFF80000
|
||||
endif
|
||||
|
||||
PLATFORM_CPPFLAGS += -DCONFIG_440=1
|
||||
|
||||
ifeq ($(debug),1)
|
||||
PLATFORM_CPPFLAGS += -DDEBUG
|
||||
endif
|
||||
|
||||
ifeq ($(dbcr),1)
|
||||
PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
|
||||
endif
|
||||
|
|
@ -0,0 +1,324 @@
|
|||
/* ****************************************************************
|
||||
* Common defs for reg spec for chip ka_of
|
||||
* Auto-generated by trex2: DO NOT HAND-EDIT!!
|
||||
* ****************************************************************
|
||||
*/
|
||||
|
||||
#ifndef HAL_KA_OF_AUTO_H
|
||||
#define HAL_KA_OF_AUTO_H
|
||||
|
||||
|
||||
/* ----------------------------------------------------------------
|
||||
* For block: 'ofem'
|
||||
*/
|
||||
|
||||
/* ---- Block instance addressing (for block-select) */
|
||||
#define OFEM_BLOCK_ADDR_BIT_L 6
|
||||
#define OFEM_BLOCK_ADDR_BIT_H 9
|
||||
#define OFEM_BLOCK_ADDR_WIDTH 4
|
||||
|
||||
#define OFEM_ADDR 0x0
|
||||
|
||||
/* ---- Reg addressing (within block) */
|
||||
#define OFEM_REG_ADDR_BIT_L 2
|
||||
#define OFEM_REG_ADDR_BIT_H 5
|
||||
#define OFEM_REG_ADDR_WIDTH 4
|
||||
|
||||
|
||||
/* ================================================================
|
||||
* ---- Register KA_OF_OFEM_REVISION */
|
||||
#define SAND_HAL_KA_OF_OFEM_REVISION_OFFSET 0x000
|
||||
#ifndef SAND_HAL_KA_OF_OFEM_REVISION_NO_TEST_MASK
|
||||
#define SAND_HAL_KA_OF_OFEM_REVISION_NO_TEST_MASK 0x000
|
||||
#endif
|
||||
#define SAND_HAL_KA_OF_OFEM_REVISION_MASK 0xffffffff
|
||||
#define SAND_HAL_KA_OF_OFEM_REVISION_MSB 31
|
||||
#define SAND_HAL_KA_OF_OFEM_REVISION_LSB 0
|
||||
|
||||
/* ================================================================
|
||||
* ---- Register KA_OF_OFEM_RESET */
|
||||
#define SAND_HAL_KA_OF_OFEM_RESET_OFFSET 0x004
|
||||
#ifndef SAND_HAL_KA_OF_OFEM_RESET_NO_TEST_MASK
|
||||
#define SAND_HAL_KA_OF_OFEM_RESET_NO_TEST_MASK 0x000
|
||||
#endif
|
||||
#define SAND_HAL_KA_OF_OFEM_RESET_MASK 0xffffffff
|
||||
#define SAND_HAL_KA_OF_OFEM_RESET_MSB 31
|
||||
#define SAND_HAL_KA_OF_OFEM_RESET_LSB 0
|
||||
|
||||
/* ================================================================
|
||||
* ---- Register KA_OF_OFEM_CNTL */
|
||||
#define SAND_HAL_KA_OF_OFEM_CNTL_OFFSET 0x018
|
||||
#ifndef SAND_HAL_KA_OF_OFEM_CNTL_NO_TEST_MASK
|
||||
#define SAND_HAL_KA_OF_OFEM_CNTL_NO_TEST_MASK 0x000
|
||||
#endif
|
||||
#define SAND_HAL_KA_OF_OFEM_CNTL_MASK 0xffffffff
|
||||
#define SAND_HAL_KA_OF_OFEM_CNTL_MSB 31
|
||||
#define SAND_HAL_KA_OF_OFEM_CNTL_LSB 0
|
||||
|
||||
/* ================================================================
|
||||
* ---- Register KA_OF_OFEM_MAC_FLOW_CTL */
|
||||
#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_OFFSET 0x01c
|
||||
#ifndef SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_NO_TEST_MASK
|
||||
#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_NO_TEST_MASK 0x000
|
||||
#endif
|
||||
#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MASK 0xffffffff
|
||||
#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MSB 31
|
||||
#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LSB 0
|
||||
|
||||
/* ================================================================
|
||||
* ---- Register KA_OF_OFEM_INTERRUPT */
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_OFFSET 0x008
|
||||
#ifndef SAND_HAL_KA_OF_OFEM_INTERRUPT_NO_TEST_MASK
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_NO_TEST_MASK 0x000
|
||||
#endif
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK 0xffffffff
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MSB 31
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_LSB 0
|
||||
|
||||
/* ================================================================
|
||||
* ---- Register KA_OF_OFEM_INTERRUPT_MASK */
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_OFFSET 0x00c
|
||||
#ifndef SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_NO_TEST_MASK
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_NO_TEST_MASK 0x000
|
||||
#endif
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MASK 0xffffffff
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MSB 31
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_LSB 0
|
||||
|
||||
/* ================================================================
|
||||
* ---- Register KA_OF_OFEM_SCRATCH */
|
||||
#define SAND_HAL_KA_OF_OFEM_SCRATCH_OFFSET 0x010
|
||||
#ifndef SAND_HAL_KA_OF_OFEM_SCRATCH_NO_TEST_MASK
|
||||
#define SAND_HAL_KA_OF_OFEM_SCRATCH_NO_TEST_MASK 0x000
|
||||
#endif
|
||||
#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK 0xffffffff
|
||||
#define SAND_HAL_KA_OF_OFEM_SCRATCH_MSB 31
|
||||
#define SAND_HAL_KA_OF_OFEM_SCRATCH_LSB 0
|
||||
|
||||
/* ================================================================
|
||||
* ---- Register KA_OF_OFEM_SCRATCH_MASK */
|
||||
#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_OFFSET 0x014
|
||||
#ifndef SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_NO_TEST_MASK
|
||||
#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_NO_TEST_MASK 0x000
|
||||
#endif
|
||||
#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_MASK 0xffffffff
|
||||
#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_MSB 31
|
||||
#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_LSB 0
|
||||
|
||||
/* ================================================================
|
||||
* Field info for register KA_OF_OFEM_REVISION */
|
||||
#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_MASK 0x0000ff00
|
||||
#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_SHIFT 8
|
||||
#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_MSB 15
|
||||
#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_LSB 8
|
||||
#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_DEFAULT 0x00000024
|
||||
#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_MASK 0x000000ff
|
||||
#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_SHIFT 0
|
||||
#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_MSB 7
|
||||
#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_LSB 0
|
||||
#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_DEFAULT 0x00000000
|
||||
|
||||
/* ================================================================
|
||||
* Field info for register KA_OF_OFEM_RESET */
|
||||
#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_MASK 0x00000004
|
||||
#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_SHIFT 2
|
||||
#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_MSB 2
|
||||
#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_LSB 2
|
||||
#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_MASK 0x00000002
|
||||
#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_SHIFT 1
|
||||
#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_MSB 1
|
||||
#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_LSB 1
|
||||
#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_MASK 0x00000001
|
||||
#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_SHIFT 0
|
||||
#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_MSB 0
|
||||
#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_LSB 0
|
||||
#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_DEFAULT 0x00000000
|
||||
|
||||
/* ================================================================
|
||||
* Field info for register KA_OF_OFEM_CNTL */
|
||||
#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_MASK 0x000000c0
|
||||
#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_SHIFT 6
|
||||
#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_MSB 7
|
||||
#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_LSB 6
|
||||
#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_MASK 0x00000030
|
||||
#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_SHIFT 4
|
||||
#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_MSB 5
|
||||
#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_LSB 4
|
||||
#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_MASK 0x0000000c
|
||||
#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_SHIFT 2
|
||||
#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_MSB 3
|
||||
#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_LSB 2
|
||||
#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_MASK 0x00000003
|
||||
#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_SHIFT 0
|
||||
#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_MSB 1
|
||||
#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_LSB 0
|
||||
#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_DEFAULT 0x00000000
|
||||
|
||||
/* ================================================================
|
||||
* Field info for register KA_OF_OFEM_MAC_FLOW_CTL */
|
||||
#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_MASK 0x00000100
|
||||
#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_SHIFT 8
|
||||
#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_MSB 8
|
||||
#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_LSB 8
|
||||
#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_MASK 0x00000010
|
||||
#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_SHIFT 4
|
||||
#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_MSB 4
|
||||
#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_LSB 4
|
||||
#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_MASK 0x0000000f
|
||||
#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_SHIFT 0
|
||||
#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_MSB 3
|
||||
#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_LSB 0
|
||||
#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_DEFAULT 0x00000000
|
||||
|
||||
/* ================================================================
|
||||
* Field info for register KA_OF_OFEM_INTERRUPT */
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_MASK 0x00000100
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_SHIFT 8
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_MSB 8
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_LSB 8
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_MASK 0x00000080
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_SHIFT 7
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_MSB 7
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_LSB 7
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_MASK 0x00000040
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_SHIFT 6
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_MSB 6
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_LSB 6
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_MASK 0x00000020
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_SHIFT 5
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_MSB 5
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_LSB 5
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_MASK 0x00000010
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_SHIFT 4
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_MSB 4
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_LSB 4
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_MASK 0x00000008
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_SHIFT 3
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_MSB 3
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_LSB 3
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_MASK 0x00000004
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_SHIFT 2
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_MSB 2
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_LSB 2
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_MASK 0x00000002
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_SHIFT 1
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_MSB 1
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_LSB 1
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_MASK 0x00000001
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_SHIFT 0
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_MSB 0
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_LSB 0
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_DEFAULT 0x00000000
|
||||
|
||||
/* ================================================================
|
||||
* Field info for register KA_OF_OFEM_INTERRUPT_MASK */
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_MASK 0x00000100
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_SHIFT 8
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_MSB 8
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_LSB 8
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_DEFAULT 0x00000001
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_MASK 0x00000080
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_SHIFT 7
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_MSB 7
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_LSB 7
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_DEFAULT 0x00000001
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_MASK 0x00000040
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_SHIFT 6
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_MSB 6
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_LSB 6
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_DEFAULT 0x00000001
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_MASK 0x00000020
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_SHIFT 5
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_MSB 5
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_LSB 5
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_DEFAULT 0x00000001
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_MASK 0x00000010
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_SHIFT 4
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_MSB 4
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_LSB 4
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_DEFAULT 0x00000001
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_MASK 0x00000008
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_SHIFT 3
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_MSB 3
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_LSB 3
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_DEFAULT 0x00000001
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_MASK 0x00000004
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_SHIFT 2
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_MSB 2
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_LSB 2
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_DEFAULT 0x00000001
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_MASK 0x00000002
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_SHIFT 1
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_MSB 1
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_LSB 1
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_DEFAULT 0x00000001
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_MASK 0x00000001
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_SHIFT 0
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_MSB 0
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_LSB 0
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_DEFAULT 0x00000001
|
||||
|
||||
/* ================================================================
|
||||
* Field info for register KA_OF_OFEM_SCRATCH */
|
||||
#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_MASK 0xffffffff
|
||||
#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_SHIFT 0
|
||||
#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_MSB 31
|
||||
#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_LSB 0
|
||||
#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_DEFAULT 0x00000000
|
||||
|
||||
/* ================================================================
|
||||
* Field info for register KA_OF_OFEM_SCRATCH_MASK */
|
||||
#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_MASK 0xffffffff
|
||||
#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_SHIFT 0
|
||||
#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_MSB 31
|
||||
#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_LSB 0
|
||||
#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_DEFAULT 0xffffffff
|
||||
|
||||
#endif /* matches #ifndef HAL_KA_OF_AUTO_H */
|
||||
|
|
@ -0,0 +1,836 @@
|
|||
/* ****************************************************************
|
||||
* Common defs for reg spec for chip ka_sc
|
||||
* Auto-generated by trex2: DO NOT HAND-EDIT!!
|
||||
* ****************************************************************
|
||||
*/
|
||||
|
||||
#ifndef HAL_KA_SC_AUTO_H
|
||||
#define HAL_KA_SC_AUTO_H
|
||||
|
||||
|
||||
/* ----------------------------------------------------------------
|
||||
* For block: 'scan'
|
||||
*/
|
||||
|
||||
/* ---- Block instance addressing (for block-select) */
|
||||
#define SCAN_BLOCK_ADDR_BIT_L 7
|
||||
#define SCAN_BLOCK_ADDR_BIT_H 9
|
||||
#define SCAN_BLOCK_ADDR_WIDTH 3
|
||||
|
||||
#define SCAN_ADDR 0x0
|
||||
|
||||
/* ---- Reg addressing (within block) */
|
||||
#define SCAN_REG_ADDR_BIT_L 2
|
||||
#define SCAN_REG_ADDR_BIT_H 6
|
||||
#define SCAN_REG_ADDR_WIDTH 5
|
||||
|
||||
|
||||
/* ================================================================
|
||||
* ---- Register KA_SC_SCAN_REVISION */
|
||||
#define SAND_HAL_KA_SC_SCAN_REVISION_OFFSET 0x000
|
||||
#ifndef SAND_HAL_KA_SC_SCAN_REVISION_NO_TEST_MASK
|
||||
#define SAND_HAL_KA_SC_SCAN_REVISION_NO_TEST_MASK 0x000
|
||||
#endif
|
||||
#define SAND_HAL_KA_SC_SCAN_REVISION_MASK 0xffffffff
|
||||
#define SAND_HAL_KA_SC_SCAN_REVISION_MSB 31
|
||||
#define SAND_HAL_KA_SC_SCAN_REVISION_LSB 0
|
||||
|
||||
/* ================================================================
|
||||
* ---- Register KA_SC_SCAN_RESET */
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_OFFSET 0x004
|
||||
#ifndef SAND_HAL_KA_SC_SCAN_RESET_NO_TEST_MASK
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_NO_TEST_MASK 0x000
|
||||
#endif
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_MASK 0xffffffff
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_MSB 31
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_LSB 0
|
||||
|
||||
/* ================================================================
|
||||
* ---- Register KA_SC_SCAN_STATUS */
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_OFFSET 0x008
|
||||
#ifndef SAND_HAL_KA_SC_SCAN_STATUS_NO_TEST_MASK
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_NO_TEST_MASK 0x000
|
||||
#endif
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_MASK 0xffffffff
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_MSB 31
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_LSB 0
|
||||
|
||||
/* ================================================================
|
||||
* ---- Register KA_SC_SCAN_CNTL */
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_OFFSET 0x01c
|
||||
#ifndef SAND_HAL_KA_SC_SCAN_CNTL_NO_TEST_MASK
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_NO_TEST_MASK 0x000
|
||||
#endif
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_MASK 0xffffffff
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_MSB 31
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_LSB 0
|
||||
|
||||
/* ================================================================
|
||||
* ---- Register KA_SC_SCAN_BRD_INFO */
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_INFO_OFFSET 0x020
|
||||
#ifndef SAND_HAL_KA_SC_SCAN_BRD_INFO_NO_TEST_MASK
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_INFO_NO_TEST_MASK 0x000
|
||||
#endif
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_INFO_MASK 0xffffffff
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_INFO_MSB 31
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_INFO_LSB 0
|
||||
|
||||
/* ================================================================
|
||||
* ---- Register KA_SC_SCAN_SCAN_FROM_0 */
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_OFFSET 0x024
|
||||
#ifndef SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_NO_TEST_MASK
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_NO_TEST_MASK 0x000
|
||||
#endif
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_MASK 0xffffffff
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_MSB 31
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_LSB 0
|
||||
|
||||
/* ================================================================
|
||||
* ---- Register KA_SC_SCAN_SCAN_FROM_1 */
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_OFFSET 0x028
|
||||
#ifndef SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_NO_TEST_MASK
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_NO_TEST_MASK 0x000
|
||||
#endif
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_MASK 0xffffffff
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_MSB 31
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_LSB 0
|
||||
|
||||
/* ================================================================
|
||||
* ---- Register KA_SC_SCAN_SCAN_TO_0 */
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_OFFSET 0x02c
|
||||
#ifndef SAND_HAL_KA_SC_SCAN_SCAN_TO_0_NO_TEST_MASK
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_NO_TEST_MASK 0x000
|
||||
#endif
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_MASK 0xffffffff
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_MSB 31
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_LSB 0
|
||||
|
||||
/* ================================================================
|
||||
* ---- Register KA_SC_SCAN_SCAN_TO_1 */
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_OFFSET 0x030
|
||||
#ifndef SAND_HAL_KA_SC_SCAN_SCAN_TO_1_NO_TEST_MASK
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_NO_TEST_MASK 0x000
|
||||
#endif
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_MASK 0xffffffff
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_MSB 31
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_LSB 0
|
||||
|
||||
/* ================================================================
|
||||
* ---- Register KA_SC_SCAN_SCAN_CTRL */
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_OFFSET 0x034
|
||||
#ifndef SAND_HAL_KA_SC_SCAN_SCAN_CTRL_NO_TEST_MASK
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_NO_TEST_MASK 0x000
|
||||
#endif
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_MASK 0xffffffff
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_MSB 31
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_LSB 0
|
||||
|
||||
/* ================================================================
|
||||
* ---- Register KA_SC_SCAN_PLL_CTRL */
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_OFFSET 0x038
|
||||
#ifndef SAND_HAL_KA_SC_SCAN_PLL_CTRL_NO_TEST_MASK
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_NO_TEST_MASK 0x000
|
||||
#endif
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_MASK 0xffffffff
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_MSB 31
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_LSB 0
|
||||
|
||||
/* ================================================================
|
||||
* ---- Register KA_SC_SCAN_CORE_CLK_COUNT */
|
||||
#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_OFFSET 0x03c
|
||||
#ifndef SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_NO_TEST_MASK
|
||||
#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_NO_TEST_MASK 0x000
|
||||
#endif
|
||||
#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_MASK 0xffffffff
|
||||
#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_MSB 31
|
||||
#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_LSB 0
|
||||
|
||||
/* ================================================================
|
||||
* ---- Register KA_SC_SCAN_DR_CLK_COUNT */
|
||||
#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_OFFSET 0x040
|
||||
#ifndef SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_NO_TEST_MASK
|
||||
#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_NO_TEST_MASK 0x000
|
||||
#endif
|
||||
#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_MASK 0xffffffff
|
||||
#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_MSB 31
|
||||
#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_LSB 0
|
||||
|
||||
/* ================================================================
|
||||
* ---- Register KA_SC_SCAN_SPI_CLK_COUNT */
|
||||
#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_OFFSET 0x044
|
||||
#ifndef SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_NO_TEST_MASK
|
||||
#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_NO_TEST_MASK 0x000
|
||||
#endif
|
||||
#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_MASK 0xffffffff
|
||||
#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_MSB 31
|
||||
#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_LSB 0
|
||||
|
||||
/* ================================================================
|
||||
* ---- Register KA_SC_SCAN_BRD_BRD_OUT_DATA */
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_OFFSET 0x048
|
||||
#ifndef SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_NO_TEST_MASK
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_NO_TEST_MASK 0x000
|
||||
#endif
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_MASK 0xffffffff
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_MSB 31
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_LSB 0
|
||||
|
||||
/* ================================================================
|
||||
* ---- Register KA_SC_SCAN_BRD_BRD_OUT_ENABLE */
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_OFFSET 0x04c
|
||||
#ifndef SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_NO_TEST_MASK
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_NO_TEST_MASK 0x000
|
||||
#endif
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_MASK 0xffffffff
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_MSB 31
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_LSB 0
|
||||
|
||||
/* ================================================================
|
||||
* ---- Register KA_SC_SCAN_BRD_BRD_IN */
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_OFFSET 0x050
|
||||
#ifndef SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_NO_TEST_MASK
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_NO_TEST_MASK 0x000
|
||||
#endif
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_MASK 0xffffffff
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_MSB 31
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_LSB 0
|
||||
|
||||
/* ================================================================
|
||||
* ---- Register KA_SC_SCAN_MISC */
|
||||
#define SAND_HAL_KA_SC_SCAN_MISC_OFFSET 0x054
|
||||
#ifndef SAND_HAL_KA_SC_SCAN_MISC_NO_TEST_MASK
|
||||
#define SAND_HAL_KA_SC_SCAN_MISC_NO_TEST_MASK 0x000
|
||||
#endif
|
||||
#define SAND_HAL_KA_SC_SCAN_MISC_MASK 0xffffffff
|
||||
#define SAND_HAL_KA_SC_SCAN_MISC_MSB 31
|
||||
#define SAND_HAL_KA_SC_SCAN_MISC_LSB 0
|
||||
|
||||
/* ================================================================
|
||||
* ---- Register KA_SC_SCAN_INTERRUPT */
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OFFSET 0x00c
|
||||
#ifndef SAND_HAL_KA_SC_SCAN_INTERRUPT_NO_TEST_MASK
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_NO_TEST_MASK 0x000
|
||||
#endif
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK 0xffffffff
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MSB 31
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_LSB 0
|
||||
|
||||
/* ================================================================
|
||||
* ---- Register KA_SC_SCAN_INTERRUPT_MASK */
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OFFSET 0x010
|
||||
#ifndef SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_NO_TEST_MASK
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_NO_TEST_MASK 0x000
|
||||
#endif
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_MASK 0xffffffff
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_MSB 31
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_LSB 0
|
||||
|
||||
/* ================================================================
|
||||
* ---- Register KA_SC_SCAN_SCRATCH */
|
||||
#define SAND_HAL_KA_SC_SCAN_SCRATCH_OFFSET 0x014
|
||||
#ifndef SAND_HAL_KA_SC_SCAN_SCRATCH_NO_TEST_MASK
|
||||
#define SAND_HAL_KA_SC_SCAN_SCRATCH_NO_TEST_MASK 0x000
|
||||
#endif
|
||||
#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK 0xffffffff
|
||||
#define SAND_HAL_KA_SC_SCAN_SCRATCH_MSB 31
|
||||
#define SAND_HAL_KA_SC_SCAN_SCRATCH_LSB 0
|
||||
|
||||
/* ================================================================
|
||||
* ---- Register KA_SC_SCAN_SCRATCH_MASK */
|
||||
#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_OFFSET 0x018
|
||||
#ifndef SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_NO_TEST_MASK
|
||||
#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_NO_TEST_MASK 0x000
|
||||
#endif
|
||||
#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_MASK 0xffffffff
|
||||
#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_MSB 31
|
||||
#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_LSB 0
|
||||
|
||||
/* ================================================================
|
||||
* Field info for register KA_SC_SCAN_REVISION */
|
||||
#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_MASK 0x0000ff00
|
||||
#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_SHIFT 8
|
||||
#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_MSB 15
|
||||
#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_LSB 8
|
||||
#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_DEFAULT 0x00000023
|
||||
#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_MASK 0x000000ff
|
||||
#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_SHIFT 0
|
||||
#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_MSB 7
|
||||
#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_LSB 0
|
||||
#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_DEFAULT 0x00000000
|
||||
|
||||
/* ================================================================
|
||||
* Field info for register KA_SC_SCAN_RESET */
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK 0x00000200
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_SHIFT 9
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MSB 9
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_LSB 9
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_MASK 0x00000100
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_SHIFT 8
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_MSB 8
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_LSB 8
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_MASK 0x00000080
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_SHIFT 7
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_MSB 7
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_LSB 7
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_MASK 0x00000040
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_SHIFT 6
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_MSB 6
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_LSB 6
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_MASK 0x00000020
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_SHIFT 5
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_MSB 5
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_LSB 5
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_MASK 0x00000010
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_SHIFT 4
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_MSB 4
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_LSB 4
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_MASK 0x00000008
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_SHIFT 3
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_MSB 3
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_LSB 3
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_MASK 0x00000002
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_SHIFT 1
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_MSB 1
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_LSB 1
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_MASK 0x00000001
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_SHIFT 0
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_MSB 0
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_LSB 0
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_DEFAULT 0x00000000
|
||||
|
||||
/* ================================================================
|
||||
* Field info for register KA_SC_SCAN_STATUS */
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_MASK 0x00000040
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_SHIFT 6
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_MSB 6
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_LSB 6
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_MASK 0x00000020
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_SHIFT 5
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_MSB 5
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_LSB 5
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_MASK 0x00000010
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_SHIFT 4
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_MSB 4
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_LSB 4
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_MASK 0x00000008
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_SHIFT 3
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_MSB 3
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_LSB 3
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_MASK 0x00000004
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_SHIFT 2
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_MSB 2
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_LSB 2
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_MASK 0x00000002
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_SHIFT 1
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_MSB 1
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_LSB 1
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_MASK 0x00000001
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_SHIFT 0
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_MSB 0
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_LSB 0
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_DEFAULT 0x00000000
|
||||
|
||||
/* ================================================================
|
||||
* Field info for register KA_SC_SCAN_CNTL */
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_MASK 0x00000400
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_SHIFT 10
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_MSB 10
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_LSB 10
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_MASK 0x00000200
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_SHIFT 9
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_MSB 9
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_LSB 9
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_DEFAULT 0x00000001
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_MASK 0x00000100
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_SHIFT 8
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_MSB 8
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_LSB 8
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_DEFAULT 0x00000001
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_MASK 0x000000c0
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_SHIFT 6
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_MSB 7
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_LSB 6
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_MASK 0x00000030
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_SHIFT 4
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_MSB 5
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_LSB 4
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_MASK 0x0000000c
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_SHIFT 2
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_MSB 3
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_LSB 2
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_MASK 0x00000003
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_SHIFT 0
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_MSB 1
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_LSB 0
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_DEFAULT 0x00000000
|
||||
|
||||
/* ================================================================
|
||||
* Field info for register KA_SC_SCAN_BRD_INFO */
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MASK 0x0000f000
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_SHIFT 12
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MSB 15
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_LSB 12
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_MASK 0x00000300
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_SHIFT 8
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_MSB 9
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_LSB 8
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_MASK 0x000000f0
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_SHIFT 4
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_MSB 7
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_LSB 4
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_MASK 0x00000003
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_SHIFT 0
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_MSB 1
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_LSB 0
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_DEFAULT 0x00000000
|
||||
|
||||
/* ================================================================
|
||||
* Field info for register KA_SC_SCAN_SCAN_FROM_0 */
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_MASK 0xffffffff
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_SHIFT 0
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_MSB 31
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_LSB 0
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_DEFAULT 0x00000000
|
||||
|
||||
/* ================================================================
|
||||
* Field info for register KA_SC_SCAN_SCAN_FROM_1 */
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_MASK 0xffffffff
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_SHIFT 0
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_MSB 31
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_LSB 0
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_DEFAULT 0x00000000
|
||||
|
||||
/* ================================================================
|
||||
* Field info for register KA_SC_SCAN_SCAN_TO_0 */
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_MASK 0xffffffff
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_SHIFT 0
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_MSB 31
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_LSB 0
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_DEFAULT 0x00000000
|
||||
|
||||
/* ================================================================
|
||||
* Field info for register KA_SC_SCAN_SCAN_TO_1 */
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_MASK 0xffffffff
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_SHIFT 0
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_MSB 31
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_LSB 0
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_DEFAULT 0x00000000
|
||||
|
||||
/* ================================================================
|
||||
* Field info for register KA_SC_SCAN_SCAN_CTRL */
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_MASK 0x04000000
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_SHIFT 26
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_MSB 26
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_LSB 26
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_MASK 0x03000000
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_SHIFT 24
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_MSB 25
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_LSB 24
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_MASK 0x00100000
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_SHIFT 20
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_MSB 20
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_LSB 20
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_MASK 0x00080000
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_SHIFT 19
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_MSB 19
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_LSB 19
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_MASK 0x00040000
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_SHIFT 18
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_MSB 18
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_LSB 18
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_MASK 0x00020000
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_SHIFT 17
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_MSB 17
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_LSB 17
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_MASK 0x00010000
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_SHIFT 16
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_MSB 16
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_LSB 16
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_MASK 0x00001000
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_SHIFT 12
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_MSB 12
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_LSB 12
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_MASK 0x00000800
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SHIFT 11
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_MSB 11
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_LSB 11
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_MASK 0x00000400
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SHIFT 10
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_MSB 10
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_LSB 10
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_MASK 0x00000200
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SHIFT 9
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_MSB 9
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_LSB 9
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_MASK 0x00000100
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SHIFT 8
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_MSB 8
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_LSB 8
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_MASK 0x00000018
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_SHIFT 3
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_MSB 4
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_LSB 3
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_MASK 0x00000004
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_SHIFT 2
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_MSB 2
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_LSB 2
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_MASK 0x00000002
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_SHIFT 1
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_MSB 1
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_LSB 1
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_MASK 0x00000001
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_SHIFT 0
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_MSB 0
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_LSB 0
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_DEFAULT 0x00000000
|
||||
|
||||
/* ================================================================
|
||||
* Field info for register KA_SC_SCAN_PLL_CTRL */
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_MASK 0x00002000
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_SHIFT 13
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_MSB 13
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_LSB 13
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_MASK 0x00001000
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_SHIFT 12
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_MSB 12
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_LSB 12
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_MASK 0x00000800
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_SHIFT 11
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_MSB 11
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_LSB 11
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_MASK 0x00000400
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_SHIFT 10
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_MSB 10
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_LSB 10
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_MASK 0x00000200
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_SHIFT 9
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_MSB 9
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_LSB 9
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_MASK 0x00000100
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_SHIFT 8
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_MSB 8
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_LSB 8
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_MASK 0x00000080
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_SHIFT 7
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_MSB 7
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_LSB 7
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_MASK 0x00000040
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_SHIFT 6
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_MSB 6
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_LSB 6
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_MASK 0x00000020
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_SHIFT 5
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_MSB 5
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_LSB 5
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_MASK 0x00000010
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_SHIFT 4
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_MSB 4
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_LSB 4
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_MASK 0x00000008
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_SHIFT 3
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_MSB 3
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_LSB 3
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_MASK 0x00000007
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_SHIFT 0
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_MSB 2
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_LSB 0
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_DEFAULT 0x00000000
|
||||
|
||||
/* ================================================================
|
||||
* Field info for register KA_SC_SCAN_CORE_CLK_COUNT */
|
||||
#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MASK 0x02000000
|
||||
#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_SHIFT 25
|
||||
#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MSB 25
|
||||
#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_LSB 25
|
||||
#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_MASK 0x01000000
|
||||
#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_SHIFT 24
|
||||
#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_MSB 24
|
||||
#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_LSB 24
|
||||
#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_MASK 0x00ffffff
|
||||
#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_SHIFT 0
|
||||
#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_MSB 23
|
||||
#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_LSB 0
|
||||
#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_DEFAULT 0x00000000
|
||||
|
||||
/* ================================================================
|
||||
* Field info for register KA_SC_SCAN_DR_CLK_COUNT */
|
||||
#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MASK 0x02000000
|
||||
#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_SHIFT 25
|
||||
#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MSB 25
|
||||
#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_LSB 25
|
||||
#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_MASK 0x01000000
|
||||
#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_SHIFT 24
|
||||
#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_MSB 24
|
||||
#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_LSB 24
|
||||
#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_MASK 0x00ffffff
|
||||
#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_SHIFT 0
|
||||
#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_MSB 23
|
||||
#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_LSB 0
|
||||
#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_DEFAULT 0x00000000
|
||||
|
||||
/* ================================================================
|
||||
* Field info for register KA_SC_SCAN_SPI_CLK_COUNT */
|
||||
#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MASK 0x02000000
|
||||
#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_SHIFT 25
|
||||
#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MSB 25
|
||||
#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_LSB 25
|
||||
#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_MASK 0x01000000
|
||||
#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_SHIFT 24
|
||||
#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_MSB 24
|
||||
#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_LSB 24
|
||||
#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_MASK 0x00ffffff
|
||||
#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_SHIFT 0
|
||||
#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_MSB 23
|
||||
#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_LSB 0
|
||||
#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_DEFAULT 0x00000000
|
||||
|
||||
/* ================================================================
|
||||
* Field info for register KA_SC_SCAN_BRD_BRD_OUT_DATA */
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_MASK 0x001fffff
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_SHIFT 0
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_MSB 20
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_LSB 0
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_DEFAULT 0x00000000
|
||||
|
||||
/* ================================================================
|
||||
* Field info for register KA_SC_SCAN_BRD_BRD_OUT_ENABLE */
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_MASK 0x001fffff
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_SHIFT 0
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_MSB 20
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_LSB 0
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_DEFAULT 0x00000000
|
||||
|
||||
/* ================================================================
|
||||
* Field info for register KA_SC_SCAN_BRD_BRD_IN */
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_MASK 0x001fffff
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_SHIFT 0
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_MSB 20
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_LSB 0
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_DEFAULT 0x00000000
|
||||
|
||||
/* ================================================================
|
||||
* Field info for register KA_SC_SCAN_MISC */
|
||||
#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_MASK 0x00000002
|
||||
#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_SHIFT 1
|
||||
#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_MSB 1
|
||||
#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_LSB 1
|
||||
#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_MASK 0x00000001
|
||||
#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_SHIFT 0
|
||||
#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_MSB 0
|
||||
#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_LSB 0
|
||||
#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_DEFAULT 0x00000000
|
||||
|
||||
/* ================================================================
|
||||
* Field info for register KA_SC_SCAN_INTERRUPT */
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_MASK 0x00000010
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_SHIFT 4
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_MSB 4
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_LSB 4
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_MASK 0x00000008
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_SHIFT 3
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_MSB 3
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_LSB 3
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_MASK 0x00000004
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_SHIFT 2
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_MSB 2
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_LSB 2
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_MASK 0x00000002
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_SHIFT 1
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_MSB 1
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_LSB 1
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_MASK 0x00000001
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_SHIFT 0
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_MSB 0
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_LSB 0
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_DEFAULT 0x00000000
|
||||
|
||||
/* ================================================================
|
||||
* Field info for register KA_SC_SCAN_INTERRUPT_MASK */
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_MASK 0x00000010
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_SHIFT 4
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_MSB 4
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_LSB 4
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_DEFAULT 0x00000001
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_MASK 0x00000008
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_SHIFT 3
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_MSB 3
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_LSB 3
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_DEFAULT 0x00000001
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_MASK 0x00000004
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_SHIFT 2
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_MSB 2
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_LSB 2
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_DEFAULT 0x00000001
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_MASK 0x00000002
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_SHIFT 1
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_MSB 1
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_LSB 1
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_DEFAULT 0x00000001
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_MASK 0x00000001
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_SHIFT 0
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_MSB 0
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_LSB 0
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_DEFAULT 0x00000001
|
||||
|
||||
/* ================================================================
|
||||
* Field info for register KA_SC_SCAN_SCRATCH */
|
||||
#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_MASK 0xffffffff
|
||||
#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_SHIFT 0
|
||||
#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_MSB 31
|
||||
#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_LSB 0
|
||||
#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_DEFAULT 0x00000000
|
||||
|
||||
/* ================================================================
|
||||
* Field info for register KA_SC_SCAN_SCRATCH_MASK */
|
||||
#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_MASK 0xffffffff
|
||||
#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_SHIFT 0
|
||||
#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_MSB 31
|
||||
#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_LSB 0
|
||||
#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_DEFAULT 0xffffffff
|
||||
|
||||
#endif /* matches #ifndef HAL_KA_SC_AUTO_H */
|
||||
|
|
@ -0,0 +1,101 @@
|
|||
/*
|
||||
* Copyright (C) 2005 Sandburst Corporation
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
/*
|
||||
* Ported from Ebony init.S by Travis B. Sawyer
|
||||
*/
|
||||
|
||||
#include <ppc_asm.tmpl>
|
||||
#include <config.h>
|
||||
|
||||
/* General */
|
||||
#define TLB_VALID 0x00000200
|
||||
|
||||
/* Supported page sizes */
|
||||
|
||||
#define SZ_1K 0x00000000
|
||||
#define SZ_4K 0x00000010
|
||||
#define SZ_16K 0x00000020
|
||||
#define SZ_64K 0x00000030
|
||||
#define SZ_256K 0x00000040
|
||||
#define SZ_1M 0x00000050
|
||||
#define SZ_16M 0x00000070
|
||||
#define SZ_256M 0x00000090
|
||||
|
||||
/* Storage attributes */
|
||||
#define SA_W 0x00000800 /* Write-through */
|
||||
#define SA_I 0x00000400 /* Caching inhibited */
|
||||
#define SA_M 0x00000200 /* Memory coherence */
|
||||
#define SA_G 0x00000100 /* Guarded */
|
||||
#define SA_E 0x00000080 /* Endian */
|
||||
|
||||
/* Access control */
|
||||
#define AC_X 0x00000024 /* Execute */
|
||||
#define AC_W 0x00000012 /* Write */
|
||||
#define AC_R 0x00000009 /* Read */
|
||||
|
||||
/* Some handy macros */
|
||||
|
||||
#define EPN(e) ((e) & 0xfffffc00)
|
||||
#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) )
|
||||
#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
|
||||
#define TLB2(a) ( (a)&0x00000fbf )
|
||||
|
||||
#define tlbtab_start\
|
||||
mflr r1 ;\
|
||||
bl 0f ;
|
||||
|
||||
#define tlbtab_end\
|
||||
.long 0, 0, 0 ; \
|
||||
0: mflr r0 ; \
|
||||
mtlr r1 ; \
|
||||
blr ;
|
||||
|
||||
#define tlbentry(epn,sz,rpn,erpn,attr)\
|
||||
.long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
|
||||
|
||||
|
||||
/**************************************************************************
|
||||
* TLB TABLE
|
||||
*
|
||||
* This table is used by the cpu boot code to setup the initial tlb
|
||||
* entries. Rather than make broad assumptions in the cpu source tree,
|
||||
* this table lets each board set things up however they like.
|
||||
*
|
||||
* Pointer to the table is returned in r1
|
||||
*
|
||||
*************************************************************************/
|
||||
|
||||
.section .bootpg,"ax"
|
||||
.globl tlbtab
|
||||
|
||||
tlbtab:
|
||||
tlbtab_start
|
||||
tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
|
||||
tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
|
||||
tlbentry( CFG_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
|
||||
tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
tlbentry( CFG_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
tlbentry( CFG_SDRAM_BASE+0x20000000, SZ_256M, 0x20000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
tlbentry( CFG_SDRAM_BASE+0x30000000, SZ_256M, 0x30000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
|
||||
tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I )
|
||||
tlbtab_end
|
||||
|
|
@ -0,0 +1,607 @@
|
|||
/*
|
||||
* Copyright (C) 2005 Sandburst Corporation
|
||||
* Travis B. Sawyer
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include "karef.h"
|
||||
#include "karef_version.h"
|
||||
#include <asm/processor.h>
|
||||
#include <asm/io.h>
|
||||
#include <spd_sdram.h>
|
||||
#include <i2c.h>
|
||||
#include "../common/sb_common.h"
|
||||
#include "../common/ppc440gx_i2c.h"
|
||||
|
||||
|
||||
|
||||
void fpga_init (void);
|
||||
|
||||
KAREF_BOARD_ID_ST board_id_as[] =
|
||||
{
|
||||
{"Undefined"}, /* Not specified */
|
||||
{"Kamino Reference Design"},
|
||||
{"Reserved"}, /* Reserved for future use */
|
||||
{"Reserved"}, /* Reserved for future use */
|
||||
};
|
||||
|
||||
KAREF_BOARD_ID_ST ofem_board_id_as[] =
|
||||
{
|
||||
{"Undefined"},
|
||||
{"1x10 + 10x2"},
|
||||
{"Reserved"},
|
||||
{"Reserved"},
|
||||
};
|
||||
|
||||
|
||||
/*************************************************************************
|
||||
* board_early_init_f
|
||||
*
|
||||
* Setup chip selects, initialize the Opto-FPGA, initialize
|
||||
* interrupt polarity and triggers.
|
||||
*
|
||||
************************************************************************/
|
||||
int board_early_init_f (void)
|
||||
{
|
||||
ppc440_gpio_regs_t *gpio_regs;
|
||||
|
||||
/* Enable GPIO interrupts */
|
||||
mtsdr(sdr_pfc0, 0x00103E00);
|
||||
|
||||
/* Setup access for LEDs, and system topology info */
|
||||
gpio_regs = (ppc440_gpio_regs_t *)CFG_GPIO_BASE;
|
||||
gpio_regs->open_drain = SBCOMMON_GPIO_SYS_LEDS;
|
||||
gpio_regs->tri_state = SBCOMMON_GPIO_DBGLEDS;
|
||||
|
||||
/* Turn on all the leds for now */
|
||||
gpio_regs->out = SBCOMMON_GPIO_LEDS;
|
||||
|
||||
/*--------------------------------------------------------------------+
|
||||
| Initialize EBC CONFIG
|
||||
+-------------------------------------------------------------------*/
|
||||
mtebc(xbcfg,
|
||||
EBC_CFG_LE_UNLOCK | EBC_CFG_PTD_ENABLE |
|
||||
EBC_CFG_RTC_64PERCLK | EBC_CFG_ATC_PREVIOUS |
|
||||
EBC_CFG_DTC_PREVIOUS | EBC_CFG_CTC_PREVIOUS |
|
||||
EBC_CFG_EMC_DEFAULT | EBC_CFG_PME_DISABLE |
|
||||
EBC_CFG_PR_32);
|
||||
|
||||
/*--------------------------------------------------------------------+
|
||||
| 1/2 MB FLASH. Initialize bank 0 with default values.
|
||||
+-------------------------------------------------------------------*/
|
||||
mtebc(pb0ap,
|
||||
EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
|
||||
EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
|
||||
EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
|
||||
EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) |
|
||||
EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
|
||||
EBC_BXAP_PEN_DISABLED);
|
||||
|
||||
mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(CFG_FLASH_BASE) |
|
||||
EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
|
||||
/*--------------------------------------------------------------------+
|
||||
| 8KB NVRAM/RTC. Initialize bank 1 with default values.
|
||||
+-------------------------------------------------------------------*/
|
||||
mtebc(pb1ap,
|
||||
EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(10) |
|
||||
EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
|
||||
EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
|
||||
EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) |
|
||||
EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
|
||||
EBC_BXAP_PEN_DISABLED);
|
||||
|
||||
mtebc(pb1cr, EBC_BXCR_BAS_ENCODE(0x48000000) |
|
||||
EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
|
||||
|
||||
/*--------------------------------------------------------------------+
|
||||
| Compact Flash, uses 2 Chip Selects (2 & 6)
|
||||
+-------------------------------------------------------------------*/
|
||||
mtebc(pb2ap,
|
||||
EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
|
||||
EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
|
||||
EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
|
||||
EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) |
|
||||
EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
|
||||
EBC_BXAP_PEN_DISABLED);
|
||||
|
||||
mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(0xF0000000) |
|
||||
EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
|
||||
|
||||
/*--------------------------------------------------------------------+
|
||||
| KaRef Scan FPGA. Initialize bank 3 with default values.
|
||||
+-------------------------------------------------------------------*/
|
||||
mtebc(pb5ap,
|
||||
EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
|
||||
EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
|
||||
EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
|
||||
EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
|
||||
EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
|
||||
|
||||
mtebc(pb5cr, EBC_BXCR_BAS_ENCODE(0x48200000) |
|
||||
EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
|
||||
|
||||
/*--------------------------------------------------------------------+
|
||||
| MAC A & B for Kamino. OFEM FPGA decodes the addresses
|
||||
| Initialize bank 4 with default values.
|
||||
+-------------------------------------------------------------------*/
|
||||
mtebc(pb4ap,
|
||||
EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
|
||||
EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
|
||||
EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
|
||||
EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
|
||||
EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
|
||||
|
||||
mtebc(pb4cr, EBC_BXCR_BAS_ENCODE(0x48600000) |
|
||||
EBC_BXCR_BS_2MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
|
||||
|
||||
/*--------------------------------------------------------------------+
|
||||
| OFEM FPGA Initialize bank 5 with default values.
|
||||
+-------------------------------------------------------------------*/
|
||||
mtebc(pb3ap,
|
||||
EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
|
||||
EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
|
||||
EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
|
||||
EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
|
||||
EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
|
||||
|
||||
|
||||
mtebc(pb3cr, EBC_BXCR_BAS_ENCODE(0x48400000) |
|
||||
EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
|
||||
|
||||
|
||||
/*--------------------------------------------------------------------+
|
||||
| Compact Flash, uses 2 Chip Selects (2 & 6)
|
||||
+-------------------------------------------------------------------*/
|
||||
mtebc(pb6ap,
|
||||
EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
|
||||
EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
|
||||
EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
|
||||
EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) |
|
||||
EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
|
||||
EBC_BXAP_PEN_DISABLED);
|
||||
|
||||
mtebc(pb6cr, EBC_BXCR_BAS_ENCODE(0xF0100000) |
|
||||
EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
|
||||
|
||||
/*--------------------------------------------------------------------+
|
||||
| BME-32. Initialize bank 7 with default values.
|
||||
+-------------------------------------------------------------------*/
|
||||
mtebc(pb7ap,
|
||||
EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
|
||||
EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
|
||||
EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
|
||||
EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
|
||||
EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
|
||||
|
||||
mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48500000) |
|
||||
EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
|
||||
|
||||
|
||||
/*--------------------------------------------------------------------+
|
||||
* Setup the interrupt controller polarities, triggers, etc.
|
||||
+-------------------------------------------------------------------*/
|
||||
mtdcr (uic0sr, 0xffffffff); /* clear all */
|
||||
mtdcr (uic0er, 0x00000000); /* disable all */
|
||||
mtdcr (uic0cr, 0x00000000); /* all non- critical */
|
||||
mtdcr (uic0pr, 0xfffffe03); /* polarity */
|
||||
mtdcr (uic0tr, 0x01c00000); /* trigger edge vs level */
|
||||
mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */
|
||||
mtdcr (uic0sr, 0xffffffff); /* clear all */
|
||||
|
||||
mtdcr (uic1sr, 0xffffffff); /* clear all */
|
||||
mtdcr (uic1er, 0x00000000); /* disable all */
|
||||
mtdcr (uic1cr, 0x00000000); /* all non-critical */
|
||||
mtdcr (uic1pr, 0xffffc8ff); /* polarity */
|
||||
mtdcr (uic1tr, 0x00ff0000); /* trigger edge vs level */
|
||||
mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */
|
||||
mtdcr (uic1sr, 0xffffffff); /* clear all */
|
||||
|
||||
mtdcr (uic2sr, 0xffffffff); /* clear all */
|
||||
mtdcr (uic2er, 0x00000000); /* disable all */
|
||||
mtdcr (uic2cr, 0x00000000); /* all non-critical */
|
||||
mtdcr (uic2pr, 0xffff83ff); /* polarity */
|
||||
mtdcr (uic2tr, 0x00ff8c0f); /* trigger edge vs level */
|
||||
mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */
|
||||
mtdcr (uic2sr, 0xffffffff); /* clear all */
|
||||
|
||||
mtdcr (uicb0sr, 0xfc000000); /* clear all */
|
||||
mtdcr (uicb0er, 0x00000000); /* disable all */
|
||||
mtdcr (uicb0cr, 0x00000000); /* all non-critical */
|
||||
mtdcr (uicb0pr, 0xfc000000);
|
||||
mtdcr (uicb0tr, 0x00000000);
|
||||
mtdcr (uicb0vr, 0x00000001);
|
||||
|
||||
fpga_init();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
/*************************************************************************
|
||||
* checkboard
|
||||
*
|
||||
* Dump pertinent info to the console
|
||||
*
|
||||
************************************************************************/
|
||||
int checkboard (void)
|
||||
{
|
||||
sys_info_t sysinfo;
|
||||
unsigned char brd_rev, brd_id;
|
||||
unsigned short sernum;
|
||||
unsigned char scan_rev, scan_id, ofem_rev, ofem_id;
|
||||
unsigned char ofem_brd_rev, ofem_brd_id;
|
||||
KAREF_FPGA_REGS_ST *karef_ps;
|
||||
OFEM_FPGA_REGS_ST *ofem_ps;
|
||||
|
||||
karef_ps = (KAREF_FPGA_REGS_ST *)CFG_KAREF_FPGA_BASE;
|
||||
ofem_ps = (OFEM_FPGA_REGS_ST *)CFG_OFEM_FPGA_BASE;
|
||||
|
||||
scan_id = (unsigned char)((karef_ps->revision_ul &
|
||||
SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_MASK)
|
||||
>> SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_SHIFT);
|
||||
|
||||
scan_rev = (unsigned char)((karef_ps->revision_ul & SAND_HAL_KA_SC_SCAN_REVISION_REVISION_MASK)
|
||||
>> SAND_HAL_KA_SC_SCAN_REVISION_REVISION_SHIFT);
|
||||
|
||||
brd_rev = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_MASK)
|
||||
>> SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_SHIFT);
|
||||
|
||||
brd_id = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_MASK)
|
||||
>> SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_SHIFT);
|
||||
|
||||
ofem_brd_id = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MASK)
|
||||
>> SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_SHIFT);
|
||||
|
||||
ofem_brd_rev = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_MASK)
|
||||
>> SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_SHIFT);
|
||||
|
||||
if (0xF != ofem_brd_id) {
|
||||
ofem_id = (unsigned char)((ofem_ps->revision_ul &
|
||||
SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_MASK)
|
||||
>> SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_SHIFT);
|
||||
|
||||
ofem_rev = (unsigned char)((ofem_ps->revision_ul &
|
||||
SAND_HAL_KA_OF_OFEM_REVISION_REVISION_MASK)
|
||||
>> SAND_HAL_KA_OF_OFEM_REVISION_REVISION_SHIFT);
|
||||
}
|
||||
|
||||
get_sys_info (&sysinfo);
|
||||
|
||||
sernum = sbcommon_get_serial_number();
|
||||
|
||||
printf ("Board: Sandburst Corporation Kamino Reference Design "
|
||||
"Serial Number: %d\n", sernum);
|
||||
printf ("%s\n", KAREF_U_BOOT_REL_STR);
|
||||
|
||||
printf ("Built %s %s by %s\n", __DATE__, __TIME__, BUILDUSER);
|
||||
if (sbcommon_get_master()) {
|
||||
printf("Slot 0 - Master\nSlave board");
|
||||
if (sbcommon_secondary_present())
|
||||
printf(" present\n");
|
||||
else
|
||||
printf(" not detected\n");
|
||||
} else {
|
||||
printf("Slot 1 - Slave\n\n");
|
||||
}
|
||||
|
||||
printf ("ScanFPGA ID:\t0x%02X\tRev: 0x%02X\n", scan_id, scan_rev);
|
||||
printf ("Board Rev:\t0x%02X\tID: 0x%02X\n", brd_rev, brd_id);
|
||||
if(0xF != ofem_brd_id) {
|
||||
printf("OFemFPGA ID:\t0x%02X\tRev: 0x%02X\n", ofem_id, ofem_rev);
|
||||
printf("OFEM Board Rev:\t0x%02X\tID: 0x%02X\n", ofem_brd_id, ofem_brd_rev);
|
||||
}
|
||||
|
||||
printf ("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
|
||||
printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
|
||||
printf ("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
|
||||
printf ("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
|
||||
printf ("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000);
|
||||
|
||||
/* Fix the ack in the bme 32 */
|
||||
udelay(5000);
|
||||
out32(CFG_BME32_BASE + 0x0000000C, 0x00000001);
|
||||
asm("eieio");
|
||||
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
|
||||
/*************************************************************************
|
||||
* misc_init_f
|
||||
*
|
||||
* Initialize I2C bus one to gain access to the fans
|
||||
*
|
||||
************************************************************************/
|
||||
int misc_init_f (void)
|
||||
{
|
||||
/* Turn on i2c bus 1 */
|
||||
puts ("I2C1: ");
|
||||
i2c1_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
|
||||
puts ("ready\n");
|
||||
|
||||
/* Turn on fans 3 & 4 */
|
||||
sbcommon_fans();
|
||||
|
||||
return (0);
|
||||
}
|
||||
/*************************************************************************
|
||||
* misc_init_r
|
||||
*
|
||||
* Do nothing.
|
||||
*
|
||||
************************************************************************/
|
||||
int misc_init_r (void)
|
||||
{
|
||||
unsigned short sernum;
|
||||
char envstr[255];
|
||||
KAREF_FPGA_REGS_ST *karef_ps;
|
||||
OFEM_FPGA_REGS_ST *ofem_ps;
|
||||
unsigned char ofem_id;
|
||||
|
||||
if(NULL != getenv("secondserial")) {
|
||||
puts("secondserial is set, switching to second serial port\n");
|
||||
setenv("stderr", "serial1");
|
||||
setenv("stdout", "serial1");
|
||||
setenv("stdin", "serial1");
|
||||
}
|
||||
|
||||
setenv("ubrelver", KAREF_U_BOOT_REL_STR);
|
||||
|
||||
memset(envstr, 0, 255);
|
||||
sprintf (envstr, "Built %s %s by %s", __DATE__, __TIME__, BUILDUSER);
|
||||
setenv("bldstr", envstr);
|
||||
saveenv();
|
||||
|
||||
if( getenv("autorecover")) {
|
||||
setenv("autorecover", NULL);
|
||||
saveenv();
|
||||
sernum = sbcommon_get_serial_number();
|
||||
|
||||
printf("\nSetting up environment for automatic filesystem recovery\n");
|
||||
/*
|
||||
* Setup default bootargs
|
||||
*/
|
||||
memset(envstr, 0, 255);
|
||||
|
||||
sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 "
|
||||
"rw ip=10.100.70.%d:::255.255.0.0:karef%d:eth0:none idebus=33",
|
||||
sernum, sernum);
|
||||
setenv("bootargs", envstr);
|
||||
|
||||
/*
|
||||
* Setup Default boot command
|
||||
*/
|
||||
setenv("bootcmd", "fatload ide 0 8000000 uimage.karef;"
|
||||
"fatload ide 0 8100000 pramdisk;"
|
||||
"bootm 8000000 8100000");
|
||||
|
||||
printf("Done. Please type allow the system to continue to boot\n");
|
||||
}
|
||||
|
||||
if( getenv("fakeled")) {
|
||||
karef_ps = (KAREF_FPGA_REGS_ST *)CFG_KAREF_FPGA_BASE;
|
||||
ofem_ps = (OFEM_FPGA_REGS_ST *)CFG_OFEM_FPGA_BASE;
|
||||
ofem_ps->control_ul &= ~SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_MASK;
|
||||
karef_ps->control_ul &= ~SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_MASK;
|
||||
setenv("bootdelay", "-1");
|
||||
saveenv();
|
||||
printf("fakeled is set. use 'setenv fakeled ; setenv bootdelay 5 ; saveenv' to recover\n");
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
/*************************************************************************
|
||||
* ide_set_reset
|
||||
*
|
||||
*
|
||||
*
|
||||
************************************************************************/
|
||||
#ifdef CONFIG_IDE_RESET
|
||||
void ide_set_reset(int on)
|
||||
{
|
||||
KAREF_FPGA_REGS_ST *karef_ps;
|
||||
/* TODO: ide reset */
|
||||
karef_ps = (KAREF_FPGA_REGS_ST *)CFG_KAREF_FPGA_BASE;
|
||||
|
||||
if (on) {
|
||||
karef_ps->reset_ul &= ~SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK;
|
||||
} else {
|
||||
karef_ps->reset_ul |= SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK;
|
||||
}
|
||||
}
|
||||
#endif /* CONFIG_IDE_RESET */
|
||||
|
||||
/*************************************************************************
|
||||
* fpga_init
|
||||
*
|
||||
*
|
||||
*
|
||||
************************************************************************/
|
||||
void fpga_init(void)
|
||||
{
|
||||
KAREF_FPGA_REGS_ST *karef_ps;
|
||||
OFEM_FPGA_REGS_ST *ofem_ps;
|
||||
unsigned char ofem_id;
|
||||
unsigned long tmp;
|
||||
|
||||
/* Ensure we have power all around */
|
||||
udelay(500);
|
||||
|
||||
karef_ps = (KAREF_FPGA_REGS_ST *)CFG_KAREF_FPGA_BASE;
|
||||
tmp =
|
||||
SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK |
|
||||
SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_MASK |
|
||||
SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_MASK |
|
||||
SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_MASK |
|
||||
SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_MASK |
|
||||
SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_MASK |
|
||||
SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_MASK |
|
||||
SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_MASK |
|
||||
SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_MASK;
|
||||
|
||||
karef_ps->reset_ul = tmp;
|
||||
|
||||
/*
|
||||
* Wait a bit to allow the ofem fpga to get its brains
|
||||
*/
|
||||
udelay(5000);
|
||||
|
||||
/*
|
||||
* Check to see if the ofem is there
|
||||
*/
|
||||
ofem_id = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MASK)
|
||||
>> SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_SHIFT);
|
||||
if(0xF != ofem_id) {
|
||||
tmp =
|
||||
SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_MASK |
|
||||
SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_MASK |
|
||||
SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_MASK;
|
||||
|
||||
ofem_ps = (OFEM_FPGA_REGS_ST *)CFG_OFEM_FPGA_BASE;
|
||||
ofem_ps->reset_ul = tmp;
|
||||
|
||||
ofem_ps->control_ul |= 1 < SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_SHIFT;
|
||||
}
|
||||
|
||||
karef_ps->control_ul |= 1 << SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_SHIFT;
|
||||
|
||||
asm("eieio");
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
|
||||
int karefSetupVars(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
unsigned short sernum;
|
||||
char envstr[255];
|
||||
|
||||
sernum = sbcommon_get_serial_number();
|
||||
|
||||
memset(envstr, 0, 255);
|
||||
/*
|
||||
* Setup our ip address
|
||||
*/
|
||||
sprintf(envstr, "10.100.70.%d", sernum);
|
||||
|
||||
setenv("ipaddr", envstr);
|
||||
/*
|
||||
* Setup the host ip address
|
||||
*/
|
||||
setenv("serverip", "10.100.17.10");
|
||||
|
||||
/*
|
||||
* Setup default bootargs
|
||||
*/
|
||||
memset(envstr, 0, 255);
|
||||
|
||||
sprintf(envstr, "console=ttyS0,9600 root=/dev/nfs "
|
||||
"rw nfsroot=10.100.17.10:/home/metrobox/mbc70.%d "
|
||||
"nfsaddrs=10.100.70.%d:10.100.17.10:10.100.1.1:"
|
||||
"255.255.0.0:karef%d.sandburst.com:eth0:none idebus=33",
|
||||
sernum, sernum, sernum);
|
||||
|
||||
setenv("bootargs_nfs", envstr);
|
||||
setenv("bootargs", envstr);
|
||||
|
||||
/*
|
||||
* Setup CF bootargs
|
||||
*/
|
||||
memset(envstr, 0, 255);
|
||||
|
||||
sprintf(envstr, "console=ttyS0,9600 root=/dev/hda2 "
|
||||
"rw ip=10.100.70.%d:::255.255.0.0:karef%d:eth0:none idebus=33",
|
||||
sernum, sernum);
|
||||
|
||||
setenv("bootargs_cf", envstr);
|
||||
|
||||
/*
|
||||
* Setup Default boot command
|
||||
*/
|
||||
setenv("bootcmd_tftp", "tftp 8000000 uImage.karef;bootm 8000000");
|
||||
setenv("bootcmd", "tftp 8000000 uImage.karef;bootm 8000000");
|
||||
|
||||
/*
|
||||
* Setup compact flash boot command
|
||||
*/
|
||||
setenv("bootcmd_cf", "fatload ide 0 8000000 uimage.karef;bootm 8000000");
|
||||
|
||||
saveenv();
|
||||
|
||||
return(1);
|
||||
}
|
||||
|
||||
|
||||
int karefRecover(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
unsigned short sernum;
|
||||
char envstr[255];
|
||||
|
||||
sernum = sbcommon_get_serial_number();
|
||||
|
||||
printf("\nSetting up environment for filesystem recovery\n");
|
||||
/*
|
||||
* Setup default bootargs
|
||||
*/
|
||||
memset(envstr, 0, 255);
|
||||
|
||||
sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 "
|
||||
"rw ip=10.100.70.%d:::255.255.0.0:karef%d:eth0:none",
|
||||
sernum, sernum);
|
||||
setenv("bootargs", envstr);
|
||||
|
||||
/*
|
||||
* Setup Default boot command
|
||||
*/
|
||||
|
||||
setenv("bootcmd", "fatload ide 0 8000000 uimage.karef;"
|
||||
"fatload ide 0 8100000 pramdisk;"
|
||||
"bootm 8000000 8100000");
|
||||
|
||||
printf("Done. Please type boot<cr>.\nWhen the kernel has booted"
|
||||
" please type fsrecover.sh<cr>\n");
|
||||
|
||||
return(1);
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
U_BOOT_CMD(kasetup, 1, 1, karefSetupVars,
|
||||
"kasetup - Set environment to factory defaults\n", NULL);
|
||||
|
||||
U_BOOT_CMD(karecover, 1, 1, karefRecover,
|
||||
"karecover - Set environment to allow for fs recovery\n", NULL);
|
||||
|
||||
|
|
@ -0,0 +1,76 @@
|
|||
#ifndef __KAREF_H__
|
||||
#define __KAREF_H__
|
||||
/*
|
||||
* (C) Copyright 2005
|
||||
* Sandburst Corporation
|
||||
* Travis B. Sawyer
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/* Ka Reference Design OFEM FPGA Registers & definitions */
|
||||
#include "hal_ka_sc_auto.h"
|
||||
#include "hal_ka_of_auto.h"
|
||||
|
||||
typedef struct karef_board_id_s {
|
||||
const char name[40];
|
||||
} KAREF_BOARD_ID_ST, *KAREF_BOARD_ID_PST;
|
||||
|
||||
/* SCAN FPGA */
|
||||
typedef struct karef_fpga_regs_s
|
||||
{
|
||||
volatile unsigned long revision_ul; /* Read Only */
|
||||
volatile unsigned long reset_ul; /* Read/Write */
|
||||
volatile unsigned long interrupt_ul; /* Read Only */
|
||||
volatile unsigned long mask_ul; /* Read/Write */
|
||||
volatile unsigned long scratch_ul; /* Read/Write */
|
||||
volatile unsigned long scrmask_ul; /* Read/Write */
|
||||
volatile unsigned long status_ul; /* Read Only */
|
||||
volatile unsigned long control_ul; /* Read/Write */
|
||||
volatile unsigned long boardinfo_ul; /* Read Only */
|
||||
volatile unsigned long scan_from0_ul; /* Read Only */
|
||||
volatile unsigned long scan_from1_ul; /* Read Only */
|
||||
volatile unsigned long scan_to0_ul; /* Read/Write */
|
||||
volatile unsigned long scan_to1_ul; /* Read/Write */
|
||||
volatile unsigned long scan_control_ul; /* Read/Write */
|
||||
volatile unsigned long pll_control_ul; /* Read/Write */
|
||||
volatile unsigned long core_clock_cnt_ul; /* Read/Write */
|
||||
volatile unsigned long dr_clock_cnt_ul; /* Read/Write */
|
||||
volatile unsigned long spi_clock_cnt_ul; /* Read/Write */
|
||||
volatile unsigned long brdout_data_ul; /* Read/Write */
|
||||
volatile unsigned long brdout_enable_ul; /* Read/Write */
|
||||
volatile unsigned long brdin_data_ul; /* Read Only */
|
||||
volatile unsigned long misc_ul; /* Read/Write */
|
||||
} KAREF_FPGA_REGS_ST __attribute__((packed)), * KAREF_FPGA_REGS_PST;
|
||||
|
||||
/* OFEM FPGA */
|
||||
typedef struct ofem_fpga_regs_s
|
||||
{
|
||||
volatile unsigned long revision_ul; /* Read Only */
|
||||
volatile unsigned long reset_ul; /* Read/Write */
|
||||
volatile unsigned long interrupt_ul; /* Read Only */
|
||||
volatile unsigned long mask_ul; /* Read/Write */
|
||||
volatile unsigned long scratch_ul; /* Read/Write */
|
||||
volatile unsigned long scrmask_ul; /* Read/Write */
|
||||
volatile unsigned long control_ul; /* Read/Write */
|
||||
volatile unsigned long mac_flow_ctrl_ul; /* Read/Write */
|
||||
} OFEM_FPGA_REGS_ST __attribute__((packed)), * OFEM_FPGA_REGS_PST;
|
||||
|
||||
|
||||
#endif /* __KAREF_H__ */
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
#ifndef _KAREF_VERSION_H_
|
||||
#define _KAREF_VERSION_H_
|
||||
/*
|
||||
* Copyright (C) 2005 Sandburst Corporation
|
||||
* Travis B. Sawyer
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
#define KAREF_U_BOOT_REL_STR "Release 0.0.7"
|
||||
#endif
|
||||
|
|
@ -0,0 +1,156 @@
|
|||
/*
|
||||
* (C) Copyright 2005
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
* Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(powerpc)
|
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
|
||||
/* Do we need any of these for elf?
|
||||
__DYNAMIC = 0; */
|
||||
SECTIONS
|
||||
{
|
||||
.resetvec 0xFFFFFFFC :
|
||||
{
|
||||
*(.resetvec)
|
||||
} = 0xffff
|
||||
|
||||
.bootpg 0xFFFFF000 :
|
||||
{
|
||||
cpu/ppc4xx/start.o (.bootpg)
|
||||
} = 0xffff
|
||||
|
||||
/* Read-only sections, merged into text segment: */
|
||||
. = + SIZEOF_HEADERS;
|
||||
.interp : { *(.interp) }
|
||||
.hash : { *(.hash) }
|
||||
.dynsym : { *(.dynsym) }
|
||||
.dynstr : { *(.dynstr) }
|
||||
.rel.text : { *(.rel.text) }
|
||||
.rela.text : { *(.rela.text) }
|
||||
.rel.data : { *(.rel.data) }
|
||||
.rela.data : { *(.rela.data) }
|
||||
.rel.rodata : { *(.rel.rodata) }
|
||||
.rela.rodata : { *(.rela.rodata) }
|
||||
.rel.got : { *(.rel.got) }
|
||||
.rela.got : { *(.rela.got) }
|
||||
.rel.ctors : { *(.rel.ctors) }
|
||||
.rela.ctors : { *(.rela.ctors) }
|
||||
.rel.dtors : { *(.rel.dtors) }
|
||||
.rela.dtors : { *(.rela.dtors) }
|
||||
.rel.bss : { *(.rel.bss) }
|
||||
.rela.bss : { *(.rela.bss) }
|
||||
.rel.plt : { *(.rel.plt) }
|
||||
.rela.plt : { *(.rela.plt) }
|
||||
.init : { *(.init) }
|
||||
.plt : { *(.plt) }
|
||||
.text :
|
||||
{
|
||||
/* WARNING - the following is hand-optimized to fit within */
|
||||
/* the sector layout of our flash chips! XXX FIXME XXX */
|
||||
|
||||
cpu/ppc4xx/start.o (.text)
|
||||
board/sandburst/karef/init.o (.text)
|
||||
cpu/ppc4xx/kgdb.o (.text)
|
||||
cpu/ppc4xx/traps.o (.text)
|
||||
cpu/ppc4xx/interrupts.o (.text)
|
||||
cpu/ppc4xx/serial.o (.text)
|
||||
cpu/ppc4xx/cpu_init.o (.text)
|
||||
cpu/ppc4xx/speed.o (.text)
|
||||
cpu/ppc4xx/440gx_enet.o (.text)
|
||||
common/dlmalloc.o (.text)
|
||||
lib_generic/crc32.o (.text)
|
||||
lib_ppc/extable.o (.text)
|
||||
lib_generic/zlib.o (.text)
|
||||
|
||||
/* . = env_offset;*/
|
||||
/* common/environment.o(.text)*/
|
||||
|
||||
*(.text)
|
||||
*(.fixup)
|
||||
*(.got1)
|
||||
}
|
||||
_etext = .;
|
||||
PROVIDE (etext = .);
|
||||
.rodata :
|
||||
{
|
||||
*(.rodata)
|
||||
*(.rodata1)
|
||||
*(.rodata.str1.4)
|
||||
}
|
||||
.fini : { *(.fini) } =0
|
||||
.ctors : { *(.ctors) }
|
||||
.dtors : { *(.dtors) }
|
||||
|
||||
/* Read-write section, merged into data segment: */
|
||||
. = (. + 0x00FF) & 0xFFFFFF00;
|
||||
_erotext = .;
|
||||
PROVIDE (erotext = .);
|
||||
.reloc :
|
||||
{
|
||||
*(.got)
|
||||
_GOT2_TABLE_ = .;
|
||||
*(.got2)
|
||||
_FIXUP_TABLE_ = .;
|
||||
*(.fixup)
|
||||
}
|
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
|
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data)
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata2)
|
||||
*(.dynamic)
|
||||
CONSTRUCTORS
|
||||
}
|
||||
_edata = .;
|
||||
PROVIDE (edata = .);
|
||||
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
|
||||
__start___ex_table = .;
|
||||
__ex_table : { *(__ex_table) }
|
||||
__stop___ex_table = .;
|
||||
|
||||
. = ALIGN(256);
|
||||
__init_begin = .;
|
||||
.text.init : { *(.text.init) }
|
||||
.data.init : { *(.data.init) }
|
||||
. = ALIGN(256);
|
||||
__init_end = .;
|
||||
|
||||
__bss_start = .;
|
||||
.bss :
|
||||
{
|
||||
*(.sbss) *(.scommon)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(COMMON)
|
||||
}
|
||||
_end = . ;
|
||||
PROVIDE (end = .);
|
||||
}
|
||||
|
|
@ -0,0 +1,145 @@
|
|||
/*
|
||||
* (C) Copyright 2002-2005
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
* Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(powerpc)
|
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
|
||||
/* Do we need any of these for elf?
|
||||
__DYNAMIC = 0; */
|
||||
SECTIONS
|
||||
{
|
||||
/* Read-only sections, merged into text segment: */
|
||||
. = + SIZEOF_HEADERS;
|
||||
.interp : { *(.interp) }
|
||||
.hash : { *(.hash) }
|
||||
.dynsym : { *(.dynsym) }
|
||||
.dynstr : { *(.dynstr) }
|
||||
.rel.text : { *(.rel.text) }
|
||||
.rela.text : { *(.rela.text) }
|
||||
.rel.data : { *(.rel.data) }
|
||||
.rela.data : { *(.rela.data) }
|
||||
.rel.rodata : { *(.rel.rodata) }
|
||||
.rela.rodata : { *(.rela.rodata) }
|
||||
.rel.got : { *(.rel.got) }
|
||||
.rela.got : { *(.rela.got) }
|
||||
.rel.ctors : { *(.rel.ctors) }
|
||||
.rela.ctors : { *(.rela.ctors) }
|
||||
.rel.dtors : { *(.rel.dtors) }
|
||||
.rela.dtors : { *(.rela.dtors) }
|
||||
.rel.bss : { *(.rel.bss) }
|
||||
.rela.bss : { *(.rela.bss) }
|
||||
.rel.plt : { *(.rel.plt) }
|
||||
.rela.plt : { *(.rela.plt) }
|
||||
.init : { *(.init) }
|
||||
.plt : { *(.plt) }
|
||||
.text :
|
||||
{
|
||||
/* WARNING - the following is hand-optimized to fit within */
|
||||
/* the sector layout of our flash chips! XXX FIXME XXX */
|
||||
|
||||
cpu/ppc4xx/start.o (.text)
|
||||
board/sandburst/karef/init.o (.text)
|
||||
cpu/ppc4xx/kgdb.o (.text)
|
||||
cpu/ppc4xx/traps.o (.text)
|
||||
cpu/ppc4xx/interrupts.o (.text)
|
||||
cpu/ppc4xx/serial.o (.text)
|
||||
cpu/ppc4xx/cpu_init.o (.text)
|
||||
cpu/ppc4xx/speed.o (.text)
|
||||
cpu/ppc4xx/440gx_enet.o (.text)
|
||||
common/dlmalloc.o (.text)
|
||||
lib_generic/crc32.o (.text)
|
||||
lib_ppc/extable.o (.text)
|
||||
lib_generic/zlib.o (.text)
|
||||
|
||||
/* common/environment.o(.text) */
|
||||
|
||||
*(.text)
|
||||
*(.fixup)
|
||||
*(.got1)
|
||||
}
|
||||
_etext = .;
|
||||
PROVIDE (etext = .);
|
||||
.rodata :
|
||||
{
|
||||
*(.rodata)
|
||||
*(.rodata1)
|
||||
*(.rodata.str1.4)
|
||||
}
|
||||
.fini : { *(.fini) } =0
|
||||
.ctors : { *(.ctors) }
|
||||
.dtors : { *(.dtors) }
|
||||
|
||||
/* Read-write section, merged into data segment: */
|
||||
. = (. + 0x0FFF) & 0xFFFFF000;
|
||||
_erotext = .;
|
||||
PROVIDE (erotext = .);
|
||||
.reloc :
|
||||
{
|
||||
*(.got)
|
||||
_GOT2_TABLE_ = .;
|
||||
*(.got2)
|
||||
_FIXUP_TABLE_ = .;
|
||||
*(.fixup)
|
||||
}
|
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
|
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data)
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata2)
|
||||
*(.dynamic)
|
||||
CONSTRUCTORS
|
||||
}
|
||||
_edata = .;
|
||||
PROVIDE (edata = .);
|
||||
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
|
||||
__start___ex_table = .;
|
||||
__ex_table : { *(__ex_table) }
|
||||
__stop___ex_table = .;
|
||||
|
||||
. = ALIGN(256);
|
||||
__init_begin = .;
|
||||
.text.init : { *(.text.init) }
|
||||
.data.init : { *(.data.init) }
|
||||
. = ALIGN(256);
|
||||
__init_end = .;
|
||||
|
||||
__bss_start = .;
|
||||
.bss :
|
||||
{
|
||||
*(.sbss) *(.scommon)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(COMMON)
|
||||
}
|
||||
_end = . ;
|
||||
PROVIDE (end = .);
|
||||
}
|
||||
|
|
@ -0,0 +1,57 @@
|
|||
#
|
||||
# (C) Copyright 2005
|
||||
# Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
# TBS: add for debugging purposes
|
||||
BUILDUSER := $(shell whoami)
|
||||
FORCEBUILD := $(shell rm -f $(LIB) $(BOARD).o)
|
||||
|
||||
CFLAGS += -DBUILDUSER='"$(BUILDUSER)"'
|
||||
# TBS: end debugging
|
||||
|
||||
|
||||
LIB = lib$(BOARD).a
|
||||
|
||||
OBJS = $(BOARD).o ../common/flash.o ../common/ppc440gx_i2c.o \
|
||||
../common/sb_common.o
|
||||
SOBJS = init.o
|
||||
|
||||
|
||||
$(LIB): $(OBJS) $(SOBJS)
|
||||
$(AR) crv $@ $(OBJS)
|
||||
|
||||
clean:
|
||||
rm -f $(SOBJS) $(OBJS)
|
||||
|
||||
distclean: clean
|
||||
rm -f $(LIB) core *.bak .depend *~
|
||||
|
||||
#########################################################################
|
||||
|
||||
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
|
||||
$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
|
||||
|
||||
sinclude .depend
|
||||
|
||||
#########################################################################
|
||||
|
|
@ -0,0 +1,38 @@
|
|||
#
|
||||
# (C) Copyright 2005
|
||||
# Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
ifeq ($(ramsym),1)
|
||||
TEXT_BASE = 0x07FD0000
|
||||
else
|
||||
TEXT_BASE = 0xFFF80000
|
||||
endif
|
||||
|
||||
PLATFORM_CPPFLAGS += -DCONFIG_440=1
|
||||
|
||||
ifeq ($(debug),1)
|
||||
PLATFORM_CPPFLAGS += -DDEBUG
|
||||
endif
|
||||
|
||||
ifeq ($(dbcr),1)
|
||||
PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
|
||||
endif
|
||||
|
|
@ -0,0 +1,553 @@
|
|||
/* ****************************************************************
|
||||
* Common defs for reg spec for chip xc
|
||||
* Auto-generated by trex2: DO NOT HAND-EDIT!!
|
||||
* ****************************************************************
|
||||
*/
|
||||
|
||||
#ifndef HAL_XC_AUTO_H
|
||||
#define HAL_XC_AUTO_H
|
||||
|
||||
/* ----------------------------------------------------------------
|
||||
* For block: 'xcvr_cntl'
|
||||
*/
|
||||
|
||||
/* ---- Block instance addressing (for block-select) */
|
||||
#define XCVR_CNTL_BLOCK_ADDR_BIT_L 6
|
||||
#define XCVR_CNTL_BLOCK_ADDR_BIT_H 9
|
||||
#define XCVR_CNTL_BLOCK_ADDR_WIDTH 4
|
||||
|
||||
#define XCVR_CNTL_ADDR 0x0
|
||||
|
||||
/* ---- Reg addressing (within block) */
|
||||
#define XCVR_CNTL_REG_ADDR_BIT_L 2
|
||||
#define XCVR_CNTL_REG_ADDR_BIT_H 5
|
||||
#define XCVR_CNTL_REG_ADDR_WIDTH 4
|
||||
|
||||
|
||||
/* ================================================================
|
||||
* ---- Register XC_XCVR_CNTL_REVISION */
|
||||
#define SAND_HAL_XC_XCVR_CNTL_REVISION_OFFSET 0x000
|
||||
#ifndef SAND_HAL_XC_XCVR_CNTL_REVISION_NO_TEST_MASK
|
||||
#define SAND_HAL_XC_XCVR_CNTL_REVISION_NO_TEST_MASK 0x000
|
||||
#endif
|
||||
#define SAND_HAL_XC_XCVR_CNTL_REVISION_MASK 0xffffffff
|
||||
#define SAND_HAL_XC_XCVR_CNTL_REVISION_MSB 31
|
||||
#define SAND_HAL_XC_XCVR_CNTL_REVISION_LSB 0
|
||||
|
||||
/* ================================================================
|
||||
* ---- Register XC_XCVR_CNTL_RESET */
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_OFFSET 0x004
|
||||
#ifndef SAND_HAL_XC_XCVR_CNTL_RESET_NO_TEST_MASK
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_NO_TEST_MASK 0x000
|
||||
#endif
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_MASK 0xffffffff
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_MSB 31
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_LSB 0
|
||||
|
||||
/* ================================================================
|
||||
* ---- Register XC_XCVR_CNTL_STATUS */
|
||||
#define SAND_HAL_XC_XCVR_CNTL_STATUS_OFFSET 0x008
|
||||
#ifndef SAND_HAL_XC_XCVR_CNTL_STATUS_NO_TEST_MASK
|
||||
#define SAND_HAL_XC_XCVR_CNTL_STATUS_NO_TEST_MASK 0x000
|
||||
#endif
|
||||
#define SAND_HAL_XC_XCVR_CNTL_STATUS_MASK 0xffffffff
|
||||
#define SAND_HAL_XC_XCVR_CNTL_STATUS_MSB 31
|
||||
#define SAND_HAL_XC_XCVR_CNTL_STATUS_LSB 0
|
||||
|
||||
/* ================================================================
|
||||
* ---- Register XC_XCVR_CNTL_CNTL */
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_OFFSET 0x01c
|
||||
#ifndef SAND_HAL_XC_XCVR_CNTL_CNTL_NO_TEST_MASK
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_NO_TEST_MASK 0x000
|
||||
#endif
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_MASK 0xffffffff
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_MSB 31
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_LSB 0
|
||||
|
||||
/* ================================================================
|
||||
* ---- Register XC_XCVR_CNTL_BRD_INFO */
|
||||
#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_OFFSET 0x020
|
||||
#ifndef SAND_HAL_XC_XCVR_CNTL_BRD_INFO_NO_TEST_MASK
|
||||
#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_NO_TEST_MASK 0x000
|
||||
#endif
|
||||
#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_MASK 0xffffffff
|
||||
#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_MSB 31
|
||||
#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_LSB 0
|
||||
|
||||
/* ================================================================
|
||||
* ---- Register XC_XCVR_CNTL_MAC_FLOW_CTL */
|
||||
#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_OFFSET 0x024
|
||||
#ifndef SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_NO_TEST_MASK
|
||||
#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_NO_TEST_MASK 0x000
|
||||
#endif
|
||||
#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MASK 0xffffffff
|
||||
#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MSB 31
|
||||
#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_LSB 0
|
||||
|
||||
/* ================================================================
|
||||
* ---- Register XC_XCVR_CNTL_INTERRUPT */
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OFFSET 0x00c
|
||||
#ifndef SAND_HAL_XC_XCVR_CNTL_INTERRUPT_NO_TEST_MASK
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_NO_TEST_MASK 0x000
|
||||
#endif
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK 0xffffffff
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MSB 31
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_LSB 0
|
||||
|
||||
/* ================================================================
|
||||
* ---- Register XC_XCVR_CNTL_INTERRUPT_MASK */
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OFFSET 0x010
|
||||
#ifndef SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_NO_TEST_MASK
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_NO_TEST_MASK 0x000
|
||||
#endif
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MASK 0xffffffff
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MSB 31
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_LSB 0
|
||||
|
||||
/* ================================================================
|
||||
* ---- Register XC_XCVR_CNTL_SCRATCH */
|
||||
#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_OFFSET 0x014
|
||||
#ifndef SAND_HAL_XC_XCVR_CNTL_SCRATCH_NO_TEST_MASK
|
||||
#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_NO_TEST_MASK 0x000
|
||||
#endif
|
||||
#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK 0xffffffff
|
||||
#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MSB 31
|
||||
#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_LSB 0
|
||||
|
||||
/* ================================================================
|
||||
* ---- Register XC_XCVR_CNTL_SCRATCH_MASK */
|
||||
#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_OFFSET 0x018
|
||||
#ifndef SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_NO_TEST_MASK
|
||||
#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_NO_TEST_MASK 0x000
|
||||
#endif
|
||||
#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_MASK 0xffffffff
|
||||
#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_MSB 31
|
||||
#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_LSB 0
|
||||
|
||||
/* ================================================================
|
||||
* Field info for register XC_XCVR_CNTL_REVISION */
|
||||
#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_MASK 0x0000ff00
|
||||
#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_SHIFT 8
|
||||
#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_MSB 15
|
||||
#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_LSB 8
|
||||
#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_DEFAULT 0x00000000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK 0x000000ff
|
||||
#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT 0
|
||||
#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MSB 7
|
||||
#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_LSB 0
|
||||
#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_DEFAULT 0x00000000
|
||||
|
||||
/* ================================================================
|
||||
* Field info for register XC_XCVR_CNTL_RESET */
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_MASK 0x00020000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_SHIFT 17
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_MSB 17
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_LSB 17
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_MASK 0x00010000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_SHIFT 16
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_MSB 16
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_LSB 16
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_MASK 0x00008000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_SHIFT 15
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_MSB 15
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_LSB 15
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_MASK 0x00004000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_SHIFT 14
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_MSB 14
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_LSB 14
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_MASK 0x00002000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_SHIFT 13
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_MSB 13
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_LSB 13
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK 0x00001000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_SHIFT 12
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MSB 12
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_LSB 12
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_MASK 0x00000800
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_SHIFT 11
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_MSB 11
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_LSB 11
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_MASK 0x00000400
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_SHIFT 10
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_MSB 10
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_LSB 10
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_MASK 0x00000200
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_SHIFT 9
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_MSB 9
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_LSB 9
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_MASK 0x00000100
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_SHIFT 8
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_MSB 8
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_LSB 8
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_MASK 0x00000080
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_SHIFT 7
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_MSB 7
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_LSB 7
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_MASK 0x00000040
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_SHIFT 6
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_MSB 6
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_LSB 6
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_MASK 0x00000020
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_SHIFT 5
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_MSB 5
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_LSB 5
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_MASK 0x00000010
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_SHIFT 4
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_MSB 4
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_LSB 4
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_MASK 0x00000008
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_SHIFT 3
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_MSB 3
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_LSB 3
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_MASK 0x00000004
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_SHIFT 2
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_MSB 2
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_LSB 2
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_MASK 0x00000002
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_SHIFT 1
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_MSB 1
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_LSB 1
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_MASK 0x00000001
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_SHIFT 0
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_MSB 0
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_LSB 0
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_DEFAULT 0x00000000
|
||||
|
||||
/* ================================================================
|
||||
* Field info for register XC_XCVR_CNTL_STATUS */
|
||||
#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_MASK 0x00000004
|
||||
#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_SHIFT 2
|
||||
#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_MSB 2
|
||||
#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_LSB 2
|
||||
#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_MASK 0x00000002
|
||||
#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_SHIFT 1
|
||||
#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_MSB 1
|
||||
#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_LSB 1
|
||||
#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_MASK 0x00000001
|
||||
#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_SHIFT 0
|
||||
#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_MSB 0
|
||||
#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_LSB 0
|
||||
#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_DEFAULT 0x00000000
|
||||
|
||||
/* ================================================================
|
||||
* Field info for register XC_XCVR_CNTL_CNTL */
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_MASK 0x00000400
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_SHIFT 10
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_MSB 10
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_LSB 10
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_DEFAULT 0x00000000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_MASK 0x00000300
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_SHIFT 8
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_MSB 9
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_LSB 8
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_DEFAULT 0x00000000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_MASK 0x000000c0
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_SHIFT 6
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_MSB 7
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_LSB 6
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_DEFAULT 0x00000000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_MASK 0x00000030
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_SHIFT 4
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_MSB 5
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_LSB 4
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_DEFAULT 0x00000000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_MASK 0x0000000c
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_SHIFT 2
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_MSB 3
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_LSB 2
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_DEFAULT 0x00000000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_MASK 0x00000002
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_SHIFT 1
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_MSB 1
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_LSB 1
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_DEFAULT 0x00000001
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_MASK 0x00000001
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_SHIFT 0
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_MSB 0
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_LSB 0
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_DEFAULT 0x00000001
|
||||
|
||||
/* ================================================================
|
||||
* Field info for register XC_XCVR_CNTL_BRD_INFO */
|
||||
#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_MASK 0x000000f0
|
||||
#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_SHIFT 4
|
||||
#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_MSB 7
|
||||
#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_LSB 4
|
||||
#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_DEFAULT 0x00000000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_MASK 0x00000003
|
||||
#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_SHIFT 0
|
||||
#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_MSB 1
|
||||
#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_LSB 0
|
||||
#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_DEFAULT 0x00000000
|
||||
|
||||
/* ================================================================
|
||||
* Field info for register XC_XCVR_CNTL_MAC_FLOW_CTL */
|
||||
#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_MASK 0x00001000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_SHIFT 12
|
||||
#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_MSB 12
|
||||
#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_LSB 12
|
||||
#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_DEFAULT 0x00000000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_MASK 0x00000f00
|
||||
#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_SHIFT 8
|
||||
#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_MSB 11
|
||||
#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_LSB 8
|
||||
#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_DEFAULT 0x00000000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_MASK 0x00000010
|
||||
#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_SHIFT 4
|
||||
#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_MSB 4
|
||||
#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_LSB 4
|
||||
#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_DEFAULT 0x00000000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_MASK 0x0000000f
|
||||
#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_SHIFT 0
|
||||
#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_MSB 3
|
||||
#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_LSB 0
|
||||
#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_DEFAULT 0x00000000
|
||||
|
||||
/* ================================================================
|
||||
* Field info for register XC_XCVR_CNTL_INTERRUPT */
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_MASK 0x00002000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_SHIFT 13
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_MSB 13
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_LSB 13
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_DEFAULT 0x00000000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_MASK 0x00001000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_SHIFT 12
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_MSB 12
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_LSB 12
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_DEFAULT 0x00000000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_MASK 0x00000800
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_SHIFT 11
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_MSB 11
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_LSB 11
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_MASK 0x00000400
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_SHIFT 10
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_MSB 10
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_LSB 10
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_MASK 0x00000200
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_SHIFT 9
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_MSB 9
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_LSB 9
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_DEFAULT 0x00000000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_MASK 0x00000100
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_SHIFT 8
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_MSB 8
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_LSB 8
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_DEFAULT 0x00000000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_MASK 0x00000080
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_SHIFT 7
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_MSB 7
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_LSB 7
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_MASK 0x00000040
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_SHIFT 6
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_MSB 6
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_LSB 6
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_MASK 0x00000020
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_SHIFT 5
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_MSB 5
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_LSB 5
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_DEFAULT 0x00000000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_MASK 0x00000010
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_SHIFT 4
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_MSB 4
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_LSB 4
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_DEFAULT 0x00000000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_MASK 0x00000008
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_SHIFT 3
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_MSB 3
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_LSB 3
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_DEFAULT 0x00000000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_MASK 0x00000004
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_SHIFT 2
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_MSB 2
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_LSB 2
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_DEFAULT 0x00000000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_MASK 0x00000002
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_SHIFT 1
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_MSB 1
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_LSB 1
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_MASK 0x00000001
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_SHIFT 0
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_MSB 0
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_LSB 0
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_DEFAULT 0x00000000
|
||||
|
||||
/* ================================================================
|
||||
* Field info for register XC_XCVR_CNTL_INTERRUPT_MASK */
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_MASK 0x00002000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_SHIFT 13
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_MSB 13
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_LSB 13
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_DEFAULT 0x00000001
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_MASK 0x00001000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_SHIFT 12
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_MSB 12
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_LSB 12
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_DEFAULT 0x00000001
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_MASK 0x00000800
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_SHIFT 11
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_MSB 11
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_LSB 11
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_DEFAULT 0x00000001
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_MASK 0x00000400
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_SHIFT 10
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_MSB 10
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_LSB 10
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_DEFAULT 0x00000001
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_MASK 0x00000200
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_SHIFT 9
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_MSB 9
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_LSB 9
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_DEFAULT 0x00000001
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_MASK 0x00000100
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_SHIFT 8
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_MSB 8
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_LSB 8
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_DEFAULT 0x00000001
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_MASK 0x00000080
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_SHIFT 7
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_MSB 7
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_LSB 7
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_DEFAULT 0x00000001
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_MASK 0x00000040
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_SHIFT 6
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_MSB 6
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_LSB 6
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_DEFAULT 0x00000001
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_MASK 0x00000020
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_SHIFT 5
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_MSB 5
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_LSB 5
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_DEFAULT 0x00000001
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_MASK 0x00000010
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_SHIFT 4
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_MSB 4
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_LSB 4
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_DEFAULT 0x00000001
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_MASK 0x00000008
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_SHIFT 3
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_MSB 3
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_LSB 3
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_DEFAULT 0x00000001
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_MASK 0x00000004
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_SHIFT 2
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_MSB 2
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_LSB 2
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_DEFAULT 0x00000001
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_MASK 0x00000002
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_SHIFT 1
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_MSB 1
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_LSB 1
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_DEFAULT 0x00000001
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_MASK 0x00000001
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_SHIFT 0
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_MSB 0
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_LSB 0
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_DEFAULT 0x00000001
|
||||
|
||||
/* ================================================================
|
||||
* Field info for register XC_XCVR_CNTL_SCRATCH */
|
||||
#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_MASK 0xffffffff
|
||||
#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_SHIFT 0
|
||||
#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_MSB 31
|
||||
#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_LSB 0
|
||||
#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_DEFAULT 0x00000000
|
||||
|
||||
/* ================================================================
|
||||
* Field info for register XC_XCVR_CNTL_SCRATCH_MASK */
|
||||
#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_MASK 0xffffffff
|
||||
#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_SHIFT 0
|
||||
#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_MSB 31
|
||||
#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_LSB 0
|
||||
#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_DEFAULT 0xffffffff
|
||||
|
||||
#endif /* matches #ifndef HAL_XC_AUTO_H */
|
||||
|
|
@ -0,0 +1,99 @@
|
|||
/*
|
||||
* Copyright (C) 2005
|
||||
* Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <ppc_asm.tmpl>
|
||||
#include <config.h>
|
||||
|
||||
/* General */
|
||||
#define TLB_VALID 0x00000200
|
||||
|
||||
/* Supported page sizes */
|
||||
|
||||
#define SZ_1K 0x00000000
|
||||
#define SZ_4K 0x00000010
|
||||
#define SZ_16K 0x00000020
|
||||
#define SZ_64K 0x00000030
|
||||
#define SZ_256K 0x00000040
|
||||
#define SZ_1M 0x00000050
|
||||
#define SZ_16M 0x00000070
|
||||
#define SZ_256M 0x00000090
|
||||
|
||||
/* Storage attributes */
|
||||
#define SA_W 0x00000800 /* Write-through */
|
||||
#define SA_I 0x00000400 /* Caching inhibited */
|
||||
#define SA_M 0x00000200 /* Memory coherence */
|
||||
#define SA_G 0x00000100 /* Guarded */
|
||||
#define SA_E 0x00000080 /* Endian */
|
||||
|
||||
/* Access control */
|
||||
#define AC_X 0x00000024 /* Execute */
|
||||
#define AC_W 0x00000012 /* Write */
|
||||
#define AC_R 0x00000009 /* Read */
|
||||
|
||||
/* Some handy macros */
|
||||
|
||||
#define EPN(e) ((e) & 0xfffffc00)
|
||||
#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) )
|
||||
#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
|
||||
#define TLB2(a) ( (a)&0x00000fbf )
|
||||
|
||||
#define tlbtab_start\
|
||||
mflr r1 ;\
|
||||
bl 0f ;
|
||||
|
||||
#define tlbtab_end\
|
||||
.long 0, 0, 0 ; \
|
||||
0: mflr r0 ; \
|
||||
mtlr r1 ; \
|
||||
blr ;
|
||||
|
||||
#define tlbentry(epn,sz,rpn,erpn,attr)\
|
||||
.long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
|
||||
|
||||
|
||||
/**************************************************************************
|
||||
* TLB TABLE
|
||||
*
|
||||
* This table is used by the cpu boot code to setup the initial tlb
|
||||
* entries. Rather than make broad assumptions in the cpu source tree,
|
||||
* this table lets each board set things up however they like.
|
||||
*
|
||||
* Pointer to the table is returned in r1
|
||||
*
|
||||
*************************************************************************/
|
||||
|
||||
.section .bootpg,"ax"
|
||||
.globl tlbtab
|
||||
|
||||
tlbtab:
|
||||
tlbtab_start
|
||||
tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
|
||||
tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
|
||||
tlbentry( CFG_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
|
||||
tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
tlbentry( CFG_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
tlbentry( CFG_SDRAM_BASE+0x20000000, SZ_256M, 0x20000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
tlbentry( CFG_SDRAM_BASE+0x30000000, SZ_256M, 0x30000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
|
||||
tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I )
|
||||
tlbtab_end
|
||||
|
|
@ -0,0 +1,570 @@
|
|||
/*
|
||||
* Copyright (c) 2005
|
||||
* Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
#include <config.h>
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include "metrobox.h"
|
||||
#include "metrobox_version.h"
|
||||
#include <asm/processor.h>
|
||||
#include <asm/io.h>
|
||||
#include <spd_sdram.h>
|
||||
#include <i2c.h>
|
||||
#include "../common/ppc440gx_i2c.h"
|
||||
#include "../common/sb_common.h"
|
||||
|
||||
|
||||
|
||||
void fpga_init (void);
|
||||
|
||||
METROBOX_BOARD_ID_ST board_id_as[] =
|
||||
{ {"Undefined"}, /* Not specified */
|
||||
{"2x10Gb"}, /* 2 ports, 10 GbE */
|
||||
{"20x1Gb"}, /* 20 ports, 1 GbE */
|
||||
{"Reserved"}, /* Reserved for future use */
|
||||
};
|
||||
|
||||
|
||||
/*************************************************************************
|
||||
* board_early_init_f
|
||||
*
|
||||
* Setup chip selects, initialize the Opto-FPGA, initialize
|
||||
* interrupt polarity and triggers.
|
||||
*
|
||||
************************************************************************/
|
||||
int board_early_init_f (void)
|
||||
{
|
||||
ppc440_gpio_regs_t *gpio_regs;
|
||||
|
||||
/* Enable GPIO interrupts */
|
||||
mtsdr(sdr_pfc0, 0x00103E00);
|
||||
|
||||
/* Setup access for LEDs, and system topology info */
|
||||
gpio_regs = (ppc440_gpio_regs_t *)CFG_GPIO_BASE;
|
||||
gpio_regs->open_drain = SBCOMMON_GPIO_SYS_LEDS;
|
||||
gpio_regs->tri_state = SBCOMMON_GPIO_DBGLEDS;
|
||||
|
||||
/* Turn on all the leds for now */
|
||||
gpio_regs->out = SBCOMMON_GPIO_LEDS;
|
||||
|
||||
/*--------------------------------------------------------------------+
|
||||
| Initialize EBC CONFIG
|
||||
+-------------------------------------------------------------------*/
|
||||
mtebc(xbcfg,
|
||||
EBC_CFG_LE_UNLOCK | EBC_CFG_PTD_ENABLE |
|
||||
EBC_CFG_RTC_64PERCLK | EBC_CFG_ATC_PREVIOUS |
|
||||
EBC_CFG_DTC_PREVIOUS | EBC_CFG_CTC_PREVIOUS |
|
||||
EBC_CFG_EMC_DEFAULT | EBC_CFG_PME_DISABLE |
|
||||
EBC_CFG_PR_32);
|
||||
|
||||
/*--------------------------------------------------------------------+
|
||||
| 1/2 MB FLASH. Initialize bank 0 with default values.
|
||||
+-------------------------------------------------------------------*/
|
||||
mtebc(pb0ap,
|
||||
EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
|
||||
EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
|
||||
EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
|
||||
EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) |
|
||||
EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
|
||||
EBC_BXAP_PEN_DISABLED);
|
||||
|
||||
mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(CFG_FLASH_BASE) |
|
||||
EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
|
||||
/*--------------------------------------------------------------------+
|
||||
| 8KB NVRAM/RTC. Initialize bank 1 with default values.
|
||||
+-------------------------------------------------------------------*/
|
||||
mtebc(pb1ap,
|
||||
EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(10) |
|
||||
EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
|
||||
EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
|
||||
EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) |
|
||||
EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
|
||||
EBC_BXAP_PEN_DISABLED);
|
||||
|
||||
mtebc(pb1cr, EBC_BXCR_BAS_ENCODE(0x48000000) |
|
||||
EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
|
||||
|
||||
/*--------------------------------------------------------------------+
|
||||
| Compact Flash, uses 2 Chip Selects (2 & 6)
|
||||
+-------------------------------------------------------------------*/
|
||||
mtebc(pb2ap,
|
||||
EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
|
||||
EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
|
||||
EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
|
||||
EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) |
|
||||
EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
|
||||
EBC_BXAP_PEN_DISABLED);
|
||||
|
||||
mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(0xF0000000) |
|
||||
EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
|
||||
|
||||
/*--------------------------------------------------------------------+
|
||||
| OPTO & OFEM FPGA. Initialize bank 3 with default values.
|
||||
+-------------------------------------------------------------------*/
|
||||
mtebc(pb3ap,
|
||||
EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
|
||||
EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
|
||||
EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
|
||||
EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
|
||||
EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
|
||||
|
||||
mtebc(pb3cr, EBC_BXCR_BAS_ENCODE(0x48200000) |
|
||||
EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
|
||||
|
||||
/*--------------------------------------------------------------------+
|
||||
| MAC A for metrobox
|
||||
| MAC A & B for Kamino. OFEM FPGA decodes the addresses
|
||||
| Initialize bank 4 with default values.
|
||||
+-------------------------------------------------------------------*/
|
||||
mtebc(pb4ap,
|
||||
EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
|
||||
EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
|
||||
EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
|
||||
EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
|
||||
EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
|
||||
|
||||
mtebc(pb4cr, EBC_BXCR_BAS_ENCODE(0x48600000) |
|
||||
EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
|
||||
|
||||
/*--------------------------------------------------------------------+
|
||||
| Metrobox MAC B Initialize bank 5 with default values.
|
||||
| KA REF FPGA Initialize bank 5 with default values.
|
||||
+-------------------------------------------------------------------*/
|
||||
mtebc(pb5ap,
|
||||
EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
|
||||
EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
|
||||
EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
|
||||
EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
|
||||
EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
|
||||
|
||||
mtebc(pb5cr, EBC_BXCR_BAS_ENCODE(0x48700000) |
|
||||
EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
|
||||
|
||||
/*--------------------------------------------------------------------+
|
||||
| Compact Flash, uses 2 Chip Selects (2 & 6)
|
||||
+-------------------------------------------------------------------*/
|
||||
mtebc(pb6ap,
|
||||
EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
|
||||
EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
|
||||
EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
|
||||
EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) |
|
||||
EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
|
||||
EBC_BXAP_PEN_DISABLED);
|
||||
|
||||
mtebc(pb6cr, EBC_BXCR_BAS_ENCODE(0xF0100000) |
|
||||
EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
|
||||
|
||||
/*--------------------------------------------------------------------+
|
||||
| BME-32. Initialize bank 7 with default values.
|
||||
+-------------------------------------------------------------------*/
|
||||
mtebc(pb7ap,
|
||||
EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
|
||||
EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
|
||||
EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
|
||||
EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
|
||||
EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
|
||||
|
||||
mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48500000) |
|
||||
EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
|
||||
|
||||
|
||||
/*--------------------------------------------------------------------+
|
||||
* Setup the interrupt controller polarities, triggers, etc.
|
||||
+-------------------------------------------------------------------*/
|
||||
mtdcr (uic0sr, 0xffffffff); /* clear all */
|
||||
mtdcr (uic0er, 0x00000000); /* disable all */
|
||||
mtdcr (uic0cr, 0x00000000); /* all non- critical */
|
||||
mtdcr (uic0pr, 0xfffffe03); /* polarity */
|
||||
mtdcr (uic0tr, 0x01c00000); /* trigger edge vs level */
|
||||
mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */
|
||||
mtdcr (uic0sr, 0xffffffff); /* clear all */
|
||||
|
||||
mtdcr (uic1sr, 0xffffffff); /* clear all */
|
||||
mtdcr (uic1er, 0x00000000); /* disable all */
|
||||
mtdcr (uic1cr, 0x00000000); /* all non-critical */
|
||||
mtdcr (uic1pr, 0xffffc8ff); /* polarity */
|
||||
mtdcr (uic1tr, 0x00ff0000); /* trigger edge vs level */
|
||||
mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */
|
||||
mtdcr (uic1sr, 0xffffffff); /* clear all */
|
||||
|
||||
mtdcr (uic2sr, 0xffffffff); /* clear all */
|
||||
mtdcr (uic2er, 0x00000000); /* disable all */
|
||||
mtdcr (uic2cr, 0x00000000); /* all non-critical */
|
||||
mtdcr (uic2pr, 0xffff83ff); /* polarity */
|
||||
mtdcr (uic2tr, 0x00ff8c0f); /* trigger edge vs level */
|
||||
mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */
|
||||
mtdcr (uic2sr, 0xffffffff); /* clear all */
|
||||
|
||||
mtdcr (uicb0sr, 0xfc000000); /* clear all */
|
||||
mtdcr (uicb0er, 0x00000000); /* disable all */
|
||||
mtdcr (uicb0cr, 0x00000000); /* all non-critical */
|
||||
mtdcr (uicb0pr, 0xfc000000);
|
||||
mtdcr (uicb0tr, 0x00000000);
|
||||
mtdcr (uicb0vr, 0x00000001);
|
||||
|
||||
fpga_init();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
/*************************************************************************
|
||||
* checkboard
|
||||
*
|
||||
* Dump pertinent info to the console
|
||||
*
|
||||
************************************************************************/
|
||||
int checkboard (void)
|
||||
{
|
||||
sys_info_t sysinfo;
|
||||
unsigned char brd_rev, brd_id;
|
||||
unsigned short sernum;
|
||||
unsigned char opto_rev, opto_id;
|
||||
OPTO_FPGA_REGS_ST *opto_ps;
|
||||
|
||||
opto_ps = (OPTO_FPGA_REGS_ST *)CFG_FPGA_BASE;
|
||||
|
||||
opto_rev = (unsigned char)((opto_ps->revision_ul &
|
||||
SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK)
|
||||
>> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT);
|
||||
|
||||
opto_id = (unsigned char)((opto_ps->revision_ul &
|
||||
SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_MASK)
|
||||
>> SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_SHIFT);
|
||||
|
||||
brd_rev = (unsigned char)((opto_ps->boardinfo_ul &
|
||||
SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_MASK)
|
||||
>> SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_SHIFT);
|
||||
|
||||
brd_id = (unsigned char)((opto_ps->boardinfo_ul &
|
||||
SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_MASK)
|
||||
>> SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_SHIFT);
|
||||
|
||||
get_sys_info (&sysinfo);
|
||||
|
||||
sernum = sbcommon_get_serial_number();
|
||||
printf ("Board: Sandburst Corporation MetroBox Serial Number: %d\n", sernum);
|
||||
printf ("%s\n", METROBOX_U_BOOT_REL_STR);
|
||||
|
||||
printf ("Built %s %s by %s\n", __DATE__, __TIME__, BUILDUSER);
|
||||
if (sbcommon_get_master()) {
|
||||
printf("Slot 0 - Master\nSlave board");
|
||||
if (sbcommon_secondary_present())
|
||||
printf(" present\n");
|
||||
else
|
||||
printf(" not detected\n");
|
||||
} else {
|
||||
printf("Slot 1 - Slave\n\n");
|
||||
}
|
||||
|
||||
printf ("OptoFPGA ID:\t0x%02X\tRev: 0x%02X\n", opto_id, opto_rev);
|
||||
printf ("Board Rev:\t0x%02X\tID: %s\n", brd_rev, board_id_as[brd_id]);
|
||||
|
||||
printf ("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
|
||||
printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
|
||||
printf ("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
|
||||
printf ("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
|
||||
printf ("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000);
|
||||
|
||||
|
||||
/* Fix the ack in the bme 32 */
|
||||
udelay(5000);
|
||||
out32(CFG_BME32_BASE + 0x0000000C, 0x00000001);
|
||||
asm("eieio");
|
||||
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
|
||||
/*************************************************************************
|
||||
* misc_init_f
|
||||
*
|
||||
* Initialize I2C bus one to gain access to the fans
|
||||
*
|
||||
************************************************************************/
|
||||
int misc_init_f (void)
|
||||
{
|
||||
/* Turn on i2c bus 1 */
|
||||
puts ("I2C1: ");
|
||||
i2c1_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
|
||||
puts ("ready\n");
|
||||
|
||||
/* Turn on fans */
|
||||
sbcommon_fans();
|
||||
|
||||
return (0);
|
||||
}
|
||||
/*************************************************************************
|
||||
* misc_init_r
|
||||
*
|
||||
* Do nothing.
|
||||
*
|
||||
************************************************************************/
|
||||
int misc_init_r (void)
|
||||
{
|
||||
unsigned short sernum;
|
||||
char envstr[255];
|
||||
unsigned char opto_rev;
|
||||
OPTO_FPGA_REGS_ST *opto_ps;
|
||||
|
||||
opto_ps = (OPTO_FPGA_REGS_ST *)CFG_FPGA_BASE;
|
||||
|
||||
if(NULL != getenv("secondserial")) {
|
||||
puts("secondserial is set, switching to second serial port\n");
|
||||
setenv("stderr", "serial1");
|
||||
setenv("stdout", "serial1");
|
||||
setenv("stdin", "serial1");
|
||||
}
|
||||
|
||||
setenv("ubrelver", METROBOX_U_BOOT_REL_STR);
|
||||
|
||||
memset(envstr, 0, 255);
|
||||
sprintf (envstr, "Built %s %s by %s", __DATE__, __TIME__, BUILDUSER);
|
||||
setenv("bldstr", envstr);
|
||||
saveenv();
|
||||
|
||||
if( getenv("autorecover")) {
|
||||
setenv("autorecover", NULL);
|
||||
saveenv();
|
||||
sernum = sbcommon_get_serial_number();
|
||||
|
||||
printf("\nSetting up environment for automatic filesystem recovery\n");
|
||||
/*
|
||||
* Setup default bootargs
|
||||
*/
|
||||
memset(envstr, 0, 255);
|
||||
sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 "
|
||||
"rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none idebus=33",
|
||||
sernum, sernum);
|
||||
setenv("bootargs", envstr);
|
||||
|
||||
/*
|
||||
* Setup Default boot command
|
||||
*/
|
||||
setenv("bootcmd", "fatload ide 0 8000000 pimage.metrobox;"
|
||||
"fatload ide 0 8100000 pramdisk;"
|
||||
"bootm 8000000 8100000");
|
||||
|
||||
printf("Done. Please type allow the system to continue to boot\n");
|
||||
}
|
||||
|
||||
if( getenv("fakeled")) {
|
||||
setenv("bootdelay", "-1");
|
||||
saveenv();
|
||||
printf("fakeled is set. use 'setenv fakeled ; setenv bootdelay 5 ; saveenv' to recover\n");
|
||||
opto_rev = (unsigned char)((opto_ps->revision_ul &
|
||||
SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK)
|
||||
>> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT);
|
||||
|
||||
if(0x12 <= opto_rev) {
|
||||
opto_ps->control_ul &= ~ SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_MASK;
|
||||
}
|
||||
}
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*************************************************************************
|
||||
* ide_set_reset
|
||||
*
|
||||
*
|
||||
*
|
||||
************************************************************************/
|
||||
#ifdef CONFIG_IDE_RESET
|
||||
void ide_set_reset(int on)
|
||||
{
|
||||
OPTO_FPGA_REGS_ST *opto_ps;
|
||||
opto_ps = (OPTO_FPGA_REGS_ST *)CFG_FPGA_BASE;
|
||||
|
||||
if (on) { /* assert RESET */
|
||||
opto_ps->reset_ul &= ~SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK;
|
||||
} else { /* release RESET */
|
||||
opto_ps->reset_ul |= SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK;
|
||||
}
|
||||
}
|
||||
#endif /* CONFIG_IDE_RESET */
|
||||
|
||||
/*************************************************************************
|
||||
* fpga_init
|
||||
*
|
||||
*
|
||||
*
|
||||
************************************************************************/
|
||||
void fpga_init(void)
|
||||
{
|
||||
OPTO_FPGA_REGS_ST *opto_ps;
|
||||
unsigned char opto_rev;
|
||||
unsigned long tmp;
|
||||
|
||||
/* Ensure we have power all around */
|
||||
udelay(500);
|
||||
|
||||
/*
|
||||
* Take appropriate hw bits out of reset
|
||||
*/
|
||||
opto_ps = (OPTO_FPGA_REGS_ST *)CFG_FPGA_BASE;
|
||||
|
||||
tmp =
|
||||
SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_MASK |
|
||||
SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_MASK |
|
||||
SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_MASK |
|
||||
SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_MASK |
|
||||
SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK |
|
||||
SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_MASK |
|
||||
SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_MASK |
|
||||
SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_MASK |
|
||||
SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_MASK |
|
||||
SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_MASK |
|
||||
SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_MASK |
|
||||
SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_MASK |
|
||||
SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_MASK |
|
||||
SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_MASK |
|
||||
SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_MASK |
|
||||
SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_MASK |
|
||||
SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_MASK |
|
||||
SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_MASK;
|
||||
opto_ps->reset_ul = tmp;
|
||||
/*
|
||||
* Turn on the 'Slow Blink' for the System Error Led.
|
||||
* Ensure FPGA rev is up to at least rev 0x12
|
||||
*/
|
||||
opto_rev = (unsigned char)((opto_ps->revision_ul &
|
||||
SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK)
|
||||
>> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT);
|
||||
if(0x12 <= opto_rev) {
|
||||
opto_ps->control_ul |= 1 << SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_SHIFT;
|
||||
}
|
||||
|
||||
asm("eieio");
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
|
||||
int metroboxSetupVars(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
unsigned short sernum;
|
||||
char envstr[255];
|
||||
|
||||
sernum = sbcommon_get_serial_number();
|
||||
|
||||
memset(envstr, 0, 255);
|
||||
/*
|
||||
* Setup our ip address
|
||||
*/
|
||||
sprintf(envstr, "10.100.60.%d", sernum);
|
||||
|
||||
setenv("ipaddr", envstr);
|
||||
/*
|
||||
* Setup the host ip address
|
||||
*/
|
||||
setenv("serverip", "10.100.17.10");
|
||||
|
||||
/*
|
||||
* Setup default bootargs
|
||||
*/
|
||||
memset(envstr, 0, 255);
|
||||
|
||||
sprintf(envstr, "console=ttyS0,9600 root=/dev/nfs "
|
||||
"rw nfsroot=10.100.17.10:/home/metrobox/mbc%d "
|
||||
"nfsaddrs=10.100.60.%d:10.100.17.10:10.100.1.1"
|
||||
":255.255.0.0:metrobox%d.sandburst.com:eth0:none idebus=33",
|
||||
sernum, sernum, sernum);
|
||||
|
||||
setenv("bootargs_nfs", envstr);
|
||||
setenv("bootargs", envstr);
|
||||
|
||||
/*
|
||||
* Setup CF bootargs
|
||||
*/
|
||||
memset(envstr, 0, 255);
|
||||
sprintf(envstr, "console=ttyS0,9600 root=/dev/hda2 "
|
||||
"rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none idebus=33",
|
||||
sernum, sernum);
|
||||
|
||||
setenv("bootargs_cf", envstr);
|
||||
|
||||
/*
|
||||
* Setup Default boot command
|
||||
*/
|
||||
setenv("bootcmd_tftp", "tftp 8000000 pImage.metrobox;bootm 8000000");
|
||||
setenv("bootcmd", "tftp 8000000 pImage.metrobox;bootm 8000000");
|
||||
|
||||
/*
|
||||
* Setup compact flash boot command
|
||||
*/
|
||||
setenv("bootcmd_cf", "fatload ide 0 8000000 pimage.metrobox;bootm 8000000");
|
||||
|
||||
saveenv();
|
||||
|
||||
|
||||
return(1);
|
||||
}
|
||||
|
||||
|
||||
int metroboxRecover(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
unsigned short sernum;
|
||||
char envstr[255];
|
||||
|
||||
sernum = sbcommon_get_serial_number();
|
||||
|
||||
printf("\nSetting up environment for filesystem recovery\n");
|
||||
/*
|
||||
* Setup default bootargs
|
||||
*/
|
||||
memset(envstr, 0, 255);
|
||||
sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 "
|
||||
"rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none",
|
||||
sernum, sernum);
|
||||
|
||||
setenv("bootargs", envstr);
|
||||
|
||||
/*
|
||||
* Setup Default boot command
|
||||
*/
|
||||
setenv("bootcmd", "fatload ide 0 8000000 pimage.metrobox;"
|
||||
"fatload ide 0 8100000 pramdisk;"
|
||||
"bootm 8000000 8100000");
|
||||
|
||||
printf("Done. Please type boot<cr>.\nWhen the kernel has booted"
|
||||
" please type fsrecover.sh<cr>\n");
|
||||
|
||||
return(1);
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
U_BOOT_CMD(mbsetup, 1, 1, metroboxSetupVars,
|
||||
"mbsetup - Set environment to factory defaults\n", NULL);
|
||||
|
||||
U_BOOT_CMD(mbrecover, 1, 1, metroboxRecover,
|
||||
"mbrecover - Set environment to allow for fs recovery\n", NULL);
|
||||
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
#ifndef __METROBOX_H__
|
||||
#define __METROBOX_H__
|
||||
/*
|
||||
* (C) Copyright 2005
|
||||
* Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
typedef struct metrobox_board_id_s {
|
||||
const char name[40];
|
||||
} METROBOX_BOARD_ID_ST, *METROBOX_BOARD_ID_PST;
|
||||
|
||||
|
||||
/* Metrobox Opto-FPGA registers and definitions */
|
||||
#include "hal_xc_auto.h"
|
||||
typedef struct opto_fpga_regs_s
|
||||
{
|
||||
volatile unsigned long revision_ul; /* Read Only */
|
||||
volatile unsigned long reset_ul; /* Read/Write */
|
||||
volatile unsigned long status_ul; /* Read Only */
|
||||
volatile unsigned long interrupt_ul; /* Read Only */
|
||||
volatile unsigned long mask_ul; /* Read/Write */
|
||||
volatile unsigned long scratch_ul; /* Read/Write */
|
||||
volatile unsigned long scrmask_ul; /* Read/Write */
|
||||
volatile unsigned long control_ul; /* Read/Write */
|
||||
volatile unsigned long boardinfo_ul; /* Read Only */
|
||||
} OPTO_FPGA_REGS_ST __attribute__((packed)), *OPTO_FPGA_REGS_PST;
|
||||
|
||||
|
||||
|
||||
#endif /* __METROBOX_H__ */
|
||||
|
|
@ -0,0 +1,27 @@
|
|||
#ifndef _METROBOX_VERSION_H_
|
||||
#define _METROBOX_VERSION_H_
|
||||
/*
|
||||
* (C) Copyright 2005
|
||||
* Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
#define METROBOX_U_BOOT_REL_STR "Release 2.0.3"
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,156 @@
|
|||
/*
|
||||
* (C) Copyright 2005
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
* Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(powerpc)
|
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
|
||||
/* Do we need any of these for elf?
|
||||
__DYNAMIC = 0; */
|
||||
SECTIONS
|
||||
{
|
||||
.resetvec 0xFFFFFFFC :
|
||||
{
|
||||
*(.resetvec)
|
||||
} = 0xffff
|
||||
|
||||
.bootpg 0xFFFFF000 :
|
||||
{
|
||||
cpu/ppc4xx/start.o (.bootpg)
|
||||
} = 0xffff
|
||||
|
||||
/* Read-only sections, merged into text segment: */
|
||||
. = + SIZEOF_HEADERS;
|
||||
.interp : { *(.interp) }
|
||||
.hash : { *(.hash) }
|
||||
.dynsym : { *(.dynsym) }
|
||||
.dynstr : { *(.dynstr) }
|
||||
.rel.text : { *(.rel.text) }
|
||||
.rela.text : { *(.rela.text) }
|
||||
.rel.data : { *(.rel.data) }
|
||||
.rela.data : { *(.rela.data) }
|
||||
.rel.rodata : { *(.rel.rodata) }
|
||||
.rela.rodata : { *(.rela.rodata) }
|
||||
.rel.got : { *(.rel.got) }
|
||||
.rela.got : { *(.rela.got) }
|
||||
.rel.ctors : { *(.rel.ctors) }
|
||||
.rela.ctors : { *(.rela.ctors) }
|
||||
.rel.dtors : { *(.rel.dtors) }
|
||||
.rela.dtors : { *(.rela.dtors) }
|
||||
.rel.bss : { *(.rel.bss) }
|
||||
.rela.bss : { *(.rela.bss) }
|
||||
.rel.plt : { *(.rel.plt) }
|
||||
.rela.plt : { *(.rela.plt) }
|
||||
.init : { *(.init) }
|
||||
.plt : { *(.plt) }
|
||||
.text :
|
||||
{
|
||||
/* WARNING - the following is hand-optimized to fit within */
|
||||
/* the sector layout of our flash chips! XXX FIXME XXX */
|
||||
|
||||
cpu/ppc4xx/start.o (.text)
|
||||
board/sandburst/metrobox/init.o (.text)
|
||||
cpu/ppc4xx/kgdb.o (.text)
|
||||
cpu/ppc4xx/traps.o (.text)
|
||||
cpu/ppc4xx/interrupts.o (.text)
|
||||
cpu/ppc4xx/serial.o (.text)
|
||||
cpu/ppc4xx/cpu_init.o (.text)
|
||||
cpu/ppc4xx/speed.o (.text)
|
||||
cpu/ppc4xx/440gx_enet.o (.text)
|
||||
common/dlmalloc.o (.text)
|
||||
lib_generic/crc32.o (.text)
|
||||
lib_ppc/extable.o (.text)
|
||||
lib_generic/zlib.o (.text)
|
||||
|
||||
/* . = env_offset;*/
|
||||
/* common/environment.o(.text)*/
|
||||
|
||||
*(.text)
|
||||
*(.fixup)
|
||||
*(.got1)
|
||||
}
|
||||
_etext = .;
|
||||
PROVIDE (etext = .);
|
||||
.rodata :
|
||||
{
|
||||
*(.rodata)
|
||||
*(.rodata1)
|
||||
*(.rodata.str1.4)
|
||||
}
|
||||
.fini : { *(.fini) } =0
|
||||
.ctors : { *(.ctors) }
|
||||
.dtors : { *(.dtors) }
|
||||
|
||||
/* Read-write section, merged into data segment: */
|
||||
. = (. + 0x00FF) & 0xFFFFFF00;
|
||||
_erotext = .;
|
||||
PROVIDE (erotext = .);
|
||||
.reloc :
|
||||
{
|
||||
*(.got)
|
||||
_GOT2_TABLE_ = .;
|
||||
*(.got2)
|
||||
_FIXUP_TABLE_ = .;
|
||||
*(.fixup)
|
||||
}
|
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
|
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data)
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata2)
|
||||
*(.dynamic)
|
||||
CONSTRUCTORS
|
||||
}
|
||||
_edata = .;
|
||||
PROVIDE (edata = .);
|
||||
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
|
||||
__start___ex_table = .;
|
||||
__ex_table : { *(__ex_table) }
|
||||
__stop___ex_table = .;
|
||||
|
||||
. = ALIGN(256);
|
||||
__init_begin = .;
|
||||
.text.init : { *(.text.init) }
|
||||
.data.init : { *(.data.init) }
|
||||
. = ALIGN(256);
|
||||
__init_end = .;
|
||||
|
||||
__bss_start = .;
|
||||
.bss :
|
||||
{
|
||||
*(.sbss) *(.scommon)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(COMMON)
|
||||
}
|
||||
_end = . ;
|
||||
PROVIDE (end = .);
|
||||
}
|
||||
|
|
@ -0,0 +1,145 @@
|
|||
/*
|
||||
* (C) Copyright 2002-2005
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
* Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(powerpc)
|
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
|
||||
/* Do we need any of these for elf?
|
||||
__DYNAMIC = 0; */
|
||||
SECTIONS
|
||||
{
|
||||
/* Read-only sections, merged into text segment: */
|
||||
. = + SIZEOF_HEADERS;
|
||||
.interp : { *(.interp) }
|
||||
.hash : { *(.hash) }
|
||||
.dynsym : { *(.dynsym) }
|
||||
.dynstr : { *(.dynstr) }
|
||||
.rel.text : { *(.rel.text) }
|
||||
.rela.text : { *(.rela.text) }
|
||||
.rel.data : { *(.rel.data) }
|
||||
.rela.data : { *(.rela.data) }
|
||||
.rel.rodata : { *(.rel.rodata) }
|
||||
.rela.rodata : { *(.rela.rodata) }
|
||||
.rel.got : { *(.rel.got) }
|
||||
.rela.got : { *(.rela.got) }
|
||||
.rel.ctors : { *(.rel.ctors) }
|
||||
.rela.ctors : { *(.rela.ctors) }
|
||||
.rel.dtors : { *(.rel.dtors) }
|
||||
.rela.dtors : { *(.rela.dtors) }
|
||||
.rel.bss : { *(.rel.bss) }
|
||||
.rela.bss : { *(.rela.bss) }
|
||||
.rel.plt : { *(.rel.plt) }
|
||||
.rela.plt : { *(.rela.plt) }
|
||||
.init : { *(.init) }
|
||||
.plt : { *(.plt) }
|
||||
.text :
|
||||
{
|
||||
/* WARNING - the following is hand-optimized to fit within */
|
||||
/* the sector layout of our flash chips! XXX FIXME XXX */
|
||||
|
||||
cpu/ppc4xx/start.o (.text)
|
||||
board/sandburst/metrobox/init.o (.text)
|
||||
cpu/ppc4xx/kgdb.o (.text)
|
||||
cpu/ppc4xx/traps.o (.text)
|
||||
cpu/ppc4xx/interrupts.o (.text)
|
||||
cpu/ppc4xx/serial.o (.text)
|
||||
cpu/ppc4xx/cpu_init.o (.text)
|
||||
cpu/ppc4xx/speed.o (.text)
|
||||
cpu/ppc4xx/440gx_enet.o (.text)
|
||||
common/dlmalloc.o (.text)
|
||||
lib_generic/crc32.o (.text)
|
||||
lib_ppc/extable.o (.text)
|
||||
lib_generic/zlib.o (.text)
|
||||
|
||||
/* common/environment.o(.text) */
|
||||
|
||||
*(.text)
|
||||
*(.fixup)
|
||||
*(.got1)
|
||||
}
|
||||
_etext = .;
|
||||
PROVIDE (etext = .);
|
||||
.rodata :
|
||||
{
|
||||
*(.rodata)
|
||||
*(.rodata1)
|
||||
*(.rodata.str1.4)
|
||||
}
|
||||
.fini : { *(.fini) } =0
|
||||
.ctors : { *(.ctors) }
|
||||
.dtors : { *(.dtors) }
|
||||
|
||||
/* Read-write section, merged into data segment: */
|
||||
. = (. + 0x0FFF) & 0xFFFFF000;
|
||||
_erotext = .;
|
||||
PROVIDE (erotext = .);
|
||||
.reloc :
|
||||
{
|
||||
*(.got)
|
||||
_GOT2_TABLE_ = .;
|
||||
*(.got2)
|
||||
_FIXUP_TABLE_ = .;
|
||||
*(.fixup)
|
||||
}
|
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
|
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data)
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata2)
|
||||
*(.dynamic)
|
||||
CONSTRUCTORS
|
||||
}
|
||||
_edata = .;
|
||||
PROVIDE (edata = .);
|
||||
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
|
||||
__start___ex_table = .;
|
||||
__ex_table : { *(__ex_table) }
|
||||
__stop___ex_table = .;
|
||||
|
||||
. = ALIGN(256);
|
||||
__init_begin = .;
|
||||
.text.init : { *(.text.init) }
|
||||
.data.init : { *(.data.init) }
|
||||
. = ALIGN(256);
|
||||
__init_end = .;
|
||||
|
||||
__bss_start = .;
|
||||
.bss :
|
||||
{
|
||||
*(.sbss) *(.scommon)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(COMMON)
|
||||
}
|
||||
_end = . ;
|
||||
PROVIDE (end = .);
|
||||
}
|
||||
|
|
@ -269,7 +269,7 @@ int ppc_440x_eth_setup_bridge(int devnum, bd_t * bis)
|
|||
|
||||
static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
|
||||
{
|
||||
int i;
|
||||
int i, j;
|
||||
unsigned long reg;
|
||||
unsigned long msr;
|
||||
unsigned long speed;
|
||||
|
|
@ -448,7 +448,11 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
|
|||
* for RGMII mode.
|
||||
*/
|
||||
if ( ((devnum == 2) || (devnum ==3)) && (4 == ethgroup) ) {
|
||||
miiphy_write (reg, 23, 0x1200);
|
||||
#if defined(CONFIG_CIS8201_SHORT_ETCH)
|
||||
miiphy_write (reg, 23, 0x1300);
|
||||
#else
|
||||
miiphy_write (reg, 23, 0x1000);
|
||||
#endif
|
||||
/*
|
||||
* Vitesse VSC8201/Cicada CIS8201 errata:
|
||||
* Interoperability problem with Intel 82547EI phys
|
||||
|
|
@ -567,6 +571,8 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
|
|||
hw_p->alloc_tx_buf =
|
||||
(mal_desc_t *) malloc ((sizeof (mal_desc_t) * NUM_TX_BUFF) +
|
||||
((2 * CFG_CACHELINE_SIZE) - 2));
|
||||
if (NULL == hw_p->alloc_tx_buf)
|
||||
return -1;
|
||||
if (((int) hw_p->alloc_tx_buf & CACHELINE_MASK) != 0) {
|
||||
hw_p->tx =
|
||||
(mal_desc_t *) ((int) hw_p->alloc_tx_buf +
|
||||
|
|
@ -580,6 +586,12 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
|
|||
hw_p->alloc_rx_buf =
|
||||
(mal_desc_t *) malloc ((sizeof (mal_desc_t) * NUM_RX_BUFF) +
|
||||
((2 * CFG_CACHELINE_SIZE) - 2));
|
||||
if (NULL == hw_p->alloc_rx_buf) {
|
||||
free(hw_p->alloc_tx_buf);
|
||||
hw_p->alloc_tx_buf = NULL;
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (((int) hw_p->alloc_rx_buf & CACHELINE_MASK) != 0) {
|
||||
hw_p->rx =
|
||||
(mal_desc_t *) ((int) hw_p->alloc_rx_buf +
|
||||
|
|
@ -593,9 +605,20 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
|
|||
for (i = 0; i < NUM_TX_BUFF; i++) {
|
||||
hw_p->tx[i].ctrl = 0;
|
||||
hw_p->tx[i].data_len = 0;
|
||||
if (hw_p->first_init == 0)
|
||||
if (hw_p->first_init == 0) {
|
||||
hw_p->txbuf_ptr =
|
||||
(char *) malloc (ENET_MAX_MTU_ALIGNED);
|
||||
if (NULL == hw_p->txbuf_ptr) {
|
||||
free(hw_p->alloc_rx_buf);
|
||||
free(hw_p->alloc_tx_buf);
|
||||
hw_p->alloc_rx_buf = NULL;
|
||||
hw_p->alloc_tx_buf = NULL;
|
||||
for(j = 0; j < i; j++) {
|
||||
free(hw_p->tx[i].data_ptr);
|
||||
hw_p->tx[i].data_ptr = NULL;
|
||||
}
|
||||
}
|
||||
}
|
||||
hw_p->tx[i].data_ptr = hw_p->txbuf_ptr;
|
||||
if ((NUM_TX_BUFF - 1) == i)
|
||||
hw_p->tx[i].ctrl |= MAL_TX_CTRL_WRAP;
|
||||
|
|
|
|||
|
|
@ -302,7 +302,8 @@ void board_ether_init (void);
|
|||
#endif
|
||||
|
||||
#if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_MBX) || \
|
||||
defined(CONFIG_IAD210) || defined(CONFIG_XPEDITE1K)
|
||||
defined(CONFIG_IAD210) || defined(CONFIG_XPEDITE1K) || \
|
||||
defined(CONFIG_METROBOX) || defined(CONFIG_KAREF)
|
||||
void board_get_enetaddr (uchar *addr);
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,309 @@
|
|||
/*
|
||||
* (C) Copyright 2004 Sandburst Corporation
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/************************************************************************
|
||||
* KAMINOREFDES.h - configuration for the Sandburst Kamino Reference
|
||||
* design.
|
||||
***********************************************************************/
|
||||
|
||||
/*
|
||||
* $Id: KAREF.h,v 1.6 2005/06/03 15:05:25 tsawyer Exp $
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* High Level Configuration Options
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_KAREF 1 /* Board is Kamino Ref Variant */
|
||||
#define CONFIG_440GX 1 /* Specifc GX support */
|
||||
#define CONFIG_4xx 1 /* ... PPC4xx family */
|
||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
|
||||
#define CONFIG_MISC_INIT_F 1 /* Call board misc_init_f */
|
||||
#define CONFIG_MISC_INIT_R 1 /* Call board misc_init_r */
|
||||
#undef CFG_DRAM_TEST /* Disable-takes long time!*/
|
||||
#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */
|
||||
|
||||
#define CONFIG_VERY_BIG_RAM 1
|
||||
#define CONFIG_VERSION_VARIABLE
|
||||
|
||||
#define CONFIG_IDENT_STRING " Sandburst Kamino Reference Design"
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Base addresses -- Note these are effective addresses where the
|
||||
* actual resources get mapped (not physical addresses)
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
|
||||
#define CFG_FLASH_BASE 0xfff80000 /* start of FLASH */
|
||||
#define CFG_MONITOR_BASE 0xfff80000 /* start of monitor */
|
||||
#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
|
||||
#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */
|
||||
#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */
|
||||
#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */
|
||||
|
||||
#define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000)
|
||||
#define CFG_KAREF_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x08200000)
|
||||
#define CFG_OFEM_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x08400000)
|
||||
#define CFG_BME32_BASE (CFG_PERIPHERAL_BASE + 0x08500000)
|
||||
#define CFG_GPIO_BASE (CFG_PERIPHERAL_BASE + 0x00000700)
|
||||
|
||||
/* Here for completeness */
|
||||
#define CFG_OFEMAC_BASE (CFG_PERIPHERAL_BASE + 0x08600000)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Initial RAM & stack pointer (placed in internal SRAM)
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CFG_TEMP_STACK_OCM 1
|
||||
#define CFG_OCM_DATA_ADDR CFG_ISRAM_BASE
|
||||
#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */
|
||||
#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
|
||||
#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
|
||||
|
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
|
||||
#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
|
||||
#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR
|
||||
|
||||
#define CFG_MONITOR_LEN (256 * 1024) /* Rsrv 256kB for Mon */
|
||||
#define CFG_MALLOC_LEN (128 * 1024) /* Rsrv 128kB for malloc */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Serial Port
|
||||
*----------------------------------------------------------------------*/
|
||||
#undef CONFIG_SERIAL_SOFTWARE_FIFO
|
||||
#define CONFIG_SERIAL_MULTI 1
|
||||
#define CONFIG_BAUDRATE 9600
|
||||
|
||||
#define CFG_BAUDRATE_TABLE \
|
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* NVRAM/RTC
|
||||
*
|
||||
* NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
|
||||
* The DS1743 code assumes this condition (i.e. -- it assumes the base
|
||||
* address for the RTC registers is:
|
||||
*
|
||||
* CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE
|
||||
*
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CFG_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs*/
|
||||
#define CONFIG_RTC_DS174x 1 /* DS1743 RTC */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH related
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
|
||||
#define CFG_MAX_FLASH_SECT 8 /* sectors per device */
|
||||
|
||||
#undef CFG_FLASH_CHECKSUM
|
||||
#define CFG_FLASH_ERASE_TOUT 120000 /* Flash Erase TO (in ms) */
|
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write TO(in ms) */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* DDR SDRAM
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup*/
|
||||
#define SPD_EEPROM_ADDRESS {0x53} /* SPD i2c spd addresses */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* I2C
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_HARD_I2C 1 /* I2C hardware support */
|
||||
#undef CONFIG_SOFT_I2C /* I2C !bit-banged */
|
||||
#define CFG_I2C_SPEED 400000 /* I2C speed 400kHz */
|
||||
#define CFG_I2C_SLAVE 0x7F /* I2C slave address */
|
||||
#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
|
||||
#define CONFIG_I2C_BUS1 1 /* Include i2c bus 1 supp */
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Environment
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CFG_ENV_IS_IN_NVRAM 1 /* Environment uses NVRAM */
|
||||
#undef CFG_ENV_IS_IN_FLASH /* ... not in flash */
|
||||
#undef CFG_ENV_IS_IN_EEPROM /* ... not in EEPROM */
|
||||
#define CONFIG_ENV_OVERWRITE 1 /* allow env overwrite */
|
||||
|
||||
#define CFG_ENV_SIZE 0x1000 /* Size of Env vars */
|
||||
#define CFG_ENV_ADDR (CFG_NVRAM_BASE_ADDR)
|
||||
|
||||
#define CONFIG_BOOTDELAY 5 /* 5 second autoboot */
|
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial dnld */
|
||||
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Networking
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_MII 1 /* MII PHY management */
|
||||
#define CONFIG_NET_MULTI 1
|
||||
#define CONFIG_PHY_ADDR 0xff /* no phy on EMAC0 */
|
||||
#define CONFIG_PHY1_ADDR 0xff /* no phy on EMAC1 */
|
||||
#define CONFIG_PHY2_ADDR 0x08 /* PHY addr, MGMT, EMAC2 */
|
||||
#define CONFIG_PHY3_ADDR 0x18 /* PHY addr, LCL, EMAC3 */
|
||||
#define CONFIG_HAS_ETH0
|
||||
#define CONFIG_HAS_ETH1
|
||||
#define CONFIG_HAS_ETH2
|
||||
#define CONFIG_HAS_ETH3
|
||||
#define CONFIG_CIS8201_PHY 1 /* RGMII mode for Cicada */
|
||||
#define CONFIG_CIS8201_SHORT_ETCH 1 /* Use short etch mode */
|
||||
#define CONFIG_PHY_GIGE 1 /* GbE speed/duplex detect */
|
||||
#define CONFIG_PHY_RESET_DELAY 1000
|
||||
#define CONFIG_NETMASK 255.255.0.0
|
||||
#define CONFIG_ETHADDR 00:00:00:00:00:00 /* No EMAC 0 support */
|
||||
#define CONFIG_ETH1ADDR 00:00:00:00:00:00 /* No EMAC 1 support */
|
||||
#define CFG_RX_ETH_BUFFER 32 /* #eth rx buff & descrs */
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Console/Commands/Parser
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
|
||||
CFG_CMD_PCI | \
|
||||
CFG_CMD_IRQ | \
|
||||
CFG_CMD_I2C | \
|
||||
CFG_CMD_DHCP | \
|
||||
CFG_CMD_DATE | \
|
||||
CFG_CMD_BEDBUG | \
|
||||
CFG_CMD_PING | \
|
||||
CFG_CMD_DIAG | \
|
||||
CFG_CMD_MII | \
|
||||
CFG_CMD_NET | \
|
||||
CFG_CMD_ELF | \
|
||||
CFG_CMD_IDE | \
|
||||
CFG_CMD_FAT)
|
||||
|
||||
/* Include NetConsole support */
|
||||
#define CONFIG_NETCONSOLE
|
||||
|
||||
/* Include auto complete with tabs */
|
||||
#define CONFIG_AUTO_COMPLETE 1
|
||||
#define CFG_AUTO_COMPLETE 1
|
||||
#define CFG_ALT_MEMTEST 1 /* use real memory test */
|
||||
|
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
|
||||
#include <cmd_confdefs.h>
|
||||
|
||||
#define CFG_LONGHELP /* undef to save memory */
|
||||
#define CFG_PROMPT "KaRefDes=> " /* Monitor Command Prompt */
|
||||
|
||||
#define CFG_HUSH_PARSER 1 /* HUSH for ext'd cli */
|
||||
#define CFG_PROMPT_HUSH_PS2 "> "
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Console Buffer
|
||||
*----------------------------------------------------------------------*/
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
|
||||
/* Print Buffer Size */
|
||||
#define CFG_MAXARGS 16 /* max number of cmd args */
|
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Arg Buffer Size */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Memory Test
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
|
||||
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Compact Flash (in true IDE mode)
|
||||
*----------------------------------------------------------------------*/
|
||||
#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
|
||||
#undef CONFIG_IDE_LED /* no led for ide supported */
|
||||
|
||||
#define CONFIG_IDE_RESET /* reset for ide supported */
|
||||
#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */
|
||||
#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
|
||||
|
||||
#define CFG_ATA_BASE_ADDR 0xF0000000
|
||||
#define CFG_ATA_IDE0_OFFSET 0x0000
|
||||
#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
|
||||
#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses*/
|
||||
#define CFG_ATA_ALT_OFFSET 0x100000 /* Offset for alternate registers */
|
||||
|
||||
#define CFG_ATA_STRIDE 2 /* Directly connected CF, needs a stride
|
||||
to get to the correct offset */
|
||||
#define CONFIG_DOS_PARTITION 1 /* Include dos partition */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCI
|
||||
*----------------------------------------------------------------------*/
|
||||
/* General PCI */
|
||||
#define CONFIG_PCI /* include pci support */
|
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */
|
||||
#define CONFIG_PCI_SCAN_SHOW /* show pci devices */
|
||||
#define CFG_PCI_TARGBASE (CFG_PCI_MEMBASE)
|
||||
|
||||
/* Board-specific PCI */
|
||||
#define CFG_PCI_PRE_INIT /* enable board pci_pre_init*/
|
||||
#define CFG_PCI_TARGET_INIT /* let board init pci target*/
|
||||
|
||||
#define CFG_PCI_SUBSYS_VENDORID 0x17BA /* Sandburst */
|
||||
#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration
|
||||
*/
|
||||
#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
|
||||
#define CFG_CACHELINE_SIZE 32
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Internal Definitions
|
||||
*
|
||||
* Boot Flags
|
||||
*/
|
||||
#define BOOTFLAG_COLD 0x01 /* Normal PowerOn: Boot from FLASH */
|
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port baud */
|
||||
#define CONFIG_KGDB_SER_INDEX 2 /* kgdb serial port */
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Miscellaneous configurable options
|
||||
*----------------------------------------------------------------------*/
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
||||
#define CFG_LOAD_ADDR 0x8000000 /* default load address */
|
||||
#define CFG_EXTBDINFO 1 /* use extended board_info */
|
||||
|
||||
#define CFG_HZ 100 /* decr freq: 1 ms ticks */
|
||||
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
|
@ -0,0 +1,377 @@
|
|||
/*
|
||||
* (C) Copyright 2004 Sandburst Corporation
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/************************************************************************
|
||||
* METROBOX.h - configuration Sandburst MetroBox
|
||||
***********************************************************************/
|
||||
|
||||
/*
|
||||
* $Id: METROBOX.h,v 1.21 2005/06/03 15:05:25 tsawyer Exp $
|
||||
*
|
||||
*
|
||||
* $Log: METROBOX.h,v $
|
||||
* Revision 1.21 2005/06/03 15:05:25 tsawyer
|
||||
* MB rev 2.0.3 KA rev 0.0.7. Add CONFIG_VERSION_VARIABLE, Add fakeled to MB
|
||||
*
|
||||
* Revision 1.20 2005/04/11 20:51:11 tsawyer
|
||||
* fix ethernet
|
||||
*
|
||||
* Revision 1.19 2005/04/06 15:13:36 tsawyer
|
||||
* Update appropriate files to coincide with u-boot 1.1.3
|
||||
*
|
||||
* Revision 1.18 2005/03/10 14:16:02 tsawyer
|
||||
* add def'n for cis8201 short etch option.
|
||||
*
|
||||
* Revision 1.17 2005/03/09 19:49:51 tsawyer
|
||||
* Remove KGDB to allow use of 2nd serial port
|
||||
*
|
||||
* Revision 1.16 2004/12/02 19:00:23 tsawyer
|
||||
* Add misc_init_f to turn on i2c-1 and all four fans before sdram init
|
||||
*
|
||||
* Revision 1.15 2004/09/15 18:04:12 tsawyer
|
||||
* add multiple serial port support
|
||||
*
|
||||
* Revision 1.14 2004/09/03 15:27:51 tsawyer
|
||||
* All metrobox boards are at 66.66 sys clock
|
||||
*
|
||||
* Revision 1.13 2004/08/05 20:27:46 tsawyer
|
||||
* Remove system ace definitions, add net console support
|
||||
*
|
||||
* Revision 1.12 2004/07/29 20:00:13 tsawyer
|
||||
* Add i2c bus 1
|
||||
*
|
||||
* Revision 1.11 2004/07/21 13:44:18 tsawyer
|
||||
* SystemACE is out, CF direct to local bus is in
|
||||
*
|
||||
* Revision 1.10 2004/06/29 19:08:55 tsawyer
|
||||
* Add CONFIG_MISC_INIT_R
|
||||
*
|
||||
* Revision 1.9 2004/06/28 21:30:53 tsawyer
|
||||
* Fix default BOOTARGS
|
||||
*
|
||||
* Revision 1.8 2004/06/17 15:51:08 tsawyer
|
||||
* auto complete
|
||||
*
|
||||
* Revision 1.7 2004/06/17 15:08:49 tsawyer
|
||||
* Add autocomplete
|
||||
*
|
||||
* Revision 1.6 2004/06/15 12:33:57 tsawyer
|
||||
* debugging checkpoint
|
||||
*
|
||||
* Revision 1.5 2004/06/12 19:48:28 tsawyer
|
||||
* Debugging checkpoint
|
||||
*
|
||||
* Revision 1.4 2004/06/02 13:03:06 tsawyer
|
||||
* Fix eth addrs
|
||||
*
|
||||
* Revision 1.3 2004/05/18 19:56:10 tsawyer
|
||||
* Change default bootcommand to pImage.metrobox
|
||||
*
|
||||
* Revision 1.2 2004/05/18 14:13:44 tsawyer
|
||||
* Add bringup values for bootargs and bootcommand.
|
||||
* Remove definition of ipaddress and serverip addresses.
|
||||
*
|
||||
* Revision 1.1 2004/04/16 15:08:54 tsawyer
|
||||
* Initial Revision
|
||||
*
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* High Level Configuration Options
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_METROBOX 1 /* Board is Metrobox */
|
||||
#define CONFIG_440GX 1 /* Specifc GX support */
|
||||
#define CONFIG_4xx 1 /* ... PPC4xx family */
|
||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
|
||||
#define CONFIG_MISC_INIT_F 1 /* Call board misc_init_f */
|
||||
#define CONFIG_MISC_INIT_R 1 /* Call board misc_init_r */
|
||||
#undef CFG_DRAM_TEST /* Disable-takes long time!*/
|
||||
#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */
|
||||
|
||||
#define CONFIG_VERY_BIG_RAM 1
|
||||
#define CONFIG_VERSION_VARIABLE
|
||||
|
||||
#define CONFIG_IDENT_STRING " Sandburst Metrobox"
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Base addresses -- Note these are effective addresses where the
|
||||
* actual resources get mapped (not physical addresses)
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
|
||||
#define CFG_FLASH_BASE 0xfff80000 /* start of FLASH */
|
||||
#define CFG_MONITOR_BASE 0xfff80000 /* start of monitor */
|
||||
#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
|
||||
#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */
|
||||
#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */
|
||||
#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */
|
||||
|
||||
#define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000)
|
||||
#define CFG_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x08200000)
|
||||
#define CFG_BME32_BASE (CFG_PERIPHERAL_BASE + 0x08500000)
|
||||
#define CFG_GPIO_BASE (CFG_PERIPHERAL_BASE + 0x00000700)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Initial RAM & stack pointer (placed in internal SRAM)
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CFG_TEMP_STACK_OCM 1
|
||||
#define CFG_OCM_DATA_ADDR CFG_ISRAM_BASE
|
||||
#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */
|
||||
#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
|
||||
#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
|
||||
|
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
|
||||
#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
|
||||
#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR
|
||||
|
||||
#define CFG_MONITOR_LEN (256 * 1024) /* Rsrv 256kB for Mon */
|
||||
#define CFG_MALLOC_LEN (128 * 1024) /* Rsrv 128kB for malloc */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Serial Port
|
||||
*----------------------------------------------------------------------*/
|
||||
#undef CONFIG_SERIAL_SOFTWARE_FIFO
|
||||
#define CONFIG_SERIAL_MULTI 1
|
||||
#define CONFIG_BAUDRATE 9600
|
||||
|
||||
#define CFG_BAUDRATE_TABLE \
|
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* NVRAM/RTC
|
||||
*
|
||||
* NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
|
||||
* The DS1743 code assumes this condition (i.e. -- it assumes the base
|
||||
* address for the RTC registers is:
|
||||
*
|
||||
* CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE
|
||||
*
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CFG_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs*/
|
||||
#define CONFIG_RTC_DS174x 1 /* DS1743 RTC */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH related
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
|
||||
#define CFG_MAX_FLASH_SECT 8 /* sectors per device */
|
||||
|
||||
#undef CFG_FLASH_CHECKSUM
|
||||
#define CFG_FLASH_ERASE_TOUT 120000 /* Flash Erase TO (in ms) */
|
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write TO(in ms) */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* DDR SDRAM
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup*/
|
||||
#define SPD_EEPROM_ADDRESS {0x53} /* SPD i2c spd addresses */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* I2C
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_HARD_I2C 1 /* I2C hardware support */
|
||||
#undef CONFIG_SOFT_I2C /* I2C !bit-banged */
|
||||
#define CFG_I2C_SPEED 400000 /* I2C speed 400kHz */
|
||||
#define CFG_I2C_SLAVE 0x7F /* I2C slave address */
|
||||
#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
|
||||
#define CONFIG_I2C_BUS1 1 /* Include i2c bus 1 supp */
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Environment
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CFG_ENV_IS_IN_NVRAM 1 /* Environment uses NVRAM */
|
||||
#undef CFG_ENV_IS_IN_FLASH /* ... not in flash */
|
||||
#undef CFG_ENV_IS_IN_EEPROM /* ... not in EEPROM */
|
||||
#define CONFIG_ENV_OVERWRITE 1 /* allow env overwrite */
|
||||
|
||||
#define CFG_ENV_SIZE 0x1000 /* Size of Env vars */
|
||||
#define CFG_ENV_ADDR (CFG_NVRAM_BASE_ADDR)
|
||||
|
||||
#define CONFIG_BOOTARGS "console=ttyS0,9600 root=/dev/nfs rw nfsroot=$serverip:/home/metrobox0 nfsaddrs=$ipaddr:::::eth0:none "
|
||||
#define CONFIG_BOOTCOMMAND "tftp 8000000 pImage.metrobox;bootm 8000000"
|
||||
#define CONFIG_BOOTDELAY 5 /* disable autoboot */
|
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial dnld */
|
||||
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Networking
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_MII 1 /* MII PHY management */
|
||||
#define CONFIG_NET_MULTI 1
|
||||
#define CONFIG_PHY_ADDR 0xff /* no phy on EMAC0 */
|
||||
#define CONFIG_PHY1_ADDR 0xff /* no phy on EMAC1 */
|
||||
#define CONFIG_PHY2_ADDR 0x08 /* PHY addr, MGMT, EMAC2 */
|
||||
#define CONFIG_PHY3_ADDR 0x18 /* PHY addr, LCL, EMAC3 */
|
||||
#define CONFIG_HAS_ETH0
|
||||
#define CONFIG_HAS_ETH1
|
||||
#define CONFIG_HAS_ETH2
|
||||
#define CONFIG_HAS_ETH3
|
||||
#define CONFIG_CIS8201_PHY 1 /* RGMII mode for Cicada */
|
||||
#define CONFIG_CIS8201_SHORT_ETCH 1 /* Use short etch mode */
|
||||
#define CONFIG_PHY_GIGE 1 /* GbE speed/duplex detect */
|
||||
#define CONFIG_PHY_RESET_DELAY 1000
|
||||
#define CONFIG_NETMASK 255.255.0.0
|
||||
#define CONFIG_ETHADDR 00:00:00:00:00:00 /* No EMAC 0 support */
|
||||
#define CONFIG_ETH1ADDR 00:00:00:00:00:00 /* No EMAC 1 support */
|
||||
#define CFG_RX_ETH_BUFFER 32 /* #eth rx buff & descrs */
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Console/Commands/Parser
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
|
||||
CFG_CMD_PCI | \
|
||||
CFG_CMD_IRQ | \
|
||||
CFG_CMD_I2C | \
|
||||
CFG_CMD_DHCP | \
|
||||
CFG_CMD_DATE | \
|
||||
CFG_CMD_BEDBUG | \
|
||||
CFG_CMD_PING | \
|
||||
CFG_CMD_DIAG | \
|
||||
CFG_CMD_MII | \
|
||||
CFG_CMD_NET | \
|
||||
CFG_CMD_ELF | \
|
||||
CFG_CMD_IDE | \
|
||||
CFG_CMD_FAT)
|
||||
|
||||
/* tbs 09-March-2005 Removed to be able to use 2nd serial */
|
||||
/* CFG_CMD_KGDB | \ */
|
||||
|
||||
|
||||
/* Include NetConsole support */
|
||||
#define CONFIG_NETCONSOLE
|
||||
|
||||
/* Include auto complete with tabs */
|
||||
#define CONFIG_AUTO_COMPLETE 1
|
||||
#define CFG_AUTO_COMPLETE 1
|
||||
#define CFG_ALT_MEMTEST 1 /* use real memory test */
|
||||
|
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
|
||||
#include <cmd_confdefs.h>
|
||||
|
||||
#define CFG_LONGHELP /* undef to save memory */
|
||||
#define CFG_PROMPT "MetroBox=> " /* Monitor Command Prompt */
|
||||
|
||||
#define CFG_HUSH_PARSER 1 /* HUSH for ext'd cli */
|
||||
#define CFG_PROMPT_HUSH_PS2 "> "
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Console Buffer
|
||||
*----------------------------------------------------------------------*/
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
|
||||
/* Print Buffer Size */
|
||||
#define CFG_MAXARGS 16 /* max number of cmd args */
|
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Arg Buffer Size */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Memory Test
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
|
||||
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Compact Flash (in true IDE mode)
|
||||
*----------------------------------------------------------------------*/
|
||||
#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
|
||||
#undef CONFIG_IDE_LED /* no led for ide supported */
|
||||
|
||||
#define CONFIG_IDE_RESET /* reset for ide supported */
|
||||
#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */
|
||||
#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
|
||||
|
||||
#define CFG_ATA_BASE_ADDR 0xF0000000
|
||||
#define CFG_ATA_IDE0_OFFSET 0x0000
|
||||
#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
|
||||
#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses*/
|
||||
#define CFG_ATA_ALT_OFFSET 0x100000 /* Offset for alternate registers */
|
||||
|
||||
#define CFG_ATA_STRIDE 2 /* Directly connected CF, needs a stride
|
||||
to get to the correct offset */
|
||||
#define CONFIG_DOS_PARTITION 1 /* Include dos partition */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCI
|
||||
*----------------------------------------------------------------------*/
|
||||
/* General PCI */
|
||||
#define CONFIG_PCI /* include pci support */
|
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */
|
||||
#define CONFIG_PCI_SCAN_SHOW /* show pci devices */
|
||||
#define CFG_PCI_TARGBASE (CFG_PCI_MEMBASE)
|
||||
|
||||
/* Board-specific PCI */
|
||||
#define CFG_PCI_PRE_INIT /* enable board pci_pre_init*/
|
||||
#define CFG_PCI_TARGET_INIT /* let board init pci target*/
|
||||
|
||||
#define CFG_PCI_SUBSYS_VENDORID 0x17BA /* Sandburst */
|
||||
#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration
|
||||
*/
|
||||
#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
|
||||
#define CFG_CACHELINE_SIZE 32
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Internal Definitions
|
||||
*
|
||||
* Boot Flags
|
||||
*/
|
||||
#define BOOTFLAG_COLD 0x01 /* Normal PowerOn: Boot from FLASH */
|
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port baud */
|
||||
#define CONFIG_KGDB_SER_INDEX 2 /* kgdb serial port */
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Miscellaneous configurable options
|
||||
*----------------------------------------------------------------------*/
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
||||
#define CFG_LOAD_ADDR 0x8000000 /* default load address */
|
||||
#define CFG_EXTBDINFO 1 /* use extended board_info */
|
||||
|
||||
#define CFG_HZ 100 /* decr freq: 1 ms ticks */
|
||||
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
|
@ -842,7 +842,7 @@
|
|||
#define EBC_BXCR_BW_MASK 0x00006000
|
||||
#define EBC_BXCR_BW_8BIT 0x00000000
|
||||
#define EBC_BXCR_BW_16BIT 0x00002000
|
||||
|
||||
#define EBC_BXCR_BW_32BIT 0x00006000
|
||||
#define EBC_BXAP_BME_ENABLED 0x80000000
|
||||
#define EBC_BXAP_BME_DISABLED 0x00000000
|
||||
#define EBC_BXAP_TWT_ENCODE(n) ((((unsigned long)(n))&0xFF)<<23)
|
||||
|
|
|
|||
|
|
@ -828,7 +828,7 @@ void board_init_r (gd_t *id, ulong dest_addr)
|
|||
/* handle the 3rd ethernet address */
|
||||
|
||||
s = getenv ("eth2addr");
|
||||
#if defined(CONFIG_XPEDITE1K)
|
||||
#if defined(CONFIG_XPEDITE1K) || defined(CONFIG_METROBOX) || defined(CONFIG_KAREF)
|
||||
if (s == NULL)
|
||||
board_get_enetaddr(bd->bi_enet2addr);
|
||||
else
|
||||
|
|
@ -843,7 +843,7 @@ void board_init_r (gd_t *id, ulong dest_addr)
|
|||
#ifdef CONFIG_HAS_ETH3
|
||||
/* handle 4th ethernet address */
|
||||
s = getenv("eth3addr");
|
||||
#if defined(CONFIG_XPEDITE1K)
|
||||
#if defined(CONFIG_XPEDITE1K) || defined(CONFIG_METROBOX) || defined(CONFIG_KAREF)
|
||||
if (s == NULL)
|
||||
board_get_enetaddr(bd->bi_enet3addr);
|
||||
else
|
||||
|
|
|
|||
Loading…
Reference in New Issue