[ppc4xx] Add initial lwmon5 board support
This patch adds initial support for the Liebherr lwmon5 board euqipped with an AMCC 440EPx PowerPC. Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Roese
parent
85f737376d
commit
b765ffb773
|
|
@ -282,6 +282,7 @@ Stefan Roese <sr@denx.de>
|
|||
bunbinga PPC405EP
|
||||
ebony PPC440GP
|
||||
katmai PPC440SPe
|
||||
lwmon5 PPC440EPx
|
||||
ocotea PPC440GX
|
||||
p3p440 PPC440GP
|
||||
pcs440ep PPC440EP
|
||||
|
|
|
|||
18
MAKEALL
18
MAKEALL
|
|
@ -83,15 +83,15 @@ LIST_4xx=" \
|
|||
csb272 csb472 DASA_SIM DP405 \
|
||||
DU405 ebony ERIC EXBITGEN \
|
||||
G2000 HH405 HUB405 JSE \
|
||||
KAREF katmai luan METROBOX \
|
||||
MIP405 MIP405T ML2 ml300 \
|
||||
ocotea OCRTC ORSG p3p440 \
|
||||
PCI405 pcs440ep PIP405 PLU405 \
|
||||
PMC405 PPChameleonEVB sbc405 sc3 \
|
||||
sequoia sequoia_nand taishan VOH405 \
|
||||
VOM405 W7OLMC W7OLMG walnut \
|
||||
WUH405 XPEDITE1K yellowstone yosemite \
|
||||
yucca \
|
||||
KAREF katmai luan lwmon5 \
|
||||
METROBOX MIP405 MIP405T ML2 \
|
||||
ml300 ocotea OCRTC ORSG \
|
||||
p3p440 PCI405 pcs440ep PIP405 \
|
||||
PLU405 PMC405 PPChameleonEVB sbc405 \
|
||||
sc3 sequoia sequoia_nand taishan \
|
||||
VOH405 VOM405 W7OLMC W7OLMG \
|
||||
walnut WUH405 XPEDITE1K yellowstone \
|
||||
yosemite yucca \
|
||||
"
|
||||
|
||||
#########################################################################
|
||||
|
|
|
|||
3
Makefile
3
Makefile
|
|
@ -1139,6 +1139,9 @@ katmai_config: unconfig
|
|||
luan_config: unconfig
|
||||
@$(MKCONFIG) $(@:_config=) ppc ppc4xx luan amcc
|
||||
|
||||
lwmon5_config: unconfig
|
||||
@$(MKCONFIG) $(@:_config=) ppc ppc4xx lwmon5
|
||||
|
||||
METROBOX_config: unconfig
|
||||
@$(MKCONFIG) $(@:_config=) ppc ppc4xx metrobox sandburst
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,51 @@
|
|||
#
|
||||
# (C) Copyright 2002-2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS = $(BOARD).o sdram.o
|
||||
SOBJS = init.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(OBJS) $(SOBJS)
|
||||
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
|
||||
|
||||
clean:
|
||||
rm -f $(SOBJS) $(OBJS)
|
||||
|
||||
distclean: clean
|
||||
rm -f $(LIB) core *.bak .depend
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
|
|
@ -0,0 +1,39 @@
|
|||
#
|
||||
# (C) Copyright 2002
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
#
|
||||
# lwmon5 (440EPx)
|
||||
#
|
||||
|
||||
ifndef TEXT_BASE
|
||||
TEXT_BASE = 0xFFF80000
|
||||
endif
|
||||
|
||||
PLATFORM_CPPFLAGS += -DCONFIG_440=1
|
||||
|
||||
ifeq ($(debug),1)
|
||||
PLATFORM_CPPFLAGS += -DDEBUG
|
||||
endif
|
||||
|
||||
ifeq ($(dbcr),1)
|
||||
PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
|
||||
endif
|
||||
|
|
@ -0,0 +1,90 @@
|
|||
/*
|
||||
* (C) Copyright 2007
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <ppc_asm.tmpl>
|
||||
#include <config.h>
|
||||
#include <asm-ppc/mmu.h>
|
||||
|
||||
/**************************************************************************
|
||||
* TLB TABLE
|
||||
*
|
||||
* This table is used by the cpu boot code to setup the initial tlb
|
||||
* entries. Rather than make broad assumptions in the cpu source tree,
|
||||
* this table lets each board set things up however they like.
|
||||
*
|
||||
* Pointer to the table is returned in r1
|
||||
*
|
||||
*************************************************************************/
|
||||
.section .bootpg,"ax"
|
||||
.globl tlbtab
|
||||
|
||||
tlbtab:
|
||||
tlbtab_start
|
||||
|
||||
/*
|
||||
* BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
|
||||
* speed up boot process. It is patched after relocation to enable SA_I
|
||||
*/
|
||||
tlbentry(CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G)
|
||||
|
||||
/*
|
||||
* TLB entries for SDRAM are not needed on this platform.
|
||||
* They are dynamically generated in the SPD DDR(2) detection
|
||||
* routine.
|
||||
*/
|
||||
|
||||
#ifdef CFG_INIT_RAM_DCACHE
|
||||
/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
|
||||
tlbentry(CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G)
|
||||
#endif
|
||||
|
||||
/* TLB-entry for PCI Memory */
|
||||
tlbentry(CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I)
|
||||
tlbentry(CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I)
|
||||
tlbentry(CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I)
|
||||
tlbentry(CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I)
|
||||
|
||||
/* TLB-entry for the FPGA Chip select 2 */
|
||||
tlbentry(CFG_FPGA_BASE_0, SZ_1M, CFG_FPGA_BASE_0, 1, AC_R|AC_W|AC_X|SA_I|SA_G)
|
||||
|
||||
/* TLB-entry for the FPGA Chip select 3 */
|
||||
tlbentry(CFG_FPGA_BASE_1, SZ_1M, CFG_FPGA_BASE_1, 1,AC_R|AC_W|AC_X|SA_I|SA_G)
|
||||
|
||||
/* TLB-entry for the LIME Controller */
|
||||
tlbentry(CFG_LIME_BASE_0, SZ_16M, CFG_LIME_BASE_0, 1, AC_R|AC_W|AC_X|SA_I|SA_G)
|
||||
tlbentry(CFG_LIME_BASE_1, SZ_16M, CFG_LIME_BASE_1, 1, AC_R|AC_W|AC_X|SA_I|SA_G)
|
||||
tlbentry(CFG_LIME_BASE_2, SZ_16M, CFG_LIME_BASE_2, 1, AC_R|AC_W|AC_X|SA_I|SA_G)
|
||||
tlbentry(CFG_LIME_BASE_3, SZ_16M, CFG_LIME_BASE_3, 1, AC_R|AC_W|AC_X|SA_I|SA_G)
|
||||
|
||||
/* TLB-entry for Internal Registers & OCM */
|
||||
tlbentry(0xe0000000, SZ_16M, 0xe0000000, 0, AC_R|AC_W|AC_X|SA_I)
|
||||
|
||||
/*TLB-entry PCI registers*/
|
||||
tlbentry(0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
|
||||
|
||||
/* TLB-entry for peripherals */
|
||||
tlbentry(0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
|
||||
|
||||
tlbtab_end
|
||||
|
|
@ -0,0 +1,464 @@
|
|||
/*
|
||||
* (C) Copyright 2007
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/processor.h>
|
||||
#include <ppc440.h>
|
||||
#include <asm/gpio.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
|
||||
|
||||
ulong flash_get_size (ulong base, int banknum);
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
u32 sdr0_pfc1, sdr0_pfc2;
|
||||
u32 reg;
|
||||
|
||||
/* PLB Write pipelining disabled. Denali Core workaround */
|
||||
mtdcr(plb0_acr, 0xDE000000);
|
||||
mtdcr(plb1_acr, 0xDE000000);
|
||||
|
||||
/*--------------------------------------------------------------------
|
||||
* Setup the interrupt controller polarities, triggers, etc.
|
||||
*-------------------------------------------------------------------*/
|
||||
mtdcr(uic0sr, 0xffffffff); /* clear all. if write with 1 then the status is cleared */
|
||||
mtdcr(uic0er, 0x00000000); /* disable all */
|
||||
mtdcr(uic0cr, 0x00000000); /* we have not critical interrupts at the moment */
|
||||
mtdcr(uic0pr, 0xfffff7ff); /* Adjustment of the polarity */
|
||||
mtdcr(uic0tr, 0x00000810); /* per ref-board manual */
|
||||
mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */
|
||||
mtdcr(uic0sr, 0xffffffff); /* clear all */
|
||||
|
||||
mtdcr(uic1sr, 0xffffffff); /* clear all */
|
||||
mtdcr(uic1er, 0x00000000); /* disable all */
|
||||
mtdcr(uic1cr, 0x00000000); /* all non-critical */
|
||||
mtdcr(uic1pr, 0xFFFFC7AD); /* Adjustment of the polarity */
|
||||
mtdcr(uic1tr, 0x0600384A); /* per ref-board manual */
|
||||
mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */
|
||||
mtdcr(uic1sr, 0xffffffff); /* clear all */
|
||||
|
||||
mtdcr(uic2sr, 0xffffffff); /* clear all */
|
||||
mtdcr(uic2er, 0x00000000); /* disable all */
|
||||
mtdcr(uic2cr, 0x00000000); /* all non-critical */
|
||||
mtdcr(uic2pr, 0x27C00000); /* Adjustment of the polarity */
|
||||
mtdcr(uic2tr, 0xDFC00000); /* per ref-board manual */
|
||||
mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */
|
||||
mtdcr(uic2sr, 0xffffffff); /* clear all. Why this??? */
|
||||
|
||||
/* Trace Pins are disabled. SDR0_PFC0 Register */
|
||||
mtsdr(SDR0_PFC0, 0x0);
|
||||
|
||||
/* select Ethernet pins */
|
||||
mfsdr(SDR0_PFC1, sdr0_pfc1);
|
||||
/* SMII via ZMII */
|
||||
sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
|
||||
SDR0_PFC1_SELECT_CONFIG_6;
|
||||
mfsdr(SDR0_PFC2, sdr0_pfc2);
|
||||
sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
|
||||
SDR0_PFC2_SELECT_CONFIG_6;
|
||||
|
||||
/* enable SPI (SCP) */
|
||||
sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_SCP_SEL;
|
||||
|
||||
mtsdr(SDR0_PFC2, sdr0_pfc2);
|
||||
mtsdr(SDR0_PFC1, sdr0_pfc1);
|
||||
|
||||
mtsdr(SDR0_PFC4, 0x80000000);
|
||||
|
||||
/* PCI arbiter disabled */
|
||||
/* PCI Host Configuration disbaled */
|
||||
mfsdr(sdr_pci0, reg);
|
||||
reg = 0;
|
||||
mtsdr(sdr_pci0, 0x00000000 | reg);
|
||||
|
||||
gpio_write_bit(CFG_GPIO_FLASH_WP, 1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------+
|
||||
| misc_init_r.
|
||||
+---------------------------------------------------------------------------*/
|
||||
int misc_init_r(void)
|
||||
{
|
||||
u32 pbcr;
|
||||
int size_val = 0;
|
||||
u32 reg;
|
||||
unsigned long usb2d0cr = 0;
|
||||
unsigned long usb2phy0cr, usb2h0cr = 0;
|
||||
unsigned long sdr0_pfc1;
|
||||
|
||||
/*
|
||||
* FLASH stuff...
|
||||
*/
|
||||
|
||||
/* Re-do sizing to get full correct info */
|
||||
|
||||
/* adjust flash start and offset */
|
||||
gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
|
||||
gd->bd->bi_flashoffset = 0;
|
||||
|
||||
mfebc(pb0cr, pbcr);
|
||||
switch (gd->bd->bi_flashsize) {
|
||||
case 1 << 20:
|
||||
size_val = 0;
|
||||
break;
|
||||
case 2 << 20:
|
||||
size_val = 1;
|
||||
break;
|
||||
case 4 << 20:
|
||||
size_val = 2;
|
||||
break;
|
||||
case 8 << 20:
|
||||
size_val = 3;
|
||||
break;
|
||||
case 16 << 20:
|
||||
size_val = 4;
|
||||
break;
|
||||
case 32 << 20:
|
||||
size_val = 5;
|
||||
break;
|
||||
case 64 << 20:
|
||||
size_val = 6;
|
||||
break;
|
||||
case 128 << 20:
|
||||
size_val = 7;
|
||||
break;
|
||||
}
|
||||
pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
|
||||
mtebc(pb0cr, pbcr);
|
||||
|
||||
/*
|
||||
* Re-check to get correct base address
|
||||
*/
|
||||
flash_get_size(gd->bd->bi_flashstart, 0);
|
||||
|
||||
/* Monitor protection ON by default */
|
||||
(void)flash_protect(FLAG_PROTECT_SET,
|
||||
-CFG_MONITOR_LEN,
|
||||
0xffffffff,
|
||||
&flash_info[0]);
|
||||
|
||||
/* Env protection ON by default */
|
||||
(void)flash_protect(FLAG_PROTECT_SET,
|
||||
CFG_ENV_ADDR_REDUND,
|
||||
CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1,
|
||||
&flash_info[0]);
|
||||
|
||||
/*
|
||||
* USB suff...
|
||||
*/
|
||||
/* SDR Setting */
|
||||
mfsdr(SDR0_PFC1, sdr0_pfc1);
|
||||
mfsdr(SDR0_USB0, usb2d0cr);
|
||||
mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
|
||||
mfsdr(SDR0_USB2H0CR, usb2h0cr);
|
||||
|
||||
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
|
||||
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/
|
||||
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
|
||||
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/
|
||||
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
|
||||
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/
|
||||
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
|
||||
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/
|
||||
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
|
||||
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/
|
||||
|
||||
/* An 8-bit/60MHz interface is the only possible alternative
|
||||
when connecting the Device to the PHY */
|
||||
usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
|
||||
usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/
|
||||
|
||||
mtsdr(SDR0_PFC1, sdr0_pfc1);
|
||||
mtsdr(SDR0_USB0, usb2d0cr);
|
||||
mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
|
||||
mtsdr(SDR0_USB2H0CR, usb2h0cr);
|
||||
|
||||
/*
|
||||
* Clear resets
|
||||
*/
|
||||
udelay (1000);
|
||||
mtsdr(SDR0_SRST1, 0x00000000);
|
||||
udelay (1000);
|
||||
mtsdr(SDR0_SRST0, 0x00000000);
|
||||
|
||||
printf("USB: Host(int phy) Device(ext phy)\n");
|
||||
|
||||
/*
|
||||
* Clear PLB4A0_ACR[WRP]
|
||||
* This fix will make the MAL burst disabling patch for the Linux
|
||||
* EMAC driver obsolete.
|
||||
*/
|
||||
reg = mfdcr(plb4_acr) & ~PLB4_ACR_WRP;
|
||||
mtdcr(plb4_acr, reg);
|
||||
|
||||
/*
|
||||
* Reset Lime controller
|
||||
*/
|
||||
gpio_write_bit(CFG_GPIO_LIME_S, 1);
|
||||
udelay(500);
|
||||
gpio_write_bit(CFG_GPIO_LIME_RST, 1);
|
||||
|
||||
/*
|
||||
* Reset PHY's
|
||||
*/
|
||||
gpio_write_bit(CFG_GPIO_PHY0_RST, 0);
|
||||
gpio_write_bit(CFG_GPIO_PHY1_RST, 0);
|
||||
udelay(100);
|
||||
gpio_write_bit(CFG_GPIO_PHY0_RST, 1);
|
||||
gpio_write_bit(CFG_GPIO_PHY1_RST, 1);
|
||||
|
||||
/*
|
||||
* Reset USB hub
|
||||
*/
|
||||
gpio_write_bit(CFG_GPIO_HUB_RST, 0);
|
||||
udelay(100);
|
||||
gpio_write_bit(CFG_GPIO_HUB_RST, 1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
char *s = getenv("serial#");
|
||||
|
||||
printf("Board: lwmon5");
|
||||
|
||||
if (s != NULL) {
|
||||
puts(", serial# ");
|
||||
puts(s);
|
||||
}
|
||||
putc('\n');
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
#if defined(CFG_DRAM_TEST)
|
||||
int testdram(void)
|
||||
{
|
||||
unsigned long *mem = (unsigned long *)0;
|
||||
const unsigned long kend = (1024 / sizeof(unsigned long));
|
||||
unsigned long k, n;
|
||||
|
||||
mtmsr(0);
|
||||
|
||||
for (k = 0; k < CFG_MBYTES_SDRAM;
|
||||
++k, mem += (1024 / sizeof(unsigned long))) {
|
||||
if ((k & 1023) == 0) {
|
||||
printf("%3d MB\r", k / 1024);
|
||||
}
|
||||
|
||||
memset(mem, 0xaaaaaaaa, 1024);
|
||||
for (n = 0; n < kend; ++n) {
|
||||
if (mem[n] != 0xaaaaaaaa) {
|
||||
printf("SDRAM test fails at: %08x\n",
|
||||
(uint) & mem[n]);
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
||||
memset(mem, 0x55555555, 1024);
|
||||
for (n = 0; n < kend; ++n) {
|
||||
if (mem[n] != 0x55555555) {
|
||||
printf("SDRAM test fails at: %08x\n",
|
||||
(uint) & mem[n]);
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
}
|
||||
printf("SDRAM test passes\n");
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
/*************************************************************************
|
||||
* pci_pre_init
|
||||
*
|
||||
* This routine is called just prior to registering the hose and gives
|
||||
* the board the opportunity to check things. Returning a value of zero
|
||||
* indicates that things are bad & PCI initialization should be aborted.
|
||||
*
|
||||
* Different boards may wish to customize the pci controller structure
|
||||
* (add regions, override default access routines, etc) or perform
|
||||
* certain pre-initialization actions.
|
||||
*
|
||||
************************************************************************/
|
||||
#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
|
||||
int pci_pre_init(struct pci_controller *hose)
|
||||
{
|
||||
unsigned long addr;
|
||||
|
||||
/*-------------------------------------------------------------------------+
|
||||
| Set priority for all PLB3 devices to 0.
|
||||
| Set PLB3 arbiter to fair mode.
|
||||
+-------------------------------------------------------------------------*/
|
||||
mfsdr(sdr_amp1, addr);
|
||||
mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
|
||||
addr = mfdcr(plb3_acr);
|
||||
mtdcr(plb3_acr, addr | 0x80000000);
|
||||
|
||||
/*-------------------------------------------------------------------------+
|
||||
| Set priority for all PLB4 devices to 0.
|
||||
+-------------------------------------------------------------------------*/
|
||||
mfsdr(sdr_amp0, addr);
|
||||
mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
|
||||
addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
|
||||
mtdcr(plb4_acr, addr);
|
||||
|
||||
/*-------------------------------------------------------------------------+
|
||||
| Set Nebula PLB4 arbiter to fair mode.
|
||||
+-------------------------------------------------------------------------*/
|
||||
/* Segment0 */
|
||||
addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
|
||||
addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
|
||||
addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
|
||||
addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
|
||||
mtdcr(plb0_acr, addr);
|
||||
|
||||
/* Segment1 */
|
||||
addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
|
||||
addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
|
||||
addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
|
||||
addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
|
||||
mtdcr(plb1_acr, addr);
|
||||
|
||||
return 1;
|
||||
}
|
||||
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
|
||||
|
||||
/*************************************************************************
|
||||
* pci_target_init
|
||||
*
|
||||
* The bootstrap configuration provides default settings for the pci
|
||||
* inbound map (PIM). But the bootstrap config choices are limited and
|
||||
* may not be sufficient for a given board.
|
||||
*
|
||||
************************************************************************/
|
||||
#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
|
||||
void pci_target_init(struct pci_controller *hose)
|
||||
{
|
||||
/*--------------------------------------------------------------------------+
|
||||
* Set up Direct MMIO registers
|
||||
*--------------------------------------------------------------------------*/
|
||||
/*--------------------------------------------------------------------------+
|
||||
| PowerPC440EPX PCI Master configuration.
|
||||
| Map one 1Gig range of PLB/processor addresses to PCI memory space.
|
||||
| PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
|
||||
| Use byte reversed out routines to handle endianess.
|
||||
| Make this region non-prefetchable.
|
||||
+--------------------------------------------------------------------------*/
|
||||
out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
|
||||
out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */
|
||||
out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
|
||||
out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
|
||||
out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */
|
||||
|
||||
out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
|
||||
out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
|
||||
out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */
|
||||
out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
|
||||
out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */
|
||||
|
||||
out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
|
||||
out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
|
||||
out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
|
||||
out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
|
||||
|
||||
/*--------------------------------------------------------------------------+
|
||||
* Set up Configuration registers
|
||||
*--------------------------------------------------------------------------*/
|
||||
|
||||
/* Program the board's subsystem id/vendor id */
|
||||
pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
|
||||
CFG_PCI_SUBSYS_VENDORID);
|
||||
pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
|
||||
|
||||
/* Configure command register as bus master */
|
||||
pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
|
||||
|
||||
/* 240nS PCI clock */
|
||||
pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
|
||||
|
||||
/* No error reporting */
|
||||
pci_write_config_word(0, PCI_ERREN, 0);
|
||||
|
||||
pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
|
||||
|
||||
}
|
||||
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
|
||||
|
||||
/*************************************************************************
|
||||
* pci_master_init
|
||||
*
|
||||
************************************************************************/
|
||||
#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
|
||||
void pci_master_init(struct pci_controller *hose)
|
||||
{
|
||||
unsigned short temp_short;
|
||||
|
||||
/*--------------------------------------------------------------------------+
|
||||
| Write the PowerPC440 EP PCI Configuration regs.
|
||||
| Enable PowerPC440 EP to be a master on the PCI bus (PMM).
|
||||
| Enable PowerPC440 EP to act as a PCI memory target (PTM).
|
||||
+--------------------------------------------------------------------------*/
|
||||
pci_read_config_word(0, PCI_COMMAND, &temp_short);
|
||||
pci_write_config_word(0, PCI_COMMAND,
|
||||
temp_short | PCI_COMMAND_MASTER |
|
||||
PCI_COMMAND_MEMORY);
|
||||
}
|
||||
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
|
||||
|
||||
/*************************************************************************
|
||||
* is_pci_host
|
||||
*
|
||||
* This routine is called to determine if a pci scan should be
|
||||
* performed. With various hardware environments (especially cPCI and
|
||||
* PPMC) it's insufficient to depend on the state of the arbiter enable
|
||||
* bit in the strap register, or generic host/adapter assumptions.
|
||||
*
|
||||
* Rather than hard-code a bad assumption in the general 440 code, the
|
||||
* 440 pci code requires the board to decide at runtime.
|
||||
*
|
||||
* Return 0 for adapter mode, non-zero for host (monarch) mode.
|
||||
*
|
||||
*
|
||||
************************************************************************/
|
||||
#if defined(CONFIG_PCI)
|
||||
int is_pci_host(struct pci_controller *hose)
|
||||
{
|
||||
/* Cactus is always configured as host. */
|
||||
return (1);
|
||||
}
|
||||
#endif /* defined(CONFIG_PCI) */
|
||||
|
||||
void hw_watchdog_reset(void)
|
||||
{
|
||||
int val;
|
||||
|
||||
/*
|
||||
* Toggle watchdog output
|
||||
*/
|
||||
val = gpio_read_out_bit(CFG_GPIO_WATCHDOG) == 0 ? 1 : 0;
|
||||
gpio_write_bit(CFG_GPIO_WATCHDOG, val);
|
||||
}
|
||||
|
|
@ -0,0 +1,598 @@
|
|||
/*
|
||||
* (C) Copyright 2006
|
||||
* Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com
|
||||
* Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
|
||||
* Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com
|
||||
* Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
|
||||
* Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com
|
||||
*
|
||||
* (C) Copyright 2007
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/* define DEBUG for debugging output (obviously ;-)) */
|
||||
#if 0
|
||||
#define DEBUG
|
||||
#endif
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/mmu.h>
|
||||
#include <asm/io.h>
|
||||
#include <ppc440.h>
|
||||
|
||||
#include "sdram.h"
|
||||
|
||||
/*
|
||||
* This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
|
||||
* region. Right now the cache should still be disabled in U-Boot because of the
|
||||
* EMAC driver, that need it's buffer descriptor to be located in non cached
|
||||
* memory.
|
||||
*
|
||||
* If at some time this restriction doesn't apply anymore, just define
|
||||
* CFG_ENABLE_SDRAM_CACHE in the board config file and this code should setup
|
||||
* everything correctly.
|
||||
*/
|
||||
#ifdef CFG_ENABLE_SDRAM_CACHE
|
||||
#define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */
|
||||
#else
|
||||
#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */
|
||||
#endif
|
||||
|
||||
void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value);
|
||||
void dcbz_area(u32 start_address, u32 num_bytes);
|
||||
void dflush(void);
|
||||
|
||||
#ifdef CONFIG_ADD_RAM_INFO
|
||||
static u32 is_ecc_enabled(void)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
mfsdram(DDR0_22, val);
|
||||
val &= DDR0_22_CTRL_RAW_MASK;
|
||||
if (val)
|
||||
return 1;
|
||||
else
|
||||
return 0;
|
||||
}
|
||||
|
||||
void board_add_ram_info(int use_default)
|
||||
{
|
||||
PPC440_SYS_INFO board_cfg;
|
||||
u32 val;
|
||||
|
||||
if (is_ecc_enabled())
|
||||
puts(" (ECC");
|
||||
else
|
||||
puts(" (ECC not");
|
||||
|
||||
get_sys_info(&board_cfg);
|
||||
printf(" enabled, %d MHz", (board_cfg.freqPLB * 2) / 1000000);
|
||||
|
||||
mfsdram(DDR0_03, val);
|
||||
val = DDR0_03_CASLAT_DECODE(val);
|
||||
printf(", CL%d)", val);
|
||||
}
|
||||
#endif
|
||||
|
||||
static int wait_for_dlllock(void)
|
||||
{
|
||||
u32 val;
|
||||
int wait = 0;
|
||||
|
||||
/*
|
||||
* Wait for the DCC master delay line to finish calibration
|
||||
*/
|
||||
mtdcr(ddrcfga, DDR0_17);
|
||||
val = DDR0_17_DLLLOCKREG_UNLOCKED;
|
||||
|
||||
while (wait != 0xffff) {
|
||||
val = mfdcr(ddrcfgd);
|
||||
if ((val & DDR0_17_DLLLOCKREG_MASK) == DDR0_17_DLLLOCKREG_LOCKED)
|
||||
/* dlllockreg bit on */
|
||||
return 0;
|
||||
else
|
||||
wait++;
|
||||
}
|
||||
debug("0x%04x: DDR0_17 Value (dlllockreg bit): 0x%08x\n", wait, val);
|
||||
debug("Waiting for dlllockreg bit to raise\n");
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_DDR_DATA_EYE)
|
||||
int wait_for_dram_init_complete(void)
|
||||
{
|
||||
u32 val;
|
||||
int wait = 0;
|
||||
|
||||
/*
|
||||
* Wait for 'DRAM initialization complete' bit in status register
|
||||
*/
|
||||
mtdcr(ddrcfga, DDR0_00);
|
||||
|
||||
while (wait != 0xffff) {
|
||||
val = mfdcr(ddrcfgd);
|
||||
if ((val & DDR0_00_INT_STATUS_BIT6) == DDR0_00_INT_STATUS_BIT6)
|
||||
/* 'DRAM initialization complete' bit */
|
||||
return 0;
|
||||
else
|
||||
wait++;
|
||||
}
|
||||
|
||||
debug("DRAM initialization complete bit in status register did not rise\n");
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
#define NUM_TRIES 64
|
||||
#define NUM_READS 10
|
||||
|
||||
void denali_core_search_data_eye(u32 start_addr, u32 memory_size)
|
||||
{
|
||||
int k, j;
|
||||
u32 val;
|
||||
u32 wr_dqs_shift, dqs_out_shift, dll_dqs_delay_X;
|
||||
u32 max_passing_cases = 0, wr_dqs_shift_with_max_passing_cases = 0;
|
||||
u32 passing_cases = 0, dll_dqs_delay_X_sw_val = 0;
|
||||
u32 dll_dqs_delay_X_start_window = 0, dll_dqs_delay_X_end_window = 0;
|
||||
volatile u32 *ram_pointer;
|
||||
u32 test[NUM_TRIES] = {
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
|
||||
0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
|
||||
0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
|
||||
0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
|
||||
0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
|
||||
0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
|
||||
0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
|
||||
0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
|
||||
0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
|
||||
0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
|
||||
0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
|
||||
0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 };
|
||||
|
||||
ram_pointer = (volatile u32 *)start_addr;
|
||||
|
||||
for (wr_dqs_shift = 64; wr_dqs_shift < 96; wr_dqs_shift++) {
|
||||
/*for (wr_dqs_shift=1; wr_dqs_shift<96; wr_dqs_shift++) {*/
|
||||
|
||||
/*
|
||||
* De-assert 'start' parameter.
|
||||
*/
|
||||
mtdcr(ddrcfga, DDR0_02);
|
||||
val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF;
|
||||
mtdcr(ddrcfgd, val);
|
||||
|
||||
/*
|
||||
* Set 'wr_dqs_shift'
|
||||
*/
|
||||
mtdcr(ddrcfga, DDR0_09);
|
||||
val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK)
|
||||
| DDR0_09_WR_DQS_SHIFT_ENCODE(wr_dqs_shift);
|
||||
mtdcr(ddrcfgd, val);
|
||||
|
||||
/*
|
||||
* Set 'dqs_out_shift' = wr_dqs_shift + 32
|
||||
*/
|
||||
dqs_out_shift = wr_dqs_shift + 32;
|
||||
mtdcr(ddrcfga, DDR0_22);
|
||||
val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK)
|
||||
| DDR0_22_DQS_OUT_SHIFT_ENCODE(dqs_out_shift);
|
||||
mtdcr(ddrcfgd, val);
|
||||
|
||||
passing_cases = 0;
|
||||
|
||||
for (dll_dqs_delay_X = 1; dll_dqs_delay_X < 64; dll_dqs_delay_X++) {
|
||||
/*for (dll_dqs_delay_X=1; dll_dqs_delay_X<128; dll_dqs_delay_X++) {*/
|
||||
/*
|
||||
* Set 'dll_dqs_delay_X'.
|
||||
*/
|
||||
/* dll_dqs_delay_0 */
|
||||
mtdcr(ddrcfga, DDR0_17);
|
||||
val = (mfdcr(ddrcfgd) & ~DDR0_17_DLL_DQS_DELAY_0_MASK)
|
||||
| DDR0_17_DLL_DQS_DELAY_0_ENCODE(dll_dqs_delay_X);
|
||||
mtdcr(ddrcfgd, val);
|
||||
/* dll_dqs_delay_1 to dll_dqs_delay_4 */
|
||||
mtdcr(ddrcfga, DDR0_18);
|
||||
val = (mfdcr(ddrcfgd) & ~DDR0_18_DLL_DQS_DELAY_X_MASK)
|
||||
| DDR0_18_DLL_DQS_DELAY_4_ENCODE(dll_dqs_delay_X)
|
||||
| DDR0_18_DLL_DQS_DELAY_3_ENCODE(dll_dqs_delay_X)
|
||||
| DDR0_18_DLL_DQS_DELAY_2_ENCODE(dll_dqs_delay_X)
|
||||
| DDR0_18_DLL_DQS_DELAY_1_ENCODE(dll_dqs_delay_X);
|
||||
mtdcr(ddrcfgd, val);
|
||||
/* dll_dqs_delay_5 to dll_dqs_delay_8 */
|
||||
mtdcr(ddrcfga, DDR0_19);
|
||||
val = (mfdcr(ddrcfgd) & ~DDR0_19_DLL_DQS_DELAY_X_MASK)
|
||||
| DDR0_19_DLL_DQS_DELAY_8_ENCODE(dll_dqs_delay_X)
|
||||
| DDR0_19_DLL_DQS_DELAY_7_ENCODE(dll_dqs_delay_X)
|
||||
| DDR0_19_DLL_DQS_DELAY_6_ENCODE(dll_dqs_delay_X)
|
||||
| DDR0_19_DLL_DQS_DELAY_5_ENCODE(dll_dqs_delay_X);
|
||||
mtdcr(ddrcfgd, val);
|
||||
|
||||
ppcMsync();
|
||||
ppcMbar();
|
||||
|
||||
/*
|
||||
* Assert 'start' parameter.
|
||||
*/
|
||||
mtdcr(ddrcfga, DDR0_02);
|
||||
val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_ON;
|
||||
mtdcr(ddrcfgd, val);
|
||||
|
||||
ppcMsync();
|
||||
ppcMbar();
|
||||
|
||||
/*
|
||||
* Wait for the DCC master delay line to finish calibration
|
||||
*/
|
||||
if (wait_for_dlllock() != 0) {
|
||||
printf("dlllock did not occur !!!\n");
|
||||
printf("denali_core_search_data_eye!!!\n");
|
||||
printf("wr_dqs_shift = %d - dll_dqs_delay_X = %d\n",
|
||||
wr_dqs_shift, dll_dqs_delay_X);
|
||||
hang();
|
||||
}
|
||||
ppcMsync();
|
||||
ppcMbar();
|
||||
|
||||
if (wait_for_dram_init_complete() != 0) {
|
||||
printf("dram init complete did not occur !!!\n");
|
||||
printf("denali_core_search_data_eye!!!\n");
|
||||
printf("wr_dqs_shift = %d - dll_dqs_delay_X = %d\n",
|
||||
wr_dqs_shift, dll_dqs_delay_X);
|
||||
hang();
|
||||
}
|
||||
udelay(100); /* wait 100us to ensure init is really completed !!! */
|
||||
|
||||
/* write values */
|
||||
for (j=0; j<NUM_TRIES; j++) {
|
||||
ram_pointer[j] = test[j];
|
||||
|
||||
/* clear any cache at ram location */
|
||||
__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
|
||||
}
|
||||
|
||||
/* read values back */
|
||||
for (j=0; j<NUM_TRIES; j++) {
|
||||
for (k=0; k<NUM_READS; k++) {
|
||||
/* clear any cache at ram location */
|
||||
__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
|
||||
|
||||
if (ram_pointer[j] != test[j])
|
||||
break;
|
||||
}
|
||||
|
||||
/* read error */
|
||||
if (k != NUM_READS)
|
||||
break;
|
||||
}
|
||||
|
||||
/* See if the dll_dqs_delay_X value passed.*/
|
||||
if (j < NUM_TRIES) {
|
||||
/* Failed */
|
||||
passing_cases = 0;
|
||||
/* break; */
|
||||
} else {
|
||||
/* Passed */
|
||||
if (passing_cases == 0)
|
||||
dll_dqs_delay_X_sw_val = dll_dqs_delay_X;
|
||||
passing_cases++;
|
||||
if (passing_cases >= max_passing_cases) {
|
||||
max_passing_cases = passing_cases;
|
||||
wr_dqs_shift_with_max_passing_cases = wr_dqs_shift;
|
||||
dll_dqs_delay_X_start_window = dll_dqs_delay_X_sw_val;
|
||||
dll_dqs_delay_X_end_window = dll_dqs_delay_X;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* De-assert 'start' parameter.
|
||||
*/
|
||||
mtdcr(ddrcfga, DDR0_02);
|
||||
val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF;
|
||||
mtdcr(ddrcfgd, val);
|
||||
|
||||
} /* for (dll_dqs_delay_X=0; dll_dqs_delay_X<128; dll_dqs_delay_X++) */
|
||||
|
||||
} /* for (wr_dqs_shift=0; wr_dqs_shift<96; wr_dqs_shift++) */
|
||||
|
||||
/*
|
||||
* Largest passing window is now detected.
|
||||
*/
|
||||
|
||||
/* Compute dll_dqs_delay_X value */
|
||||
dll_dqs_delay_X = (dll_dqs_delay_X_end_window + dll_dqs_delay_X_start_window) / 2;
|
||||
wr_dqs_shift = wr_dqs_shift_with_max_passing_cases;
|
||||
|
||||
debug("DQS calibration - Window detected:\n");
|
||||
debug("max_passing_cases = %d\n", max_passing_cases);
|
||||
debug("wr_dqs_shift = %d\n", wr_dqs_shift);
|
||||
debug("dll_dqs_delay_X = %d\n", dll_dqs_delay_X);
|
||||
debug("dll_dqs_delay_X window = %d - %d\n",
|
||||
dll_dqs_delay_X_start_window, dll_dqs_delay_X_end_window);
|
||||
|
||||
/*
|
||||
* De-assert 'start' parameter.
|
||||
*/
|
||||
mtdcr(ddrcfga, DDR0_02);
|
||||
val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF;
|
||||
mtdcr(ddrcfgd, val);
|
||||
|
||||
/*
|
||||
* Set 'wr_dqs_shift'
|
||||
*/
|
||||
mtdcr(ddrcfga, DDR0_09);
|
||||
val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK)
|
||||
| DDR0_09_WR_DQS_SHIFT_ENCODE(wr_dqs_shift);
|
||||
mtdcr(ddrcfgd, val);
|
||||
debug("DDR0_09=0x%08lx\n", val);
|
||||
|
||||
/*
|
||||
* Set 'dqs_out_shift' = wr_dqs_shift + 32
|
||||
*/
|
||||
dqs_out_shift = wr_dqs_shift + 32;
|
||||
mtdcr(ddrcfga, DDR0_22);
|
||||
val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK)
|
||||
| DDR0_22_DQS_OUT_SHIFT_ENCODE(dqs_out_shift);
|
||||
mtdcr(ddrcfgd, val);
|
||||
debug("DDR0_22=0x%08lx\n", val);
|
||||
|
||||
/*
|
||||
* Set 'dll_dqs_delay_X'.
|
||||
*/
|
||||
/* dll_dqs_delay_0 */
|
||||
mtdcr(ddrcfga, DDR0_17);
|
||||
val = (mfdcr(ddrcfgd) & ~DDR0_17_DLL_DQS_DELAY_0_MASK)
|
||||
| DDR0_17_DLL_DQS_DELAY_0_ENCODE(dll_dqs_delay_X);
|
||||
mtdcr(ddrcfgd, val);
|
||||
debug("DDR0_17=0x%08lx\n", val);
|
||||
|
||||
/* dll_dqs_delay_1 to dll_dqs_delay_4 */
|
||||
mtdcr(ddrcfga, DDR0_18);
|
||||
val = (mfdcr(ddrcfgd) & ~DDR0_18_DLL_DQS_DELAY_X_MASK)
|
||||
| DDR0_18_DLL_DQS_DELAY_4_ENCODE(dll_dqs_delay_X)
|
||||
| DDR0_18_DLL_DQS_DELAY_3_ENCODE(dll_dqs_delay_X)
|
||||
| DDR0_18_DLL_DQS_DELAY_2_ENCODE(dll_dqs_delay_X)
|
||||
| DDR0_18_DLL_DQS_DELAY_1_ENCODE(dll_dqs_delay_X);
|
||||
mtdcr(ddrcfgd, val);
|
||||
debug("DDR0_18=0x%08lx\n", val);
|
||||
|
||||
/* dll_dqs_delay_5 to dll_dqs_delay_8 */
|
||||
mtdcr(ddrcfga, DDR0_19);
|
||||
val = (mfdcr(ddrcfgd) & ~DDR0_19_DLL_DQS_DELAY_X_MASK)
|
||||
| DDR0_19_DLL_DQS_DELAY_8_ENCODE(dll_dqs_delay_X)
|
||||
| DDR0_19_DLL_DQS_DELAY_7_ENCODE(dll_dqs_delay_X)
|
||||
| DDR0_19_DLL_DQS_DELAY_6_ENCODE(dll_dqs_delay_X)
|
||||
| DDR0_19_DLL_DQS_DELAY_5_ENCODE(dll_dqs_delay_X);
|
||||
mtdcr(ddrcfgd, val);
|
||||
debug("DDR0_19=0x%08lx\n", val);
|
||||
|
||||
/*
|
||||
* Assert 'start' parameter.
|
||||
*/
|
||||
mtdcr(ddrcfga, DDR0_02);
|
||||
val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_ON;
|
||||
mtdcr(ddrcfgd, val);
|
||||
|
||||
ppcMsync();
|
||||
ppcMbar();
|
||||
|
||||
/*
|
||||
* Wait for the DCC master delay line to finish calibration
|
||||
*/
|
||||
if (wait_for_dlllock() != 0) {
|
||||
printf("dlllock did not occur !!!\n");
|
||||
hang();
|
||||
}
|
||||
ppcMsync();
|
||||
ppcMbar();
|
||||
|
||||
if (wait_for_dram_init_complete() != 0) {
|
||||
printf("dram init complete did not occur !!!\n");
|
||||
hang();
|
||||
}
|
||||
udelay(100); /* wait 100us to ensure init is really completed !!! */
|
||||
}
|
||||
#endif /* CONFIG_DDR_DATA_EYE */
|
||||
|
||||
#ifdef CONFIG_DDR_ECC
|
||||
static void wait_ddr_idle(void)
|
||||
{
|
||||
/*
|
||||
* Controller idle status cannot be determined for Denali
|
||||
* DDR2 code. Just return here.
|
||||
*/
|
||||
}
|
||||
|
||||
static void blank_string(int size)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i=0; i<size; i++)
|
||||
putc('\b');
|
||||
for (i=0; i<size; i++)
|
||||
putc(' ');
|
||||
for (i=0; i<size; i++)
|
||||
putc('\b');
|
||||
}
|
||||
|
||||
static void program_ecc(u32 start_address,
|
||||
u32 num_bytes,
|
||||
u32 tlb_word2_i_value)
|
||||
{
|
||||
u32 current_address;
|
||||
u32 end_address;
|
||||
u32 address_increment;
|
||||
u32 val;
|
||||
char str[] = "ECC generation -";
|
||||
char slash[] = "\\|/-\\|/-";
|
||||
int loop = 0;
|
||||
int loopi = 0;
|
||||
|
||||
current_address = start_address;
|
||||
|
||||
sync();
|
||||
eieio();
|
||||
wait_ddr_idle();
|
||||
|
||||
if (tlb_word2_i_value == TLB_WORD2_I_ENABLE) {
|
||||
/* ECC bit set method for non-cached memory */
|
||||
address_increment = 4;
|
||||
end_address = current_address + num_bytes;
|
||||
|
||||
puts(str);
|
||||
|
||||
while (current_address < end_address) {
|
||||
*((u32 *)current_address) = 0x00000000;
|
||||
current_address += address_increment;
|
||||
|
||||
if ((loop++ % (2 << 20)) == 0) {
|
||||
putc('\b');
|
||||
putc(slash[loopi++ % 8]);
|
||||
}
|
||||
}
|
||||
|
||||
blank_string(strlen(str));
|
||||
} else {
|
||||
/* ECC bit set method for cached memory */
|
||||
dcbz_area(start_address, num_bytes);
|
||||
dflush();
|
||||
}
|
||||
|
||||
sync();
|
||||
eieio();
|
||||
wait_ddr_idle();
|
||||
|
||||
/* Clear error status */
|
||||
mfsdram(DDR0_00, val);
|
||||
mtsdram(DDR0_00, val | DDR0_00_INT_ACK_ALL);
|
||||
|
||||
/* Set 'int_mask' parameter to functionnal value */
|
||||
mfsdram(DDR0_01, val);
|
||||
mtsdram(DDR0_01, ((val &~ DDR0_01_INT_MASK_MASK) | DDR0_01_INT_MASK_ALL_OFF));
|
||||
|
||||
sync();
|
||||
eieio();
|
||||
wait_ddr_idle();
|
||||
}
|
||||
#endif
|
||||
|
||||
static __inline__ u32 get_mcsr(void)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
asm volatile("mfspr %0, 0x23c" : "=r" (val) :);
|
||||
return val;
|
||||
}
|
||||
|
||||
static __inline__ void set_mcsr(u32 val)
|
||||
{
|
||||
asm volatile("mtspr 0x23c, %0" : "=r" (val) :);
|
||||
}
|
||||
|
||||
/*************************************************************************
|
||||
*
|
||||
* initdram -- 440EPx's DDR controller is a DENALI Core
|
||||
*
|
||||
************************************************************************/
|
||||
long int initdram (int board_type)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
mtsdram(DDR0_02, 0x00000000);
|
||||
|
||||
mtsdram(DDR0_00, 0x0000190A);
|
||||
mtsdram(DDR0_01, 0x01000000);
|
||||
mtsdram(DDR0_03, 0x02030603); /* A suitable burst length was taken. CAS is right for our board */
|
||||
|
||||
mtsdram(DDR0_04, 0x0A030300);
|
||||
mtsdram(DDR0_05, 0x02020308);
|
||||
mtsdram(DDR0_06, 0x0103C812);
|
||||
mtsdram(DDR0_07, 0x00090100);
|
||||
mtsdram(DDR0_08, 0x02c80001);
|
||||
mtsdram(DDR0_09, 0x00011D5F);
|
||||
mtsdram(DDR0_10, 0x00000300);
|
||||
mtsdram(DDR0_11, 0x000CC800);
|
||||
mtsdram(DDR0_12, 0x00000003);
|
||||
mtsdram(DDR0_14, 0x00000000);
|
||||
mtsdram(DDR0_17, 0x1e000000);
|
||||
mtsdram(DDR0_18, 0x1e1e1e1e);
|
||||
mtsdram(DDR0_19, 0x1e1e1e1e);
|
||||
mtsdram(DDR0_20, 0x0B0B0B0B);
|
||||
mtsdram(DDR0_21, 0x0B0B0B0B);
|
||||
#ifdef CONFIG_DDR_ECC
|
||||
mtsdram(DDR0_22, 0x00267F0B | DDR0_22_CTRL_RAW_ECC_ENABLE); /* enable ECC */
|
||||
#else
|
||||
mtsdram(DDR0_22, 0x00267F0B);
|
||||
#endif
|
||||
|
||||
mtsdram(DDR0_23, 0x01000000);
|
||||
mtsdram(DDR0_24, 0x01010001);
|
||||
|
||||
mtsdram(DDR0_26, 0x2D93028A);
|
||||
mtsdram(DDR0_27, 0x0784682B);
|
||||
|
||||
mtsdram(DDR0_28, 0x00000080);
|
||||
mtsdram(DDR0_31, 0x00000000);
|
||||
mtsdram(DDR0_42, 0x01000006);
|
||||
|
||||
mtsdram(DDR0_43, 0x030A0200);
|
||||
mtsdram(DDR0_44, 0x00000003);
|
||||
mtsdram(DDR0_02, 0x00000001); /* Activate the denali core */
|
||||
|
||||
wait_for_dlllock();
|
||||
|
||||
/*
|
||||
* Program tlb entries for this size (dynamic)
|
||||
*/
|
||||
program_tlb(0, 0, CFG_MBYTES_SDRAM << 20, MY_TLB_WORD2_I_ENABLE);
|
||||
|
||||
/*
|
||||
* Setup 2nd TLB with same physical address but different virtual address
|
||||
* with cache enabled. This is done for fast ECC generation.
|
||||
*/
|
||||
program_tlb(0, CFG_DDR_CACHED_ADDR, CFG_MBYTES_SDRAM << 20, 0);
|
||||
|
||||
#ifdef CONFIG_DDR_DATA_EYE
|
||||
/*
|
||||
* Perform data eye search if requested.
|
||||
*/
|
||||
denali_core_search_data_eye(CFG_DDR_CACHED_ADDR, CFG_MBYTES_SDRAM << 20);
|
||||
|
||||
/*
|
||||
* Clear possible errors resulting from data-eye-search.
|
||||
* If not done, then we could get an interrupt later on when
|
||||
* exceptions are enabled.
|
||||
*/
|
||||
val = get_mcsr();
|
||||
set_mcsr(val);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_DDR_ECC
|
||||
/*
|
||||
* If ECC is enabled, initialize the parity bits.
|
||||
*/
|
||||
program_ecc(CFG_DDR_CACHED_ADDR, CFG_MBYTES_SDRAM << 20, 0);
|
||||
#endif
|
||||
|
||||
return (CFG_MBYTES_SDRAM << 20);
|
||||
}
|
||||
|
|
@ -0,0 +1,505 @@
|
|||
/*
|
||||
* (C) Copyright 2006
|
||||
* Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com
|
||||
* Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
|
||||
* Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com
|
||||
* Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
|
||||
* Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef _SPD_SDRAM_DENALI_H_
|
||||
#define _SPD_SDRAM_DENALI_H_
|
||||
|
||||
#define ppcMsync sync
|
||||
#define ppcMbar eieio
|
||||
|
||||
/* General definitions */
|
||||
#define MAX_SPD_BYTE 128 /* highest SPD byte # to read */
|
||||
#define DENALI_REG_NUMBER 45 /* 45 Regs in PPC440EPx Denali Core */
|
||||
#define SUPPORTED_DIMMS_NB 7 /* Number of supported DIMM modules types */
|
||||
#define SDRAM_NONE 0 /* No DIMM detected in Slot */
|
||||
#define MAXRANKS 2 /* 2 ranks maximum */
|
||||
|
||||
/* Supported PLB Frequencies */
|
||||
#define PLB_FREQ_133MHZ 133333333
|
||||
#define PLB_FREQ_152MHZ 152000000
|
||||
#define PLB_FREQ_160MHZ 160000000
|
||||
#define PLB_FREQ_166MHZ 166666666
|
||||
|
||||
/* Denali Core Registers */
|
||||
#define SDRAM_DCR_BASE 0x10
|
||||
|
||||
#define DDR_DCR_BASE 0x10
|
||||
#define ddrcfga (DDR_DCR_BASE+0x0) /* DDR configuration address reg */
|
||||
#define ddrcfgd (DDR_DCR_BASE+0x1) /* DDR configuration data reg */
|
||||
|
||||
/*-----------------------------------------------------------------------------+
|
||||
| Values for ddrcfga register - indirect addressing of these regs
|
||||
+-----------------------------------------------------------------------------*/
|
||||
|
||||
#define DDR0_00 0x00
|
||||
#define DDR0_00_INT_ACK_MASK 0x7F000000 /* Write only */
|
||||
#define DDR0_00_INT_ACK_ALL 0x7F000000
|
||||
#define DDR0_00_INT_ACK_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
|
||||
#define DDR0_00_INT_ACK_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
|
||||
/* Status */
|
||||
#define DDR0_00_INT_STATUS_MASK 0x00FF0000 /* Read only */
|
||||
/* Bit0. A single access outside the defined PHYSICAL memory space detected. */
|
||||
#define DDR0_00_INT_STATUS_BIT0 0x00010000
|
||||
/* Bit1. Multiple accesses outside the defined PHYSICAL memory space detected. */
|
||||
#define DDR0_00_INT_STATUS_BIT1 0x00020000
|
||||
/* Bit2. Single correctable ECC event detected */
|
||||
#define DDR0_00_INT_STATUS_BIT2 0x00040000
|
||||
/* Bit3. Multiple correctable ECC events detected. */
|
||||
#define DDR0_00_INT_STATUS_BIT3 0x00080000
|
||||
/* Bit4. Single uncorrectable ECC event detected. */
|
||||
#define DDR0_00_INT_STATUS_BIT4 0x00100000
|
||||
/* Bit5. Multiple uncorrectable ECC events detected. */
|
||||
#define DDR0_00_INT_STATUS_BIT5 0x00200000
|
||||
/* Bit6. DRAM initialization complete. */
|
||||
#define DDR0_00_INT_STATUS_BIT6 0x00400000
|
||||
/* Bit7. Logical OR of all lower bits. */
|
||||
#define DDR0_00_INT_STATUS_BIT7 0x00800000
|
||||
|
||||
#define DDR0_00_INT_STATUS_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16)
|
||||
#define DDR0_00_INT_STATUS_DECODE(n) ((((unsigned long)(n))>>16)&0xFF)
|
||||
#define DDR0_00_DLL_INCREMENT_MASK 0x00007F00
|
||||
#define DDR0_00_DLL_INCREMENT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
|
||||
#define DDR0_00_DLL_INCREMENT_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
|
||||
#define DDR0_00_DLL_START_POINT_MASK 0x0000007F
|
||||
#define DDR0_00_DLL_START_POINT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
|
||||
#define DDR0_00_DLL_START_POINT_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
|
||||
|
||||
|
||||
#define DDR0_01 0x01
|
||||
#define DDR0_01_PLB0_DB_CS_LOWER_MASK 0x1F000000
|
||||
#define DDR0_01_PLB0_DB_CS_LOWER_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
|
||||
#define DDR0_01_PLB0_DB_CS_LOWER_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
|
||||
#define DDR0_01_PLB0_DB_CS_UPPER_MASK 0x001F0000
|
||||
#define DDR0_01_PLB0_DB_CS_UPPER_ENCODE(n) ((((unsigned long)(n))&0x1F)<<16)
|
||||
#define DDR0_01_PLB0_DB_CS_UPPER_DECODE(n) ((((unsigned long)(n))>>16)&0x1F)
|
||||
#define DDR0_01_OUT_OF_RANGE_TYPE_MASK 0x00000700 /* Read only */
|
||||
#define DDR0_01_OUT_OF_RANGE_TYPE_ENCODE(n) ((((unsigned long)(n))&0x7)<<8)
|
||||
#define DDR0_01_OUT_OF_RANGE_TYPE_DECODE(n) ((((unsigned long)(n))>>8)&0x7)
|
||||
#define DDR0_01_INT_MASK_MASK 0x000000FF
|
||||
#define DDR0_01_INT_MASK_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0)
|
||||
#define DDR0_01_INT_MASK_DECODE(n) ((((unsigned long)(n))>>0)&0xFF)
|
||||
#define DDR0_01_INT_MASK_ALL_ON 0x000000FF
|
||||
#define DDR0_01_INT_MASK_ALL_OFF 0x00000000
|
||||
|
||||
#define DDR0_02 0x02
|
||||
#define DDR0_02_MAX_CS_REG_MASK 0x02000000 /* Read only */
|
||||
#define DDR0_02_MAX_CS_REG_ENCODE(n) ((((unsigned long)(n))&0x2)<<24)
|
||||
#define DDR0_02_MAX_CS_REG_DECODE(n) ((((unsigned long)(n))>>24)&0x2)
|
||||
#define DDR0_02_MAX_COL_REG_MASK 0x000F0000 /* Read only */
|
||||
#define DDR0_02_MAX_COL_REG_ENCODE(n) ((((unsigned long)(n))&0xF)<<16)
|
||||
#define DDR0_02_MAX_COL_REG_DECODE(n) ((((unsigned long)(n))>>16)&0xF)
|
||||
#define DDR0_02_MAX_ROW_REG_MASK 0x00000F00 /* Read only */
|
||||
#define DDR0_02_MAX_ROW_REG_ENCODE(n) ((((unsigned long)(n))&0xF)<<8)
|
||||
#define DDR0_02_MAX_ROW_REG_DECODE(n) ((((unsigned long)(n))>>8)&0xF)
|
||||
#define DDR0_02_START_MASK 0x00000001
|
||||
#define DDR0_02_START_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
|
||||
#define DDR0_02_START_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
|
||||
#define DDR0_02_START_OFF 0x00000000
|
||||
#define DDR0_02_START_ON 0x00000001
|
||||
|
||||
#define DDR0_03 0x03
|
||||
#define DDR0_03_BSTLEN_MASK 0x07000000
|
||||
#define DDR0_03_BSTLEN_ENCODE(n) ((((unsigned long)(n))&0x7)<<24)
|
||||
#define DDR0_03_BSTLEN_DECODE(n) ((((unsigned long)(n))>>24)&0x7)
|
||||
#define DDR0_03_CASLAT_MASK 0x00070000
|
||||
#define DDR0_03_CASLAT_ENCODE(n) ((((unsigned long)(n))&0x7)<<16)
|
||||
#define DDR0_03_CASLAT_DECODE(n) ((((unsigned long)(n))>>16)&0x7)
|
||||
#define DDR0_03_CASLAT_LIN_MASK 0x00000F00
|
||||
#define DDR0_03_CASLAT_LIN_ENCODE(n) ((((unsigned long)(n))&0xF)<<8)
|
||||
#define DDR0_03_CASLAT_LIN_DECODE(n) ((((unsigned long)(n))>>8)&0xF)
|
||||
#define DDR0_03_INITAREF_MASK 0x0000000F
|
||||
#define DDR0_03_INITAREF_ENCODE(n) ((((unsigned long)(n))&0xF)<<0)
|
||||
#define DDR0_03_INITAREF_DECODE(n) ((((unsigned long)(n))>>0)&0xF)
|
||||
|
||||
#define DDR0_04 0x04
|
||||
#define DDR0_04_TRC_MASK 0x1F000000
|
||||
#define DDR0_04_TRC_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
|
||||
#define DDR0_04_TRC_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
|
||||
#define DDR0_04_TRRD_MASK 0x00070000
|
||||
#define DDR0_04_TRRD_ENCODE(n) ((((unsigned long)(n))&0x7)<<16)
|
||||
#define DDR0_04_TRRD_DECODE(n) ((((unsigned long)(n))>>16)&0x7)
|
||||
#define DDR0_04_TRTP_MASK 0x00000700
|
||||
#define DDR0_04_TRTP_ENCODE(n) ((((unsigned long)(n))&0x7)<<8)
|
||||
#define DDR0_04_TRTP_DECODE(n) ((((unsigned long)(n))>>8)&0x7)
|
||||
|
||||
#define DDR0_05 0x05
|
||||
#define DDR0_05_TMRD_MASK 0x1F000000
|
||||
#define DDR0_05_TMRD_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
|
||||
#define DDR0_05_TMRD_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
|
||||
#define DDR0_05_TEMRS_MASK 0x00070000
|
||||
#define DDR0_05_TEMRS_ENCODE(n) ((((unsigned long)(n))&0x7)<<16)
|
||||
#define DDR0_05_TEMRS_DECODE(n) ((((unsigned long)(n))>>16)&0x7)
|
||||
#define DDR0_05_TRP_MASK 0x00000F00
|
||||
#define DDR0_05_TRP_ENCODE(n) ((((unsigned long)(n))&0xF)<<8)
|
||||
#define DDR0_05_TRP_DECODE(n) ((((unsigned long)(n))>>8)&0xF)
|
||||
#define DDR0_05_TRAS_MIN_MASK 0x000000FF
|
||||
#define DDR0_05_TRAS_MIN_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0)
|
||||
#define DDR0_05_TRAS_MIN_DECODE(n) ((((unsigned long)(n))>>0)&0xFF)
|
||||
|
||||
#define DDR0_06 0x06
|
||||
#define DDR0_06_WRITEINTERP_MASK 0x01000000
|
||||
#define DDR0_06_WRITEINTERP_ENCODE(n) ((((unsigned long)(n))&0x1)<<24)
|
||||
#define DDR0_06_WRITEINTERP_DECODE(n) ((((unsigned long)(n))>>24)&0x1)
|
||||
#define DDR0_06_TWTR_MASK 0x00070000
|
||||
#define DDR0_06_TWTR_ENCODE(n) ((((unsigned long)(n))&0x7)<<16)
|
||||
#define DDR0_06_TWTR_DECODE(n) ((((unsigned long)(n))>>16)&0x7)
|
||||
#define DDR0_06_TDLL_MASK 0x0000FF00
|
||||
#define DDR0_06_TDLL_ENCODE(n) ((((unsigned long)(n))&0xFF)<<8)
|
||||
#define DDR0_06_TDLL_DECODE(n) ((((unsigned long)(n))>>8)&0xFF)
|
||||
#define DDR0_06_TRFC_MASK 0x0000007F
|
||||
#define DDR0_06_TRFC_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
|
||||
#define DDR0_06_TRFC_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
|
||||
|
||||
#define DDR0_07 0x07
|
||||
#define DDR0_07_NO_CMD_INIT_MASK 0x01000000
|
||||
#define DDR0_07_NO_CMD_INIT_ENCODE(n) ((((unsigned long)(n))&0x1)<<24)
|
||||
#define DDR0_07_NO_CMD_INIT_DECODE(n) ((((unsigned long)(n))>>24)&0x1)
|
||||
#define DDR0_07_TFAW_MASK 0x001F0000
|
||||
#define DDR0_07_TFAW_ENCODE(n) ((((unsigned long)(n))&0x1F)<<16)
|
||||
#define DDR0_07_TFAW_DECODE(n) ((((unsigned long)(n))>>16)&0x1F)
|
||||
#define DDR0_07_AUTO_REFRESH_MODE_MASK 0x00000100
|
||||
#define DDR0_07_AUTO_REFRESH_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<8)
|
||||
#define DDR0_07_AUTO_REFRESH_MODE_DECODE(n) ((((unsigned long)(n))>>8)&0x1)
|
||||
#define DDR0_07_AREFRESH_MASK 0x00000001
|
||||
#define DDR0_07_AREFRESH_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
|
||||
#define DDR0_07_AREFRESH_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
|
||||
|
||||
#define DDR0_08 0x08
|
||||
#define DDR0_08_WRLAT_MASK 0x07000000
|
||||
#define DDR0_08_WRLAT_ENCODE(n) ((((unsigned long)(n))&0x7)<<24)
|
||||
#define DDR0_08_WRLAT_DECODE(n) ((((unsigned long)(n))>>24)&0x7)
|
||||
#define DDR0_08_TCPD_MASK 0x00FF0000
|
||||
#define DDR0_08_TCPD_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16)
|
||||
#define DDR0_08_TCPD_DECODE(n) ((((unsigned long)(n))>>16)&0xFF)
|
||||
#define DDR0_08_DQS_N_EN_MASK 0x00000100
|
||||
#define DDR0_08_DQS_N_EN_ENCODE(n) ((((unsigned long)(n))&0x1)<<8)
|
||||
#define DDR0_08_DQS_N_EN_DECODE(n) ((((unsigned long)(n))>>8)&0x1)
|
||||
#define DDR0_08_DDRII_SDRAM_MODE_MASK 0x00000001
|
||||
#define DDR0_08_DDRII_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
|
||||
#define DDR0_08_DDRII_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
|
||||
|
||||
#define DDR0_09 0x09
|
||||
#define DDR0_09_OCD_ADJUST_PDN_CS_0_MASK 0x1F000000
|
||||
#define DDR0_09_OCD_ADJUST_PDN_CS_0_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
|
||||
#define DDR0_09_OCD_ADJUST_PDN_CS_0_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
|
||||
#define DDR0_09_RTT_0_MASK 0x00030000
|
||||
#define DDR0_09_RTT_0_ENCODE(n) ((((unsigned long)(n))&0x3)<<16)
|
||||
#define DDR0_09_RTT_0_DECODE(n) ((((unsigned long)(n))>>16)&0x3)
|
||||
#define DDR0_09_WR_DQS_SHIFT_BYPASS_MASK 0x00007F00
|
||||
#define DDR0_09_WR_DQS_SHIFT_BYPASS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
|
||||
#define DDR0_09_WR_DQS_SHIFT_BYPASS_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
|
||||
#define DDR0_09_WR_DQS_SHIFT_MASK 0x0000007F
|
||||
#define DDR0_09_WR_DQS_SHIFT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
|
||||
#define DDR0_09_WR_DQS_SHIFT_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
|
||||
|
||||
#define DDR0_10 0x0A
|
||||
#define DDR0_10_WRITE_MODEREG_MASK 0x00010000 /* Write only */
|
||||
#define DDR0_10_WRITE_MODEREG_ENCODE(n) ((((unsigned long)(n))&0x1)<<16)
|
||||
#define DDR0_10_WRITE_MODEREG_DECODE(n) ((((unsigned long)(n))>>16)&0x1)
|
||||
#define DDR0_10_CS_MAP_MASK 0x00000300
|
||||
#define DDR0_10_CS_MAP_NO_MEM 0x00000000
|
||||
#define DDR0_10_CS_MAP_RANK0_INSTALLED 0x00000100
|
||||
#define DDR0_10_CS_MAP_RANK1_INSTALLED 0x00000200
|
||||
#define DDR0_10_CS_MAP_ENCODE(n) ((((unsigned long)(n))&0x3)<<8)
|
||||
#define DDR0_10_CS_MAP_DECODE(n) ((((unsigned long)(n))>>8)&0x3)
|
||||
#define DDR0_10_OCD_ADJUST_PUP_CS_0_MASK 0x0000001F
|
||||
#define DDR0_10_OCD_ADJUST_PUP_CS_0_ENCODE(n) ((((unsigned long)(n))&0x1F)<<0)
|
||||
#define DDR0_10_OCD_ADJUST_PUP_CS_0_DECODE(n) ((((unsigned long)(n))>>0)&0x1F)
|
||||
|
||||
#define DDR0_11 0x0B
|
||||
#define DDR0_11_SREFRESH_MASK 0x01000000
|
||||
#define DDR0_11_SREFRESH_ENCODE(n) ((((unsigned long)(n))&0x1)<<24)
|
||||
#define DDR0_11_SREFRESH_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
|
||||
#define DDR0_11_TXSNR_MASK 0x00FF0000
|
||||
#define DDR0_11_TXSNR_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16)
|
||||
#define DDR0_11_TXSNR_DECODE(n) ((((unsigned long)(n))>>16)&0xFF)
|
||||
#define DDR0_11_TXSR_MASK 0x0000FF00
|
||||
#define DDR0_11_TXSR_ENCODE(n) ((((unsigned long)(n))&0xFF)<<8)
|
||||
#define DDR0_11_TXSR_DECODE(n) ((((unsigned long)(n))>>8)&0xFF)
|
||||
|
||||
#define DDR0_12 0x0C
|
||||
#define DDR0_12_TCKE_MASK 0x0000007
|
||||
#define DDR0_12_TCKE_ENCODE(n) ((((unsigned long)(n))&0x7)<<0)
|
||||
#define DDR0_12_TCKE_DECODE(n) ((((unsigned long)(n))>>0)&0x7)
|
||||
|
||||
#define DDR0_13 0x0D
|
||||
|
||||
#define DDR0_14 0x0E
|
||||
#define DDR0_14_DLL_BYPASS_MODE_MASK 0x01000000
|
||||
#define DDR0_14_DLL_BYPASS_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<24)
|
||||
#define DDR0_14_DLL_BYPASS_MODE_DECODE(n) ((((unsigned long)(n))>>24)&0x1)
|
||||
#define DDR0_14_REDUC_MASK 0x00010000
|
||||
#define DDR0_14_REDUC_64BITS 0x00000000
|
||||
#define DDR0_14_REDUC_32BITS 0x00010000
|
||||
#define DDR0_14_REDUC_ENCODE(n) ((((unsigned long)(n))&0x1)<<16)
|
||||
#define DDR0_14_REDUC_DECODE(n) ((((unsigned long)(n))>>16)&0x1)
|
||||
#define DDR0_14_REG_DIMM_ENABLE_MASK 0x00000100
|
||||
#define DDR0_14_REG_DIMM_ENABLE_ENCODE(n) ((((unsigned long)(n))&0x1)<<8)
|
||||
#define DDR0_14_REG_DIMM_ENABLE_DECODE(n) ((((unsigned long)(n))>>8)&0x1)
|
||||
|
||||
#define DDR0_15 0x0F
|
||||
|
||||
#define DDR0_16 0x10
|
||||
|
||||
#define DDR0_17 0x11
|
||||
#define DDR0_17_DLL_DQS_DELAY_0_MASK 0x7F000000
|
||||
#define DDR0_17_DLL_DQS_DELAY_0_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
|
||||
#define DDR0_17_DLL_DQS_DELAY_0_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
|
||||
#define DDR0_17_DLLLOCKREG_MASK 0x00010000 /* Read only */
|
||||
#define DDR0_17_DLLLOCKREG_LOCKED 0x00010000
|
||||
#define DDR0_17_DLLLOCKREG_UNLOCKED 0x00000000
|
||||
#define DDR0_17_DLLLOCKREG_ENCODE(n) ((((unsigned long)(n))&0x1)<<16)
|
||||
#define DDR0_17_DLLLOCKREG_DECODE(n) ((((unsigned long)(n))>>16)&0x1)
|
||||
#define DDR0_17_DLL_LOCK_MASK 0x00007F00 /* Read only */
|
||||
#define DDR0_17_DLL_LOCK_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
|
||||
#define DDR0_17_DLL_LOCK_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
|
||||
|
||||
#define DDR0_18 0x12
|
||||
#define DDR0_18_DLL_DQS_DELAY_X_MASK 0x7F7F7F7F
|
||||
#define DDR0_18_DLL_DQS_DELAY_4_MASK 0x7F000000
|
||||
#define DDR0_18_DLL_DQS_DELAY_4_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
|
||||
#define DDR0_18_DLL_DQS_DELAY_4_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
|
||||
#define DDR0_18_DLL_DQS_DELAY_3_MASK 0x007F0000
|
||||
#define DDR0_18_DLL_DQS_DELAY_3_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
|
||||
#define DDR0_18_DLL_DQS_DELAY_3_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
|
||||
#define DDR0_18_DLL_DQS_DELAY_2_MASK 0x00007F00
|
||||
#define DDR0_18_DLL_DQS_DELAY_2_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
|
||||
#define DDR0_18_DLL_DQS_DELAY_2_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
|
||||
#define DDR0_18_DLL_DQS_DELAY_1_MASK 0x0000007F
|
||||
#define DDR0_18_DLL_DQS_DELAY_1_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
|
||||
#define DDR0_18_DLL_DQS_DELAY_1_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
|
||||
|
||||
#define DDR0_19 0x13
|
||||
#define DDR0_19_DLL_DQS_DELAY_X_MASK 0x7F7F7F7F
|
||||
#define DDR0_19_DLL_DQS_DELAY_8_MASK 0x7F000000
|
||||
#define DDR0_19_DLL_DQS_DELAY_8_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
|
||||
#define DDR0_19_DLL_DQS_DELAY_8_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
|
||||
#define DDR0_19_DLL_DQS_DELAY_7_MASK 0x007F0000
|
||||
#define DDR0_19_DLL_DQS_DELAY_7_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
|
||||
#define DDR0_19_DLL_DQS_DELAY_7_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
|
||||
#define DDR0_19_DLL_DQS_DELAY_6_MASK 0x00007F00
|
||||
#define DDR0_19_DLL_DQS_DELAY_6_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
|
||||
#define DDR0_19_DLL_DQS_DELAY_6_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
|
||||
#define DDR0_19_DLL_DQS_DELAY_5_MASK 0x0000007F
|
||||
#define DDR0_19_DLL_DQS_DELAY_5_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
|
||||
#define DDR0_19_DLL_DQS_DELAY_5_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
|
||||
|
||||
#define DDR0_20 0x14
|
||||
#define DDR0_20_DLL_DQS_BYPASS_3_MASK 0x7F000000
|
||||
#define DDR0_20_DLL_DQS_BYPASS_3_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
|
||||
#define DDR0_20_DLL_DQS_BYPASS_3_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
|
||||
#define DDR0_20_DLL_DQS_BYPASS_2_MASK 0x007F0000
|
||||
#define DDR0_20_DLL_DQS_BYPASS_2_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
|
||||
#define DDR0_20_DLL_DQS_BYPASS_2_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
|
||||
#define DDR0_20_DLL_DQS_BYPASS_1_MASK 0x00007F00
|
||||
#define DDR0_20_DLL_DQS_BYPASS_1_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
|
||||
#define DDR0_20_DLL_DQS_BYPASS_1_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
|
||||
#define DDR0_20_DLL_DQS_BYPASS_0_MASK 0x0000007F
|
||||
#define DDR0_20_DLL_DQS_BYPASS_0_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
|
||||
#define DDR0_20_DLL_DQS_BYPASS_0_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
|
||||
|
||||
#define DDR0_21 0x15
|
||||
#define DDR0_21_DLL_DQS_BYPASS_7_MASK 0x7F000000
|
||||
#define DDR0_21_DLL_DQS_BYPASS_7_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
|
||||
#define DDR0_21_DLL_DQS_BYPASS_7_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
|
||||
#define DDR0_21_DLL_DQS_BYPASS_6_MASK 0x007F0000
|
||||
#define DDR0_21_DLL_DQS_BYPASS_6_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
|
||||
#define DDR0_21_DLL_DQS_BYPASS_6_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
|
||||
#define DDR0_21_DLL_DQS_BYPASS_5_MASK 0x00007F00
|
||||
#define DDR0_21_DLL_DQS_BYPASS_5_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
|
||||
#define DDR0_21_DLL_DQS_BYPASS_5_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
|
||||
#define DDR0_21_DLL_DQS_BYPASS_4_MASK 0x0000007F
|
||||
#define DDR0_21_DLL_DQS_BYPASS_4_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
|
||||
#define DDR0_21_DLL_DQS_BYPASS_4_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
|
||||
|
||||
#define DDR0_22 0x16
|
||||
/* ECC */
|
||||
#define DDR0_22_CTRL_RAW_MASK 0x03000000
|
||||
#define DDR0_22_CTRL_RAW_ECC_DISABLE 0x00000000 /* ECC not being used */
|
||||
#define DDR0_22_CTRL_RAW_ECC_CHECK_ONLY 0x01000000 /* ECC checking is on, but no attempts to correct*/
|
||||
#define DDR0_22_CTRL_RAW_NO_ECC_RAM 0x02000000 /* No ECC RAM storage available */
|
||||
#define DDR0_22_CTRL_RAW_ECC_ENABLE 0x03000000 /* ECC checking and correcting on */
|
||||
#define DDR0_22_CTRL_RAW_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
|
||||
#define DDR0_22_CTRL_RAW_DECODE(n) ((((unsigned long)(n))>>24)&0x3)
|
||||
|
||||
#define DDR0_22_DQS_OUT_SHIFT_BYPASS_MASK 0x007F0000
|
||||
#define DDR0_22_DQS_OUT_SHIFT_BYPASS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
|
||||
#define DDR0_22_DQS_OUT_SHIFT_BYPASS_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
|
||||
#define DDR0_22_DQS_OUT_SHIFT_MASK 0x00007F00
|
||||
#define DDR0_22_DQS_OUT_SHIFT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
|
||||
#define DDR0_22_DQS_OUT_SHIFT_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
|
||||
#define DDR0_22_DLL_DQS_BYPASS_8_MASK 0x0000007F
|
||||
#define DDR0_22_DLL_DQS_BYPASS_8_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
|
||||
#define DDR0_22_DLL_DQS_BYPASS_8_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
|
||||
|
||||
|
||||
#define DDR0_23 0x17
|
||||
#define DDR0_23_ODT_RD_MAP_CS0_MASK 0x03000000
|
||||
#define DDR0_23_ODT_RD_MAP_CS0_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
|
||||
#define DDR0_23_ODT_RD_MAP_CS0_DECODE(n) ((((unsigned long)(n))>>24)&0x3)
|
||||
#define DDR0_23_ECC_C_SYND_MASK 0x00FF0000 /* Read only */
|
||||
#define DDR0_23_ECC_C_SYND_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16)
|
||||
#define DDR0_23_ECC_C_SYND_DECODE(n) ((((unsigned long)(n))>>16)&0xFF)
|
||||
#define DDR0_23_ECC_U_SYND_MASK 0x0000FF00 /* Read only */
|
||||
#define DDR0_23_ECC_U_SYND_ENCODE(n) ((((unsigned long)(n))&0xFF)<<8)
|
||||
#define DDR0_23_ECC_U_SYND_DECODE(n) ((((unsigned long)(n))>>8)&0xFF)
|
||||
#define DDR0_23_FWC_MASK 0x00000001 /* Write only */
|
||||
#define DDR0_23_FWC_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
|
||||
#define DDR0_23_FWC_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
|
||||
|
||||
#define DDR0_24 0x18
|
||||
#define DDR0_24_RTT_PAD_TERMINATION_MASK 0x03000000
|
||||
#define DDR0_24_RTT_PAD_TERMINATION_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
|
||||
#define DDR0_24_RTT_PAD_TERMINATION_DECODE(n) ((((unsigned long)(n))>>24)&0x3)
|
||||
#define DDR0_24_ODT_WR_MAP_CS1_MASK 0x00030000
|
||||
#define DDR0_24_ODT_WR_MAP_CS1_ENCODE(n) ((((unsigned long)(n))&0x3)<<16)
|
||||
#define DDR0_24_ODT_WR_MAP_CS1_DECODE(n) ((((unsigned long)(n))>>16)&0x3)
|
||||
#define DDR0_24_ODT_RD_MAP_CS1_MASK 0x00000300
|
||||
#define DDR0_24_ODT_RD_MAP_CS1_ENCODE(n) ((((unsigned long)(n))&0x3)<<8)
|
||||
#define DDR0_24_ODT_RD_MAP_CS1_DECODE(n) ((((unsigned long)(n))>>8)&0x3)
|
||||
#define DDR0_24_ODT_WR_MAP_CS0_MASK 0x00000003
|
||||
#define DDR0_24_ODT_WR_MAP_CS0_ENCODE(n) ((((unsigned long)(n))&0x3)<<0)
|
||||
#define DDR0_24_ODT_WR_MAP_CS0_DECODE(n) ((((unsigned long)(n))>>0)&0x3)
|
||||
|
||||
#define DDR0_25 0x19
|
||||
#define DDR0_25_VERSION_MASK 0xFFFF0000 /* Read only */
|
||||
#define DDR0_25_VERSION_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16)
|
||||
#define DDR0_25_VERSION_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF)
|
||||
#define DDR0_25_OUT_OF_RANGE_LENGTH_MASK 0x000003FF /* Read only */
|
||||
#define DDR0_25_OUT_OF_RANGE_LENGTH_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0)
|
||||
#define DDR0_25_OUT_OF_RANGE_LENGTH_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF)
|
||||
|
||||
#define DDR0_26 0x1A
|
||||
#define DDR0_26_TRAS_MAX_MASK 0xFFFF0000
|
||||
#define DDR0_26_TRAS_MAX_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16)
|
||||
#define DDR0_26_TRAS_MAX_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF)
|
||||
#define DDR0_26_TREF_MASK 0x00003FFF
|
||||
#define DDR0_26_TREF_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0)
|
||||
#define DDR0_26_TREF_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF)
|
||||
|
||||
#define DDR0_27 0x1B
|
||||
#define DDR0_27_EMRS_DATA_MASK 0x3FFF0000
|
||||
#define DDR0_27_EMRS_DATA_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<16)
|
||||
#define DDR0_27_EMRS_DATA_DECODE(n) ((((unsigned long)(n))>>16)&0x3FFF)
|
||||
#define DDR0_27_TINIT_MASK 0x0000FFFF
|
||||
#define DDR0_27_TINIT_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<0)
|
||||
#define DDR0_27_TINIT_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFF)
|
||||
|
||||
#define DDR0_28 0x1C
|
||||
#define DDR0_28_EMRS3_DATA_MASK 0x3FFF0000
|
||||
#define DDR0_28_EMRS3_DATA_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<16)
|
||||
#define DDR0_28_EMRS3_DATA_DECODE(n) ((((unsigned long)(n))>>16)&0x3FFF)
|
||||
#define DDR0_28_EMRS2_DATA_MASK 0x00003FFF
|
||||
#define DDR0_28_EMRS2_DATA_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<0)
|
||||
#define DDR0_28_EMRS2_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0x3FFF)
|
||||
|
||||
#define DDR0_29 0x1D
|
||||
|
||||
#define DDR0_30 0x1E
|
||||
|
||||
#define DDR0_31 0x1F
|
||||
#define DDR0_31_XOR_CHECK_BITS_MASK 0x0000FFFF
|
||||
#define DDR0_31_XOR_CHECK_BITS_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<0)
|
||||
#define DDR0_31_XOR_CHECK_BITS_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFF)
|
||||
|
||||
#define DDR0_32 0x20
|
||||
#define DDR0_32_OUT_OF_RANGE_ADDR_MASK 0xFFFFFFFF /* Read only */
|
||||
#define DDR0_32_OUT_OF_RANGE_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
|
||||
#define DDR0_32_OUT_OF_RANGE_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
|
||||
|
||||
#define DDR0_33 0x21
|
||||
#define DDR0_33_OUT_OF_RANGE_ADDR_MASK 0x00000001 /* Read only */
|
||||
#define DDR0_33_OUT_OF_RANGE_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
|
||||
#define DDR0_33_OUT_OF_RANGE_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
|
||||
|
||||
#define DDR0_34 0x22
|
||||
#define DDR0_34_ECC_U_ADDR_MASK 0xFFFFFFFF /* Read only */
|
||||
#define DDR0_34_ECC_U_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
|
||||
#define DDR0_34_ECC_U_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
|
||||
|
||||
#define DDR0_35 0x23
|
||||
#define DDR0_35_ECC_U_ADDR_MASK 0x00000001 /* Read only */
|
||||
#define DDR0_35_ECC_U_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
|
||||
#define DDR0_35_ECC_U_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
|
||||
|
||||
#define DDR0_36 0x24
|
||||
#define DDR0_36_ECC_U_DATA_MASK 0xFFFFFFFF /* Read only */
|
||||
#define DDR0_36_ECC_U_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
|
||||
#define DDR0_36_ECC_U_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
|
||||
|
||||
#define DDR0_37 0x25
|
||||
#define DDR0_37_ECC_U_DATA_MASK 0xFFFFFFFF /* Read only */
|
||||
#define DDR0_37_ECC_U_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
|
||||
#define DDR0_37_ECC_U_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
|
||||
|
||||
#define DDR0_38 0x26
|
||||
#define DDR0_38_ECC_C_ADDR_MASK 0xFFFFFFFF /* Read only */
|
||||
#define DDR0_38_ECC_C_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
|
||||
#define DDR0_38_ECC_C_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
|
||||
|
||||
#define DDR0_39 0x27
|
||||
#define DDR0_39_ECC_C_ADDR_MASK 0x00000001 /* Read only */
|
||||
#define DDR0_39_ECC_C_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
|
||||
#define DDR0_39_ECC_C_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
|
||||
|
||||
#define DDR0_40 0x28
|
||||
#define DDR0_40_ECC_C_DATA_MASK 0xFFFFFFFF /* Read only */
|
||||
#define DDR0_40_ECC_C_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
|
||||
#define DDR0_40_ECC_C_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
|
||||
|
||||
#define DDR0_41 0x29
|
||||
#define DDR0_41_ECC_C_DATA_MASK 0xFFFFFFFF /* Read only */
|
||||
#define DDR0_41_ECC_C_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
|
||||
#define DDR0_41_ECC_C_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
|
||||
|
||||
#define DDR0_42 0x2A
|
||||
#define DDR0_42_ADDR_PINS_MASK 0x07000000
|
||||
#define DDR0_42_ADDR_PINS_ENCODE(n) ((((unsigned long)(n))&0x7)<<24)
|
||||
#define DDR0_42_ADDR_PINS_DECODE(n) ((((unsigned long)(n))>>24)&0x7)
|
||||
#define DDR0_42_CASLAT_LIN_GATE_MASK 0x0000000F
|
||||
#define DDR0_42_CASLAT_LIN_GATE_ENCODE(n) ((((unsigned long)(n))&0xF)<<0)
|
||||
#define DDR0_42_CASLAT_LIN_GATE_DECODE(n) ((((unsigned long)(n))>>0)&0xF)
|
||||
|
||||
#define DDR0_43 0x2B
|
||||
#define DDR0_43_TWR_MASK 0x07000000
|
||||
#define DDR0_43_TWR_ENCODE(n) ((((unsigned long)(n))&0x7)<<24)
|
||||
#define DDR0_43_TWR_DECODE(n) ((((unsigned long)(n))>>24)&0x7)
|
||||
#define DDR0_43_APREBIT_MASK 0x000F0000
|
||||
#define DDR0_43_APREBIT_ENCODE(n) ((((unsigned long)(n))&0xF)<<16)
|
||||
#define DDR0_43_APREBIT_DECODE(n) ((((unsigned long)(n))>>16)&0xF)
|
||||
#define DDR0_43_COLUMN_SIZE_MASK 0x00000700
|
||||
#define DDR0_43_COLUMN_SIZE_ENCODE(n) ((((unsigned long)(n))&0x7)<<8)
|
||||
#define DDR0_43_COLUMN_SIZE_DECODE(n) ((((unsigned long)(n))>>8)&0x7)
|
||||
#define DDR0_43_EIGHT_BANK_MODE_MASK 0x00000001
|
||||
#define DDR0_43_EIGHT_BANK_MODE_8_BANKS 0x00000001
|
||||
#define DDR0_43_EIGHT_BANK_MODE_4_BANKS 0x00000000
|
||||
#define DDR0_43_EIGHT_BANK_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
|
||||
#define DDR0_43_EIGHT_BANK_MODE_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
|
||||
|
||||
#define DDR0_44 0x2C
|
||||
#define DDR0_44_TRCD_MASK 0x000000FF
|
||||
#define DDR0_44_TRCD_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0)
|
||||
#define DDR0_44_TRCD_DECODE(n) ((((unsigned long)(n))>>0)&0xFF)
|
||||
|
||||
#endif /* _SPD_SDRAM_DENALI_H_ */
|
||||
|
|
@ -0,0 +1,145 @@
|
|||
/*
|
||||
* (C) Copyright 2002
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(powerpc)
|
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
|
||||
/* Do we need any of these for elf?
|
||||
__DYNAMIC = 0; */
|
||||
SECTIONS
|
||||
{
|
||||
.resetvec 0xFFFFFFFC :
|
||||
{
|
||||
*(.resetvec)
|
||||
} = 0xffff
|
||||
|
||||
.bootpg 0xFFFFF000 :
|
||||
{
|
||||
cpu/ppc4xx/start.o (.bootpg)
|
||||
} = 0xffff
|
||||
|
||||
/* Read-only sections, merged into text segment: */
|
||||
. = + SIZEOF_HEADERS;
|
||||
.interp : { *(.interp) }
|
||||
.hash : { *(.hash) }
|
||||
.dynsym : { *(.dynsym) }
|
||||
.dynstr : { *(.dynstr) }
|
||||
.rel.text : { *(.rel.text) }
|
||||
.rela.text : { *(.rela.text) }
|
||||
.rel.data : { *(.rel.data) }
|
||||
.rela.data : { *(.rela.data) }
|
||||
.rel.rodata : { *(.rel.rodata) }
|
||||
.rela.rodata : { *(.rela.rodata) }
|
||||
.rel.got : { *(.rel.got) }
|
||||
.rela.got : { *(.rela.got) }
|
||||
.rel.ctors : { *(.rel.ctors) }
|
||||
.rela.ctors : { *(.rela.ctors) }
|
||||
.rel.dtors : { *(.rel.dtors) }
|
||||
.rela.dtors : { *(.rela.dtors) }
|
||||
.rel.bss : { *(.rel.bss) }
|
||||
.rela.bss : { *(.rela.bss) }
|
||||
.rel.plt : { *(.rel.plt) }
|
||||
.rela.plt : { *(.rela.plt) }
|
||||
.init : { *(.init) }
|
||||
.plt : { *(.plt) }
|
||||
.text :
|
||||
{
|
||||
/* WARNING - the following is hand-optimized to fit within */
|
||||
/* the sector layout of our flash chips! XXX FIXME XXX */
|
||||
|
||||
cpu/ppc4xx/start.o (.text)
|
||||
|
||||
*(.text)
|
||||
*(.fixup)
|
||||
*(.got1)
|
||||
}
|
||||
_etext = .;
|
||||
PROVIDE (etext = .);
|
||||
.rodata :
|
||||
{
|
||||
*(.rodata)
|
||||
*(.rodata1)
|
||||
*(.rodata.str1.4)
|
||||
}
|
||||
.fini : { *(.fini) } =0
|
||||
.ctors : { *(.ctors) }
|
||||
.dtors : { *(.dtors) }
|
||||
|
||||
/* Read-write section, merged into data segment: */
|
||||
. = (. + 0x00FF) & 0xFFFFFF00;
|
||||
_erotext = .;
|
||||
PROVIDE (erotext = .);
|
||||
.reloc :
|
||||
{
|
||||
*(.got)
|
||||
_GOT2_TABLE_ = .;
|
||||
*(.got2)
|
||||
_FIXUP_TABLE_ = .;
|
||||
*(.fixup)
|
||||
}
|
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
|
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data)
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata2)
|
||||
*(.dynamic)
|
||||
CONSTRUCTORS
|
||||
}
|
||||
_edata = .;
|
||||
PROVIDE (edata = .);
|
||||
|
||||
. = .;
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
|
||||
. = .;
|
||||
__start___ex_table = .;
|
||||
__ex_table : { *(__ex_table) }
|
||||
__stop___ex_table = .;
|
||||
|
||||
. = ALIGN(256);
|
||||
__init_begin = .;
|
||||
.text.init : { *(.text.init) }
|
||||
.data.init : { *(.data.init) }
|
||||
. = ALIGN(256);
|
||||
__init_end = .;
|
||||
|
||||
__bss_start = .;
|
||||
.bss :
|
||||
{
|
||||
*(.sbss) *(.scommon)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(COMMON)
|
||||
}
|
||||
|
||||
ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified.");
|
||||
|
||||
_end = . ;
|
||||
PROVIDE (end = .);
|
||||
}
|
||||
|
|
@ -0,0 +1,437 @@
|
|||
/*
|
||||
* (C) Copyright 2007
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/************************************************************************
|
||||
* lwmon5.h - configuration for lwmon5 board
|
||||
***********************************************************************/
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* High Level Configuration Options
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_LWMON5 1 /* Board is lwmon5 */
|
||||
#define CONFIG_440EPX 1 /* Specific PPC440EPx */
|
||||
#define CONFIG_4xx 1 /* ... PPC4xx family */
|
||||
#define CONFIG_SYS_CLK_FREQ 33300000 /* external freq to pll */
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
|
||||
#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
|
||||
#define CONFIG_ADD_RAM_INFO 1 /* Print additional info */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Base addresses -- Note these are effective addresses where the
|
||||
* actual resources get mapped (not physical addresses)
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
|
||||
#define CFG_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc() */
|
||||
|
||||
#define CFG_BOOT_BASE_ADDR 0xf0000000
|
||||
#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
|
||||
#define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */
|
||||
#define CFG_MONITOR_BASE TEXT_BASE
|
||||
#define CFG_LIME_BASE_0 0xc0000000
|
||||
#define CFG_LIME_BASE_1 0xc1000000
|
||||
#define CFG_LIME_BASE_2 0xc2000000
|
||||
#define CFG_LIME_BASE_3 0xc3000000
|
||||
#define CFG_FPGA_BASE_0 0xc4000000
|
||||
#define CFG_FPGA_BASE_1 0xc4200000
|
||||
#define CFG_OCM_BASE 0xe0010000 /* ocm */
|
||||
#define CFG_PCI_BASE 0xe0000000 /* Internal PCI regs */
|
||||
#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
|
||||
#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
|
||||
#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000
|
||||
#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000
|
||||
|
||||
/* Don't change either of these */
|
||||
#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */
|
||||
|
||||
#define CFG_USB2D0_BASE 0xe0000100
|
||||
#define CFG_USB_DEVICE 0xe0000000
|
||||
#define CFG_USB_HOST 0xe0000400
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Initial RAM & stack pointer
|
||||
*----------------------------------------------------------------------*/
|
||||
/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */
|
||||
#define CFG_INIT_RAM_OCM 1 /* OCM as init ram */
|
||||
#define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */
|
||||
|
||||
#define CFG_INIT_RAM_END (4 << 10)
|
||||
#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
|
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
|
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Serial Port
|
||||
*----------------------------------------------------------------------*/
|
||||
#undef CFG_EXT_SERIAL_CLOCK /* no external clock provided */
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
#define CONFIG_SERIAL_MULTI 1
|
||||
/* define this if you want console on UART1 */
|
||||
#define CONFIG_UART1_CONSOLE 1 /* use UART1 as console */
|
||||
|
||||
#define CFG_BAUDRATE_TABLE \
|
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Environment
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH related
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CFG_FLASH_CFI /* The flash is CFI compatible */
|
||||
#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
|
||||
|
||||
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
|
||||
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
|
||||
#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
|
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
|
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
|
||||
|
||||
#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
|
||||
#define CFG_FLASH_PROTECTION 1 /* use hardware flash protection */
|
||||
|
||||
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
|
||||
#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
|
||||
|
||||
#define CFG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */
|
||||
#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
|
||||
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
|
||||
|
||||
/* Address and size of Redundant Environment Sector */
|
||||
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
|
||||
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* DDR SDRAM
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CFG_MBYTES_SDRAM (256) /* 256MB */
|
||||
#define CFG_DDR_CACHED_ADDR 0x40000000 /* setup 2nd TLB cached here */
|
||||
#define CONFIG_DDR_DATA_EYE 1 /* use DDR2 optimization */
|
||||
#if 0 /* test-only: disable ECC for now */
|
||||
#define CONFIG_DDR_ECC 1 /* enable ECC */
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* I2C
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
|
||||
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
|
||||
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
|
||||
#define CFG_I2C_SLAVE 0x7F
|
||||
|
||||
#define CFG_I2C_MULTI_EEPROMS
|
||||
#define CFG_I2C_EEPROM_ADDR (0xa8>>1)
|
||||
#define CFG_I2C_EEPROM_ADDR_LEN 1
|
||||
#define CFG_EEPROM_PAGE_WRITE_ENABLE
|
||||
#define CFG_EEPROM_PAGE_WRITE_BITS 3
|
||||
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
|
||||
|
||||
#define CONFIG_RTC_PCF8563 1 /* enable Philips PCF8563 RTC */
|
||||
#define CFG_I2C_RTC_ADDR 0x51 /* Philips PCF8563 RTC address */
|
||||
|
||||
#define CONFIG_PREBOOT "echo;" \
|
||||
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
|
||||
"echo"
|
||||
|
||||
#undef CONFIG_BOOTARGS
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"hostname=lwmon5\0" \
|
||||
"netdev=eth0\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=${serverip}:${rootpath}\0" \
|
||||
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
||||
"addip=setenv bootargs ${bootargs} " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
|
||||
":${hostname}:${netdev}:off panic=1\0" \
|
||||
"addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0"\
|
||||
"flash_nfs=run nfsargs addip addtty;" \
|
||||
"bootm ${kernel_addr}\0" \
|
||||
"flash_self=run ramargs addip addtty;" \
|
||||
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
|
||||
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
|
||||
"bootm\0" \
|
||||
"rootpath=/opt/eldk/ppc_4xxFP\0" \
|
||||
"bootfile=/tftpboot/lwmon5/uImage\0" \
|
||||
"kernel_addr=FC000000\0" \
|
||||
"ramdisk_addr=FC180000\0" \
|
||||
"load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0" \
|
||||
"update=protect off FFF80000 FFFFFFFF;era FFF80000 FFFFFFFF;" \
|
||||
"cp.b 200000 FFF80000 80000\0" \
|
||||
"upd=run load;run update\0" \
|
||||
""
|
||||
#define CONFIG_BOOTCOMMAND "run flash_self"
|
||||
|
||||
#if 0
|
||||
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
|
||||
#else
|
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
|
||||
#endif
|
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
||||
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
|
||||
|
||||
#define CONFIG_IBM_EMAC4_V4 1
|
||||
#define CONFIG_MII 1 /* MII PHY management */
|
||||
#define CONFIG_PHY_ADDR 3 /* PHY address, See schematics */
|
||||
|
||||
#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
|
||||
|
||||
#define CONFIG_HAS_ETH0
|
||||
#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
|
||||
|
||||
#define CONFIG_NET_MULTI 1
|
||||
#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
|
||||
#define CONFIG_PHY1_ADDR 1
|
||||
|
||||
/* USB */
|
||||
#ifdef CONFIG_440EPX
|
||||
#define CONFIG_USB_OHCI
|
||||
#define CONFIG_USB_STORAGE
|
||||
|
||||
/* Comment this out to enable USB 1.1 device */
|
||||
#define USB_2_0_DEVICE
|
||||
|
||||
#define CMD_USB CFG_CMD_USB
|
||||
#else
|
||||
#define CMD_USB 0 /* no USB on 440GRx */
|
||||
#endif /* CONFIG_440EPX */
|
||||
|
||||
/* Partitions */
|
||||
#define CONFIG_MAC_PARTITION
|
||||
#define CONFIG_DOS_PARTITION
|
||||
#define CONFIG_ISO_PARTITION
|
||||
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
|
||||
CFG_CMD_ASKENV | \
|
||||
CFG_CMD_DATE | \
|
||||
CFG_CMD_DHCP | \
|
||||
CFG_CMD_DIAG | \
|
||||
CFG_CMD_EEPROM | \
|
||||
CFG_CMD_ELF | \
|
||||
CFG_CMD_FAT | \
|
||||
CFG_CMD_I2C | \
|
||||
CFG_CMD_IRQ | \
|
||||
CFG_CMD_MII | \
|
||||
CFG_CMD_NET | \
|
||||
CFG_CMD_NFS | \
|
||||
CFG_CMD_PCI | \
|
||||
CFG_CMD_PING | \
|
||||
CFG_CMD_REGINFO | \
|
||||
CFG_CMD_SDRAM | \
|
||||
CMD_USB)
|
||||
|
||||
#define CONFIG_SUPPORT_VFAT
|
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
|
||||
#include <cmd_confdefs.h>
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Miscellaneous configurable options
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CFG_LONGHELP /* undef to save memory */
|
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CFG_MAXARGS 16 /* max number of command args */
|
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
|
||||
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
|
||||
|
||||
#define CFG_LOAD_ADDR 0x100000 /* default load address */
|
||||
#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
|
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
|
||||
|
||||
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
|
||||
#define CONFIG_LOOPW 1 /* enable loopw command */
|
||||
#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
|
||||
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
|
||||
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCI stuff
|
||||
*----------------------------------------------------------------------*/
|
||||
/* General PCI */
|
||||
#define CONFIG_PCI /* include pci support */
|
||||
#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
|
||||
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
||||
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
|
||||
|
||||
/* Board-specific PCI */
|
||||
#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
|
||||
#define CFG_PCI_TARGET_INIT
|
||||
#define CFG_PCI_MASTER_INIT
|
||||
|
||||
#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
|
||||
#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */
|
||||
|
||||
#define CONFIG_HW_WATCHDOG 1 /* Use external HW-Watchdog */
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* External Bus Controller (EBC) Setup
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CFG_FLASH CFG_FLASH_BASE
|
||||
|
||||
/* Memory Bank 0 (NOR-FLASH) initialization */
|
||||
#define CFG_EBC_PB0AP 0x03050200
|
||||
#define CFG_EBC_PB0CR (CFG_FLASH | 0xdc000)
|
||||
|
||||
/* Memory Bank 1 (Lime) initialization */
|
||||
#define CFG_EBC_PB1AP 0x01004380
|
||||
#define CFG_EBC_PB1CR (CFG_LIME_BASE_0 | 0xdc000)
|
||||
|
||||
/* Memory Bank 2 (FPGA) initialization */
|
||||
#define CFG_EBC_PB2AP 0x01004400
|
||||
#define CFG_EBC_PB2CR (CFG_FPGA_BASE_0 | 0x1c000)
|
||||
|
||||
/* Memory Bank 3 (FPGA2) initialization */
|
||||
#define CFG_EBC_PB3AP 0x01004400
|
||||
#define CFG_EBC_PB3CR (CFG_FPGA_BASE_1 | 0x1c000)
|
||||
|
||||
#define CFG_EBC_CFG 0xb8400000
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* GPIO Setup
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CFG_GPIO_PHY1_RST 12
|
||||
#define CFG_GPIO_FLASH_WP 14
|
||||
#define CFG_GPIO_PHY0_RST 22
|
||||
#define CFG_GPIO_HUB_RST 50
|
||||
#define CFG_GPIO_WATCHDOG 58
|
||||
#define CFG_GPIO_LIME_S 59
|
||||
#define CFG_GPIO_LIME_RST 60
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PPC440 GPIO Configuration
|
||||
*/
|
||||
#define CFG_440_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
|
||||
{ \
|
||||
/* GPIO Core 0 */ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 EBC_CS_N(1) */ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 EBC_CS_N(2) */ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 EBC_CS_N(3) */ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 EBC_CS_N(4) */ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5) */ \
|
||||
{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR */ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO12 */ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO13 */ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO14 */ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO15 */ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMCTxD(4) */ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMCTxD(5) */ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMCTxD(6) */ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMCTxD(7) */ \
|
||||
{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 RejectPkt0 */ \
|
||||
{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 RejectPkt1 */ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO22 */ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 SCPD0 */ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 GMCTxD(2) */ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 GMCTxD(3) */ \
|
||||
{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26 */ \
|
||||
{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO28 USB2D_TXVALID */ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \
|
||||
{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \
|
||||
{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \
|
||||
}, \
|
||||
{ \
|
||||
/* GPIO Core 1 */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO32 USB2D_OPMODE0 EBC_DATA(2) */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO33 USB2D_OPMODE1 EBC_DATA(3) */ \
|
||||
{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_0}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N EBC_DATA(0) UART3_SIN*/ \
|
||||
{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N EBC_DATA(1) UART3_SOUT*/ \
|
||||
{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0) */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1) */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2) */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3) */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \
|
||||
{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO49 Unselect via TraceSelect Bit */ \
|
||||
{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \
|
||||
{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO53 Unselect via TraceSelect Bit */ \
|
||||
{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \
|
||||
{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO55 Unselect via TraceSelect Bit */ \
|
||||
{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \
|
||||
{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO57 Unselect via TraceSelect Bit */ \
|
||||
{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO58 Unselect via TraceSelect Bit */ \
|
||||
{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \
|
||||
{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \
|
||||
{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \
|
||||
} \
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */
|
||||
#define CFG_CACHELINE_SIZE 32 /* ... */
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Internal Definitions
|
||||
*
|
||||
* Boot Flags
|
||||
*/
|
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
|
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
|
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
|
||||
#endif
|
||||
#endif /* __CONFIG_H */
|
||||
|
|
@ -956,7 +956,8 @@
|
|||
#define plb1_bearl (PLB_ARBITER_BASE+ 0x0C)
|
||||
#define plb1_bearh (PLB_ARBITER_BASE+ 0x0D)
|
||||
|
||||
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
|
||||
#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
|
||||
defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
|
||||
/* Pin Function Control Register 1 */
|
||||
#define SDR0_PFC1 0x4101
|
||||
#define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */
|
||||
|
|
@ -1103,6 +1104,8 @@
|
|||
#define SDR0_PFC2_SELECT_CONFIG_5 0xC0000000 /* 2xRTBI using RGMII bridge */
|
||||
#define SDR0_PFC2_SELECT_CONFIG_6 0x40000000 /* 2xSMII using ZMII bridge */
|
||||
|
||||
#define SDR0_PFC4 0x4104
|
||||
|
||||
/* USB2PHY0 Control Register */
|
||||
#define SDR0_USB2PHY0CR 0x4103
|
||||
#define SDR0_USB2PHY0CR_UTMICN_MASK 0x00100000 /* PHY UTMI interface connection */
|
||||
|
|
|
|||
Loading…
Reference in New Issue