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Update register definitions for MCF5271.

This commit is contained in:
Marian Balakowicz 2006-05-09 11:43:59 +02:00
parent 0c056f0e27
commit b4853b779e
2 changed files with 39 additions and 16 deletions
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2
CHANGELOG
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@ -2,6 +2,8 @@
Changes since U-Boot 1.1.4:
======================================================================
* Update register definitions for MCF5271.
* Fix serial console support for MCF5271.
* Fixes for gcc 3.4 based m68k toolchain,

53
include/asm-m68k/m5271.h
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@ -51,19 +51,39 @@
#define MCF_RCM_RCR_FRCRSTOUT 0x40
#define MCF_RCM_RCR_SOFTRST 0x80
#define MCF_GPIO_PAR_AD 0x100040
#define MCF_GPIO_PAR_CS 0x100045
#define MCF_GPIO_PAR_SDRAM 0x100046
#define MCF_GPIO_PAR_FECI2C 0x100047
#define MCF_GPIO_PAR_UART 0x100048
#define MCF_GPIO_PAR_CS_PAR_CS2 (0x04)
#define MCF_GPIO_AD_ADDR23 0x80
#define MCF_GPIO_AD_ADDR22 0x40
#define MCF_GPIO_AD_ADDR21 0x20
#define MCF_GPIO_AD_DATAL 0x01
#define MCF_GPIO_AD_MASK 0xe1
#define MCF_GPIO_PAR_UART_U0RTS (0x0001)
#define MCF_GPIO_PAR_UART_U0CTS (0x0002)
#define MCF_GPIO_PAR_UART_U0TXD (0x0004)
#define MCF_GPIO_PAR_UART_U0RXD (0x0008)
#define MCF_GPIO_PAR_UART_U1RXD_UART1 (0x0C00)
#define MCF_GPIO_PAR_UART_U1TXD_UART1 (0x0300)
#define MCF_GPIO_PAR_CS_PAR_CS2 0x04
#define MCF_GPIO_SDRAM_CSSDCS_00 0x00 /* CS[3:2] pins: CS3, CS2 */
#define MCF_GPIO_SDRAM_CSSDCS_01 0x40 /* CS[3:2] pins: CS3, SD_CS0 */
#define MCF_GPIO_SDRAM_CSSDCS_10 0x80 /* CS[3:2] pins: SD_CS1, SC2 */
#define MCF_GPIO_SDRAM_CSSDCS_11 0xc0 /* CS[3:2] pins: SD_CS1, SD_CS0 */
#define MCF_GPIO_SDRAM_SDWE 0x20 /* WE pin */
#define MCF_GPIO_SDRAM_SCAS 0x10 /* CAS pin */
#define MCF_GPIO_SDRAM_SRAS 0x08 /* RAS pin */
#define MCF_GPIO_SDRAM_SCKE 0x04 /* CKE pin */
#define MCF_GPIO_SDRAM_SDCS_00 0x00 /* SD_CS[0:1] pins: GPIO, GPIO */
#define MCF_GPIO_SDRAM_SDCS_01 0x01 /* SD_CS[0:1] pins: GPIO, SD_CS0 */
#define MCF_GPIO_SDRAM_SDCS_10 0x02 /* SD_CS[0:1] pins: SD_CS1, GPIO */
#define MCF_GPIO_SDRAM_SDCS_11 0x03 /* SD_CS[0:1] pins: SD_CS1, SD_CS0 */
#define MCF_GPIO_PAR_UART_U0RTS 0x0001
#define MCF_GPIO_PAR_UART_U0CTS 0x0002
#define MCF_GPIO_PAR_UART_U0TXD 0x0004
#define MCF_GPIO_PAR_UART_U0RXD 0x0008
#define MCF_GPIO_PAR_UART_U1RXD_UART1 0x0C00
#define MCF_GPIO_PAR_UART_U1TXD_UART1 0x0300
#define MCF_GPIO_PAR_SDRAM_PAR_CSSDCS(x) (((x)&0x03)<<6)
@ -73,21 +93,22 @@
#define MCF_SDRAMC_DCR_RC(x) (((x)&0x01FF)<<0)
#define MCF_SDRAMC_DCR_RTIM(x) (((x)&0x0003)<<9)
#define MCF_SDRAMC_DCR_IS (0x0800)
#define MCF_SDRAMC_DCR_COC (0x1000)
#define MCF_SDRAMC_DCR_NAM (0x2000)
#define MCF_SDRAMC_DCR_IS 0x0800
#define MCF_SDRAMC_DCR_COC 0x1000
#define MCF_SDRAMC_DCR_NAM 0x2000
#define MCF_SDRAMC_DACRn_IP (0x00000008)
#define MCF_SDRAMC_DACRn_IP 0x00000008
#define MCF_SDRAMC_DACRn_PS(x) (((x)&0x00000003)<<4)
#define MCF_SDRAMC_DACRn_MRS (0x00000040)
#define MCF_SDRAMC_DACRn_MRS 0x00000040
#define MCF_SDRAMC_DACRn_CBM(x) (((x)&0x00000007)<<8)
#define MCF_SDRAMC_DACRn_CASL(x) (((x)&0x00000003)<<12)
#define MCF_SDRAMC_DACRn_RE (0x00008000)
#define MCF_SDRAMC_DACRn_RE 0x00008000
#define MCF_SDRAMC_DACRn_BA(x) (((x)&0x00003FFF)<<18)
#define MCF_SDRAMC_DMRn_BAM_8M (0x007C0000)
#define MCF_SDRAMC_DMRn_V (0x00000001)
#define MCF_SDRAMC_DMRn_BAM_8M 0x007C0000
#define MCF_SDRAMC_DMRn_BAM_16M 0x00FC0000
#define MCF_SDRAMC_DMRn_V 0x00000001
#define MCFSIM_ICR1 (0x000C41)
#define MCFSIM_ICR1 0x000C41
#endif /* _MCF5271_H_ */