Nand mxc_nand add v1.1 controller support
Add support for version 1.1 of the nfc nand flash controller which is on the i.mx25 soc. Signed-off-by: John Rigby <jcrigby@gmail.com> CC: Scott Wood <scottwood@freescale.com>
This commit is contained in:
John Rigby
Scott Wood
parent
f3bb63a304
commit
b081c2e9b9
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@ -22,27 +22,65 @@
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#include <nand.h>
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#include <linux/err.h>
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#include <asm/io.h>
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#ifdef CONFIG_MX27
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#if defined(CONFIG_MX27) || defined(CONFIG_MX25)
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#include <asm/arch/imx-regs.h>
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#endif
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#define DRIVER_NAME "mxc_nand"
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/*
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* TODO: Use same register defs here as nand_spl mxc nand driver.
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*/
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/*
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* Register map and bit definitions for the Freescale NAND Flash Controller
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* present in various i.MX devices.
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*
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* MX31 and MX27 have version 1 which has
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* 4 512 byte main buffers and
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* 4 16 byte spare buffers
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* to support up to 2K byte pagesize nand.
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* Reading or writing a 2K page requires 4 FDI/FDO cycles.
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*
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* MX25 has version 1.1 which has
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* 8 512 byte main buffers and
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* 8 64 byte spare buffers
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* to support up to 4K byte pagesize nand.
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* Reading or writing a 2K or 4K page requires only 1 FDI/FDO cycle.
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* Also some of registers are moved and/or changed meaning as seen below.
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*/
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#if defined(CONFIG_MX31) || defined(CONFIG_MX27)
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#define MXC_NFC_V1
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#elif defined(CONFIG_MX25)
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#define MXC_NFC_V1_1
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#else
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#warning "MXC NFC version not defined"
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#endif
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#if defined(MXC_NFC_V1)
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#define NAND_MXC_NR_BUFS 4
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#define NAND_MXC_SPARE_BUF_SIZE 16
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#define NAND_MXC_REG_OFFSET 0xe00
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#define is_mxc_nfc_11() 0
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#elif defined(MXC_NFC_V1_1)
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#define NAND_MXC_NR_BUFS 8
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#define NAND_MXC_SPARE_BUF_SIZE 64
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#define NAND_MXC_REG_OFFSET 0x1e00
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#define is_mxc_nfc_11() 1
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#else
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#error "define CONFIG_NAND_MXC_VXXX to use mtd mxc nand driver"
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#endif
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struct nfc_regs {
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/* NFC RAM BUFFER Main area 0 */
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uint8_t main_area0[0x200];
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uint8_t main_area1[0x200];
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uint8_t main_area2[0x200];
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uint8_t main_area3[0x200];
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/* SPARE BUFFER Spare area 0 */
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uint8_t spare_area0[0x10];
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uint8_t spare_area1[0x10];
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uint8_t spare_area2[0x10];
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uint8_t spare_area3[0x10];
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uint8_t pad[0x5c0];
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/* NFC registers */
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uint8_t main_area[NAND_MXC_NR_BUFS][0x200];
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uint8_t spare_area[NAND_MXC_NR_BUFS][NAND_MXC_SPARE_BUF_SIZE];
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/*
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* reserved size is offset of nfc registers
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* minus total main and spare sizes
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*/
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uint8_t reserved1[NAND_MXC_REG_OFFSET
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- NAND_MXC_NR_BUFS * (512 + NAND_MXC_SPARE_BUF_SIZE)];
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#if defined(MXC_NFC_V1)
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uint16_t nfc_buf_size;
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uint16_t reserved;
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uint16_t reserved2;
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uint16_t nfc_buf_addr;
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uint16_t nfc_flash_addr;
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uint16_t nfc_flash_cmd;
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@ -56,6 +94,30 @@ struct nfc_regs {
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uint16_t nfc_nf_wrprst;
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uint16_t nfc_config1;
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uint16_t nfc_config2;
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#elif defined(MXC_NFC_V1_1)
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uint16_t reserved2[2];
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uint16_t nfc_buf_addr;
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uint16_t nfc_flash_addr;
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uint16_t nfc_flash_cmd;
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uint16_t nfc_config;
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uint16_t nfc_ecc_status_result;
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uint16_t nfc_ecc_status_result2;
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uint16_t nfc_spare_area_size;
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uint16_t nfc_wrprot;
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uint16_t reserved3[2];
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uint16_t nfc_nf_wrprst;
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uint16_t nfc_config1;
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uint16_t nfc_config2;
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uint16_t reserved4;
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uint16_t nfc_unlockstart_blkaddr;
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uint16_t nfc_unlockend_blkaddr;
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uint16_t nfc_unlockstart_blkaddr1;
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uint16_t nfc_unlockend_blkaddr1;
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uint16_t nfc_unlockstart_blkaddr2;
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uint16_t nfc_unlockend_blkaddr2;
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uint16_t nfc_unlockstart_blkaddr3;
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uint16_t nfc_unlockend_blkaddr3;
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#endif
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};
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/*
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@ -100,6 +162,11 @@ struct nfc_regs {
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*/
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#define NFC_INT 0x8000
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#ifdef MXC_NFC_V1_1
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#define NFC_4_8N_ECC (1 << 0)
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#else
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#define NFC_4_8N_ECC 0
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#endif
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#define NFC_SP_EN (1 << 2)
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#define NFC_ECC_EN (1 << 3)
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#define NFC_BIG (1 << 5)
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@ -119,6 +186,7 @@ struct mxc_nand_host {
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int pagesize_2k;
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int clk_act;
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uint16_t col_addr;
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unsigned int page_addr;
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};
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static struct mxc_nand_host mxc_host;
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@ -135,26 +203,45 @@ static struct mxc_nand_host *host = &mxc_host;
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#define SPARE_SINGLEBIT_ERROR 0x1
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/* OOB placement block for use with hardware ecc generation */
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#ifdef CONFIG_MXC_NAND_HWECC
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#if defined(MXC_NFC_V1)
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#ifndef CONFIG_SYS_NAND_LARGEPAGE
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static struct nand_ecclayout nand_hw_eccoob = {
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.eccbytes = 5,
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.eccpos = {6, 7, 8, 9, 10},
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.oobfree = {{0, 5}, {11, 5}, }
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.oobfree = { {0, 5}, {11, 5}, }
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};
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#else
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static struct nand_ecclayout nand_soft_eccoob = {
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.eccbytes = 6,
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.eccpos = {6, 7, 8, 9, 10, 11},
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.oobfree = {{0, 5}, {12, 4}, }
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static struct nand_ecclayout nand_hw_eccoob2k = {
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.eccbytes = 20,
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.eccpos = {
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6, 7, 8, 9, 10,
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22, 23, 24, 25, 26,
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38, 39, 40, 41, 42,
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54, 55, 56, 57, 58,
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},
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.oobfree = { {2, 4}, {11, 11}, {27, 11}, {43, 11}, {59, 5} },
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};
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#endif
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static struct nand_ecclayout nand_hw_eccoob_largepage = {
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.eccbytes = 20,
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.eccpos = {6, 7, 8, 9, 10, 22, 23, 24, 25, 26,
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38, 39, 40, 41, 42, 54, 55, 56, 57, 58},
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.oobfree = {{2, 4}, {11, 10}, {27, 10}, {43, 10}, {59, 5}, }
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#elif defined(MXC_NFC_V1_1)
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#ifndef CONFIG_SYS_NAND_LARGEPAGE
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static struct nand_ecclayout nand_hw_eccoob = {
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.eccbytes = 9,
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.eccpos = {7, 8, 9, 10, 11, 12, 13, 14, 15},
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.oobfree = { {2, 5} }
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};
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#else
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static struct nand_ecclayout nand_hw_eccoob2k = {
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.eccbytes = 36,
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.eccpos = {
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7, 8, 9, 10, 11, 12, 13, 14, 15,
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23, 24, 25, 26, 27, 28, 29, 30, 31,
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39, 40, 41, 42, 43, 44, 45, 46, 47,
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55, 56, 57, 58, 59, 60, 61, 62, 63,
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},
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.oobfree = { {2, 5}, {16, 7}, {32, 7}, {48, 7} },
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};
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#endif
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#endif
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#ifdef CONFIG_MX27
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static int is_16bit_nand(void)
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@ -178,6 +265,17 @@ static int is_16bit_nand(void)
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else
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return 0;
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}
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#elif defined(CONFIG_MX25)
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static int is_16bit_nand(void)
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{
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struct ccm_regs *ccm =
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(struct ccm_regs *)IMX_CCM_BASE;
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if (readl(&ccm->rcsr) & CCM_RCSR_NF_16BIT_SEL)
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return 1;
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else
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return 0;
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}
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#else
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#warning "8/16 bit NAND autodetection not supported"
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static int is_16bit_nand(void)
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@ -258,7 +356,24 @@ static void send_addr(struct mxc_nand_host *host, uint16_t addr)
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static void send_prog_page(struct mxc_nand_host *host, uint8_t buf_id,
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int spare_only)
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{
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MTDDEBUG(MTD_DEBUG_LEVEL3, "send_prog_page (%d)\n", spare_only);
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if (spare_only)
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MTDDEBUG(MTD_DEBUG_LEVEL1, "send_prog_page (%d)\n", spare_only);
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if (is_mxc_nfc_11()) {
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int i;
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/*
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* The controller copies the 64 bytes of spare data from
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* the first 16 bytes of each of the 4 64 byte spare buffers.
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* Copy the contiguous data starting in spare_area[0] to
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* the four spare area buffers.
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*/
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for (i = 1; i < 4; i++) {
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void __iomem *src = &host->regs->spare_area[0][i * 16];
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void __iomem *dst = &host->regs->spare_area[i][0];
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mxc_nand_memcpy32(dst, src, 16);
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}
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}
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writew(buf_id, &host->regs->nfc_buf_addr);
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@ -303,6 +418,22 @@ static void send_read_page(struct mxc_nand_host *host, uint8_t buf_id,
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/* Wait for operation to complete */
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wait_op_done(host, TROP_US_DELAY, spare_only);
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if (is_mxc_nfc_11()) {
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int i;
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/*
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* The controller copies the 64 bytes of spare data to
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* the first 16 bytes of each of the 4 spare buffers.
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* Make the data contiguous starting in spare_area[0].
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*/
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for (i = 1; i < 4; i++) {
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void __iomem *src = &host->regs->spare_area[i][0];
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void __iomem *dst = &host->regs->spare_area[0][i * 16];
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mxc_nand_memcpy32(dst, src, 16);
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}
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}
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}
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/* Request the NANDFC to perform a read of the NAND device ID. */
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@ -330,7 +461,7 @@ static void send_read_id(struct mxc_nand_host *host)
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*/
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static uint16_t get_dev_status(struct mxc_nand_host *host)
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{
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void __iomem *main_buf = host->regs->main_area1;
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void __iomem *main_buf = host->regs->main_area[1];
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uint32_t store;
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uint16_t ret, tmp;
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/* Issue status request to NAND device */
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@ -379,6 +510,330 @@ static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
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*/
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}
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#ifdef MXC_NFC_V1_1
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static void _mxc_nand_enable_hwecc(struct mtd_info *mtd, int on)
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{
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struct nand_chip *nand_chip = mtd->priv;
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struct mxc_nand_host *host = nand_chip->priv;
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uint16_t tmp = readw(&host->regs->nfc_config1);
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if (on)
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tmp |= NFC_ECC_EN;
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else
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tmp &= ~NFC_ECC_EN;
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writew(tmp, &host->regs->nfc_config1);
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}
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static int mxc_nand_read_oob_syndrome(struct mtd_info *mtd,
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struct nand_chip *chip,
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int page, int sndcmd)
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{
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struct mxc_nand_host *host = chip->priv;
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uint8_t *buf = chip->oob_poi;
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int length = mtd->oobsize;
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int eccpitch = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
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uint8_t *bufpoi = buf;
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int i, toread;
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MTDDEBUG(MTD_DEBUG_LEVEL0,
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"%s: Reading OOB area of page %u to oob %p\n",
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__FUNCTION__, host->page_addr, buf);
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chip->cmdfunc(mtd, NAND_CMD_READOOB, mtd->writesize, page);
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for (i = 0; i < chip->ecc.steps; i++) {
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toread = min_t(int, length, chip->ecc.prepad);
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if (toread) {
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chip->read_buf(mtd, bufpoi, toread);
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bufpoi += toread;
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length -= toread;
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}
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bufpoi += chip->ecc.bytes;
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host->col_addr += chip->ecc.bytes;
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length -= chip->ecc.bytes;
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toread = min_t(int, length, chip->ecc.postpad);
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if (toread) {
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chip->read_buf(mtd, bufpoi, toread);
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bufpoi += toread;
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length -= toread;
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}
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}
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if (length > 0)
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chip->read_buf(mtd, bufpoi, length);
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_mxc_nand_enable_hwecc(mtd, 0);
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chip->cmdfunc(mtd, NAND_CMD_READOOB,
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mtd->writesize + chip->ecc.prepad, page);
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bufpoi = buf + chip->ecc.prepad;
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length = mtd->oobsize - chip->ecc.prepad;
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for (i = 0; i < chip->ecc.steps; i++) {
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toread = min_t(int, length, chip->ecc.bytes);
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chip->read_buf(mtd, bufpoi, toread);
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bufpoi += eccpitch;
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length -= eccpitch;
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host->col_addr += chip->ecc.postpad + chip->ecc.prepad;
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}
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_mxc_nand_enable_hwecc(mtd, 1);
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return 1;
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}
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static int mxc_nand_read_page_raw_syndrome(struct mtd_info *mtd,
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struct nand_chip *chip,
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uint8_t *buf,
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int page)
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{
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struct mxc_nand_host *host = chip->priv;
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int eccsize = chip->ecc.size;
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int eccbytes = chip->ecc.bytes;
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int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
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uint8_t *oob = chip->oob_poi;
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int steps, size;
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int n;
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_mxc_nand_enable_hwecc(mtd, 0);
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chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, host->page_addr);
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for (n = 0, steps = chip->ecc.steps; steps > 0; n++, steps--) {
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host->col_addr = n * eccsize;
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chip->read_buf(mtd, buf, eccsize);
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buf += eccsize;
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host->col_addr = mtd->writesize + n * eccpitch;
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if (chip->ecc.prepad) {
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chip->read_buf(mtd, oob, chip->ecc.prepad);
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oob += chip->ecc.prepad;
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}
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chip->read_buf(mtd, oob, eccbytes);
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oob += eccbytes;
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if (chip->ecc.postpad) {
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chip->read_buf(mtd, oob, chip->ecc.postpad);
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oob += chip->ecc.postpad;
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}
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}
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size = mtd->oobsize - (oob - chip->oob_poi);
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if (size)
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chip->read_buf(mtd, oob, size);
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_mxc_nand_enable_hwecc(mtd, 0);
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return 0;
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}
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static int mxc_nand_read_page_syndrome(struct mtd_info *mtd,
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struct nand_chip *chip,
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uint8_t *buf,
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int page)
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{
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struct mxc_nand_host *host = chip->priv;
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int n, eccsize = chip->ecc.size;
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int eccbytes = chip->ecc.bytes;
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int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
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int eccsteps = chip->ecc.steps;
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uint8_t *p = buf;
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uint8_t *oob = chip->oob_poi;
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MTDDEBUG(MTD_DEBUG_LEVEL1, "Reading page %u to buf %p oob %p\n",
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host->page_addr, buf, oob);
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/* first read out the data area and the available portion of OOB */
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for (n = 0; eccsteps; n++, eccsteps--, p += eccsize) {
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int stat;
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host->col_addr = n * eccsize;
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chip->read_buf(mtd, p, eccsize);
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host->col_addr = mtd->writesize + n * eccpitch;
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if (chip->ecc.prepad) {
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chip->read_buf(mtd, oob, chip->ecc.prepad);
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oob += chip->ecc.prepad;
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}
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stat = chip->ecc.correct(mtd, p, oob, NULL);
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if (stat < 0)
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mtd->ecc_stats.failed++;
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else
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mtd->ecc_stats.corrected += stat;
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oob += eccbytes;
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if (chip->ecc.postpad) {
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chip->read_buf(mtd, oob, chip->ecc.postpad);
|
||||
oob += chip->ecc.postpad;
|
||||
}
|
||||
}
|
||||
|
||||
/* Calculate remaining oob bytes */
|
||||
n = mtd->oobsize - (oob - chip->oob_poi);
|
||||
if (n)
|
||||
chip->read_buf(mtd, oob, n);
|
||||
|
||||
/* Then switch ECC off and read the OOB area to get the ECC code */
|
||||
_mxc_nand_enable_hwecc(mtd, 0);
|
||||
chip->cmdfunc(mtd, NAND_CMD_READOOB, mtd->writesize, host->page_addr);
|
||||
eccsteps = chip->ecc.steps;
|
||||
oob = chip->oob_poi + chip->ecc.prepad;
|
||||
for (n = 0; eccsteps; n++, eccsteps--, p += eccsize) {
|
||||
host->col_addr = mtd->writesize +
|
||||
n * eccpitch +
|
||||
chip->ecc.prepad;
|
||||
chip->read_buf(mtd, oob, eccbytes);
|
||||
oob += eccbytes + chip->ecc.postpad;
|
||||
}
|
||||
_mxc_nand_enable_hwecc(mtd, 1);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mxc_nand_write_oob_syndrome(struct mtd_info *mtd,
|
||||
struct nand_chip *chip, int page)
|
||||
{
|
||||
struct mxc_nand_host *host = chip->priv;
|
||||
int eccpitch = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
|
||||
int length = mtd->oobsize;
|
||||
int i, len, status, steps = chip->ecc.steps;
|
||||
const uint8_t *bufpoi = chip->oob_poi;
|
||||
|
||||
chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
|
||||
for (i = 0; i < steps; i++) {
|
||||
len = min_t(int, length, eccpitch);
|
||||
|
||||
chip->write_buf(mtd, bufpoi, len);
|
||||
bufpoi += len;
|
||||
length -= len;
|
||||
host->col_addr += chip->ecc.prepad + chip->ecc.postpad;
|
||||
}
|
||||
if (length > 0)
|
||||
chip->write_buf(mtd, bufpoi, length);
|
||||
|
||||
chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
|
||||
status = chip->waitfunc(mtd, chip);
|
||||
return status & NAND_STATUS_FAIL ? -EIO : 0;
|
||||
}
|
||||
|
||||
static void mxc_nand_write_page_raw_syndrome(struct mtd_info *mtd,
|
||||
struct nand_chip *chip,
|
||||
const uint8_t *buf)
|
||||
{
|
||||
struct mxc_nand_host *host = chip->priv;
|
||||
int eccsize = chip->ecc.size;
|
||||
int eccbytes = chip->ecc.bytes;
|
||||
int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
|
||||
uint8_t *oob = chip->oob_poi;
|
||||
int steps, size;
|
||||
int n;
|
||||
|
||||
for (n = 0, steps = chip->ecc.steps; steps > 0; n++, steps--) {
|
||||
host->col_addr = n * eccsize;
|
||||
chip->write_buf(mtd, buf, eccsize);
|
||||
buf += eccsize;
|
||||
|
||||
host->col_addr = mtd->writesize + n * eccpitch;
|
||||
|
||||
if (chip->ecc.prepad) {
|
||||
chip->write_buf(mtd, oob, chip->ecc.prepad);
|
||||
oob += chip->ecc.prepad;
|
||||
}
|
||||
|
||||
host->col_addr += eccbytes;
|
||||
oob += eccbytes;
|
||||
|
||||
if (chip->ecc.postpad) {
|
||||
chip->write_buf(mtd, oob, chip->ecc.postpad);
|
||||
oob += chip->ecc.postpad;
|
||||
}
|
||||
}
|
||||
|
||||
size = mtd->oobsize - (oob - chip->oob_poi);
|
||||
if (size)
|
||||
chip->write_buf(mtd, oob, size);
|
||||
}
|
||||
|
||||
static void mxc_nand_write_page_syndrome(struct mtd_info *mtd,
|
||||
struct nand_chip *chip,
|
||||
const uint8_t *buf)
|
||||
{
|
||||
struct mxc_nand_host *host = chip->priv;
|
||||
int i, n, eccsize = chip->ecc.size;
|
||||
int eccbytes = chip->ecc.bytes;
|
||||
int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
|
||||
int eccsteps = chip->ecc.steps;
|
||||
const uint8_t *p = buf;
|
||||
uint8_t *oob = chip->oob_poi;
|
||||
|
||||
chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
|
||||
|
||||
for (i = n = 0;
|
||||
eccsteps;
|
||||
n++, eccsteps--, i += eccbytes, p += eccsize) {
|
||||
host->col_addr = n * eccsize;
|
||||
|
||||
chip->write_buf(mtd, p, eccsize);
|
||||
|
||||
host->col_addr = mtd->writesize + n * eccpitch;
|
||||
|
||||
if (chip->ecc.prepad) {
|
||||
chip->write_buf(mtd, oob, chip->ecc.prepad);
|
||||
oob += chip->ecc.prepad;
|
||||
}
|
||||
|
||||
chip->write_buf(mtd, oob, eccbytes);
|
||||
oob += eccbytes;
|
||||
|
||||
if (chip->ecc.postpad) {
|
||||
chip->write_buf(mtd, oob, chip->ecc.postpad);
|
||||
oob += chip->ecc.postpad;
|
||||
}
|
||||
}
|
||||
|
||||
/* Calculate remaining oob bytes */
|
||||
i = mtd->oobsize - (oob - chip->oob_poi);
|
||||
if (i)
|
||||
chip->write_buf(mtd, oob, i);
|
||||
}
|
||||
|
||||
static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
|
||||
u_char *read_ecc, u_char *calc_ecc)
|
||||
{
|
||||
struct nand_chip *nand_chip = mtd->priv;
|
||||
struct mxc_nand_host *host = nand_chip->priv;
|
||||
uint16_t ecc_status = readw(&host->regs->nfc_ecc_status_result);
|
||||
int subpages = mtd->writesize / nand_chip->subpagesize;
|
||||
int pg2blk_shift = nand_chip->phys_erase_shift -
|
||||
nand_chip->page_shift;
|
||||
|
||||
do {
|
||||
if ((ecc_status & 0xf) > 4) {
|
||||
static int last_bad = -1;
|
||||
|
||||
if (last_bad != host->page_addr >> pg2blk_shift) {
|
||||
last_bad = host->page_addr >> pg2blk_shift;
|
||||
printk(KERN_DEBUG
|
||||
"MXC_NAND: HWECC uncorrectable ECC error"
|
||||
" in block %u page %u subpage %d\n",
|
||||
last_bad, host->page_addr,
|
||||
mtd->writesize / nand_chip->subpagesize
|
||||
- subpages);
|
||||
}
|
||||
return -1;
|
||||
}
|
||||
ecc_status >>= 4;
|
||||
subpages--;
|
||||
} while (subpages > 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#else
|
||||
#define mxc_nand_read_page_syndrome NULL
|
||||
#define mxc_nand_read_page_raw_syndrome NULL
|
||||
#define mxc_nand_read_oob_syndrome NULL
|
||||
#define mxc_nand_write_page_syndrome NULL
|
||||
#define mxc_nand_write_page_raw_syndrome NULL
|
||||
#define mxc_nand_write_oob_syndrome NULL
|
||||
#define mxc_nfc_11_nand_correct_data NULL
|
||||
|
||||
static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
|
||||
u_char *read_ecc, u_char *calc_ecc)
|
||||
{
|
||||
|
|
@ -400,6 +855,9 @@ static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
|
|||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
|
||||
u_char *ecc_code)
|
||||
|
|
@ -415,9 +873,9 @@ static u_char mxc_nand_read_byte(struct mtd_info *mtd)
|
|||
uint8_t ret = 0;
|
||||
uint16_t col;
|
||||
uint16_t __iomem *main_buf =
|
||||
(uint16_t __iomem *)host->regs->main_area0;
|
||||
(uint16_t __iomem *)host->regs->main_area[0];
|
||||
uint16_t __iomem *spare_buf =
|
||||
(uint16_t __iomem *)host->regs->spare_area0;
|
||||
(uint16_t __iomem *)host->regs->spare_area[0];
|
||||
union {
|
||||
uint16_t word;
|
||||
uint8_t bytes[2];
|
||||
|
|
@ -464,9 +922,10 @@ static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
|
|||
col += mtd->writesize;
|
||||
|
||||
if (col < mtd->writesize) {
|
||||
p = (uint16_t __iomem *)(host->regs->main_area0 + (col >> 1));
|
||||
p = (uint16_t __iomem *)(host->regs->main_area[0] +
|
||||
(col >> 1));
|
||||
} else {
|
||||
p = (uint16_t __iomem *)(host->regs->spare_area0 +
|
||||
p = (uint16_t __iomem *)(host->regs->spare_area[0] +
|
||||
((col - mtd->writesize) >> 1));
|
||||
}
|
||||
|
||||
|
|
@ -525,9 +984,9 @@ static void mxc_nand_write_buf(struct mtd_info *mtd,
|
|||
void __iomem *p;
|
||||
|
||||
if (col < mtd->writesize) {
|
||||
p = host->regs->main_area0 + (col & ~3);
|
||||
p = host->regs->main_area[0] + (col & ~3);
|
||||
} else {
|
||||
p = host->regs->spare_area0 -
|
||||
p = host->regs->spare_area[0] -
|
||||
mtd->writesize + (col & ~3);
|
||||
}
|
||||
|
||||
|
|
@ -595,9 +1054,9 @@ static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
|
|||
void __iomem *p;
|
||||
|
||||
if (col < mtd->writesize) {
|
||||
p = host->regs->main_area0 + (col & ~3);
|
||||
p = host->regs->main_area[0] + (col & ~3);
|
||||
} else {
|
||||
p = host->regs->spare_area0 -
|
||||
p = host->regs->spare_area[0] -
|
||||
mtd->writesize + (col & ~3);
|
||||
}
|
||||
|
||||
|
|
@ -683,7 +1142,7 @@ static void mxc_nand_select_chip(struct mtd_info *mtd, int chip)
|
|||
* Used by the upper layer to write command to NAND Flash for
|
||||
* different operations to be carried out on NAND Flash
|
||||
*/
|
||||
static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
|
||||
void mxc_nand_command(struct mtd_info *mtd, unsigned command,
|
||||
int column, int page_addr)
|
||||
{
|
||||
struct nand_chip *nand_chip = mtd->priv;
|
||||
|
|
@ -705,6 +1164,7 @@ static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
|
|||
break;
|
||||
|
||||
case NAND_CMD_READ0:
|
||||
host->page_addr = page_addr;
|
||||
host->col_addr = column;
|
||||
host->spare_only = false;
|
||||
break;
|
||||
|
|
@ -750,7 +1210,7 @@ static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
|
|||
case NAND_CMD_PAGEPROG:
|
||||
send_prog_page(host, 0, host->spare_only);
|
||||
|
||||
if (host->pagesize_2k) {
|
||||
if (host->pagesize_2k && !is_mxc_nfc_11()) {
|
||||
/* data in 4 areas datas */
|
||||
send_prog_page(host, 1, host->spare_only);
|
||||
send_prog_page(host, 2, host->spare_only);
|
||||
|
|
@ -780,30 +1240,12 @@ static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
|
|||
|
||||
/* Write out page address, if necessary */
|
||||
if (page_addr != -1) {
|
||||
/* paddr_0 - p_addr_7 */
|
||||
send_addr(host, (page_addr & 0xff));
|
||||
|
||||
if (host->pagesize_2k) {
|
||||
send_addr(host, (page_addr >> 8) & 0xFF);
|
||||
if (mtd->size >= 0x10000000) {
|
||||
/* paddr_8 - paddr_15 */
|
||||
send_addr(host, (page_addr >> 8) & 0xff);
|
||||
send_addr(host, (page_addr >> 16) & 0xff);
|
||||
} else {
|
||||
/* paddr_8 - paddr_15 */
|
||||
send_addr(host, (page_addr >> 8) & 0xff);
|
||||
}
|
||||
} else {
|
||||
/* One more address cycle for higher density devices */
|
||||
if (mtd->size >= 0x4000000) {
|
||||
/* paddr_8 - paddr_15 */
|
||||
send_addr(host, (page_addr >> 8) & 0xff);
|
||||
send_addr(host, (page_addr >> 16) & 0xff);
|
||||
} else {
|
||||
/* paddr_8 - paddr_15 */
|
||||
send_addr(host, (page_addr >> 8) & 0xff);
|
||||
}
|
||||
}
|
||||
u32 page_mask = nand_chip->pagemask;
|
||||
do {
|
||||
send_addr(host, page_addr & 0xFF);
|
||||
page_addr >>= 8;
|
||||
page_mask >>= 8;
|
||||
} while (page_mask);
|
||||
}
|
||||
|
||||
/* Command post-processing step */
|
||||
|
|
@ -819,9 +1261,11 @@ static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
|
|||
send_cmd(host, NAND_CMD_READSTART);
|
||||
/* read for each AREA */
|
||||
send_read_page(host, 0, host->spare_only);
|
||||
send_read_page(host, 1, host->spare_only);
|
||||
send_read_page(host, 2, host->spare_only);
|
||||
send_read_page(host, 3, host->spare_only);
|
||||
if (!is_mxc_nfc_11()) {
|
||||
send_read_page(host, 1, host->spare_only);
|
||||
send_read_page(host, 2, host->spare_only);
|
||||
send_read_page(host, 3, host->spare_only);
|
||||
}
|
||||
} else {
|
||||
send_read_page(host, 0, host->spare_only);
|
||||
}
|
||||
|
|
@ -843,6 +1287,24 @@ static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
|
|||
}
|
||||
}
|
||||
|
||||
#ifdef MXC_NFC_V1_1
|
||||
static void mxc_setup_config1(void)
|
||||
{
|
||||
uint16_t tmp;
|
||||
|
||||
tmp = readw(&host->regs->nfc_config1);
|
||||
tmp |= NFC_ONE_CYCLE;
|
||||
tmp |= NFC_4_8N_ECC;
|
||||
writew(tmp, &host->regs->nfc_config1);
|
||||
if (host->pagesize_2k)
|
||||
writew(64/2, &host->regs->nfc_spare_area_size);
|
||||
else
|
||||
writew(16/2, &host->regs->nfc_spare_area_size);
|
||||
}
|
||||
#else
|
||||
#define mxc_setup_config1()
|
||||
#endif
|
||||
|
||||
int board_nand_init(struct nand_chip *this)
|
||||
{
|
||||
struct mtd_info *mtd;
|
||||
|
|
@ -874,10 +1336,23 @@ int board_nand_init(struct nand_chip *this)
|
|||
this->ecc.calculate = mxc_nand_calculate_ecc;
|
||||
this->ecc.hwctl = mxc_nand_enable_hwecc;
|
||||
this->ecc.correct = mxc_nand_correct_data;
|
||||
this->ecc.mode = NAND_ECC_HW;
|
||||
if (is_mxc_nfc_11()) {
|
||||
this->ecc.mode = NAND_ECC_HW_SYNDROME;
|
||||
this->ecc.read_page = mxc_nand_read_page_syndrome;
|
||||
this->ecc.read_page_raw = mxc_nand_read_page_raw_syndrome;
|
||||
this->ecc.read_oob = mxc_nand_read_oob_syndrome;
|
||||
this->ecc.write_page = mxc_nand_write_page_syndrome;
|
||||
this->ecc.write_page_raw = mxc_nand_write_page_raw_syndrome;
|
||||
this->ecc.write_oob = mxc_nand_write_oob_syndrome;
|
||||
this->ecc.bytes = 9;
|
||||
this->ecc.prepad = 7;
|
||||
} else {
|
||||
this->ecc.mode = NAND_ECC_HW;
|
||||
}
|
||||
|
||||
host->pagesize_2k = 0;
|
||||
|
||||
this->ecc.size = 512;
|
||||
this->ecc.bytes = 3;
|
||||
this->ecc.layout = &nand_hw_eccoob;
|
||||
tmp = readw(&host->regs->nfc_config1);
|
||||
tmp |= NFC_ECC_EN;
|
||||
writew(tmp, &host->regs->nfc_config1);
|
||||
|
|
@ -888,7 +1363,6 @@ int board_nand_init(struct nand_chip *this)
|
|||
tmp &= ~NFC_ECC_EN;
|
||||
writew(tmp, &host->regs->nfc_config1);
|
||||
#endif
|
||||
|
||||
/* Reset NAND */
|
||||
this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
|
||||
|
||||
|
|
@ -911,10 +1385,11 @@ int board_nand_init(struct nand_chip *this)
|
|||
|
||||
#ifdef CONFIG_SYS_NAND_LARGEPAGE
|
||||
host->pagesize_2k = 1;
|
||||
this->ecc.layout = &nand_hw_eccoob_largepage;
|
||||
this->ecc.layout = &nand_hw_eccoob2k;
|
||||
#else
|
||||
host->pagesize_2k = 0;
|
||||
this->ecc.layout = &nand_hw_eccoob;
|
||||
#endif
|
||||
|
||||
mxc_setup_config1();
|
||||
return err;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue