* Patch by Yuli Barcohen, 3 Dec 2003:
"revive" U-Boot support for old Motorola MPC860ADS board * Patch by Cam(ilo?), 03 Dec 2003: make examples build even with broken Montavista objcopy * Patch by Pavel Bartusek, 27 Nov 2003: fix conversion problem with "bootretry" evironment variable
This commit is contained in:
wdenk
parent
b4676a25e2
commit
b028f71513
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@ -2,6 +2,15 @@
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Changes since U-Boot 1.0.0:
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======================================================================
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* Patch by Yuli Barcohen, 3 Dec 2003:
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"revive" U-Boot support for old Motorola MPC860ADS board
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* Patch by Cam(ilo?), 03 Dec 2003:
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make examples build even with broken Montavista objcopy
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* Patch by Pavel Bartusek, 27 Nov 2003:
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fix conversion problem with "bootretry" evironment variable
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* Patch by Andre Schwarz, 24 Nov 2003:
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add support for mvblue (mvBlueLYNX and mvBlueBOX) boards
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3
Makefile
3
Makefile
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@ -115,6 +115,7 @@ SUBDIRS = tools \
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examples \
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post \
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post/cpu
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.PHONY : $(SUBDIRS)
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#########################################################################
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#########################################################################
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@ -150,7 +151,7 @@ $(LIBS):
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$(SUBDIRS):
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@echo "#### MAKE $@ ####"
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$(MAKE) -C $@
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$(MAKE) -C $@ all
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gdbtools:
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$(MAKE) -C tools/gdb || exit 1
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@ -22,9 +22,9 @@
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#
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#
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# FADS boards
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# Motorola old MPC821/860ADS, MPC8xxFADS, and new MPC866ADS boards
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#
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#TEXT_BASE = 0xFE000000
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TEXT_BASE = 0x02800000
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OBJCFLAGS = --set-section-flags=.ppcenv=contents,alloc,load,data
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TEXT_BASE = 0xFE000000
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#TEXT_BASE = 0x02800000
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#OBJCFLAGS = --set-section-flags=.ppcenv=contents,alloc,load,data
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@ -360,7 +360,11 @@ static int _draminit (uint base, uint noMbytes, uint edo, uint delay)
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switch (noMbytes) {
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case 4: /* 4 Mbyte uses only CS2 */
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#ifdef CONFIG_ADS
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memctl->memc_mamr = 0xc0a21114;
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#else
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memctl->memc_mamr = 0x13a01114; /* PTA 0x13 AMA 010 */
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#endif
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memctl->memc_or2 = 0xffc00800; /* 4M */
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break;
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@ -393,17 +397,18 @@ static int _draminit (uint base, uint noMbytes, uint edo, uint delay)
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memctl->memc_br2 = 0x81 + base; /* use upma */
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*((uint *) BCSR1) &= ~BCSR1_DRAM_EN; /* enable dram */
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/* if no dimm is inserted, noMbytes is still detected as 8m, so
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* sanity check top and bottom of memory */
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*((uint *) BCSR1) &= ~BCSR1_DRAM_EN; /* enable dram */
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/* check bytes / 2 because dram_size tests at base+bytes, which
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* is not mapped */
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if (dram_size ((long *) base, noMbytes << 19) != noMbytes << 19) {
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*((uint *) BCSR1) |= BCSR1_DRAM_EN; /* disable dram */
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return -1;
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}
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if (noMbytes == 8)
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if (dram_size ((long *) base, noMbytes << 19) != noMbytes << 19) {
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*((uint *) BCSR1) |= BCSR1_DRAM_EN; /* disable dram */
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return -1;
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}
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return 0;
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}
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@ -1,4 +1,7 @@
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#include <config.h>
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#ifndef CONFIG_ADS /* Old ADS has not got any user-controllable LED */
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#include <common.h>
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void
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@ -40,3 +43,5 @@ fast_blink(unsigned int n)
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signal_delay(0x00100000);
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}
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}
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#endif /* !CONFIG_ADS */
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@ -22,9 +22,6 @@
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*/
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OUTPUT_ARCH(powerpc)
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SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
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/* Do we need any of these for elf?
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__DYNAMIC = 0; */
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SECTIONS
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{
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/* Read-only sections, merged into text segment: */
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@ -33,41 +30,30 @@ SECTIONS
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.hash : { *(.hash) }
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.dynsym : { *(.dynsym) }
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.dynstr : { *(.dynstr) }
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.rel.text : { *(.rel.text) }
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.rel.text : { *(.rel.text) }
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.rela.text : { *(.rela.text) }
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.rel.data : { *(.rel.data) }
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.rel.data : { *(.rel.data) }
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.rela.data : { *(.rela.data) }
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.rel.rodata : { *(.rel.rodata) }
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.rela.rodata : { *(.rela.rodata) }
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.rel.got : { *(.rel.got) }
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.rela.got : { *(.rela.got) }
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.rel.got : { *(.rel.got) }
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.rela.got : { *(.rela.got) }
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.rel.ctors : { *(.rel.ctors) }
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.rela.ctors : { *(.rela.ctors) }
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.rel.dtors : { *(.rel.dtors) }
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.rela.dtors : { *(.rela.dtors) }
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.rel.bss : { *(.rel.bss) }
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.rela.bss : { *(.rela.bss) }
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.rel.plt : { *(.rel.plt) }
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.rela.plt : { *(.rela.plt) }
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.init : { *(.init) }
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.rel.bss : { *(.rel.bss) }
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.rela.bss : { *(.rela.bss) }
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.rel.plt : { *(.rel.plt) }
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.rela.plt : { *(.rela.plt) }
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.init : { *(.init) }
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.plt : { *(.plt) }
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.text :
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{
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/* WARNING - the following is hand-optimized to fit within */
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/* the sector layout of our flash chips! XXX FIXME XXX */
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cpu/mpc8xx/start.o (.text)
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cpu/mpc8xx/start.o (.text)
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/*
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cpu/mpc8xx/start.o (.text)
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common/dlmalloc.o (.text)
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lib_ppc/ppcstring.o (.text)
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lib_generic/vsprintf.o (.text)
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lib_generic/crc32.o (.text)
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lib_generic/zlib.o (.text)
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. = env_offset;
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common/environment.o(.text)
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*/
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. = DEFINED(env_offset) ? env_offset : .;
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common/environment.o (.ppcenv)
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*(.text)
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*(.fixup)
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@ -136,11 +122,7 @@ SECTIONS
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*(.bss)
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*(COMMON)
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}
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. = ALIGN(256 * 1024);
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.ppcenv :
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{
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common/environment.o (.ppcenv)
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}
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_end = . ;
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PROVIDE (end = .);
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}
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ENTRY(_start)
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@ -57,7 +57,7 @@
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#include <command.h>
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#include <config.h>
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#include <pcmcia.h>
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#if defined(CONFIG_IDE_8xx_PCCARD) && defined(CONFIG_8xx)
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#if defined(CONFIG_8xx)
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#include <mpc8xx.h>
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#endif
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#if defined(CONFIG_LWMON)
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@ -505,7 +505,7 @@ void init_cmd_timeout(void)
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char *s = getenv ("bootretry");
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if (s != NULL)
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retry_time = (int)simple_strtoul(s, NULL, 10);
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retry_time = (int)simple_strtol(s, NULL, 10);
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else
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retry_time = CONFIG_BOOT_RETRY_TIME;
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@ -145,9 +145,7 @@ void cpu_init_f (volatile immap_t * immr)
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defined(CONFIG_R360MPI) || \
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defined(CONFIG_RPXCLASSIC) || \
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defined(CONFIG_RPXLITE) || \
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defined(CONFIG_SPD823TS) || \
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defined(CONFIG_MPC86xADS) || \
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(defined(CONFIG_MPC860T) && defined(CONFIG_FADS))
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defined(CONFIG_SPD823TS)
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memctl->memc_br0 = CFG_BR0_PRELIM;
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#endif
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@ -153,7 +153,7 @@ int serial_init (void)
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# endif
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#endif
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#if defined(CONFIG_FADS)
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#if defined(CONFIG_FADS) || defined(CONFIG_ADS)
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/* Enable RS232 */
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#if defined(CONFIG_8xx_CONS_SMC1)
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*((uint *) BCSR1) &= ~BCSR1_RS232EN_1;
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@ -104,7 +104,7 @@ $(LIB): .depend $(LIBOBJS)
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$(OBJCOPY) -O srec $(<:.o=) $@
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%.bin: %.srec
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$(OBJCOPY) -O binary $< $@ 2>/dev/null
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$(OBJCOPY) -O binary $(<:.srec=) $@ 2>/dev/null
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#########################################################################
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@ -16,29 +16,31 @@
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* High Level Configuration Options
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* (easy to change)
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*/
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#include <mpc8xx_irq.h>
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/* Board type */
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#define CONFIG_ADS 1 /* Old Motorola MPC821/860ADS */
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/* Processor type */
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#define CONFIG_MPC860 1
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#define CONFIG_MPC860T 1
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#define CONFIG_ADS 1
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#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
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#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
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#undef CONFIG_8xx_CONS_SMC2
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#undef CONFIG_8xx_CONS_NONE
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#define CONFIG_BAUDRATE 19200 /* console baudrate */
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#define CONFIG_PCMCIA 1 /* To enable PCMCIA support */
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#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
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#define CFG_I2C_SPEED 400000 /* I2C speed and slave address defaults */
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#define CFG_I2C_SLAVE 0x7F
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#define CONFIG_BAUDRATE 38400 /* Console baudrate */
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/* CFG_8XX_FACT * CFG_8XX_XIN = 50 MHz */
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#if 0
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#define CFG_8XX_XIN 32768 /* 32.768 kHz input frequency */
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#define CFG_8XX_FACT 0x5F6 /* Multiply by 1526 */
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/* MPC8XX_FACT * MPC8XX_XIN = 50 MHz */
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#else
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#define CFG_8XX_XIN 4000000 /* 4 MHz input frequency */
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#define CFG_8XX_FACT 12 /* Multiply by 12 */
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#endif
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#define CONFIG_8xx_GCLK_FREQ ((CFG_8XX_XIN) * (CFG_8XX_FACT))
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#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
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#define CONFIG_DRAM_50MHZ 1
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#if 0
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#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
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|
@ -47,11 +49,11 @@
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#endif
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#undef CONFIG_BOOTARGS
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#define CONFIG_BOOTCOMMAND \
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"bootp; " \
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"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
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"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
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"bootm"
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#define CONFIG_BOOTCOMMAND \
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"dhcp;" \
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"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
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"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
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"bootm"
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
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|
@ -60,18 +62,16 @@
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#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
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#if 0 /* private command defs */
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#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_I2C | \
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CFG_CMD_IDE | CFG_CMD_PCMCIA)
|
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#endif
|
||||
/* default command defs */
|
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#define CONFIG_COMMANDS (CONFIG_CMD_DFL & ~CFG_CMD_CACHE)
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#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
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| CFG_CMD_DHCP \
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| CFG_CMD_IMMAP \
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| CFG_CMD_PCMCIA \
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| CFG_CMD_PING \
|
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)
|
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
|
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#include <cmd_confdefs.h>
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||||
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
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|
@ -103,7 +103,7 @@
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/*-----------------------------------------------------------------------
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* Internal Memory Mapped Register
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*/
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#define CFG_IMMR 0xfff00000
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#define CFG_IMMR 0xFF000000
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#define CFG_IMMR_SIZE ((uint)(64 * 1024))
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||||
|
||||
/*-----------------------------------------------------------------------
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||||
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|
@ -121,13 +121,6 @@
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* Please note that CFG_SDRAM_BASE _must_ start at 0
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*/
|
||||
#define CFG_SDRAM_BASE 0x00000000
|
||||
#define CFG_SRAM_BASE 0x00000000
|
||||
#define CFG_FLASH_BASE 0xfe000000
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||||
#define CFG_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */
|
||||
|
||||
#define CFG_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
|
||||
#define CFG_MONITOR_BASE CFG_FLASH_BASE
|
||||
#define CFG_MALLOC_LEN (384 << 10) /* Reserve 384 kB for malloc() */
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
|
|
@ -138,6 +131,9 @@
|
|||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization
|
||||
*/
|
||||
#define CFG_FLASH_BASE TEXT_BASE
|
||||
#define CFG_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */
|
||||
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
|
||||
#define CFG_MAX_FLASH_SECT 16 /* max number of sectors on one chip */
|
||||
|
||||
|
|
@ -148,9 +144,14 @@
|
|||
#undef CFG_ENV_IS_IN_EEPROM
|
||||
#define CFG_ENV_IS_IN_FLASH 1
|
||||
|
||||
#define CFG_ENV_OFFSET 0x00040000
|
||||
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
|
||||
#define CFG_ENV_SECT_SIZE 0x40000 /* see README - env sector total size */
|
||||
#define CFG_ENV_OFFSET CFG_ENV_SECT_SIZE
|
||||
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment */
|
||||
|
||||
#define CFG_MONITOR_BASE CFG_FLASH_BASE
|
||||
#define CFG_MONITOR_LEN (256 << 10) /* Reserve one flash sector
|
||||
(256 KB) for monitor */
|
||||
#define CFG_MALLOC_LEN (384 << 10) /* Reserve 384 kB for malloc() */
|
||||
|
||||
/* the other CS:s are determined by looking at parameters in BCSRx */
|
||||
|
||||
|
|
@ -162,6 +163,15 @@
|
|||
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* I2C configuration
|
||||
*/
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_I2C)
|
||||
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
|
||||
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address defaults */
|
||||
#define CFG_I2C_SLAVE 0x7F
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SYPCR - System Protection Control 11-9
|
||||
* SYPCR can only be written once after reset!
|
||||
|
|
@ -176,7 +186,7 @@
|
|||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SUMCR - SIU Module Configuration 11-6
|
||||
* SUMCR - SIU Module Configuration 11-6
|
||||
*-----------------------------------------------------------------------
|
||||
* PCMCIA config., multi-function pin tri-state
|
||||
*/
|
||||
|
|
@ -234,40 +244,22 @@
|
|||
/*
|
||||
* Init Memory Controller:
|
||||
*
|
||||
* BR0/1 and OR0/1 (FLASH)
|
||||
* BR0 and OR0 (FLASH)
|
||||
* BR1 and OR1 (BCSR)
|
||||
*/
|
||||
/* the other CS:s are determined by looking at parameters in BCSRx */
|
||||
|
||||
#define BCSR_ADDR ((uint) 0xff010000)
|
||||
#define BCSR_SIZE ((uint)(64 * 1024))
|
||||
|
||||
#define FLASH_BASE0_PRELIM 0xfe000000 /* FLASH bank #0 */
|
||||
#define FLASH_BASE1_PRELIM 0x00000000 /* FLASH bank #1 */
|
||||
|
||||
#define CFG_REMAP_OR_AM 0xff000000 /* OR addr mask */
|
||||
#define CFG_PRELIM_OR_AM 0xffe00000 /* OR addr mask */
|
||||
#define CFG_PRELIM_OR_AM 0xff800000 /* OR addr mask */
|
||||
|
||||
/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */
|
||||
#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
|
||||
|
||||
#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
|
||||
|
||||
#ifdef USE_REAL_FLASH_VALUES
|
||||
/*
|
||||
* These values fit our FADS860T ...
|
||||
* The "default" behaviour with 1Mbyte initial doesn't work for us!
|
||||
*/
|
||||
#define CFG_BR0_PRELIM 0x0fe000001 /* Real values for the board */
|
||||
#define CFG_OR0_PRELIM 0x0ffe00d34
|
||||
#define CFG_BR2_PRELIM 0x000000081
|
||||
#define CFG_OR2_PRELIM 0x0ff000800
|
||||
#else
|
||||
#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) /* 1 Mbyte until detected and only 1 Mbyte is needed*/
|
||||
#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
|
||||
#endif
|
||||
#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) /* 8 Mbyte until detected */
|
||||
#define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_V)
|
||||
|
||||
/* BCSRx - Board Control and Status Registers */
|
||||
/* #define CFG_OR1_REMAP CFG_OR0_REMAP */
|
||||
#define CFG_OR1_PRELIM 0xffff8110 /* 64Kbyte address space */
|
||||
#define CFG_BR1_PRELIM ((BCSR_ADDR) | BR_V )
|
||||
|
||||
|
|
@ -275,9 +267,6 @@
|
|||
* Memory Periodic Timer Prescaler
|
||||
*/
|
||||
|
||||
/* periodic timer for refresh */
|
||||
#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */
|
||||
|
||||
/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
|
||||
#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
|
||||
#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
|
||||
|
|
@ -286,20 +275,6 @@
|
|||
#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
|
||||
#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
|
||||
|
||||
/*
|
||||
* MAMR settings for SDRAM
|
||||
*/
|
||||
|
||||
/* 8 column SDRAM */
|
||||
#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
|
||||
MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
|
||||
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
|
||||
/* 9 column SDRAM */
|
||||
#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
|
||||
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
|
||||
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
|
||||
|
||||
#define CFG_MAMR 0x13a01114
|
||||
/*
|
||||
* Internal Definitions
|
||||
*
|
||||
|
|
@ -310,11 +285,10 @@
|
|||
|
||||
|
||||
/* values according to the manual */
|
||||
#define BCSR0 ((uint) (BCSR_ADDR + 00))
|
||||
#define BCSR1 ((uint) (BCSR_ADDR + 0x04))
|
||||
#define BCSR2 ((uint) (BCSR_ADDR + 0x08))
|
||||
#define BCSR3 ((uint) (BCSR_ADDR + 0x0c))
|
||||
#define BCSR4 ((uint) (BCSR_ADDR + 0x10))
|
||||
#define BCSR0 (BCSR_ADDR + 0x00)
|
||||
#define BCSR1 (BCSR_ADDR + 0x04)
|
||||
#define BCSR2 (BCSR_ADDR + 0x08)
|
||||
#define BCSR3 (BCSR_ADDR + 0x0c)
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
|
|
@ -322,6 +296,10 @@
|
|||
*-----------------------------------------------------------------------
|
||||
*
|
||||
*/
|
||||
#ifdef CONFIG_MPC860
|
||||
#define PCMCIA_SLOT_A 1
|
||||
#endif
|
||||
|
||||
#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
|
||||
#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
|
||||
#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
|
||||
|
|
@ -331,7 +309,6 @@
|
|||
#define CFG_PCMCIA_IO_ADDR (0xEC000000)
|
||||
#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* IDE/ATA stuff
|
||||
*-----------------------------------------------------------------------
|
||||
|
|
@ -346,7 +323,6 @@
|
|||
#define CFG_PIO_MODE 0 /* IDE interface in PIO Mode 0 */
|
||||
#define CFG_PC_IDE_RESET ((ushort)0x0008) /* PC 12 */
|
||||
|
||||
/* #define CFG_ATA_BASE_ADDR 0xFE100000 */
|
||||
#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
|
||||
#define CFG_ATA_IDE0_OFFSET 0x0000
|
||||
|
||||
|
|
@ -354,6 +330,8 @@
|
|||
#define CFG_ATA_REG_OFFSET 0x0080 /* Offset for normal register accesses */
|
||||
#define CFG_ATA_ALT_OFFSET 0x0100 /* Offset for alternate registers */
|
||||
|
||||
#define CONFIG_DISK_SPINUP_TIME 1000000
|
||||
#undef CONFIG_DISK_SPINUP_TIME /* usin´ Compact Flash */
|
||||
|
||||
/* (F)ADS bitvalues by Helmut Buchsbaum
|
||||
* see MPC8xxADS User's Manual for a proper description
|
||||
|
|
@ -399,65 +377,6 @@
|
|||
#define BCSR3_BREVN1 ((ushort)0x0008)
|
||||
#define BCSR3_BREVN2_MASK ((ushort)0x0003)
|
||||
|
||||
#define BCSR4_ETHLOOP ((uint)0x80000000)
|
||||
#define BCSR4_TFPLDL ((uint)0x40000000)
|
||||
#define BCSR4_TPSQEL ((uint)0x20000000)
|
||||
#define BCSR4_SIGNAL_LAMP ((uint)0x10000000)
|
||||
#ifdef CONFIG_MPC823
|
||||
#define BCSR4_USB_EN ((uint)0x08000000)
|
||||
#endif /* CONFIG_MPC823 */
|
||||
#ifdef CONFIG_MPC860SAR
|
||||
#define BCSR4_UTOPIA_EN ((uint)0x08000000)
|
||||
#endif /* CONFIG_MPC860SAR */
|
||||
#ifdef CONFIG_MPC860T
|
||||
#define BCSR4_FETH_EN ((uint)0x08000000)
|
||||
#endif /* CONFIG_MPC860T */
|
||||
#ifdef CONFIG_MPC823
|
||||
#define BCSR4_USB_SPEED ((uint)0x04000000)
|
||||
#endif /* CONFIG_MPC823 */
|
||||
#ifdef CONFIG_MPC860T
|
||||
#define BCSR4_FETHCFG0 ((uint)0x04000000)
|
||||
#endif /* CONFIG_MPC860T */
|
||||
#ifdef CONFIG_MPC823
|
||||
#define BCSR4_VCCO ((uint)0x02000000)
|
||||
#endif /* CONFIG_MPC823 */
|
||||
#ifdef CONFIG_MPC860T
|
||||
#define BCSR4_FETHFDE ((uint)0x02000000)
|
||||
#endif /* CONFIG_MPC860T */
|
||||
#ifdef CONFIG_MPC823
|
||||
#define BCSR4_VIDEO_ON ((uint)0x00800000)
|
||||
#endif /* CONFIG_MPC823 */
|
||||
#ifdef CONFIG_MPC823
|
||||
#define BCSR4_VDO_EKT_CLK_EN ((uint)0x00400000)
|
||||
#endif /* CONFIG_MPC823 */
|
||||
#ifdef CONFIG_MPC860T
|
||||
#define BCSR4_FETHCFG1 ((uint)0x00400000)
|
||||
#endif /* CONFIG_MPC860T */
|
||||
#ifdef CONFIG_MPC823
|
||||
#define BCSR4_VIDEO_RST ((uint)0x00200000)
|
||||
#endif /* CONFIG_MPC823 */
|
||||
#ifdef CONFIG_MPC860T
|
||||
#define BCSR4_FETHRST ((uint)0x00200000)
|
||||
#endif /* CONFIG_MPC860T */
|
||||
#ifdef CONFIG_MPC823
|
||||
#define BCSR4_MODEM_EN ((uint)0x00100000)
|
||||
#endif /* CONFIG_MPC823 */
|
||||
#ifdef CONFIG_MPC823
|
||||
#define BCSR4_DATA_VOICE ((uint)0x00080000)
|
||||
#endif /* CONFIG_MPC823 */
|
||||
#ifdef CONFIG_MPC850
|
||||
#define BCSR4_DATA_VOICE ((uint)0x00080000)
|
||||
#endif /* CONFIG_MPC850 */
|
||||
|
||||
#define CONFIG_DRAM_50MHZ 1
|
||||
#define CONFIG_SDRAM_50MHZ
|
||||
|
||||
#ifdef CONFIG_MPC860T
|
||||
/* Interrupt level assignments.
|
||||
*/
|
||||
#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */
|
||||
#endif /* CONFIG_MPC860T */
|
||||
|
||||
/* We don't use the 8259.
|
||||
*/
|
||||
#define NR_8259_INTS 0
|
||||
|
|
@ -466,17 +385,4 @@
|
|||
*/
|
||||
#define _MACH_8xx (_MACH_ads)
|
||||
|
||||
#if 0
|
||||
#define CONFIG_DISK_SPINUP_TIME 1000000
|
||||
#endif
|
||||
#undef CONFIG_DISK_SPINUP_TIME /* usin´ Compact Flash */
|
||||
|
||||
|
||||
/* PCMCIA configuration
|
||||
*/
|
||||
#define PCMCIA_MAX_SLOTS 2
|
||||
#ifdef CONFIG_MPC860
|
||||
#define PCMCIA_SLOT_A 1
|
||||
#endif
|
||||
|
||||
#endif /* _CONFIG_ADS860_H */
|
||||
|
|
|
|||
|
|
@ -30,7 +30,6 @@
|
|||
* High Level Configuration Options
|
||||
* (easy to change)
|
||||
*/
|
||||
#include <mpc8xx_irq.h>
|
||||
|
||||
/* board type */
|
||||
#define CONFIG_FADS 1 /* old/new FADS + new ADS */
|
||||
|
|
@ -58,9 +57,6 @@
|
|||
/* in general, we always know this for FADS+new ADS anyway */
|
||||
#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ
|
||||
|
||||
/* most vanilla kernels do not like this, set to 0 if in doubt */
|
||||
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
|
||||
|
||||
#if 1
|
||||
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
|
||||
#else
|
||||
|
|
@ -163,11 +159,11 @@
|
|||
# define CFG_SDRAM_SIZE 0x00000000 /* NO SDRAM */
|
||||
#endif
|
||||
|
||||
#define CFG_FLASH_BASE 0x02800000
|
||||
#define CFG_FLASH_BASE TEXT_BASE
|
||||
|
||||
#define CFG_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */
|
||||
|
||||
#define CFG_MONITOR_LEN (272 << 10) /* Reserve 272 kB for Monitor */
|
||||
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
|
||||
#define CFG_MONITOR_BASE CFG_FLASH_BASE
|
||||
#define CFG_MALLOC_LEN (384 << 10) /* Reserve 384 kB for malloc() */
|
||||
|
||||
|
|
@ -184,7 +180,7 @@
|
|||
#define CFG_MAX_FLASH_SECT 16 /* max number of sectors on one chip */
|
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
|
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
|
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
|
||||
|
||||
#define CFG_ENV_IS_IN_FLASH 1
|
||||
#define CFG_ENV_OFFSET 0x00040000
|
||||
|
|
@ -276,14 +272,11 @@
|
|||
#define BCSR_ADDR ((uint) 0xFF010000)
|
||||
#define BCSR_SIZE ((uint)(64 * 1024))
|
||||
|
||||
#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
|
||||
#define CFG_PRELIM_OR_AM 0xFF800000 /* OR addr mask */
|
||||
|
||||
/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */
|
||||
/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */
|
||||
#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
|
||||
|
||||
#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
|
||||
|
||||
#ifdef USE_REAL_FLASH_VALUES
|
||||
/*
|
||||
* These values fit our FADS860T ...
|
||||
|
|
@ -297,7 +290,6 @@
|
|||
#endif
|
||||
|
||||
/* BCSRx - Board Control and Status Registers */
|
||||
#define CFG_OR1_REMAP CFG_OR0_REMAP
|
||||
#define CFG_OR1_PRELIM 0xffff8110 /* 64Kbyte address space */
|
||||
#define CFG_BR1_PRELIM ((BCSR_ADDR) | BR_V )
|
||||
|
||||
|
|
@ -316,7 +308,7 @@
|
|||
#define PCMCIA_MEM_ADDR ((uint)0xff020000)
|
||||
#define PCMCIA_MEM_SIZE ((uint)(64 * 1024))
|
||||
|
||||
#define BCSR0 ((uint) (BCSR_ADDR + 00))
|
||||
#define BCSR0 ((uint) (BCSR_ADDR + 0x00))
|
||||
#define BCSR1 ((uint) (BCSR_ADDR + 0x04))
|
||||
#define BCSR2 ((uint) (BCSR_ADDR + 0x08))
|
||||
#define BCSR3 ((uint) (BCSR_ADDR + 0x0c))
|
||||
|
|
@ -418,14 +410,6 @@
|
|||
#define CONFIG_DRAM_50MHZ 1
|
||||
#define CONFIG_SDRAM_50MHZ 1
|
||||
|
||||
#ifdef CONFIG_MPC860T
|
||||
|
||||
/* Interrupt level assignments.
|
||||
*/
|
||||
#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */
|
||||
|
||||
#endif /* CONFIG_MPC860T */
|
||||
|
||||
/* We don't use the 8259.
|
||||
*/
|
||||
#define NR_8259_INTS 0
|
||||
|
|
@ -439,8 +423,6 @@
|
|||
|
||||
/* PCMCIA configuration */
|
||||
|
||||
#define PCMCIA_MAX_SLOTS 2
|
||||
|
||||
#ifdef CONFIG_MPC860
|
||||
#define PCMCIA_SLOT_A 1
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -9,10 +9,10 @@
|
|||
* 1999-nov-26: The FADS is using the following physical memorymap:
|
||||
*
|
||||
* ff020000 -> ff02ffff : pcmcia
|
||||
* ff010000 -> ff01ffff : BCSR connected to CS1, setup by 8xxrom
|
||||
* ff010000 -> ff01ffff : BCSR connected to CS1
|
||||
* ff000000 -> ff00ffff : IMAP internal in the cpu
|
||||
* fe000000 -> ffnnnnnn : flash connected to CS0, setup by 8xxrom
|
||||
* 00000000 -> nnnnnnnn : sdram/dram setup by 8xxrom
|
||||
* fe000000 -> fennnnnn : flash connected to CS0
|
||||
* 00000000 -> nnnnnnnn : sdram connected to CS4
|
||||
*/
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
|
@ -28,7 +28,6 @@
|
|||
* High Level Configuration Options
|
||||
* (easy to change)
|
||||
*/
|
||||
#include <mpc8xx_irq.h>
|
||||
|
||||
/* board type */
|
||||
#define CONFIG_MPC86xADS 1 /* new ADS */
|
||||
|
|
@ -66,9 +65,6 @@
|
|||
/* in general, we always know this for FADS+new ADS anyway */
|
||||
#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ
|
||||
|
||||
/* most vanilla kernels do not like this, set to 0 if in doubt */
|
||||
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
|
||||
|
||||
#if 1
|
||||
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
|
||||
#else
|
||||
|
|
@ -76,14 +72,12 @@
|
|||
#endif
|
||||
|
||||
#undef CONFIG_BOOTARGS
|
||||
#define CONFIG_BOOTCOMMAND \
|
||||
"bootp; " \
|
||||
"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
|
||||
"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
|
||||
#define CONFIG_BOOTCOMMAND \
|
||||
"dhcp;" \
|
||||
"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
|
||||
"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
|
||||
"bootm"
|
||||
|
||||
/* #include "local.h" */
|
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
||||
|
||||
/* ATA / IDE and partition support */
|
||||
|
|
@ -96,21 +90,27 @@
|
|||
#undef CONFIG_IDE_LED /* LED for ide not supported */
|
||||
#undef CONFIG_IDE_RESET /* reset for ide not supported */
|
||||
|
||||
/* choose SCC1 ethernet (10BASET on motherboard)
|
||||
* or FEC ethernet (10/100 on daughterboard)
|
||||
/*
|
||||
* New MPC86xADS provides two Ethernet connectivity options:
|
||||
* 10Mbit/s on SCC1 and 100Mbit/s on FEC. All new PQ1 chips
|
||||
* has got FEC so FEC is the default.
|
||||
*/
|
||||
#if 0
|
||||
#define CONFIG_SCC1_ENET 1 /* use SCC1 ethernet */
|
||||
#undef CONFIG_FEC_ENET /* disable FEC ethernet */
|
||||
#else /* all 86x cores have FECs, if in doubt, use it */
|
||||
#undef CONFIG_SCC1_ENET /* disable SCC1 ethernet */
|
||||
#define CONFIG_FEC_ENET 1 /* use FEC ethernet */
|
||||
#ifdef CONFIG_FEC_ENET
|
||||
#define CFG_DISCOVER_PHY
|
||||
#endif
|
||||
#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
|
||||
#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
|
||||
#endif
|
||||
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
|
||||
| CFG_CMD_DHCP \
|
||||
| CFG_CMD_IMMAP \
|
||||
| CFG_CMD_MII \
|
||||
| CFG_CMD_PING \
|
||||
)
|
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
|
||||
#include <cmd_confdefs.h>
|
||||
|
||||
|
|
@ -128,13 +128,6 @@
|
|||
#define CFG_MAXARGS 16 /* max number of command args */
|
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
#define CFG_MEMTEST_START 0x0100000 /* memtest works on */
|
||||
#if (CFG_SDRAM_SIZE)
|
||||
#define CFG_MEMTEST_END CFG_SDRAM_SIZE /* 1 ... SDRAM_SIZE */
|
||||
#else
|
||||
#define CFG_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */
|
||||
#endif
|
||||
|
||||
#define CFG_LOAD_ADDR 0x00100000
|
||||
|
||||
#define CFG_HZ 1000 /* decr freq: 1 ms ticks */
|
||||
|
|
@ -167,23 +160,20 @@
|
|||
* Please note that CFG_SDRAM_BASE _must_ start at 0
|
||||
*/
|
||||
#define CFG_SDRAM_BASE 0x00000000
|
||||
#ifdef CONFIG_FADS
|
||||
# ifdef CONFIG_MPC86xADS /* new ADS */
|
||||
# define CFG_SDRAM_SIZE 0x00800000 /* 8 meg */
|
||||
# else /* old/new FADS */
|
||||
# define CFG_SDRAM_SIZE 0x00400000 /* 4 meg */
|
||||
# endif
|
||||
#else /* !CONFIG_FADS */ /* old ADS */
|
||||
# define CFG_SDRAM_SIZE 0x00000000 /* NO SDRAM */
|
||||
#if defined(CONFIG_MPC86xADS) /* new ADS */
|
||||
#define CFG_SDRAM_SIZE 0x00800000 /* 8 meg */
|
||||
#elif defined(CONFIG_FADS) /* old/new FADS */
|
||||
#define CFG_SDRAM_SIZE 0x00400000 /* 4 meg */
|
||||
#else /* old ADS */
|
||||
#define CFG_SDRAM_SIZE 0x00000000 /* No SDRAM */
|
||||
#endif
|
||||
|
||||
#define CFG_FLASH_BASE 0x02800000
|
||||
|
||||
#define CFG_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */
|
||||
|
||||
#define CFG_MONITOR_LEN (272 << 10) /* Reserve 272 kB for Monitor */
|
||||
#define CFG_MONITOR_BASE CFG_FLASH_BASE
|
||||
#define CFG_MALLOC_LEN (384 << 10) /* Reserve 384 kB for malloc() */
|
||||
#define CFG_MEMTEST_START 0x0100000 /* memtest works on */
|
||||
#if (CFG_SDRAM_SIZE)
|
||||
#define CFG_MEMTEST_END CFG_SDRAM_SIZE /* 1 ... SDRAM_SIZE */
|
||||
#else
|
||||
#define CFG_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */
|
||||
#endif /* CFG_SDRAM_SIZE */
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
|
|
@ -194,6 +184,9 @@
|
|||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization
|
||||
*/
|
||||
#define CFG_FLASH_BASE TEXT_BASE
|
||||
#define CFG_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */
|
||||
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
|
||||
#define CFG_MAX_FLASH_SECT 16 /* max number of sectors on one chip */
|
||||
|
||||
|
|
@ -201,10 +194,13 @@
|
|||
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
|
||||
|
||||
#define CFG_ENV_IS_IN_FLASH 1
|
||||
#define CFG_ENV_OFFSET 0x00040000
|
||||
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
|
||||
|
||||
#define CFG_ENV_SECT_SIZE 0x40000 /* see README - env sector total size */
|
||||
#define CFG_ENV_OFFSET CFG_ENV_SECT_SIZE
|
||||
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment */
|
||||
|
||||
#define CFG_MONITOR_BASE CFG_FLASH_BASE
|
||||
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 KB for monitor */
|
||||
#define CFG_MALLOC_LEN (384 << 10) /* Reserve 384 kB for malloc() */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration
|
||||
|
|
@ -215,7 +211,7 @@
|
|||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SYPCR - System Protection Control 11-9
|
||||
* SYPCR - System Protection Control 11-9
|
||||
* SYPCR can only be written once after reset!
|
||||
*-----------------------------------------------------------------------
|
||||
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
|
||||
|
|
@ -228,14 +224,14 @@
|
|||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SIUMCR - SIU Module Configuration 11-6
|
||||
* SIUMCR - SIU Module Configuration 11-6
|
||||
*-----------------------------------------------------------------------
|
||||
* PCMCIA config., multi-function pin tri-state
|
||||
*/
|
||||
#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* TBSCR - Time Base Status and Control 11-26
|
||||
* TBSCR - Time Base Status and Control 11-26
|
||||
*-----------------------------------------------------------------------
|
||||
* Clear Reference Interrupt Status, Timebase freezing enabled
|
||||
*/
|
||||
|
|
@ -249,9 +245,9 @@
|
|||
#define CFG_PISCR (PISCR_PS | PISCR_PITF)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
|
||||
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
|
||||
*-----------------------------------------------------------------------
|
||||
* set the PLL, the low-power modes and the reset control (15-29)
|
||||
* set the PLL, the low-power modes and the reset control (15-29)
|
||||
*/
|
||||
#define CFG_PLPRCR ((CFG_8XX_FACT << PLPRCR_MFI_SHIFT) | \
|
||||
PLPRCR_SPLSS | PLPRCR_TEXPS)
|
||||
|
|
@ -283,34 +279,23 @@
|
|||
/*
|
||||
* Init Memory Controller:
|
||||
*
|
||||
* BR0/1 and OR0/1 (FLASH)
|
||||
* BR0/OR0 (Flash)
|
||||
* BR1/OR1 (BCSR)
|
||||
*/
|
||||
/* the other CS:s are determined by looking at parameters in BCSRx */
|
||||
|
||||
#define BCSR_ADDR ((uint) 0xFF010000)
|
||||
#define BCSR_SIZE ((uint)(64 * 1024))
|
||||
|
||||
#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
|
||||
#define CFG_PRELIM_OR_AM 0xFF800000 /* OR addr mask */
|
||||
|
||||
/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */
|
||||
/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */
|
||||
#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
|
||||
|
||||
#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
|
||||
|
||||
#ifdef USE_REAL_FLASH_VALUES
|
||||
/*
|
||||
* The "default" behaviour with 1Mbyte initial doesn't work for us!
|
||||
*/
|
||||
#define CFG_OR0_PRELIM 0x0FFC00D34 /* Real values for the board */
|
||||
#define CFG_BR0_PRELIM 0x02800001 /* Real values for the board */
|
||||
#else
|
||||
#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) /* 8 Mbyte until detected */
|
||||
#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BR_BA_MSK) | BR_V )
|
||||
#endif
|
||||
|
||||
/* BCSRx - Board Control and Status Registers */
|
||||
#define CFG_OR1_REMAP CFG_OR0_REMAP
|
||||
#define CFG_OR1_PRELIM 0xffff8110 /* 64Kbyte address space */
|
||||
#define CFG_BR1_PRELIM ((BCSR_ADDR) | BR_V )
|
||||
|
||||
|
|
@ -327,7 +312,7 @@
|
|||
#define PCMCIA_MEM_ADDR ((uint)0xff020000)
|
||||
#define PCMCIA_MEM_SIZE ((uint)(64 * 1024))
|
||||
|
||||
#define BCSR0 ((uint) (BCSR_ADDR + 00))
|
||||
#define BCSR0 ((uint) (BCSR_ADDR + 0x00))
|
||||
#define BCSR1 ((uint) (BCSR_ADDR + 0x04))
|
||||
#define BCSR2 ((uint) (BCSR_ADDR + 0x08))
|
||||
#define BCSR3 ((uint) (BCSR_ADDR + 0x0c))
|
||||
|
|
@ -389,10 +374,6 @@
|
|||
#define CONFIG_DRAM_50MHZ 1
|
||||
#define CONFIG_SDRAM_50MHZ 1
|
||||
|
||||
/* Interrupt level assignments.
|
||||
*/
|
||||
#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */
|
||||
|
||||
/* We don't use the 8259.
|
||||
*/
|
||||
#define NR_8259_INTS 0
|
||||
|
|
@ -406,12 +387,10 @@
|
|||
|
||||
/* PCMCIA configuration */
|
||||
|
||||
#define PCMCIA_MAX_SLOTS 2
|
||||
|
||||
#ifdef CONFIG_MPC860
|
||||
#define PCMCIA_SLOT_A 1
|
||||
#endif
|
||||
/*#define CFG_PCMCIA_MEM_SIZE ( 64 << 20) */
|
||||
|
||||
#define CFG_PCMCIA_MEM_ADDR (0x50000000)
|
||||
#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
|
||||
#define CFG_PCMCIA_DMA_ADDR (0x54000000)
|
||||
|
|
|
|||
Loading…
Reference in New Issue