Blackfin: bfin_mac: cleanup MII/PHY functions
Cleanup and rewrite the MII/PHY related functions so that we can reuse the existing common linux/miiphy.h code and hook into the `mii` command. Signed-off-by: Mike Frysinger <vapier@gentoo.org> Acked-by: Ben Warren <biggerbadderben@gmail.com>
This commit is contained in:
Mike Frysinger
parent
6b310a05f0
commit
ac45af4e63
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@ -12,6 +12,8 @@
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#include <netdev.h>
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#include <command.h>
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#include <malloc.h>
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#include <miiphy.h>
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#include <linux/mii.h>
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#include <asm/blackfin.h>
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#include <asm/mach-common/bits/dma.h>
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@ -43,8 +45,6 @@ ADI_ETHER_BUFFER *rxbuf[PKTBUFSRX];
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static u16 txIdx; /* index of the current RX buffer */
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static u16 rxIdx; /* index of the current TX buffer */
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u16 PHYregs[NO_PHY_REGS]; /* u16 PHYADDR; */
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/* DMAx_CONFIG values at DMA Restart */
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const ADI_DMA_CONFIG_REG rxdmacfg = {
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.b_DMA_EN = 1, /* enabled */
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@ -70,10 +70,38 @@ const ADI_DMA_CONFIG_REG txdmacfg = {
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.b_FLOW = 7 /* large desc flow */
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};
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static int bfin_miiphy_wait(void)
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{
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/* poll the STABUSY bit */
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while (bfin_read_EMAC_STAADD() & STABUSY)
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continue;
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return 0;
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}
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static int bfin_miiphy_read(char *devname, uchar addr, uchar reg, ushort *val)
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{
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if (bfin_miiphy_wait())
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return 1;
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bfin_write_EMAC_STAADD(SET_PHYAD(addr) | SET_REGAD(reg) | STABUSY);
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if (bfin_miiphy_wait())
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return 1;
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*val = bfin_read_EMAC_STADAT();
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return 0;
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}
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static int bfin_miiphy_write(char *devname, uchar addr, uchar reg, ushort val)
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{
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if (bfin_miiphy_wait())
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return 1;
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bfin_write_EMAC_STADAT(val);
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bfin_write_EMAC_STAADD(SET_PHYAD(addr) | SET_REGAD(reg) | STAOP | STABUSY);
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return 0;
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}
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int bfin_EMAC_initialize(bd_t *bis)
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{
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struct eth_device *dev;
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dev = (struct eth_device *)malloc(sizeof(*dev));
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dev = malloc(sizeof(*dev));
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if (dev == NULL)
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hang();
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@ -89,6 +117,10 @@ int bfin_EMAC_initialize(bd_t *bis)
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eth_register(dev);
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#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
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miiphy_register(dev->name, bfin_miiphy_read, bfin_miiphy_write);
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#endif
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return 0;
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}
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@ -182,6 +214,100 @@ static int bfin_EMAC_recv(struct eth_device *dev)
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*
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*************************************************************/
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/* MDC = SCLK / MDC_freq / 2 - 1 */
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#define MDC_FREQ_TO_DIV(mdc_freq) (get_sclk() / (mdc_freq) / 2 - 1)
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static int bfin_miiphy_init(struct eth_device *dev, int *opmode)
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{
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u16 phydat;
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size_t count;
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/* Enable PHY output */
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*pVR_CTL |= CLKBUFOE;
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/* Set all the pins to peripheral mode */
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#ifdef CONFIG_BFIN_MAC_RMII
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/* grab RMII pins */
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# if defined(__ADSPBF51x__)
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*pPORTF_MUX = (*pPORTF_MUX & \
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~(PORT_x_MUX_3_MASK | PORT_x_MUX_4_MASK | PORT_x_MUX_5_MASK)) | \
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PORT_x_MUX_3_FUNC_1 | PORT_x_MUX_4_FUNC_1 | PORT_x_MUX_5_FUNC_1;
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*pPORTF_FER |= PF8 | PF9 | PF10 | PF11 | PF12 | PF13 | PF14 | PF15;
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*pPORTG_MUX = (*pPORTG_MUX & ~PORT_x_MUX_0_MASK) | PORT_x_MUX_0_FUNC_1;
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*pPORTG_FER |= PG0 | PG1 | PG2;
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# elif defined(__ADSPBF52x__)
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*pPORTG_MUX = (*pPORTG_MUX & ~PORT_x_MUX_6_MASK) | PORT_x_MUX_6_FUNC_2;
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*pPORTG_FER |= PG14 | PG15;
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*pPORTH_MUX = (*pPORTH_MUX & ~(PORT_x_MUX_0_MASK | PORT_x_MUX_1_MASK)) | \
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PORT_x_MUX_0_FUNC_2 | PORT_x_MUX_1_FUNC_2;
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*pPORTH_FER |= PH0 | PH1 | PH2 | PH3 | PH4 | PH5 | PH6 | PH7 | PH8;
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# else
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*pPORTH_FER |= PH0 | PH1 | PH4 | PH5 | PH6 | PH8 | PH9 | PH14 | PH15;
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# endif
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#else
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/* grab MII & RMII pins */
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# if defined(__ADSPBF51x__)
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*pPORTF_MUX = (*pPORTF_MUX & \
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~(PORT_x_MUX_0_MASK | PORT_x_MUX_1_MASK | PORT_x_MUX_3_MASK | PORT_x_MUX_4_MASK | PORT_x_MUX_5_MASK)) | \
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PORT_x_MUX_0_FUNC_1 | PORT_x_MUX_1_FUNC_1 | PORT_x_MUX_3_FUNC_1 | PORT_x_MUX_4_FUNC_1 | PORT_x_MUX_5_FUNC_1;
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*pPORTF_FER |= PF0 | PF1 | PF2 | PF3 | PF4 | PF5 | PF6 | PF8 | PF9 | PF10 | PF11 | PF12 | PF13 | PF14 | PF15;
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*pPORTG_MUX = (*pPORTG_MUX & ~PORT_x_MUX_0_MASK) | PORT_x_MUX_0_FUNC_1;
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*pPORTG_FER |= PG0 | PG1 | PG2;
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# elif defined(__ADSPBF52x__)
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*pPORTG_MUX = (*pPORTG_MUX & ~PORT_x_MUX_6_MASK) | PORT_x_MUX_6_FUNC_2;
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*pPORTG_FER |= PG14 | PG15;
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*pPORTH_MUX = PORT_x_MUX_0_FUNC_2 | PORT_x_MUX_1_FUNC_2 | PORT_x_MUX_2_FUNC_2;
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*pPORTH_FER = -1; /* all pins */
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# else
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*pPORTH_FER = -1; /* all pins */
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# endif
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#endif
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/* Odd word alignment for Receive Frame DMA word */
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/* Configure checksum support and rcve frame word alignment */
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bfin_write_EMAC_SYSCTL(RXDWA | RXCKS | SET_MDCDIV(MDC_FREQ_TO_DIV(2500000)));
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/* turn on auto-negotiation and wait for link to come up */
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bfin_miiphy_write(dev->name, PHYADDR, MII_BMCR, BMCR_ANENABLE);
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count = 0;
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while (1) {
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++count;
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if (bfin_miiphy_read(dev->name, PHYADDR, MII_BMSR, &phydat))
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return -1;
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if (phydat & BMSR_LSTATUS)
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break;
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if (count > 30000) {
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printf("%s: link down, check cable\n", dev->name);
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return -1;
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}
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udelay(100);
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}
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/* see what kind of link we have */
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if (bfin_miiphy_read(dev->name, PHYADDR, MII_LPA, &phydat))
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return -1;
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if (phydat & LPA_DUPLEX)
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*opmode = FDMODE;
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else
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*opmode = 0;
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bfin_write_EMAC_MMC_CTL(RSTC | CROLL);
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/* Initialize the TX DMA channel registers */
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*pDMA2_X_COUNT = 0;
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*pDMA2_X_MODIFY = 4;
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*pDMA2_Y_COUNT = 0;
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*pDMA2_Y_MODIFY = 0;
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/* Initialize the RX DMA channel registers */
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*pDMA1_X_COUNT = 0;
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*pDMA1_X_MODIFY = 4;
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*pDMA1_Y_COUNT = 0;
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*pDMA1_Y_MODIFY = 0;
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return 0;
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}
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static int bfin_EMAC_init(struct eth_device *dev, bd_t *bd)
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{
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u32 opmode;
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@ -192,14 +318,14 @@ static int bfin_EMAC_init(struct eth_device *dev, bd_t *bd)
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txIdx = 0;
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rxIdx = 0;
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/* Initialize System Register */
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if (SetupSystemRegs(&dat) < 0)
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/* Initialize System Register */
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if (bfin_miiphy_init(dev, &dat) < 0)
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return -1;
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/* Initialize EMAC address */
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/* Initialize EMAC address */
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bfin_EMAC_setup_addr(bd);
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/* Initialize TX and RX buffer */
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/* Initialize TX and RX buffer */
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for (i = 0; i < PKTBUFSRX; i++) {
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rxbuf[i] = SetupRxBuffer(i);
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if (i > 0) {
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@ -226,7 +352,7 @@ static int bfin_EMAC_init(struct eth_device *dev, bd_t *bd)
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*pDMA1_CONFIG = *((u16 *) (void *)&rxbuf[0]->Dma[0].CONFIG);
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/* Wait MII done */
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PollMdcDone();
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bfin_miiphy_wait();
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/* We enable only RX here */
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/* ASTP : Enable Automatic Pad Stripping
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@ -271,148 +397,6 @@ void bfin_EMAC_setup_addr(bd_t *bd)
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bd->bi_enetaddr[5] << 8;
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}
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static void PollMdcDone(void)
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{
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/* poll the STABUSY bit */
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while (*pEMAC_STAADD & STABUSY) ;
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}
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static void WrPHYReg(u16 PHYAddr, u16 RegAddr, u16 Data)
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{
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PollMdcDone();
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*pEMAC_STADAT = Data;
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*pEMAC_STAADD = SET_PHYAD(PHYAddr) | SET_REGAD(RegAddr) |
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STAOP | STAIE | STABUSY;
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}
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/*********************************************************************************
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* Read an off-chip register in a PHY through the MDC/MDIO port *
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*********************************************************************************/
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static u16 RdPHYReg(u16 PHYAddr, u16 RegAddr)
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{
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u16 Data;
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PollMdcDone();
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*pEMAC_STAADD = SET_PHYAD(PHYAddr) | SET_REGAD(RegAddr) |
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STAIE | STABUSY;
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PollMdcDone();
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Data = (u16) * pEMAC_STADAT;
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PHYregs[RegAddr] = Data; /* save shadow copy */
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return Data;
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}
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#if 0 /* dead code ? */
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static void SoftResetPHY(void)
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{
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u16 phydat;
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/* set the reset bit */
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WrPHYReg(PHYADDR, PHY_MODECTL, PHY_RESET);
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/* and clear it again */
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WrPHYReg(PHYADDR, PHY_MODECTL, 0x0000);
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do {
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/* poll until reset is complete */
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phydat = RdPHYReg(PHYADDR, PHY_MODECTL);
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} while ((phydat & PHY_RESET) != 0);
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}
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#endif
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/* MDC = SCLK / MDC_freq / 2 - 1 */
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#define MDC_FREQ_TO_DIV(mdc_freq) (get_sclk() / (mdc_freq) / 2 - 1)
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static int SetupSystemRegs(int *opmode)
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{
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u16 phydat;
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int count = 0;
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/* Enable PHY output */
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*pVR_CTL |= CLKBUFOE;
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/* Set all the pins to peripheral mode */
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#ifdef CONFIG_BFIN_MAC_RMII
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/* grab RMII pins */
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# if defined(__ADSPBF51x__)
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*pPORTF_MUX = (*pPORTF_MUX & \
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~(PORT_x_MUX_3_MASK | PORT_x_MUX_4_MASK | PORT_x_MUX_5_MASK)) | \
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PORT_x_MUX_3_FUNC_1 | PORT_x_MUX_4_FUNC_1 | PORT_x_MUX_5_FUNC_1;
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*pPORTF_FER |= PF8 | PF9 | PF10 | PF11 | PF12 | PF13 | PF14 | PF15;
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*pPORTG_MUX = (*pPORTG_MUX & ~PORT_x_MUX_0_MASK) | PORT_x_MUX_0_FUNC_1;
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*pPORTG_FER |= PG0 | PG1 | PG2;
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# elif defined(__ADSPBF52x__)
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*pPORTG_MUX = (*pPORTG_MUX & ~PORT_x_MUX_6_MASK) | PORT_x_MUX_6_FUNC_2;
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*pPORTG_FER |= PG14 | PG15;
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*pPORTH_MUX = (*pPORTH_MUX & ~(PORT_x_MUX_0_MASK | PORT_x_MUX_1_MASK)) | \
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PORT_x_MUX_0_FUNC_2 | PORT_x_MUX_1_FUNC_2;
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*pPORTH_FER |= PH0 | PH1 | PH2 | PH3 | PH4 | PH5 | PH6 | PH7 | PH8;
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# else
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*pPORTH_FER |= PH0 | PH1 | PH4 | PH5 | PH6 | PH8 | PH9 | PH14 | PH15;
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# endif
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#else
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/* grab MII & RMII pins */
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# if defined(__ADSPBF51x__)
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*pPORTF_MUX = (*pPORTF_MUX & \
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~(PORT_x_MUX_0_MASK | PORT_x_MUX_1_MASK | PORT_x_MUX_3_MASK | PORT_x_MUX_4_MASK | PORT_x_MUX_5_MASK)) | \
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PORT_x_MUX_0_FUNC_1 | PORT_x_MUX_1_FUNC_1 | PORT_x_MUX_3_FUNC_1 | PORT_x_MUX_4_FUNC_1 | PORT_x_MUX_5_FUNC_1;
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*pPORTF_FER |= PF0 | PF1 | PF2 | PF3 | PF4 | PF5 | PF6 | PF8 | PF9 | PF10 | PF11 | PF12 | PF13 | PF14 | PF15;
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*pPORTG_MUX = (*pPORTG_MUX & ~PORT_x_MUX_0_MASK) | PORT_x_MUX_0_FUNC_1;
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*pPORTG_FER |= PG0 | PG1 | PG2;
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# elif defined(__ADSPBF52x__)
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*pPORTG_MUX = (*pPORTG_MUX & ~PORT_x_MUX_6_MASK) | PORT_x_MUX_6_FUNC_2;
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*pPORTG_FER |= PG14 | PG15;
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*pPORTH_MUX = PORT_x_MUX_0_FUNC_2 | PORT_x_MUX_1_FUNC_2 | PORT_x_MUX_2_FUNC_2;
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*pPORTH_FER = -1; /* all pins */
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# else
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*pPORTH_FER = -1; /* all pins */
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# endif
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#endif
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/* Odd word alignment for Receive Frame DMA word */
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/* Configure checksum support and rcve frame word alignment */
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*pEMAC_SYSCTL = RXDWA | RXCKS | SET_MDCDIV(MDC_FREQ_TO_DIV(2500000));
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/* auto negotiation on */
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/* full duplex */
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/* 100 Mbps */
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phydat = PHY_ANEG_EN | PHY_DUPLEX | PHY_SPD_SET;
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WrPHYReg(PHYADDR, PHY_MODECTL, phydat);
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do {
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udelay(1000);
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phydat = RdPHYReg(PHYADDR, PHY_MODESTAT);
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if (count > 3000) {
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printf
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("Link is down, please check your network connection\n");
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return -1;
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}
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count++;
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} while (!(phydat & 0x0004));
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phydat = RdPHYReg(PHYADDR, PHY_ANLPAR);
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if ((phydat & 0x0100) || (phydat & 0x0040))
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*opmode = FDMODE;
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else
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*opmode = 0;
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*pEMAC_MMC_CTL = RSTC | CROLL;
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/* Initialize the TX DMA channel registers */
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*pDMA2_X_COUNT = 0;
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*pDMA2_X_MODIFY = 4;
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*pDMA2_Y_COUNT = 0;
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*pDMA2_Y_MODIFY = 0;
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/* Initialize the RX DMA channel registers */
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*pDMA1_X_COUNT = 0;
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*pDMA1_X_MODIFY = 4;
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*pDMA1_Y_COUNT = 0;
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*pDMA1_Y_MODIFY = 0;
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return 0;
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}
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ADI_ETHER_BUFFER *SetupRxBuffer(int no)
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{
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ADI_ETHER_FRAME_BUFFER *frmbuf;
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@ -10,28 +10,8 @@
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#define __BFIN_MAC_H__
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#define PHYADDR 0x01
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#define NO_PHY_REGS 0x20
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#define DEFAULT_PHY_PHYID1 0x0007
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#define DEFAULT_PHY_PHYID2 0xC0A3
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#define PHY_MODECTL 0x00
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#define PHY_MODESTAT 0x01
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#define PHY_PHYID1 0x02
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#define PHY_PHYID2 0x03
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#define PHY_ANAR 0x04
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#define PHY_ANLPAR 0x05
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#define PHY_ANER 0x06
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#define PHY_RESET 0x8000
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#define PHY_ANEG_EN 0x1000
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#define PHY_DUPLEX 0x0100
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#define PHY_SPD_SET 0x2000
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#define RECV_BUFSIZE (0x614)
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typedef volatile u32 reg32;
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typedef volatile u16 reg16;
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typedef struct ADI_DMA_CONFIG_REG {
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u16 b_DMA_EN:1; /* 0 Enabled */
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u16 b_WNR:1; /* 1 Direction */
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@ -79,11 +59,6 @@ static void bfin_EMAC_halt(struct eth_device *dev);
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static int bfin_EMAC_send(struct eth_device *dev, volatile void *packet, int length);
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static int bfin_EMAC_recv(struct eth_device *dev);
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static void PollMdcDone(void);
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static void WrPHYReg(u16 PHYAddr, u16 RegAddr, u16 Data);
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static u16 RdPHYReg(u16 PHYAddr, u16 RegAddr);
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static int SetupSystemRegs(int *opmode);
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static void bfin_EMAC_setup_addr(bd_t *bd);
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#endif
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