Memory configuration changes for ZPC.1900 board
- Fix SDRAM timing on both local bus and 60x bus - Add support for second flash bank (SIMM) - Change boot flash base Patch by Yuli Barcohen, 05 Jun 2005
This commit is contained in:
Wolfgang Denk
parent
5797b821dc
commit
aba9f1af60
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@ -2,6 +2,12 @@
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Changes since U-Boot 1.1.4:
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======================================================================
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* Memory configuration changes for ZPC.1900 board
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- Fix SDRAM timing on both local bus and 60x bus
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- Add support for second flash bank (SIMM)
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- Change boot flash base
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Patch by Yuli Barcohen, 05 Jun 2005
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* Add support for Adder boards with 16MB SDRAM;
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add support for second FEC on Adder87x board.
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Patch by Yuli Barcohen, 05 Jun 2005
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@ -27,4 +27,4 @@
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# ZPC.1900 board
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#
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TEXT_BASE = 0xFFE00000
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TEXT_BASE = 0xFE000000
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@ -2,7 +2,7 @@
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* (C) Copyright 2001-2003
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2003 Arabella Software Ltd.
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* (C) Copyright 2003-2005 Arabella Software Ltd.
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* Yuli Barcohen <yuli@arabellasw.com>
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*
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* See file CREDITS for list of people who contributed to this
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@ -27,9 +27,6 @@
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#include <common.h>
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#include <ioports.h>
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#include <mpc8260.h>
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#include <asm/m8260_pci.h>
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#include <i2c.h>
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#include <spd.h>
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#include <miiphy.h>
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/*
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@ -167,8 +164,8 @@ const iop_conf_t iop_conf_tab[4][32] = {
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/* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */
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/* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
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/* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
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/* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
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/* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
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/* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
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/* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SCL */
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/* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
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/* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
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/* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
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@ -231,11 +228,10 @@ long int initdram(int board_type)
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vu_char *ramaddr;
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uchar c = 0xFF;
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long int msize = CFG_SDRAM_SIZE;
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uint psdmr = CFG_PSDMR;
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int i;
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if (bcsr[4] & BCSR_PCI_MODE) { /* PCI mode selected by JP9 */
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immap->im_clkrst.car_sccr |= M826X_SCCR_PCI_MODE_EN;
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immap->im_clkrst.car_sccr |= SCCR_PCI_MODE;
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immap->im_siu_conf.sc_siumcr =
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(immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11)
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| SIUMCR_LBPC01;
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@ -255,10 +251,10 @@ long int initdram(int board_type)
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*/
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if ((immap->im_siu_conf.sc_siumcr & SIUMCR_LBPC11) == SIUMCR_LBPC00) {
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memctl->memc_lsrt = CFG_LSRT;
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memctl->memc_or4 = 0xFFC01480;
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memctl->memc_br4 = CFG_LSDRAM_BASE | 0x00001861;
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memctl->memc_lsdmr = CFG_LSDMR | PSDMR_OP_PREA;
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memctl->memc_or4 = CFG_LSDRAM_OR;
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memctl->memc_br4 = CFG_LSDRAM_BR;
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ramaddr = (vu_char *)CFG_LSDRAM_BASE;
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memctl->memc_lsdmr = CFG_LSDMR | PSDMR_OP_PREA;
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*ramaddr = c;
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memctl->memc_lsdmr = CFG_LSDMR | PSDMR_OP_CBRR;
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for (i = 0; i < 8; i++)
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@ -271,8 +267,8 @@ long int initdram(int board_type)
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/* Initialise 60x bus SDRAM */
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memctl->memc_psrt = CFG_PSRT;
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memctl->memc_or2 = 0xFC0028C0;
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memctl->memc_br2 = CFG_SDRAM_BASE | 0x00000041;
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memctl->memc_or2 = CFG_PSDRAM_OR;
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memctl->memc_br2 = CFG_PSDRAM_BR;
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/*
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* The mode data for Mode Register Write command must appear on
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* the address lines during a mode-set cycle. It is driven by
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@ -283,15 +279,15 @@ long int initdram(int board_type)
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* length must be 4.
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*/
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ramaddr = (vu_char *)(CFG_SDRAM_BASE |
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((psdmr & PSDMR_CL_MSK) << 7) | 0x10);
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memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; /* Precharge all banks */
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((CFG_PSDMR & PSDMR_CL_MSK) << 7) | 0x10);
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memctl->memc_psdmr = CFG_PSDMR | PSDMR_OP_PREA; /* Precharge all banks */
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*ramaddr = c;
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memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; /* CBR refresh */
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memctl->memc_psdmr = CFG_PSDMR | PSDMR_OP_CBRR; /* CBR refresh */
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for (i = 0; i < 8; i++)
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*ramaddr = c;
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memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; /* Mode Register write */
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memctl->memc_psdmr = CFG_PSDMR | PSDMR_OP_MRW; /* Mode Register write */
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*ramaddr = c;
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memctl->memc_psdmr = psdmr | PSDMR_RFEN; /* Refresh enable */
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memctl->memc_psdmr = CFG_PSDMR | PSDMR_RFEN; /* Refresh enable */
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*ramaddr = c;
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#endif /* CFG_RAMBOOT */
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@ -1,5 +1,5 @@
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/*
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* Copyright (C) 2003-2004 Arabella Software Ltd.
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* Copyright (C) 2003-2005 Arabella Software Ltd.
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* Yuli Barcohen <yuli@arabellasw.com>
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*
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* U-Boot configuration for Zephyr Engineering ZPC.1900 board.
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@ -32,11 +32,7 @@
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#define CPU_ID_STR "MPC8265"
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#define CONFIG_CPM2 1 /* Has a CPM2 */
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#undef DEBUG
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#undef CONFIG_BOARD_EARLY_INIT_F /* Don't call board_early_init_f */
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/* Allow serial number (serial) and MAC address (ethaddr) to be overwritten */
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/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
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#define CONFIG_ENV_OVERWRITE
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/*
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@ -113,7 +109,6 @@
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#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
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| CFG_CMD_ASKENV \
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| CFG_CMD_DHCP \
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| CFG_CMD_ECHO \
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| CFG_CMD_IMMAP \
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| CFG_CMD_MII \
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| CFG_CMD_PING \
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@ -154,31 +149,30 @@
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
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#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
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#define CFG_MEMTEST_END 0x03800000 /* 1 ... 56 MB in DRAM */
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#define CFG_LOAD_ADDR 0x100000 /* default load address */
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#define CFG_LOAD_ADDR 0x400000 /* default load address */
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#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
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#define CFG_FLASH_BASE 0xFFE00000
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#define CFG_FLASH_CFI
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#define CFG_FLASH_CFI_DRIVER
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#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */
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#define CFG_MAX_FLASH_SECT 32 /* max num of sects on one chip */
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#define CFG_DEFAULT_IMMR 0x0F010000
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#define CFG_IMMR 0xF0000000
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#define CFG_SDRAM_BASE 0x00000000
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#define CFG_SDRAM_SIZE 64
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#define CFG_FLSIMM_BASE 0xFC000000
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#define CFG_LSDRAM_BASE 0xFE000000
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#define CFG_IMMR 0xF0000000
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#define CFG_LSDRAM_BASE 0xFC000000
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#define CFG_FLASH_BASE 0xFE000000
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#define CFG_BCSR 0xFEA00000
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#define CFG_EEPROM 0xFEB00000
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#define CFG_FLSIMM_BASE 0xFF000000
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#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
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#define CFG_FLASH_CFI
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#define CFG_FLASH_CFI_DRIVER
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#define CFG_MAX_FLASH_BANKS 2 /* max num of flash banks */
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#define CFG_MAX_FLASH_SECT 32 /* max num of sects on one chip */
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#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLSIMM_BASE }
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#define BCSR_PCI_MODE 0x01
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@ -190,10 +184,10 @@
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/* Hard reset configuration word */
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#define CFG_HRCW_MASTER (HRCW_EBM | HRCW_BPS01| HRCW_CIP |\
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HRCW_L2CPC10 | HRCW_DPPC00 | HRCW_ISB010 |\
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HRCW_BMS | HRCW_LBPC01 | HRCW_APPC10 |\
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HRCW_MODCK_H0101 \
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) /* 0x16828605 */
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HRCW_L2CPC10 | HRCW_DPPC00 | HRCW_ISB100 |\
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HRCW_BMS | HRCW_LBPC00 | HRCW_APPC10 |\
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HRCW_MODCK_H0111 \
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) /* 0x16848207 */
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/* No slaves */
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#define CFG_HRCW_SLAVE1 0
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#define CFG_HRCW_SLAVE2 0
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@ -211,7 +205,7 @@
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#define CFG_RAMBOOT
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#endif
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#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
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#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
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#define CFG_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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@ -233,14 +227,14 @@
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# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
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#endif
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#define CFG_HID0_INIT 0
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#define CFG_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE )
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#define CFG_HID0_INIT (HID0_ICFI)
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#define CFG_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE)
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#define CFG_HID2 0
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#define CFG_SIUMCR 0x42200000
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#define CFG_SYPCR 0xFFFFFFC3
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#define CFG_BCR 0x90400000
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#define CFG_BCR 0x90000000
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#define CFG_SCCR SCCR_DFBRG01
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#define CFG_RMR RMR_CSRE
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@ -248,18 +242,23 @@
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#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
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#define CFG_RCCR 0
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#define CFG_PSDMR 0x014EB45A
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#define CFG_PSRT 0x0C
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#define CFG_LSDMR 0x008AB552
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#define CFG_LSRT 0x0E
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#define CFG_PSDMR /* 0x834DA43B */0x014DA43A
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#define CFG_PSRT 0x0F/* 0x0C */
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#define CFG_LSDMR 0x0085A562
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#define CFG_LSRT 0x0F
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#define CFG_MPTPR 0x4000
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#define CFG_PSDRAM_BR CFG_SDRAM_BASE | 0x00000041
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#define CFG_PSDRAM_OR 0xFC0028C0
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#define CFG_LSDRAM_BR CFG_LSDRAM_BASE | 0x00001861
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#define CFG_LSDRAM_OR 0xFF803480
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#define CFG_BR0_PRELIM CFG_FLASH_BASE | 0x00000801
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#define CFG_OR0_PRELIM 0xFFE00856
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#define CFG_BR5_PRELIM CFG_EEPROM | 0x00000801
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#define CFG_OR5_PRELIM 0xFFFF03F6
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#define CFG_BR6_PRELIM CFG_FLSIMM_BASE | 0x00000801
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#define CFG_OR6_PRELIM 0xFE000856
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#define CFG_BR6_PRELIM CFG_FLSIMM_BASE | 0x00001801
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#define CFG_OR6_PRELIM 0xFF000856
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#define CFG_BR7_PRELIM CFG_BCSR | 0x00000801
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#define CFG_OR7_PRELIM 0xFFFF83F6
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