ColdFire: Add M5373EVB platform support - 2
Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com> Signed-off by: John Rigby <jrigby@freescale.com>
This commit is contained in:
TsiChungLiew
parent
1ac559d4aa
commit
aa5f1f9dc8
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@ -649,6 +649,7 @@ TsiChung Liew <Tsi-Chung.Liew@freescale.com>
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M5235EVB mcf52x2
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M5329EVB mcf532x
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M5373EVB mcf532x
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M54455EVB mcf5445x
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Hayden Fraser <Hayden.Fraser@freescale.com>
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3
MAKEALL
3
MAKEALL
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@ -649,7 +649,8 @@ LIST_coldfire=" \
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M5271EVB \
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M5272C3 \
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M5282EVB \
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M5329EVB \
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M5329AFEE \
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M5373EVB \
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M54455EVB \
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r5200 \
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TASREG \
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10
Makefile
10
Makefile
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@ -1811,6 +1811,16 @@ M5329BFEE_config : unconfig
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fi
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@$(MKCONFIG) -a M5329EVB m68k mcf532x m5329evb freescale
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M5373EVB_config : unconfig
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@case "$@" in \
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M5373EVB_config) NAND=16;; \
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esac; \
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>include/config.h ; \
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if [ "$${NAND}" != "0" ] ; then \
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echo "#define NANDFLASH_SIZE $${NAND}" > $(obj)include/config.h ; \
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fi
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@$(MKCONFIG) -a M5373EVB m68k mcf532x m5373evb freescale
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M54455EVB_config \
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M54455EVB_atmel_config \
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M54455EVB_intel_config \
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@ -64,6 +64,18 @@ int checkcpu(void)
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case 0x61:
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id = 5327;
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break;
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case 0x65:
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id = 5373;
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break;
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case 0x68:
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id = 53721;
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break;
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case 0x69:
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id = 5372;
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break;
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case 0x6B:
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id = 5372;
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break;
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}
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if (id) {
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@ -84,6 +96,7 @@ void watchdog_reset(void)
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volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
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wdp->sr = 0x5555; /* Count register */
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wdp->sr = 0xAAAA; /* Count register */
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}
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int watchdog_disable(void)
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@ -104,8 +117,11 @@ int watchdog_init(void)
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/* set timeout and enable watchdog */
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wdog_module = ((CFG_CLK / 1000) * CONFIG_WATCHDOG_TIMEOUT);
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wdog_module |= (wdog_module / 8192);
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wdp->mr = wdog_module;
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#ifdef CONFIG_M5329
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wdp->mr = (wdog_module / 8192);
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#else
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wdp->mr = (wdog_module / 4096);
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#endif
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wdp->cr = WTM_WCR_EN;
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puts("WATCHDOG:enabled\n");
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@ -0,0 +1,333 @@
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Freescale MCF5373EVB ColdFire Development Board
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================================================
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TsiChung Liew(Tsi-Chung.Liew@freescale.com)
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Created 11/08/07
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===========================================
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Changed files:
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==============
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- board/freescale/m5373evb/m5373evb.c Dram setup
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- board/freescale/m5373evb/mii.c Mii access
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- board/freescale/m5373evb/Makefile Makefile
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- board/freescale/m5373evb/config.mk config make
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- board/freescale/m5373evb/u-boot.lds Linker description
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- cpu/mcf532x/cpu.c cpu specific code
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- cpu/mcf532x/cpu_init.c FBCS, Mux pins, icache and RTC extra regs
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- cpu/mcf532x/interrupts.c cpu specific interrupt support
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- cpu/mcf532x/speed.c system, pci, flexbus, and cpu clock
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- cpu/mcf532x/Makefile Makefile
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- cpu/mcf532x/config.mk config make
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- cpu/mcf532x/start.S start up assembly code
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- doc/README.m5373evb This readme file
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- drivers/net/mcffec.c ColdFire common FEC driver
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- drivers/serial/mcfuart.c ColdFire common UART driver
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- drivers/rtc/mcfrtc.c Realtime clock Driver
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- include/asm-m68k/bitops.h Bit operation function export
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- include/asm-m68k/byteorder.h Byte order functions
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- include/asm-m68k/fec.h FEC structure and definition
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- include/asm-m68k/fsl_i2c.h I2C structure and definition
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- include/asm-m68k/global_data.h Global data structure
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- include/asm-m68k/immap.h ColdFire specific header file and driver macros
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- include/asm-m68k/immap_532x.h mcf532x specific header file
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- include/asm-m68k/io.h io functions
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- include/asm-m68k/m532x.h mcf532x specific header file
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- include/asm-m68k/posix_types.h Posix
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- include/asm-m68k/processor.h header file
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- include/asm-m68k/ptrace.h Exception structure
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- include/asm-m68k/rtc.h Realtime clock header file
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- include/asm-m68k/string.h String function export
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- include/asm-m68k/timer.h Timer structure and definition
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- include/asm-m68k/types.h Data types definition
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- include/asm-m68k/uart.h Uart structure and definition
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- include/asm-m68k/u-boot.h u-boot structure
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- include/configs/M5373EVB.h Board specific configuration file
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- lib_m68k/board.c board init function
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- lib_m68k/cache.c
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- lib_m68k/interrupts Coldfire common interrupt functions
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- lib_m68k/m68k_linux.c
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- lib_m68k/time.c Timer functions (Dma timer and PIT)
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- lib_m68k/traps.c Exception init code
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1 MCF5373 specific Options/Settings
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====================================
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1.1 pre-loader is no longer suppoer in thie coldfire family
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1.2 Configuration settings for M5373EVB Development Board
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CONFIG_MCF532x -- define for all MCF532x CPUs
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CONFIG_M5373 -- define for all Freescale MCF5373 CPUs
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CONFIG_M5373EVB -- define for M5373EVB board
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CONFIG_MCFUART -- define to use common CF Uart driver
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CFG_UART_PORT -- define UART port number, start with 0, 1 and 2
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CONFIG_BAUDRATE -- define UART baudrate
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CONFIG_MCFRTC -- define to use common CF RTC driver
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CFG_MCFRTC_BASE -- provide base address for RTC in immap.h
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CFG_RTC_OSCILLATOR -- define RTC clock frequency
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RTC_DEBUG -- define to show RTC debug message
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CONFIG_CMD_DATE -- enable to use date feature in u-boot
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CONFIG_MCFFEC -- define to use common CF FEC driver
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CONFIG_NET_MULTI -- define to use multi FEC in u-boot
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CONFIG_MII -- enable to use MII driver
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CONFIG_CF_DOMII -- enable to use MII feature in cmd_mii.c
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CFG_DISCOVER_PHY -- enable PHY discovery
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CFG_RX_ETH_BUFFER -- Set FEC Receive buffer
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CFG_FAULT_ECHO_LINK_DOWN--
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CFG_FEC0_PINMUX -- Set FEC0 Pin configuration
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CFG_FEC0_MIIBASE -- Set FEC0 MII base register
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MCFFEC_TOUT_LOOP -- set FEC timeout loop
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CONFIG_MCFTMR -- define to use DMA timer
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CONFIG_MCFPIT -- define to use PIT timer
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CONFIG_FSL_I2C -- define to use FSL common I2C driver
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CONFIG_HARD_I2C -- define for I2C hardware support
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CONFIG_SOFT_I2C -- define for I2C bit-banged
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CFG_I2C_SPEED -- define for I2C speed
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CFG_I2C_SLAVE -- define for I2C slave address
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CFG_I2C_OFFSET -- define for I2C base address offset
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CFG_IMMR -- define for MBAR offset
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CFG_MBAR -- define MBAR offset
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CONFIG_MONITOR_IS_IN_RAM -- Not support
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CFG_INIT_RAM_ADDR -- defines the base address of the MCF5373 internal SRAM
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CFG_CSn_BASE -- defines the Chip Select Base register
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CFG_CSn_MASK -- defines the Chip Select Mask register
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CFG_CSn_CTRL -- defines the Chip Select Control register
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CFG_SDRAM_BASE -- defines the DRAM Base
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2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL
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===========================================
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2.1. System memory map:
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Flash: 0x00000000-0x3FFFFFFF (1024MB)
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DDR: 0x40000000-0x7FFFFFFF (1024MB)
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SRAM: 0x80000000-0x8FFFFFFF (256MB)
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IP: 0xF0000000-0xFFFFFFFF (256MB)
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2.2. For the initial bringup, we adopted a consistent memory scheme between u-boot and
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linux kernel, you can customize it based on your system requirements:
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Flash0: 0x00000000-0x00FFFFFF (16MB)
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DDR: 0x40000000-0x4FFFFFFF (256MB)
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SRAM: 0x80000000-0x80007FFF (32KB)
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IP: 0xFC000000-0xFC0FFFFF (64KB)
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3. COMPILATION
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==============
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3.1 To create U-Boot the gcc-4.1-xx compiler set (ColdFire ELF or
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uClinux version) from codesourcery.com was used. Download it from:
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http://www.codesourcery.com/gnu_toolchains/coldfire/download.html
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3.2 Compilation
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export CROSS_COMPILE=cross-compile-prefix
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cd u-boot-1.x.x
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make distclean
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make M5373EVB_config
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make
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4. SCREEN DUMP
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==============
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4.1 M5373EVB Development board
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(NOTE: May not show exactly the same)
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U-Boot 1.3.0 (Nov 8 2007 - 12:44:08)
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CPU: Freescale MCF5373 (Mask:65 Version:1)
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CPU CLK 240 Mhz BUS CLK 80 Mhz
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Board: Freescale FireEngine 5373 EVB
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I2C: ready
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DRAM: 32 MB
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FLASH: 2 MB
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In: serial
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Out: serial
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Err: serial
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NAND: 16 MiB
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Net: FEC0
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-> print
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bootdelay=1
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baudrate=115200
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ethaddr=00:e0:0c:bc:e5:60
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hostname=M5373EVB
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netdev=eth0
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loadaddr=40010000
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load=tftp ${loadaddr) ${u-boot}
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upd=run load; run prog
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prog=prot off 0 2ffff;era 0 2ffff;cp.b ${loadaddr} 0 ${filesize};save
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ethact=FEC0
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u-boot=u-boot.bin
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gatewayip=192.168.1.1
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netmask=255.255.255.0
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ipaddr=192.168.1.3
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serverip=192.168.1.2
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stdin=serial
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stdout=serial
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stderr=serial
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mem=261632k
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Environment size: 401/8188 bytes
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-> bdinfo
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memstart = 0x40000000
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memsize = 0x02000000
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flashstart = 0x00000000
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flashsize = 0x00200000
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flashoffset = 0x00000000
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sramstart = 0x80000000
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sramsize = 0x00008000
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mbar = 0xFC000000
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busfreq = 80 MHz
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ethaddr = 00:E0:0C:BC:E5:60
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ip_addr = 192.168.1.3
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baudrate = 115200 bps
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->
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-> help
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? - alias for 'help'
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autoscr - run script from memory
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base - print or set address offset
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bdinfo - print Board Info structure
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boot - boot default, i.e., run 'bootcmd'
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bootd - boot default, i.e., run 'bootcmd'
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bootelf - Boot from an ELF image in memory
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bootm - boot application image from memory
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bootp - boot image via network using BootP/TFTP protocol
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bootvx - Boot vxWorks from an ELF image
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cmp - memory compare
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coninfo - print console devices and information
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cp - memory copy
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crc32 - checksum calculation
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date - get/set/reset date & time
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dcache - enable or disable data cache
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echo - echo args to console
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erase - erase FLASH memory
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flinfo - print FLASH memory information
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go - start application at address 'addr'
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help - print online help
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icache - enable or disable instruction cache
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icrc32 - checksum calculation
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iloop - infinite loop on address range
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imd - i2c memory display
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iminfo - print header information for application image
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imls - list all images found in flash
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imm - i2c memory modify (auto-incrementing)
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imw - memory write (fill)
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inm - memory modify (constant address)
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iprobe - probe to discover valid I2C chip addresses
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itest - return true/false on integer compare
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loadb - load binary file over serial line (kermit mode)
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loads - load S-Record file over serial line
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loady - load binary file over serial line (ymodem mode)
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loop - infinite loop on address range
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ls - list files in a directory (default /)
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md - memory display
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mii - MII utility commands
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mm - memory modify (auto-incrementing)
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mtest - simple RAM test
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mw - memory write (fill)
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nand - NAND sub-system
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nboot - boot from NAND device
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nfs - boot image via network using NFS protocol
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nm - memory modify (constant address)
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ping - send ICMP ECHO_REQUEST to network host
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printenv- print environment variables
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protect - enable or disable FLASH write protection
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rarpboot- boot image via network using RARP/TFTP protocol
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reset - Perform RESET of the CPU
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run - run commands in an environment variable
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saveenv - save environment variables to persistent storage
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setenv - set environment variables
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sleep - delay execution for some time
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tftpboot- boot image via network using TFTP protocol
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version - print monitor version
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-> tftp 0x40800000 uImage
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Using FEC0 device
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TFTP from server 192.168.1.3; our IP address is 192.168.1.3 Filename 'uImage'.
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Load address: 0x40800000
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Loading: #################################################################
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#################################################################
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##########
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done
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Bytes transferred = 2053270 (1f5496 hex)
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-> bootm 0x40800000
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## Booting image at 40800000 ...
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Image Name: Linux Kernel Image
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Created: 2007-11-07 20:33:08 UTC
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Image Type: M68K Linux Kernel Image (gzip compressed)
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Data Size: 2053206 Bytes = 2 MB
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Load Address: 40020000
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Entry Point: 40020000
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Verifying Checksum ... OK
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Uncompressing Kernel Image ... OK
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Linux version 2.6.22-uc1 (mattw@loa) (gcc version 4.2.1 (Sourcery G++ Lite 4.2-7
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uClinux/COLDFIRE(m537x)
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COLDFIRE port done by Greg Ungerer, gerg@snapgear.com Flat model support (C) 1998,1999 Kenneth Albanowski, D. Jeff Dionne Built 1 zonelists. Total pages: 8128 Kernel command line: rootfstype=romfs PID hash table entries: 128 (order: 7, 512 bytes) Dentry cache hash table entries: 4096 (order: 2, 16384 bytes) Inode-cache hash table entries: 2048 (order: 1, 8192 bytes) Memory available: 28092k/32768k RAM, (1788k kernel code, 244k data) Mount-cache hash table entries: 512
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NET: Registered protocol family 16
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USB-MCF537x: (HOST module) EHCI device is registered
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USB-MCF537x: (OTG module) EHCI device is registered
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USB-MCF537x: (OTG module) UDC device is registered
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usbcore: registered new interface driver usbfs
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usbcore: registered new interface driver hub
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usbcore: registered new device driver usb
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NET: Registered protocol family 2
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IP route cache hash table entries: 1024 (order: 0, 4096 bytes) TCP established hash table entries: 1024 (order: 1, 8192 bytes) TCP bind hash table entries: 1024 (order: 0, 4096 bytes)
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TCP: Hash tables configured (established 1024 bind 1024) TCP reno registered
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JFFS2 version 2.2. (NAND) © 2001-2006 Red Hat, Inc.
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io scheduler noop registered
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io scheduler cfq registered (default)
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ColdFire internal UART serial driver version 1.00 ttyS0 at 0xfc060000 (irq = 90) is a builtin ColdFire UART
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ttyS1 at 0xfc064000 (irq = 91) is a builtin ColdFire UART
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ttyS2 at 0xfc068000 (irq = 92) is a builtin ColdFire UART RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize
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loop: module loaded
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nbd: registered device at major 43
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usbcore: registered new interface driver ub FEC ENET Version 0.2
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fec: PHY @ 0x1, ID 0x20005c90 -- DP83848
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eth0: ethernet 00:e0:0c:bc:e5:60
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uclinux[mtd]: RAM probe address=0x4021c22c size=0x22b000 Creating 1 MTD partitions on "RAM":
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0x00000000-0x0022b000 : "ROMfs"
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uclinux[mtd]: set ROMfs to be root filesystem NAND device: Manufacturer ID: 0x20, Chip ID: 0x73 (ST Micro NAND 16MiB 3,3V 8-b) Scanning device for bad blocks Creating 1 MTD partitions on "NAND 16MiB 3,3V 8-bit":
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0x00000000-0x01000000 : "M53xx flash partition 1"
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QSPI: spi->max_speed_hz 300000
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QSPI: Baud set to 255
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SPI: Coldfire master initialized
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M537x - Disable UART1 when using Audio
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udc: Freescale MCF53xx UDC driver version 27 October 2006 init
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udc: MCF53xx USB Device is found. ID=0x5 Rev=0x41 i2c /dev entries driver
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usbcore: registered new interface driver usbhid
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drivers/hid/usbhid/hid-core.c: v2.6:USB HID core driver TCP cubic registered
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NET: Registered protocol family 1
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NET: Registered protocol family 17
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VFS: Mounted root (romfs filesystem) readonly.
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Freeing unused kernel memory: 64k freed (0x401f5000 - 0x40204000) init started: BusyBox v1.00 (2007.11.07-19:57+0000) multi-call binary?Setting e Mounting filesystems
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mount: Mounting devpts on /dev/pts failed: No such device
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mount: Mounting usbfs on /proc/bus/usb failed: No such file or directory Starting syslogd and klogd Setting up networking on loopback device:
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Setting up networking on eth0:
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info, udhcpc (v0.9.9-pre) started
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eth0: config: auto-negotiation on, 100FDX, 100HDX, 10FDX, 10HDX.
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debug, Sending discover...
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debug, Sending discover...
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debug, Sending select for 172.27.0.130...
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info, Lease of 172.27.0.130 obtained, lease time 43200 deleting routers
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route: SIOC[ADD|DEL]RT: No such process
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adding dns 172.27.0.1
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||||
Starting the boa webserver:
|
||||
Setting time from ntp server: ntp.cs.strath.ac.uk
|
||||
ntp.cs.strath.ac.uk: Unknown host
|
||||
|
||||
|
||||
BusyBox v1.00 (2007.11.07-19:57+0000) Built-in shell (msh) Enter 'help' for a list of built-in commands.
|
||||
|
||||
#
|
||||
|
|
@ -169,7 +169,7 @@
|
|||
#endif
|
||||
#endif /* CONFIG_M5282 */
|
||||
|
||||
#ifdef CONFIG_M5329
|
||||
#if defined(CONFIG_M5329) || defined(CONFIG_M5373)
|
||||
#include <asm/immap_5329.h>
|
||||
#include <asm/m5329.h>
|
||||
|
||||
|
|
@ -197,7 +197,7 @@
|
|||
|
||||
#define CFG_INTR_BASE (MMAP_INTC0)
|
||||
#define CFG_NUM_IRQS (128)
|
||||
#endif /* CONFIG_M5329 */
|
||||
#endif /* CONFIG_M5329 && CONFIG_M5373 */
|
||||
|
||||
#ifdef CONFIG_M54455
|
||||
#include <asm/immap_5445x.h>
|
||||
|
|
|
|||
|
|
@ -378,91 +378,133 @@ typedef struct rcm {
|
|||
/* GPIO port registers */
|
||||
typedef struct gpio_ctrl {
|
||||
/* Port Output Data Registers */
|
||||
#ifdef CONFIG_M5329
|
||||
u8 podr_fech; /* 0x00 */
|
||||
u8 podr_fecl; /* 0x01 */
|
||||
#else
|
||||
u16 res00; /* 0x00 - 0x01 */
|
||||
#endif
|
||||
u8 podr_ssi; /* 0x02 */
|
||||
u8 podr_busctl; /* 0x03 */
|
||||
u8 podr_be; /* 0x04 */
|
||||
u8 podr_cs; /* 0x05 */
|
||||
u8 podr_pwm; /* 0x06 */
|
||||
u8 podr_feci2c; /* 0x07 */
|
||||
u8 res1; /* 0x08 */
|
||||
u8 res08; /* 0x08 */
|
||||
u8 podr_uart; /* 0x09 */
|
||||
u8 podr_qspi; /* 0x0A */
|
||||
u8 podr_timer; /* 0x0B */
|
||||
u8 res2; /* 0x0C */
|
||||
#ifdef CONFIG_M5329
|
||||
u8 res0C; /* 0x0C */
|
||||
u8 podr_lcddatah; /* 0x0D */
|
||||
u8 podr_lcddatam; /* 0x0E */
|
||||
u8 podr_lcddatal; /* 0x0F */
|
||||
u8 podr_lcdctlh; /* 0x10 */
|
||||
u8 podr_lcdctll; /* 0x11 */
|
||||
#else
|
||||
u16 res0C; /* 0x0C - 0x0D */
|
||||
u8 podr_fech; /* 0x0E */
|
||||
u8 podr_fecl; /* 0x0F */
|
||||
u16 res10[3]; /* 0x10 - 0x15 */
|
||||
#endif
|
||||
|
||||
/* Port Data Direction Registers */
|
||||
u16 res3; /* 0x12 - 0x13 */
|
||||
#ifdef CONFIG_M5329
|
||||
u16 res12; /* 0x12 - 0x13 */
|
||||
u8 pddr_fech; /* 0x14 */
|
||||
u8 pddr_fecl; /* 0x15 */
|
||||
#endif
|
||||
u8 pddr_ssi; /* 0x16 */
|
||||
u8 pddr_busctl; /* 0x17 */
|
||||
u8 pddr_be; /* 0x18 */
|
||||
u8 pddr_cs; /* 0x19 */
|
||||
u8 pddr_pwm; /* 0x1A */
|
||||
u8 pddr_feci2c; /* 0x1B */
|
||||
u8 res4; /* 0x1C */
|
||||
u8 res1C; /* 0x1C */
|
||||
u8 pddr_uart; /* 0x1D */
|
||||
u8 pddr_qspi; /* 0x1E */
|
||||
u8 pddr_timer; /* 0x1F */
|
||||
u8 res5; /* 0x20 */
|
||||
#ifdef CONFIG_M5329
|
||||
u8 res20; /* 0x20 */
|
||||
u8 pddr_lcddatah; /* 0x21 */
|
||||
u8 pddr_lcddatam; /* 0x22 */
|
||||
u8 pddr_lcddatal; /* 0x23 */
|
||||
u8 pddr_lcdctlh; /* 0x24 */
|
||||
u8 pddr_lcdctll; /* 0x25 */
|
||||
u16 res6; /* 0x26 - 0x27 */
|
||||
u16 res26; /* 0x26 - 0x27 */
|
||||
#else
|
||||
u16 res20; /* 0x20 - 0x21 */
|
||||
u8 pddr_fech; /* 0x22 */
|
||||
u8 pddr_fecl; /* 0x23 */
|
||||
u16 res24[3]; /* 0x24 - 0x29 */
|
||||
#endif
|
||||
|
||||
/* Port Data Direction Registers */
|
||||
#ifdef CONFIG_M5329
|
||||
u8 ppd_fech; /* 0x28 */
|
||||
u8 ppd_fecl; /* 0x29 */
|
||||
#endif
|
||||
u8 ppd_ssi; /* 0x2A */
|
||||
u8 ppd_busctl; /* 0x2B */
|
||||
u8 ppd_be; /* 0x2C */
|
||||
u8 ppd_cs; /* 0x2D */
|
||||
u8 ppd_pwm; /* 0x2E */
|
||||
u8 ppd_feci2c; /* 0x2F */
|
||||
u8 res7; /* 0x30 */
|
||||
u8 res30; /* 0x30 */
|
||||
u8 ppd_uart; /* 0x31 */
|
||||
u8 ppd_qspi; /* 0x32 */
|
||||
u8 ppd_timer; /* 0x33 */
|
||||
u8 res8; /* 0x34 */
|
||||
#ifdef CONFIG_M5329
|
||||
u8 res34; /* 0x34 */
|
||||
u8 ppd_lcddatah; /* 0x35 */
|
||||
u8 ppd_lcddatam; /* 0x36 */
|
||||
u8 ppd_lcddatal; /* 0x37 */
|
||||
u8 ppd_lcdctlh; /* 0x38 */
|
||||
u8 ppd_lcdctll; /* 0x39 */
|
||||
u16 res9; /* 0x3A - 0x3B */
|
||||
u16 res3A; /* 0x3A - 0x3B */
|
||||
#else
|
||||
u16 res34; /* 0x34 - 0x35 */
|
||||
u8 ppd_fech; /* 0x36 */
|
||||
u8 ppd_fecl; /* 0x37 */
|
||||
u16 res38[3]; /* 0x38 - 0x3D */
|
||||
#endif
|
||||
|
||||
/* Port Clear Output Data Registers */
|
||||
u8 pclrr_fech; /* 0x3C */
|
||||
u8 pclrr_fecl; /* 0x3D */
|
||||
#ifdef CONFIG_M5329
|
||||
u8 res3C; /* 0x3C */
|
||||
u8 pclrr_fech; /* 0x3D */
|
||||
u8 pclrr_fecl; /* 0x3E */
|
||||
#else
|
||||
u8 pclrr_ssi; /* 0x3E */
|
||||
#endif
|
||||
u8 pclrr_busctl; /* 0x3F */
|
||||
u8 pclrr_be; /* 0x40 */
|
||||
u8 pclrr_cs; /* 0x41 */
|
||||
u8 pclrr_pwm; /* 0x42 */
|
||||
u8 pclrr_feci2c; /* 0x43 */
|
||||
u8 res10; /* 0x44 */
|
||||
u8 res44; /* 0x44 */
|
||||
u8 pclrr_uart; /* 0x45 */
|
||||
u8 pclrr_qspi; /* 0x46 */
|
||||
u8 pclrr_timer; /* 0x47 */
|
||||
u8 res11; /* 0x48 */
|
||||
u8 pclrr_lcddatah; /* 0x49 */
|
||||
u8 pclrr_lcddatam; /* 0x4A */
|
||||
u8 pclrr_lcddatal; /* 0x4B */
|
||||
#ifdef CONFIG_M5329
|
||||
u8 pclrr_lcddatah; /* 0x48 */
|
||||
u8 pclrr_lcddatam; /* 0x49 */
|
||||
u8 pclrr_lcddatal; /* 0x4A */
|
||||
u8 pclrr_ssi; /* 0x4B */
|
||||
u8 pclrr_lcdctlh; /* 0x4C */
|
||||
u8 pclrr_lcdctll; /* 0x4D */
|
||||
u16 res12; /* 0x4E - 0x4F */
|
||||
u16 res4E; /* 0x4E - 0x4F */
|
||||
#else
|
||||
u16 res48; /* 0x48 - 0x49 */
|
||||
u8 pclrr_fech; /* 0x4A */
|
||||
u8 pclrr_fecl; /* 0x4B */
|
||||
u8 res4C[5]; /* 0x4C - 0x50 */
|
||||
#endif
|
||||
|
||||
/* Pin Assignment Registers */
|
||||
#ifdef CONFIG_M5329
|
||||
u8 par_fec; /* 0x50 */
|
||||
#endif
|
||||
u8 par_pwm; /* 0x51 */
|
||||
u8 par_busctl; /* 0x52 */
|
||||
u8 par_feci2c; /* 0x53 */
|
||||
|
|
@ -472,15 +514,20 @@ typedef struct gpio_ctrl {
|
|||
u16 par_uart; /* 0x58 */
|
||||
u16 par_qspi; /* 0x5A */
|
||||
u8 par_timer; /* 0x5C */
|
||||
#ifdef CONFIG_M5329
|
||||
u8 par_lcddata; /* 0x5D */
|
||||
u16 par_lcdctl; /* 0x5E */
|
||||
#else
|
||||
u8 par_fec; /* 0x5D */
|
||||
u16 res5E; /* 0x5E - 0x5F */
|
||||
#endif
|
||||
u16 par_irq; /* 0x60 */
|
||||
u16 res16; /* 0x62 - 0x63 */
|
||||
u16 res62; /* 0x62 - 0x63 */
|
||||
|
||||
/* Mode Select Control Registers */
|
||||
u8 mscr_flexbus; /* 0x64 */
|
||||
u8 mscr_sdram; /* 0x65 */
|
||||
u16 res17; /* 0x66 - 0x67 */
|
||||
u16 res66; /* 0x66 - 0x67 */
|
||||
|
||||
/* Drive Strength Control Registers */
|
||||
u8 dscr_i2c; /* 0x68 */
|
||||
|
|
@ -490,7 +537,11 @@ typedef struct gpio_ctrl {
|
|||
u8 dscr_qspi; /* 0x6C */
|
||||
u8 dscr_timer; /* 0x6D */
|
||||
u8 dscr_ssi; /* 0x6E */
|
||||
#ifdef CONFIG_M5329
|
||||
u8 dscr_lcd; /* 0x6F */
|
||||
#else
|
||||
u8 res6F; /* 0x6F */
|
||||
#endif
|
||||
u8 dscr_debug; /* 0x70 */
|
||||
u8 dscr_clkrst; /* 0x71 */
|
||||
u8 dscr_irq; /* 0x72 */
|
||||
|
|
|
|||
|
|
@ -1118,6 +1118,7 @@
|
|||
#define GPIO_PCLRR_LCDCTLL7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for GPIO_PAR_FEC */
|
||||
#ifdef CONFIG_M5329
|
||||
#define GPIO_PAR_FEC_MII(x) (((x)&0x03)<<0)
|
||||
#define GPIO_PAR_FEC_7W(x) (((x)&0x03)<<2)
|
||||
#define GPIO_PAR_FEC_7W_GPIO (0x00)
|
||||
|
|
@ -1126,6 +1127,10 @@
|
|||
#define GPIO_PAR_FEC_MII_GPIO (0x00)
|
||||
#define GPIO_PAR_FEC_MII_UART (0x01)
|
||||
#define GPIO_PAR_FEC_MII_FEC (0x03)
|
||||
#else
|
||||
#define GPIO_PAR_FEC_7W_FEC (0x08)
|
||||
#define GPIO_PAR_FEC_MII_FEC (0x02)
|
||||
#endif
|
||||
|
||||
/* Bit definitions and macros for GPIO_PAR_PWM */
|
||||
#define GPIO_PAR_PWM1(x) (((x)&0x03)<<0)
|
||||
|
|
|
|||
|
|
@ -0,0 +1,267 @@
|
|||
/*
|
||||
* Configuation settings for the Freescale MCF5373 FireEngine board.
|
||||
*
|
||||
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific
|
||||
*/
|
||||
|
||||
#ifndef _M5373EVB_H
|
||||
#define _M5373EVB_H
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
* (easy to change)
|
||||
*/
|
||||
#define CONFIG_MCF532x /* define processor family */
|
||||
#define CONFIG_M5373 /* define processor type */
|
||||
|
||||
#undef DEBUG
|
||||
|
||||
#define CONFIG_MCFUART
|
||||
#define CFG_UART_PORT (0)
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
|
||||
|
||||
#undef CONFIG_WATCHDOG
|
||||
#define CONFIG_WATCHDOG_TIMEOUT 3360 /* timeout in ms, max is 3.36 sec */
|
||||
|
||||
/* Command line configuration */
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#define CONFIG_CMD_CACHE
|
||||
#define CONFIG_CMD_DATE
|
||||
#define CONFIG_CMD_ELF
|
||||
#define CONFIG_CMD_FLASH
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_CMD_MEMORY
|
||||
#define CONFIG_CMD_MISC
|
||||
#define CONFIG_CMD_MII
|
||||
#define CONFIG_CMD_NET
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_REGINFO
|
||||
|
||||
#ifdef NANDFLASH_SIZE
|
||||
# define CONFIG_CMD_NAND
|
||||
#endif
|
||||
|
||||
#define CFG_UNIFY_CACHE
|
||||
|
||||
#define CONFIG_MCFFEC
|
||||
#ifdef CONFIG_MCFFEC
|
||||
# define CONFIG_NET_MULTI 1
|
||||
# define CONFIG_MII 1
|
||||
# define CFG_DISCOVER_PHY
|
||||
# define CFG_RX_ETH_BUFFER 8
|
||||
# define CFG_FAULT_ECHO_LINK_DOWN
|
||||
|
||||
# define CFG_FEC0_PINMUX 0
|
||||
# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE
|
||||
# define MCFFEC_TOUT_LOOP 50000
|
||||
/* If CFG_DISCOVER_PHY is not defined - hardcoded */
|
||||
# ifndef CFG_DISCOVER_PHY
|
||||
# define FECDUPLEX FULL
|
||||
# define FECSPEED _100BASET
|
||||
# else
|
||||
# ifndef CFG_FAULT_ECHO_LINK_DOWN
|
||||
# define CFG_FAULT_ECHO_LINK_DOWN
|
||||
# endif
|
||||
# endif /* CFG_DISCOVER_PHY */
|
||||
#endif
|
||||
|
||||
#define CONFIG_MCFRTC
|
||||
#undef RTC_DEBUG
|
||||
|
||||
/* Timer */
|
||||
#define CONFIG_MCFTMR
|
||||
#undef CONFIG_MCFPIT
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_FSL_I2C
|
||||
#define CONFIG_HARD_I2C /* I2C with hw support */
|
||||
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
|
||||
#define CFG_I2C_SPEED 80000
|
||||
#define CFG_I2C_SLAVE 0x7F
|
||||
#define CFG_I2C_OFFSET 0x58000
|
||||
#define CFG_IMMR CFG_MBAR
|
||||
|
||||
#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
|
||||
#define CONFIG_UDP_CHECKSUM
|
||||
|
||||
#ifdef CONFIG_MCFFEC
|
||||
# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
|
||||
# define CONFIG_IPADDR 192.162.1.2
|
||||
# define CONFIG_NETMASK 255.255.255.0
|
||||
# define CONFIG_SERVERIP 192.162.1.1
|
||||
# define CONFIG_GATEWAYIP 192.162.1.1
|
||||
# define CONFIG_OVERWRITE_ETHADDR_ONCE
|
||||
#endif /* FEC_ENET */
|
||||
|
||||
#define CONFIG_HOSTNAME M5373EVB
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"netdev=eth0\0" \
|
||||
"loadaddr=" MK_STR(CFG_LOAD_ADDR) "\0" \
|
||||
"u-boot=u-boot.bin\0" \
|
||||
"load=tftp ${loadaddr) ${u-boot}\0" \
|
||||
"upd=run load; run prog\0" \
|
||||
"prog=prot off 0 2ffff;" \
|
||||
"era 0 2ffff;" \
|
||||
"cp.b ${loadaddr} 0 ${filesize};" \
|
||||
"save\0" \
|
||||
""
|
||||
|
||||
#define CONFIG_PRAM 512 /* 512 KB */
|
||||
#define CFG_PROMPT "-> "
|
||||
#define CFG_LONGHELP /* undef to save memory */
|
||||
|
||||
#ifdef CONFIG_CMD_KGDB
|
||||
# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
# define CFG_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
|
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CFG_MAXARGS 16 /* max number of command args */
|
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
||||
#define CFG_LOAD_ADDR 0x40010000
|
||||
|
||||
#define CFG_HZ 1000
|
||||
#define CFG_CLK 80000000
|
||||
#define CFG_CPU_CLK CFG_CLK * 3
|
||||
|
||||
#define CFG_MBAR 0xFC000000
|
||||
|
||||
#define CFG_LATCH_ADDR (CFG_CS1_BASE + 0x80000)
|
||||
|
||||
/*
|
||||
* Low Level Configuration Settings
|
||||
* (address mappings, register initial values, etc.)
|
||||
* You should know what you are doing if you make changes here.
|
||||
*/
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM)
|
||||
*/
|
||||
#define CFG_INIT_RAM_ADDR 0x80000000
|
||||
#define CFG_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */
|
||||
#define CFG_INIT_RAM_CTRL 0x221
|
||||
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
|
||||
#define CFG_GBL_DATA_OFFSET ((CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - 0x10)
|
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration
|
||||
* (Set up by the startup code)
|
||||
* Please note that CFG_SDRAM_BASE _must_ start at 0
|
||||
*/
|
||||
#define CFG_SDRAM_BASE 0x40000000
|
||||
#define CFG_SDRAM_SIZE 32 /* SDRAM size in MB */
|
||||
#define CFG_SDRAM_CFG1 0x53722730
|
||||
#define CFG_SDRAM_CFG2 0x56670000
|
||||
#define CFG_SDRAM_CTRL 0xE1092000
|
||||
#define CFG_SDRAM_EMOD 0x40010000
|
||||
#define CFG_SDRAM_MODE 0x018D0000
|
||||
|
||||
#define CFG_MEMTEST_START CFG_SDRAM_BASE + 0x400
|
||||
#define CFG_MEMTEST_END ((CFG_SDRAM_SIZE - 3) << 20)
|
||||
|
||||
#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400)
|
||||
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
|
||||
|
||||
#define CFG_BOOTPARAMS_LEN 64*1024
|
||||
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization ??
|
||||
*/
|
||||
#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization
|
||||
*/
|
||||
#define CFG_FLASH_CFI
|
||||
#ifdef CFG_FLASH_CFI
|
||||
# define CFG_FLASH_CFI_DRIVER 1
|
||||
# define CFG_FLASH_SIZE 0x800000 /* Max size that the board might have */
|
||||
# define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT
|
||||
# define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
|
||||
# define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
|
||||
# define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
|
||||
#endif
|
||||
|
||||
#ifdef NANDFLASH_SIZE
|
||||
# define CFG_MAX_NAND_DEVICE 1
|
||||
# define CFG_NAND_BASE CFG_CS2_BASE
|
||||
# define CFG_NAND_SIZE 1
|
||||
# define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
|
||||
# define NAND_MAX_CHIPS 1
|
||||
# define NAND_ALLOW_ERASE_ALL 1
|
||||
# define CONFIG_JFFS2_NAND 1
|
||||
# define CONFIG_JFFS2_DEV "nand0"
|
||||
# define CONFIG_JFFS2_PART_SIZE (CFG_CS2_MASK & ~1)
|
||||
# define CONFIG_JFFS2_PART_OFFSET 0x00000000
|
||||
#endif
|
||||
|
||||
#define CFG_FLASH_BASE CFG_CS0_BASE
|
||||
|
||||
/* Configuration for environment
|
||||
* Environment is embedded in u-boot in the second sector of the flash
|
||||
*/
|
||||
#define CFG_ENV_OFFSET 0x4000
|
||||
#define CFG_ENV_SECT_SIZE 0x2000
|
||||
#define CFG_ENV_IS_IN_FLASH 1
|
||||
#define CFG_ENV_IS_EMBEDDED 1
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration
|
||||
*/
|
||||
#define CFG_CACHELINE_SIZE 16
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Chipselect bank definitions
|
||||
*/
|
||||
/*
|
||||
* CS0 - NOR Flash 1, 2, 4, or 8MB
|
||||
* CS1 - CompactFlash and registers
|
||||
* CS2 - NAND Flash 16, 32, or 64MB
|
||||
* CS3 - Available
|
||||
* CS4 - Available
|
||||
* CS5 - Available
|
||||
*/
|
||||
#define CFG_CS0_BASE 0
|
||||
#define CFG_CS0_MASK 0x007f0001
|
||||
#define CFG_CS0_CTRL 0x00001fa0
|
||||
|
||||
#define CFG_CS1_BASE 0x10000000
|
||||
#define CFG_CS1_MASK 0x001f0001
|
||||
#define CFG_CS1_CTRL 0x002A3780
|
||||
|
||||
#ifdef NANDFLASH_SIZE
|
||||
#define CFG_CS2_BASE 0x20000000
|
||||
#define CFG_CS2_MASK ((NANDFLASH_SIZE << 20) | 1)
|
||||
#define CFG_CS2_CTRL 0x00001f60
|
||||
#endif
|
||||
|
||||
#endif /* _M5373EVB_H */
|
||||
Loading…
Reference in New Issue