8610: Add 8610 DIU display driver
1280x1024 and 1024x768 @ 32 bpp are supported now.
DVI, Single-link LVDS, Double-link LVDS are all supported.
Environmental variable "monitor" is used to specify monitor port.
A new command "diufb" is introduced to reinitialize monitor
and display a BMP file in the memory. So far, 1-bit, 4-bit,
8-bit and 24-bit BMP formats are supported.
diufb init
- initialize the diu driver
Enable the port specified in the environmental variable "monitor"
diufb addr
- display bmp file in memory.
The bmp image should be no bigger than the resolution, 1280x1024
for DVI and double-link LVDS, 1024x768 for single-link LVDS.
Note, this driver allocate memory but doesn't free it after use
It is written on purpose -- to avoid a failure of reallocation
due to memory fragement.
ECC of DDR is disabled for DIU performance. L2 data cache is also disabled.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Jon loeliger <jdl@freescale.com>
This commit is contained in:
York Sun
Jon Loeliger
parent
52e5ddfecd
commit
a877880c69
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@ -31,7 +31,9 @@ LIB = $(obj)lib$(VENDOR).a
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COBJS := sys_eeprom.o \
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pixis.o \
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pq-mds-pib.o
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pq-mds-pib.o \
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fsl_logo_bmp.o \
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fsl_diu_fb.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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@ -0,0 +1,656 @@
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/*
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* Copyright 2007 Freescale Semiconductor, Inc.
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* York Sun <yorksun@freescale.com>
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*
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* FSL DIU Framebuffer driver
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <i2c.h>
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#include <malloc.h>
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#ifdef CONFIG_FSL_DIU_FB
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#include "fsl_diu_fb.h"
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#ifdef DEBUG
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#define DPRINTF(fmt, args...) printf("%s: " fmt,__FUNCTION__,## args)
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#else
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#define DPRINTF(fmt, args...)
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#endif
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struct fb_var_screeninfo {
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unsigned int xres; /* visible resolution */
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unsigned int yres;
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unsigned int bits_per_pixel; /* guess what */
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/* Timing: All values in pixclocks, except pixclock (of course) */
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unsigned int pixclock; /* pixel clock in ps (pico seconds) */
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unsigned int left_margin; /* time from sync to picture */
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unsigned int right_margin; /* time from picture to sync */
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unsigned int upper_margin; /* time from sync to picture */
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unsigned int lower_margin;
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unsigned int hsync_len; /* length of horizontal sync */
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unsigned int vsync_len; /* length of vertical sync */
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unsigned int sync; /* see FB_SYNC_* */
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unsigned int vmode; /* see FB_VMODE_* */
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unsigned int rotate; /* angle we rotate counter clockwise */
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};
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struct fb_info {
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struct fb_var_screeninfo var; /* Current var */
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unsigned long smem_start; /* Start of frame buffer mem */
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/* (physical address) */
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unsigned int smem_len; /* Length of frame buffer mem */
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unsigned int type; /* see FB_TYPE_* */
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unsigned int line_length; /* length of a line in bytes */
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char *screen_base;
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unsigned long screen_size;
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int logo_height;
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unsigned int logo_size;
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};
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struct fb_videomode {
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const char *name; /* optional */
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unsigned int refresh; /* optional */
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unsigned int xres;
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unsigned int yres;
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unsigned int pixclock;
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unsigned int left_margin;
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unsigned int right_margin;
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unsigned int upper_margin;
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unsigned int lower_margin;
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unsigned int hsync_len;
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unsigned int vsync_len;
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unsigned int sync;
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unsigned int vmode;
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unsigned int flag;
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};
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#define FB_SYNC_VERT_HIGH_ACT 2 /* vertical sync high active */
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#define FB_SYNC_COMP_HIGH_ACT 8 /* composite sync high active */
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#define FB_VMODE_NONINTERLACED 0 /* non interlaced */
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/*
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* These parameters give default parameters
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* for video output 1024x768,
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* FIXME - change timing to proper amounts
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* hsync 31.5kHz, vsync 60Hz
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*/
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static struct fb_videomode fsl_diu_mode_1024 = {
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.refresh = 60,
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.xres = 1024,
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.yres = 768,
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.pixclock = 15385,
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.left_margin = 160,
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.right_margin = 24,
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.upper_margin = 29,
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.lower_margin = 3,
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.hsync_len = 136,
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.vsync_len = 6,
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.sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
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.vmode = FB_VMODE_NONINTERLACED
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};
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static struct fb_videomode fsl_diu_mode_1280 = {
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.name = "1280x1024-60",
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.refresh = 60,
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.xres = 1280,
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.yres = 1024,
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.pixclock = 9375,
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.left_margin = 38,
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.right_margin = 128,
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.upper_margin = 2,
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.lower_margin = 7,
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.hsync_len = 216,
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.vsync_len = 37,
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.sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
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.vmode = FB_VMODE_NONINTERLACED
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};
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/*
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* These are the fields of area descriptor(in DDR memory) for every plane
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*/
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struct diu_ad {
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/* Word 0(32-bit) in DDR memory */
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unsigned int pix_fmt; /* hard coding pixel format */
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/* Word 1(32-bit) in DDR memory */
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unsigned int addr;
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/* Word 2(32-bit) in DDR memory */
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unsigned int src_size_g_alpha;
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/* Word 3(32-bit) in DDR memory */
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unsigned int aoi_size;
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/* Word 4(32-bit) in DDR memory */
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unsigned int offset_xyi;
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/* Word 5(32-bit) in DDR memory */
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unsigned int offset_xyd;
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/* Word 6(32-bit) in DDR memory */
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unsigned int ckmax_r:8;
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unsigned int ckmax_g:8;
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unsigned int ckmax_b:8;
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unsigned int res9:8;
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/* Word 7(32-bit) in DDR memory */
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unsigned int ckmin_r:8;
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unsigned int ckmin_g:8;
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unsigned int ckmin_b:8;
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unsigned int res10:8;
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/* Word 8(32-bit) in DDR memory */
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unsigned int next_ad;
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/* Word 9(32-bit) in DDR memory, just for 64-bit aligned */
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unsigned int res1;
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unsigned int res2;
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unsigned int res3;
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}__attribute__ ((packed));
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/*
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* DIU register map
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*/
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struct diu {
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unsigned int desc[3];
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unsigned int gamma;
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unsigned int pallete;
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unsigned int cursor;
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unsigned int curs_pos;
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unsigned int diu_mode;
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unsigned int bgnd;
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unsigned int bgnd_wb;
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unsigned int disp_size;
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unsigned int wb_size;
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unsigned int wb_mem_addr;
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unsigned int hsyn_para;
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unsigned int vsyn_para;
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unsigned int syn_pol;
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unsigned int thresholds;
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unsigned int int_status;
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unsigned int int_mask;
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unsigned int colorbar[8];
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unsigned int filling;
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unsigned int plut;
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} __attribute__ ((packed));
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struct diu_hw {
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struct diu *diu_reg;
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volatile unsigned int mode; /* DIU operation mode */
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};
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struct diu_addr {
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unsigned char * paddr; /* Virtual address */
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unsigned int offset;
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};
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#define FSL_DIU_BASE_OFFSET 0x2C000 /* Offset of Display Interface Unit */
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/*
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* Modes of operation of DIU
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*/
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#define MFB_MODE0 0 /* DIU off */
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#define MFB_MODE1 1 /* All three planes output to display */
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#define MFB_MODE2 2 /* Plane 1 to display,
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* planes 2+3 written back to memory */
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#define MFB_MODE3 3 /* All three planes written back to memory */
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#define MFB_MODE4 4 /* Color bar generation */
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#define MAX_CURS 32
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static struct fb_info fsl_fb_info;
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static struct diu_addr gamma, cursor;
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static struct diu_ad fsl_diu_fb_ad __attribute__ ((aligned(32)));
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static struct diu_ad dummy_ad __attribute__ ((aligned(32)));
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static unsigned char *dummy_fb;
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static struct diu_hw dr = {
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.mode = MFB_MODE1,
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};
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int fb_enabled = 0;
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int fb_initialized = 0;
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const int default_xres = 1280;
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const int default_pixel_format = 0x88882317;
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static int map_video_memory(struct fb_info *info, unsigned long bytes_align);
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static void enable_lcdc(void);
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static void disable_lcdc(void);
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static int fsl_diu_enable_panel(struct fb_info *info);
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static int fsl_diu_disable_panel(struct fb_info *info);
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static int allocate_buf(struct diu_addr *buf, u32 size, u32 bytes_align);
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static u32 get_busfreq(void);
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int fsl_diu_init(int xres,
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unsigned int pixel_format,
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int gamma_fix,
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unsigned char *splash_bmp)
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{
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struct fb_videomode *fsl_diu_mode_db;
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struct diu_ad *ad = &fsl_diu_fb_ad;
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struct diu *hw;
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struct fb_info *info = &fsl_fb_info;
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struct fb_var_screeninfo *var = &info->var;
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volatile immap_t *immap = (immap_t *)CFG_IMMR;
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volatile ccsr_gur_t *gur = &immap->im_gur;
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volatile unsigned int *guts_clkdvdr = &gur->clkdvdr;
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unsigned char *gamma_table_base;
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unsigned int i, j;
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unsigned long speed_ccb, temp, pixval;
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DPRINTF("Enter fsl_diu_init\n");
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dr.diu_reg = (struct diu *) (CFG_IMMR + FSL_DIU_BASE_OFFSET);
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hw = (struct diu *) dr.diu_reg;
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disable_lcdc();
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if (xres == 1280) {
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fsl_diu_mode_db = &fsl_diu_mode_1280;
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} else {
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fsl_diu_mode_db = &fsl_diu_mode_1024;
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}
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if (0 == fb_initialized) {
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allocate_buf(&gamma, 768, 32);
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DPRINTF("gamma is allocated @ 0x%x\n",
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(unsigned int)gamma.paddr);
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allocate_buf(&cursor, MAX_CURS * MAX_CURS * 2, 32);
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DPRINTF("curosr is allocated @ 0x%x\n",
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(unsigned int)cursor.paddr);
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/* create a dummy fb and dummy ad */
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dummy_fb = malloc(64);
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if (NULL == dummy_fb) {
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printf("Cannot allocate dummy fb\n");
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return -1;
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}
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dummy_ad.addr = cpu_to_le32((unsigned int)dummy_fb);
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dummy_ad.pix_fmt = 0x88882317;
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dummy_ad.src_size_g_alpha = 0x04400000; /* alpha = 0 */
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dummy_ad.aoi_size = 0x02000400;
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dummy_ad.offset_xyi = 0;
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dummy_ad.offset_xyd = 0;
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dummy_ad.next_ad = 0;
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/* Memory allocation for framebuffer */
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if (map_video_memory(info, 32)) {
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printf("Unable to allocate fb memory 1\n");
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return -1;
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}
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} else {
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memset(info->screen_base, 0, info->smem_len);
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}
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dr.diu_reg->desc[0] = (unsigned int) &dummy_ad;
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dr.diu_reg->desc[1] = (unsigned int) &dummy_ad;
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dr.diu_reg->desc[2] = (unsigned int) &dummy_ad;
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DPRINTF("dummy dr.diu_reg->desc[0] = 0x%x\n", dr.diu_reg->desc[0]);
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DPRINTF("dummy desc[0] = 0x%x\n", hw->desc[0]);
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/* read mode info */
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var->xres = fsl_diu_mode_db->xres;
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var->yres = fsl_diu_mode_db->yres;
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var->bits_per_pixel = 32;
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var->pixclock = fsl_diu_mode_db->pixclock;
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var->left_margin = fsl_diu_mode_db->left_margin;
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var->right_margin = fsl_diu_mode_db->right_margin;
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var->upper_margin = fsl_diu_mode_db->upper_margin;
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var->lower_margin = fsl_diu_mode_db->lower_margin;
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var->hsync_len = fsl_diu_mode_db->hsync_len;
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var->vsync_len = fsl_diu_mode_db->vsync_len;
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var->sync = fsl_diu_mode_db->sync;
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var->vmode = fsl_diu_mode_db->vmode;
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info->line_length = var->xres * var->bits_per_pixel / 8;
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info->logo_size = 0;
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info->logo_height = 0;
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ad->pix_fmt = pixel_format;
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ad->addr = cpu_to_le32((unsigned int)info->screen_base);
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ad->src_size_g_alpha
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= cpu_to_le32((var->yres << 12) | var->xres);
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/* fix me. AOI should not be greater than display size */
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ad->aoi_size = cpu_to_le32(( var->yres << 16) | var->xres);
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ad->offset_xyi = 0;
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ad->offset_xyd = 0;
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/* Disable chroma keying function */
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ad->ckmax_r = 0;
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ad->ckmax_g = 0;
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ad->ckmax_b = 0;
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ad->ckmin_r = 255;
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ad->ckmin_g = 255;
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ad->ckmin_b = 255;
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gamma_table_base = gamma.paddr;
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DPRINTF("gamma_table_base is allocated @ 0x%x\n",
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(unsigned int)gamma_table_base);
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/* Prep for DIU init - gamma table */
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for (i = 0; i <= 2; i++)
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for (j = 0; j <= 255; j++)
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*gamma_table_base++ = j;
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if (gamma_fix == 1) { /* fix the gamma */
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DPRINTF("Fix gamma table\n");
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gamma_table_base = gamma.paddr;
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for (i = 0; i < 256*3; i++) {
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gamma_table_base[i] = (gamma_table_base[i] << 2)
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| ((gamma_table_base[i] >> 6) & 0x03);
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}
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}
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DPRINTF("update-lcdc: HW - %p\n Disabling DIU\n", hw);
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/* Program DIU registers */
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hw->gamma = (unsigned int) gamma.paddr;
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hw->cursor= (unsigned int) cursor.paddr;
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hw->bgnd = 0x007F7F7F; /* BGND */
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hw->bgnd_wb = 0; /* BGND_WB */
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hw->disp_size = var->yres << 16 | var->xres; /* DISP SIZE */
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hw->wb_size = 0; /* WB SIZE */
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hw->wb_mem_addr = 0; /* WB MEM ADDR */
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hw->hsyn_para = var->left_margin << 22 | /* BP_H */
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var->hsync_len << 11 | /* PW_H */
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var->right_margin; /* FP_H */
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hw->vsyn_para = var->upper_margin << 22 | /* BP_V */
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var->vsync_len << 11 | /* PW_V */
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var->lower_margin; /* FP_V */
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/* Pixel Clock configuration */
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DPRINTF("DIU: Bus Frequency = %d\n", get_busfreq());
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speed_ccb = get_busfreq();
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DPRINTF("DIU pixclock in ps - %d\n", var->pixclock);
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temp = 1;
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temp *= 1000000000;
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temp /= var->pixclock;
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temp *= 1000;
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pixval = speed_ccb / temp;
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DPRINTF("DIU pixval = %lu\n", pixval);
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hw->syn_pol = 0; /* SYNC SIGNALS POLARITY */
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hw->thresholds = 0x00037800; /* The Thresholds */
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hw->int_status = 0; /* INTERRUPT STATUS */
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hw->int_mask = 0; /* INT MASK */
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hw->plut = 0x01F5F666;
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/* Modify PXCLK in GUTS CLKDVDR */
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DPRINTF("DIU: Current value of CLKDVDR = 0x%08x\n", *guts_clkdvdr);
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temp = *guts_clkdvdr & 0x2000FFFF;
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*guts_clkdvdr = temp; /* turn off clock */
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*guts_clkdvdr = temp | 0x80000000 | ((pixval & 0x1F) << 16);
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DPRINTF("DIU: Modified value of CLKDVDR = 0x%08x\n", *guts_clkdvdr);
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fb_initialized = 1;
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if (splash_bmp) {
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info->logo_height = fsl_diu_display_bmp(splash_bmp, 0, 0, 0);
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info->logo_size = info->logo_height * info->line_length;
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DPRINTF("logo height %d, logo_size 0x%x\n",
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info->logo_height,info->logo_size);
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}
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/* Enable the DIU */
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fsl_diu_enable_panel(info);
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enable_lcdc();
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return 0;
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}
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char *fsl_fb_open(struct fb_info **info)
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{
|
||||
*info = &fsl_fb_info;
|
||||
return (char *) ((unsigned int)(*info)->screen_base
|
||||
+ (*info)->logo_size);
|
||||
}
|
||||
|
||||
void fsl_diu_close(void)
|
||||
{
|
||||
struct fb_info *info = &fsl_fb_info;
|
||||
fsl_diu_disable_panel(info);
|
||||
}
|
||||
|
||||
static int fsl_diu_enable_panel(struct fb_info *info)
|
||||
{
|
||||
struct diu *hw = dr.diu_reg;
|
||||
struct diu_ad *ad = &fsl_diu_fb_ad;
|
||||
|
||||
DPRINTF("Entered: enable_panel\n");
|
||||
if (hw->desc[0] != (unsigned int)ad)
|
||||
hw->desc[0] = (unsigned int)ad;
|
||||
DPRINTF("desc[0] = 0x%x\n", hw->desc[0]);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int fsl_diu_disable_panel(struct fb_info *info)
|
||||
{
|
||||
struct diu *hw = dr.diu_reg;
|
||||
|
||||
DPRINTF("Entered: disable_panel\n");
|
||||
if (hw->desc[0] != (unsigned int)&dummy_ad)
|
||||
hw->desc[0] = (unsigned int)&dummy_ad;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int map_video_memory(struct fb_info *info, unsigned long bytes_align)
|
||||
{
|
||||
unsigned long offset;
|
||||
unsigned long mask;
|
||||
|
||||
DPRINTF("Entered: map_video_memory\n");
|
||||
/* allocate maximum 1280*1024 with 32bpp */
|
||||
info->smem_len = 1280 * 4 *1024 + bytes_align;
|
||||
DPRINTF("MAP_VIDEO_MEMORY: smem_len = %d\n", info->smem_len);
|
||||
info->screen_base = malloc(info->smem_len);
|
||||
if (info->screen_base == NULL) {
|
||||
printf("Unable to allocate fb memory\n");
|
||||
return -1;
|
||||
}
|
||||
info->smem_start = (unsigned int) info->screen_base;
|
||||
mask = bytes_align - 1;
|
||||
offset = (unsigned long)info->screen_base & mask;
|
||||
if (offset) {
|
||||
info->screen_base += offset;
|
||||
info->smem_len = info->smem_len - (bytes_align - offset);
|
||||
} else
|
||||
info->smem_len = info->smem_len - bytes_align;
|
||||
|
||||
info->screen_size = info->smem_len;
|
||||
|
||||
DPRINTF("Allocated fb @ 0x%08lx, size=%d.\n",
|
||||
info->smem_start, info->smem_len);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void enable_lcdc(void)
|
||||
{
|
||||
struct diu *hw = dr.diu_reg;
|
||||
|
||||
DPRINTF("Entered: enable_lcdc, fb_enabled = %d\n", fb_enabled);
|
||||
if (!fb_enabled) {
|
||||
hw->diu_mode = dr.mode;
|
||||
fb_enabled++;
|
||||
}
|
||||
DPRINTF("diu_mode = %d\n", hw->diu_mode);
|
||||
}
|
||||
|
||||
static void disable_lcdc(void)
|
||||
{
|
||||
struct diu *hw = dr.diu_reg;
|
||||
|
||||
DPRINTF("Entered: disable_lcdc, fb_enabled = %d\n", fb_enabled);
|
||||
if (fb_enabled) {
|
||||
hw->diu_mode = 0;
|
||||
fb_enabled = 0;
|
||||
}
|
||||
}
|
||||
|
||||
static u32 get_busfreq(void)
|
||||
{
|
||||
u32 fs_busfreq = 0;
|
||||
|
||||
fs_busfreq = get_bus_freq(0);
|
||||
return fs_busfreq;
|
||||
}
|
||||
|
||||
/*
|
||||
* Align to 64-bit(8-byte), 32-byte, etc.
|
||||
*/
|
||||
static int allocate_buf(struct diu_addr *buf, u32 size, u32 bytes_align)
|
||||
{
|
||||
u32 offset, ssize;
|
||||
u32 mask;
|
||||
|
||||
DPRINTF("Entered: allocate_buf\n");
|
||||
ssize = size + bytes_align;
|
||||
buf->paddr = malloc(ssize);
|
||||
if (!buf->paddr)
|
||||
return -1;
|
||||
|
||||
memset(buf->paddr, 0, ssize);
|
||||
mask = bytes_align - 1;
|
||||
offset = (u32)buf->paddr & mask;
|
||||
if (offset) {
|
||||
buf->offset = bytes_align - offset;
|
||||
buf->paddr = (unsigned char *) ((u32)buf->paddr + offset);
|
||||
} else
|
||||
buf->offset = 0;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int fsl_diu_display_bmp(unsigned char *bmp,
|
||||
int xoffset,
|
||||
int yoffset,
|
||||
int transpar)
|
||||
{
|
||||
struct fb_info *info = &fsl_fb_info;
|
||||
unsigned char r, g, b;
|
||||
unsigned int *fb_t, val;
|
||||
unsigned char *bitmap;
|
||||
unsigned int palette[256];
|
||||
int width, height, bpp, ncolors, raster, offset, x, y, i, k, cpp;
|
||||
|
||||
if (!bmp) {
|
||||
printf("Must supply a bitmap address\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
raster = bmp[10] + (bmp[11] << 8) + (bmp[12] << 16) + (bmp[13] << 24);
|
||||
width = (bmp[21] << 24) | (bmp[20] << 16) | (bmp[19] << 8) | bmp[18];
|
||||
height = (bmp[25] << 24) | (bmp[24] << 16) | (bmp[23] << 8) | bmp[22];
|
||||
bpp = (bmp[29] << 8) | (bmp[28]);
|
||||
ncolors = bmp[46] + (bmp[47] << 8) + (bmp[48] << 16) + (bmp[49] << 24);
|
||||
bitmap = bmp + raster;
|
||||
cpp = info->var.bits_per_pixel / 8;
|
||||
|
||||
DPRINTF("bmp = 0x%08x\n", (unsigned int)bmp);
|
||||
DPRINTF("bitmap = 0x%08x\n", (unsigned int)bitmap);
|
||||
DPRINTF("width = %d\n", width);
|
||||
DPRINTF("height = %d\n", height);
|
||||
DPRINTF("bpp = %d\n", bpp);
|
||||
DPRINTF("ncolors = %d\n", ncolors);
|
||||
|
||||
DPRINTF("xres = %d\n", info->var.xres);
|
||||
DPRINTF("yres = %d\n", info->var.yres);
|
||||
DPRINTF("Screen_base = 0x%x\n", (unsigned int)info->screen_base);
|
||||
|
||||
if (((width+xoffset) > info->var.xres) ||
|
||||
((height+yoffset) > info->var.yres)) {
|
||||
printf("bitmap is out of range, image too large or too much offset\n");
|
||||
return 0;
|
||||
}
|
||||
if (bpp < 24) {
|
||||
for (i = 0, offset = 54; i < ncolors; i++, offset += 4)
|
||||
palette[i] = (bmp[offset+2] << 16)
|
||||
+ (bmp[offset+1] << 8) + bmp[offset];
|
||||
}
|
||||
|
||||
switch (bpp) {
|
||||
case 1:
|
||||
for (y = height - 1; y >= 0; y--) {
|
||||
fb_t = (unsigned int *) ((unsigned int)info->screen_base + (((y+yoffset) * info->var.xres) + xoffset)*cpp);
|
||||
for (x = 0; x < width; x += 8) {
|
||||
b = *bitmap++;
|
||||
for (k = 0; k < 8; k++) {
|
||||
if (b & 0x80)
|
||||
*fb_t = palette[1];
|
||||
else
|
||||
*fb_t = palette[0];
|
||||
b = b << 1;
|
||||
}
|
||||
}
|
||||
for (i = (width / 2) % 4; i > 0; i--)
|
||||
bitmap++;
|
||||
}
|
||||
break;
|
||||
case 4:
|
||||
for (y = height - 1; y >= 0; y--) {
|
||||
fb_t = (unsigned int *) ((unsigned int)info->screen_base + (((y+yoffset) * info->var.xres) + xoffset)*cpp);
|
||||
for (x = 0; x < width; x += 2) {
|
||||
b = *bitmap++;
|
||||
r = (b >> 4) & 0x0F;
|
||||
g = b & 0x0F;
|
||||
*fb_t++ = palette[r];
|
||||
*fb_t++ = palette[g];
|
||||
}
|
||||
for (i = (width / 2) % 4; i > 0; i--)
|
||||
bitmap++;
|
||||
}
|
||||
break;
|
||||
case 8:
|
||||
for (y = height - 1; y >= 0; y--) {
|
||||
fb_t = (unsigned int *) ((unsigned int)info->screen_base + (((y+yoffset) * info->var.xres) + xoffset)*cpp);
|
||||
for (x = 0; x < width; x++) {
|
||||
*fb_t++ = palette[ *bitmap++ ];
|
||||
}
|
||||
for (i = (width / 2) % 4; i > 0; i--)
|
||||
bitmap++;
|
||||
}
|
||||
break;
|
||||
case 24:
|
||||
for (y = height - 1; y >= 0; y--) {
|
||||
fb_t = (unsigned int *) ((unsigned int)info->screen_base + (((y+yoffset) * info->var.xres) + xoffset)*cpp);
|
||||
for (x = 0; x < width; x++) {
|
||||
b = *bitmap++;
|
||||
g = *bitmap++;
|
||||
r = *bitmap++;
|
||||
val = (r << 16) + (g << 8) + b;
|
||||
*fb_t++ = val;
|
||||
}
|
||||
for (; (x % 4) != 0; x++) /* 4-byte alignment */
|
||||
bitmap++;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
return height;
|
||||
}
|
||||
|
||||
void fsl_diu_clear_screen(void)
|
||||
{
|
||||
struct fb_info *info = &fsl_fb_info;
|
||||
|
||||
memset(info->screen_base, 0, info->smem_len);
|
||||
}
|
||||
#endif /* CONFIG_FSL_DIU_FB */
|
||||
|
|
@ -0,0 +1,35 @@
|
|||
/*
|
||||
* Copyright 2007 Freescale Semiconductor, Inc.
|
||||
* York Sun <yorksun@freescale.com>
|
||||
*
|
||||
* FSL DIU Framebuffer driver
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
|
||||
extern int fsl_diu_init(int xres,
|
||||
unsigned int pixel_format,
|
||||
int gamma_fix,
|
||||
unsigned char *splash_bmp);
|
||||
extern void fsl_diu_clear_screen(void);
|
||||
extern int fsl_diu_display_bmp(unsigned char *bmp,
|
||||
int xoffset,
|
||||
int yoffset,
|
||||
int transpar);
|
||||
|
|
@ -29,7 +29,9 @@ LIB = $(obj)lib$(BOARD).a
|
|||
|
||||
COBJS := $(BOARD).o \
|
||||
../common/sys_eeprom.o \
|
||||
../common/pixis.o
|
||||
../common/pixis.o \
|
||||
mpc8610hpcd_diu.o \
|
||||
../common/fsl_diu_fb.o
|
||||
|
||||
SOBJS := init.o
|
||||
|
||||
|
|
|
|||
|
|
@ -54,7 +54,47 @@ int board_early_init_f(void)
|
|||
volatile immap_t *immap = (immap_t *)CFG_IMMR;
|
||||
volatile ccsr_gur_t *gur = &immap->im_gur;
|
||||
|
||||
gur->gpiocr |= 0x888a5500; /* DIU16, IR1, UART0, UART2 */
|
||||
gur->gpiocr |= 0x88aa5500; /* DIU16, IR1, UART0, UART2 */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int misc_init_r(void)
|
||||
{
|
||||
u8 tmp_val, version;
|
||||
|
||||
/*Do not use 8259PIC*/
|
||||
tmp_val = in8(PIXIS_BASE + PIXIS_BRDCFG0);
|
||||
out8(PIXIS_BASE + PIXIS_BRDCFG0, tmp_val | 0x80);
|
||||
|
||||
/*For FPGA V7 or higher, set the IRQMAPSEL to 0 to use MAP0 interrupt*/
|
||||
version = in8(PIXIS_BASE + PIXIS_PVER);
|
||||
if(version >= 0x07) {
|
||||
tmp_val = in8(PIXIS_BASE + PIXIS_BRDCFG0);
|
||||
out8(PIXIS_BASE + PIXIS_BRDCFG0, tmp_val & 0xbf);
|
||||
}
|
||||
|
||||
/* Using this for DIU init before the driver in linux takes over
|
||||
* Enable the TFP410 Encoder (I2C address 0x38)
|
||||
*/
|
||||
|
||||
tmp_val = 0xBF;
|
||||
i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
|
||||
/* Verify if enabled */
|
||||
tmp_val = 0;
|
||||
i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
|
||||
debug("DVI Encoder Read: 0x%02lx\n",tmp_val);
|
||||
|
||||
tmp_val = 0x10;
|
||||
i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
|
||||
/* Verify if enabled */
|
||||
tmp_val = 0;
|
||||
i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
|
||||
debug("DVI Encoder Read: 0x%02lx\n",tmp_val);
|
||||
|
||||
#ifdef CONFIG_FSL_DIU_FB
|
||||
mpc8610hpcd_diu_init();
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -62,7 +102,6 @@ int board_early_init_f(void)
|
|||
int checkboard(void)
|
||||
{
|
||||
volatile immap_t *immap = (immap_t *)CFG_IMMR;
|
||||
volatile ccsr_lbc_t *memctl = &immap->im_lbc;
|
||||
volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
|
||||
|
||||
puts("Board: MPC8610HPCD\n");
|
||||
|
|
@ -468,7 +507,7 @@ ft_board_setup(void *blob, bd_t *bd)
|
|||
unsigned long
|
||||
get_board_sys_clk(ulong dummy)
|
||||
{
|
||||
u8 i, go_bit, rd_clks;
|
||||
u8 i;
|
||||
ulong val = 0;
|
||||
ulong a;
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,105 @@
|
|||
/*
|
||||
* Copyright 2007 Freescale Semiconductor, Inc.
|
||||
* York Sun <yorksun@freescale.com>
|
||||
*
|
||||
* FSL DIU Framebuffer driver
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#ifdef CONFIG_FSL_DIU_FB
|
||||
|
||||
#include "../common/pixis.h"
|
||||
#include "../common/fsl_diu_fb.h"
|
||||
|
||||
|
||||
extern unsigned int FSL_Logo_BMP[];
|
||||
|
||||
|
||||
void mpc8610hpcd_diu_init(void)
|
||||
{
|
||||
char *monitor_port;
|
||||
int xres, gamma_fix;
|
||||
unsigned int pixel_format;
|
||||
unsigned char tmp_val;
|
||||
|
||||
tmp_val = in8(PIXIS_BASE + PIXIS_BRDCFG0);
|
||||
monitor_port = getenv ("monitor");
|
||||
|
||||
if (!strncmp(monitor_port, "0", 1)) { /* 0 - DVI */
|
||||
xres = 1280;
|
||||
pixel_format = 0x88882317;
|
||||
gamma_fix = 0;
|
||||
out8(PIXIS_BASE + PIXIS_BRDCFG0, tmp_val | 0x08);
|
||||
|
||||
} else if (!strncmp(monitor_port, "1", 1)) { /* 1 - Single link LVDS */
|
||||
xres = 1024;
|
||||
pixel_format = 0x88883316;
|
||||
gamma_fix = 0;
|
||||
out8(PIXIS_BASE + PIXIS_BRDCFG0, (tmp_val & 0xf7) | 0x10);
|
||||
|
||||
} else if (!strncmp(monitor_port, "2", 1)) { /* 2 - Double link LVDS */
|
||||
xres = 1280;
|
||||
pixel_format = 0x88883316;
|
||||
gamma_fix = 1;
|
||||
out8(PIXIS_BASE + PIXIS_BRDCFG0, tmp_val & 0xe7);
|
||||
|
||||
} else { /* DVI */
|
||||
xres = 1280;
|
||||
pixel_format = 0x88882317;
|
||||
gamma_fix = 0;
|
||||
out8(PIXIS_BASE + PIXIS_BRDCFG0, tmp_val | 0x08);
|
||||
}
|
||||
|
||||
fsl_diu_init(xres, pixel_format, gamma_fix,
|
||||
(unsigned char *)FSL_Logo_BMP);
|
||||
}
|
||||
|
||||
int mpc8610diu_init_show_bmp(cmd_tbl_t *cmdtp,
|
||||
int flag, int argc, char *argv[])
|
||||
{
|
||||
unsigned int addr;
|
||||
|
||||
if (argc < 2) {
|
||||
printf ("Usage:\n%s\n", cmdtp->usage);
|
||||
return 1;
|
||||
}
|
||||
|
||||
if (!strncmp(argv[1],"init",4)) {
|
||||
mpc8610hpcd_diu_init();
|
||||
} else {
|
||||
addr = simple_strtoul(argv[1], NULL, 16);
|
||||
fsl_diu_clear_screen();
|
||||
fsl_diu_display_bmp((unsigned char *)addr, 0, 0, 0);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
U_BOOT_CMD(
|
||||
diufb, CFG_MAXARGS, 1, mpc8610diu_init_show_bmp,
|
||||
"diufb init | addr - Init or Display BMP file\n",
|
||||
"init\n - initialize DIU\n"
|
||||
"addr\n - display bmp at address 'addr'\n"
|
||||
);
|
||||
#endif /* CONFIG_FSL_DIU_FB */
|
||||
|
|
@ -21,6 +21,7 @@
|
|||
#define CONFIG_NUM_CPUS 1 /* Number of CPUs in the system */
|
||||
#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
|
||||
|
||||
#define CONFIG_FSL_DIU_FB 1 /* FSL DIU */
|
||||
#ifdef RUN_DIAG
|
||||
#define CFG_DIAG_ADDR 0xff800000
|
||||
#endif
|
||||
|
|
@ -38,7 +39,7 @@
|
|||
#define CONFIG_SPD_EEPROM /* Use SPD for DDR */
|
||||
#undef CONFIG_DDR_DLL /* possible DLL fix needed */
|
||||
#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
|
||||
#define CONFIG_DDR_ECC /* only for ECC DDR module */
|
||||
#undef CONFIG_DDR_ECC /* only for ECC DDR module */
|
||||
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
|
||||
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
|
||||
#define CONFIG_NUM_DDR_CONTROLLERS 1
|
||||
|
|
@ -51,13 +52,14 @@
|
|||
*/
|
||||
#define CFG_L2
|
||||
#define L2_INIT 0
|
||||
#define L2_ENABLE (L2CR_L2E)
|
||||
#define L2_ENABLE (L2CR_L2E |0x00100000 )
|
||||
|
||||
#ifndef CONFIG_SYS_CLK_FREQ
|
||||
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
|
||||
#endif
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
|
||||
#define CONFIG_MISC_INIT_R 1
|
||||
|
||||
#undef CFG_DRAM_TEST /* memory test, takes time */
|
||||
#define CFG_MEMTEST_START 0x00200000 /* memtest region */
|
||||
|
|
@ -159,6 +161,7 @@
|
|||
#define PIXIS_RST 0x4 /* PIXIS Reset Control register */
|
||||
#define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch */
|
||||
#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
|
||||
#define PIXIS_BRDCFG0 0x8 /* PIXIS Board Configuration Register0*/
|
||||
#define PIXIS_VCTL 0x10 /* VELA Control Register */
|
||||
#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
|
||||
#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
|
||||
|
|
@ -208,7 +211,7 @@
|
|||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
|
||||
|
||||
#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
|
||||
#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
|
||||
#define CFG_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */
|
||||
|
||||
/* Serial Port */
|
||||
#define CONFIG_CONS_INDEX 1
|
||||
|
|
@ -474,6 +477,9 @@
|
|||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
||||
|
||||
/*DIU Configuration*/
|
||||
#define DIU_CONNECT_TO_DVI /* DIU controller connects to DVI encoder*/
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
|
|
@ -621,7 +627,8 @@
|
|||
"diuregs=md e002c000 1d\0" \
|
||||
"dium=mw e002c01c\0" \
|
||||
"diuerr=md e002c014 1\0" \
|
||||
"othbootargs=debug\0" \
|
||||
"othbootargs=diufb=15M video=fslfb:1280x1024-32@60,monitor=0 debug\0" \
|
||||
"monitor=0-DVI\0" \
|
||||
"pmregs=md e00e1000 2b\0" \
|
||||
"lawregs=md e0000c08 4b\0" \
|
||||
"lbcregs=md e0005000 36\0" \
|
||||
|
|
@ -641,7 +648,9 @@
|
|||
"ramdiskfile=8610hpcd/ramdisk.uboot\0" \
|
||||
"dtbaddr=c00000\0" \
|
||||
"dtbfile=8610hpcd/mpc8610_hpcd.dtb\0" \
|
||||
"bdev=sda3\0"
|
||||
"bdev=sda3\0" \
|
||||
"othbootargs=diufb=15M video=fslfb:1280x1024-32@60,monitor=0\0"\
|
||||
"monitor=0-DVI\0"
|
||||
#endif
|
||||
|
||||
#define CONFIG_NFSBOOTCOMMAND \
|
||||
|
|
|
|||
Loading…
Reference in New Issue