* Add support for HMI1001 board
* Disable "date" and "sntp" commands on TQM866M which has no RTC
This commit is contained in:
wdenk
parent
51152c173d
commit
a87589da74
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@ -2,6 +2,10 @@
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Changes for U-Boot 1.1.3:
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======================================================================
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* Add support for HMI1001 board
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* Disable "date" and "sntp" commands on TQM866M
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* Fix watchdog reset problems on LWMON board
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* Patch by Juergen Selent, 17 May 2005:
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4
Makefile
4
Makefile
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@ -227,6 +227,10 @@ PATI_config: unconfig
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#########################################################################
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## MPC5xxx Systems
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#########################################################################
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hmi1001_config: unconfig
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@./mkconfig hmi1001 ppc mpc5xxx hmi1001
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Lite5200_config \
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Lite5200_LOWBOOT_config \
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Lite5200_LOWBOOT08_config \
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@ -5,7 +5,7 @@
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* Support for the Elmeg VoVPN Gateway Module
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* ------------------------------------------
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* This is a signle bank flashdriver for INTEL 28F320J3, 28F640J3
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* and 28F128J3A flashs working in 8 Bit mode.
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* and 28F128J3A flashs working in 8 Bit mode.
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*
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* Most of this code is taken from existing u-boot source code.
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*
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@ -286,8 +286,8 @@ flash_erase(flash_info_t *info, int s_first, int s_last)
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static int
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write_buff2( volatile FLASH_WORD_SIZE *dst,
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volatile FLASH_WORD_SIZE *src,
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unsigned long cnt )
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volatile FLASH_WORD_SIZE *src,
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unsigned long cnt )
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{
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unsigned long start;
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FLASH_WORD_SIZE status;
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@ -71,8 +71,6 @@
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/* misc */
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#define M88E6060_ID ((M88X_PHY_ID0_VALUE<<16) | M88X_PHY_ID1_VALUE)
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/* ************************************************************************** */
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/* *** TYPEDEFS ************************************************************* */
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@ -82,13 +80,9 @@ typedef struct {
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unsigned short val;
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} m88x_regCfg_t;
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/* ************************************************************************** */
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/* *** PROTOTYPES *********************************************************** */
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extern int m88e6060_initialize( int );
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#endif /* _INC_m88e6060_h_ */
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@ -0,0 +1,46 @@
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#
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# (C) Copyright 2003-2004
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = lib$(BOARD).a
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OBJS := $(BOARD).o
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$(LIB): $(OBJS) $(SOBJS)
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$(AR) crv $@ $(OBJS)
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clean:
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rm -f $(SOBJS) $(OBJS)
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distclean: clean
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
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$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
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-include .depend
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#########################################################################
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@ -0,0 +1,41 @@
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#
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# (C) Copyright 2004
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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#
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# INKA 4X0 board:
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#
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# Valid values for TEXT_BASE are:
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#
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# 0xFFE00000 boot high
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#
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# 0x00100000 boot from RAM (for testing only)
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#
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ifndef TEXT_BASE
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## Standard: boot high
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TEXT_BASE = 0xFFF00000
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## For testing: boot from RAM
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#TEXT_BASE = 0x00100000
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endif
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PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
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@ -0,0 +1,172 @@
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/*
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* (C) Copyright 2003-2004
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2004
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* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
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*
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* (C) Copyright 2004
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* Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <mpc5xxx.h>
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#include <pci.h>
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#ifndef CFG_RAMBOOT
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static void sdram_start (int hi_addr)
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{
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long hi_addr_bit = hi_addr ? 0x01000000 : 0;
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/* unlock mode register */
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*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
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__asm__ volatile ("sync");
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/* precharge all banks */
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*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
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__asm__ volatile ("sync");
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#if SDRAM_DDR
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/* set mode register: extended mode */
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*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
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__asm__ volatile ("sync");
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/* set mode register: reset DLL */
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*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
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__asm__ volatile ("sync");
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#endif
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/* precharge all banks */
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*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
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__asm__ volatile ("sync");
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/* auto refresh */
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*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
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__asm__ volatile ("sync");
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/* set mode register */
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*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
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__asm__ volatile ("sync");
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/* normal operation */
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*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
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__asm__ volatile ("sync");
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}
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#endif
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/*
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* ATTENTION: Although partially referenced initdram does NOT make real use
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* use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
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* is something else than 0x00000000.
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*/
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long int initdram (int board_type)
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{
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ulong dramsize = 0;
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#ifndef CFG_RAMBOOT
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ulong test1, test2;
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/* setup SDRAM chip selects */
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*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */
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*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */
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__asm__ volatile ("sync");
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/* setup config registers */
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*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
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*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
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__asm__ volatile ("sync");
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#if SDRAM_DDR
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/* set tap delay */
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*(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
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__asm__ volatile ("sync");
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#endif
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/* find RAM size using SDRAM CS0 only */
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sdram_start(0);
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test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x20000000);
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sdram_start(1);
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test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x20000000);
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if (test1 > test2) {
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sdram_start(0);
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dramsize = test1;
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} else {
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dramsize = test2;
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}
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/* memory smaller than 1MB is impossible */
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if (dramsize < (1 << 20)) {
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dramsize = 0;
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}
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/* set SDRAM CS0 size according to the amount of RAM found */
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if (dramsize > 0) {
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*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
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__builtin_ffs(dramsize >> 20) - 1;
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} else {
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*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
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}
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*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
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#else /* CFG_RAMBOOT */
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/* retrieve size of memory connected to SDRAM CS0 */
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dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
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if (dramsize >= 0x13) {
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dramsize = (1 << (dramsize - 0x13)) << 20;
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} else {
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dramsize = 0;
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}
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/* retrieve size of memory connected to SDRAM CS1 */
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dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
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if (dramsize2 >= 0x13) {
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dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
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||||
} else {
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dramsize2 = 0;
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||||
}
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||||
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||||
#endif /* CFG_RAMBOOT */
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||||
|
||||
/* return dramsize + dramsize2; */
|
||||
return dramsize;
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||||
}
|
||||
|
||||
int checkboard (void)
|
||||
{
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||||
puts ("Board: HMI1001\n");
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||||
return 0;
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||||
}
|
||||
|
||||
int misc_init_f (void)
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||||
{
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||||
return 0;
|
||||
}
|
||||
|
||||
int board_early_init_r (void)
|
||||
{
|
||||
*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
|
||||
*(vu_long *)MPC5XXX_BOOTCS_START =
|
||||
*(vu_long *)MPC5XXX_CS0_START = START_REG(CFG_FLASH_BASE);
|
||||
*(vu_long *)MPC5XXX_BOOTCS_STOP =
|
||||
*(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CFG_FLASH_BASE, CFG_FLASH_SIZE);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,133 @@
|
|||
/*
|
||||
* (C) Copyright 2003-2004
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(powerpc)
|
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
|
||||
/* Do we need any of these for elf?
|
||||
__DYNAMIC = 0; */
|
||||
SECTIONS
|
||||
{
|
||||
/* Read-only sections, merged into text segment: */
|
||||
. = + SIZEOF_HEADERS;
|
||||
.interp : { *(.interp) }
|
||||
.hash : { *(.hash) }
|
||||
.dynsym : { *(.dynsym) }
|
||||
.dynstr : { *(.dynstr) }
|
||||
.rel.text : { *(.rel.text) }
|
||||
.rela.text : { *(.rela.text) }
|
||||
.rel.data : { *(.rel.data) }
|
||||
.rela.data : { *(.rela.data) }
|
||||
.rel.rodata : { *(.rel.rodata) }
|
||||
.rela.rodata : { *(.rela.rodata) }
|
||||
.rel.got : { *(.rel.got) }
|
||||
.rela.got : { *(.rela.got) }
|
||||
.rel.ctors : { *(.rel.ctors) }
|
||||
.rela.ctors : { *(.rela.ctors) }
|
||||
.rel.dtors : { *(.rel.dtors) }
|
||||
.rela.dtors : { *(.rela.dtors) }
|
||||
.rel.bss : { *(.rel.bss) }
|
||||
.rela.bss : { *(.rela.bss) }
|
||||
.rel.plt : { *(.rel.plt) }
|
||||
.rela.plt : { *(.rela.plt) }
|
||||
.init : { *(.init) }
|
||||
.plt : { *(.plt) }
|
||||
.text :
|
||||
{
|
||||
/* WARNING - the following is hand-optimized to fit within */
|
||||
/* the sector layout of our flash chips! XXX FIXME XXX */
|
||||
|
||||
cpu/mpc5xxx/start.o (.text)
|
||||
cpu/mpc5xxx/traps.o (.text)
|
||||
lib_generic/crc32.o (.text)
|
||||
lib_ppc/cache.o (.text)
|
||||
lib_ppc/time.o (.text)
|
||||
|
||||
. = DEFINED(env_offset) ? env_offset : .;
|
||||
common/environment.o (.ppcenv)
|
||||
|
||||
*(.text)
|
||||
*(.fixup)
|
||||
*(.got1)
|
||||
. = ALIGN(16);
|
||||
*(.rodata)
|
||||
*(.rodata1)
|
||||
*(.rodata.str1.4)
|
||||
}
|
||||
.fini : { *(.fini) } =0
|
||||
.ctors : { *(.ctors) }
|
||||
.dtors : { *(.dtors) }
|
||||
|
||||
/* Read-write section, merged into data segment: */
|
||||
. = (. + 0x0FFF) & 0xFFFFF000;
|
||||
_erotext = .;
|
||||
PROVIDE (erotext = .);
|
||||
.reloc :
|
||||
{
|
||||
*(.got)
|
||||
_GOT2_TABLE_ = .;
|
||||
*(.got2)
|
||||
_FIXUP_TABLE_ = .;
|
||||
*(.fixup)
|
||||
}
|
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
|
||||
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data)
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata2)
|
||||
*(.dynamic)
|
||||
CONSTRUCTORS
|
||||
}
|
||||
_edata = .;
|
||||
PROVIDE (edata = .);
|
||||
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
|
||||
__start___ex_table = .;
|
||||
__ex_table : { *(__ex_table) }
|
||||
__stop___ex_table = .;
|
||||
|
||||
. = ALIGN(4096);
|
||||
__init_begin = .;
|
||||
.text.init : { *(.text.init) }
|
||||
.data.init : { *(.data.init) }
|
||||
. = ALIGN(4096);
|
||||
__init_end = .;
|
||||
|
||||
__bss_start = .;
|
||||
.bss :
|
||||
{
|
||||
*(.sbss) *(.scommon)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(COMMON)
|
||||
}
|
||||
_end = . ;
|
||||
PROVIDE (end = .);
|
||||
}
|
||||
|
|
@ -175,10 +175,9 @@ do_jffs2_fsload(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
|||
int
|
||||
do_jffs2_ls(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
struct part_info* jffs2_part_info(int);
|
||||
int jffs2_1pass_ls(struct part_info *,char *);
|
||||
|
||||
char *filename = "/";
|
||||
struct part_info* jffs2_part_info(int);
|
||||
int jffs2_1pass_ls(struct part_info *,char *);
|
||||
char *filename = "/";
|
||||
int ret;
|
||||
struct part_info *part;
|
||||
|
||||
|
|
@ -235,11 +234,11 @@ do_jffs2_chpart(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
|||
{
|
||||
int tmp_part;
|
||||
char str_part_num[3];
|
||||
struct part_info* jffs2_part_info(int);
|
||||
struct part_info* jffs2_part_info(int);
|
||||
|
||||
if (argc >= 2) {
|
||||
if (argc >= 2) {
|
||||
tmp_part = simple_strtoul(argv[1], NULL, 16);
|
||||
}else{
|
||||
} else {
|
||||
puts ("Need partition number in argument list\n");
|
||||
return 0;
|
||||
|
||||
|
|
|
|||
|
|
@ -869,9 +869,10 @@ int mpc5xxx_fec_initialize(bd_t * bis)
|
|||
fec->eth = (ethernet_regs *)MPC5XXX_FEC;
|
||||
fec->tbdBase = (FEC_TBD *)FEC_BD_BASE;
|
||||
fec->rbdBase = (FEC_RBD *)(FEC_BD_BASE + FEC_TBD_NUM * sizeof(FEC_TBD));
|
||||
#if defined(CONFIG_CANMB) || defined(CONFIG_ICECUBE) || \
|
||||
defined(CONFIG_INKA4X0) || defined(CONFIG_PM520) || \
|
||||
defined(CONFIG_TOP5200) || defined(CONFIG_TQM5200)
|
||||
#if defined(CONFIG_CANMB) || defined(CONFIG_HMI1001) || \
|
||||
defined(CONFIG_ICECUBE) || defined(CONFIG_INKA4X0) || \
|
||||
defined(CONFIG_PM520) || defined(CONFIG_TOP5200) || \
|
||||
defined(CONFIG_TQM5200)
|
||||
# ifndef CONFIG_FEC_10MBIT
|
||||
fec->xcv_type = MII100;
|
||||
# else
|
||||
|
|
|
|||
|
|
@ -136,13 +136,11 @@
|
|||
|
||||
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
|
||||
CFG_CMD_ASKENV | \
|
||||
CFG_CMD_DATE | \
|
||||
CFG_CMD_DHCP | \
|
||||
CFG_CMD_EEPROM | \
|
||||
CFG_CMD_I2C | \
|
||||
CFG_CMD_IDE | \
|
||||
CFG_CMD_NFS | \
|
||||
CFG_CMD_SNTP )
|
||||
CFG_CMD_NFS )
|
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
|
||||
#include <cmd_confdefs.h>
|
||||
|
|
|
|||
|
|
@ -261,7 +261,7 @@
|
|||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CFG_BOOTMAPSZ (8 << 20)
|
||||
#define CFG_BOOTMAPSZ (8 << 20)
|
||||
|
||||
/* hard reset configuration words */
|
||||
#ifdef CONFIG_CLKIN_66MHz
|
||||
|
|
@ -342,13 +342,13 @@
|
|||
|
||||
/* TMCNTSC - time counter status and control */
|
||||
/* clear interrupts XXX jse */
|
||||
//#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR)
|
||||
/*#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR) */
|
||||
#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|\
|
||||
TMCNTSC_TCF|TMCNTSC_TCE)
|
||||
|
||||
/* PISCR - periodic interrupt status and control */
|
||||
/* clear interrupts XXX jse */
|
||||
//#define CFG_PISCR (PISCR_PS)
|
||||
/*#define CFG_PISCR (PISCR_PS) */
|
||||
#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
|
||||
|
||||
/* SCCR - system clock control */
|
||||
|
|
@ -397,7 +397,7 @@
|
|||
#define CFG_OR7_PRELIM 0xffff8104
|
||||
#define CFG_MPTPR 0x2700
|
||||
#define CFG_PSDMR 0x822a2452 /* optimal */
|
||||
//#define CFG_PSDMR 0x822a48a3 /* relaxed */
|
||||
/*#define CFG_PSDMR 0x822a48a3 */ /* relaxed */
|
||||
#define CFG_PSRT 0x1a
|
||||
|
||||
/* "bad" address */
|
||||
|
|
|
|||
|
|
@ -0,0 +1,251 @@
|
|||
/*
|
||||
* (C) Copyright 2003-2005
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
* (easy to change)
|
||||
*/
|
||||
|
||||
#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
|
||||
#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
|
||||
#define CONFIG_HMI1001 1 /* HMI1001 board */
|
||||
|
||||
#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
|
||||
|
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
|
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
||||
|
||||
#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
|
||||
#endif
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_R
|
||||
|
||||
/*
|
||||
* Serial console configuration
|
||||
*/
|
||||
#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
|
||||
#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
|
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
|
||||
|
||||
/*
|
||||
* Supported commands
|
||||
*/
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
|
||||
CFG_CMD_DHCP | \
|
||||
CFG_CMD_NFS | \
|
||||
CFG_CMD_SNTP)
|
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
|
||||
#include <cmd_confdefs.h>
|
||||
|
||||
#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */
|
||||
|
||||
#if (TEXT_BASE == 0xFFF00000) /* Boot low */
|
||||
# define CFG_LOWBOOT 1
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Autobooting
|
||||
*/
|
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
|
||||
|
||||
#define CONFIG_PREBOOT "echo;" \
|
||||
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
|
||||
"echo"
|
||||
|
||||
#undef CONFIG_BOOTARGS
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"netdev=eth0\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=$(serverip):$(rootpath)\0" \
|
||||
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
||||
"addip=setenv bootargs $(bootargs) " \
|
||||
"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
|
||||
":$(hostname):$(netdev):off panic=1\0" \
|
||||
"flash_nfs=run nfsargs addip;" \
|
||||
"bootm $(kernel_addr)\0" \
|
||||
"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
|
||||
"rootpath=/opt/eldk/ppc_82xx\0" \
|
||||
""
|
||||
|
||||
#define CONFIG_BOOTCOMMAND "run net_nfs"
|
||||
|
||||
/*
|
||||
* IPB Bus clocking configuration.
|
||||
*/
|
||||
#undef CFG_IPBSPEED_133 /* define for 133MHz speed */
|
||||
|
||||
/*
|
||||
* Flash configuration
|
||||
*/
|
||||
#define CFG_FLASH_BASE 0xFF800000
|
||||
|
||||
#define CFG_FLASH_SIZE 0x00800000 /* 8 MByte */
|
||||
#define CFG_MAX_FLASH_SECT 67 /* max num of sects on one chip */
|
||||
|
||||
#define CFG_ENV_ADDR (TEXT_BASE+0x40000) /* second sector */
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks
|
||||
(= chip selects) */
|
||||
#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
|
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
|
||||
|
||||
#define CFG_FLASH_CFI_DRIVER
|
||||
#define CFG_FLASH_CFI
|
||||
#define CFG_FLASH_EMPTY_INFO
|
||||
#define CFG_FLASH_CFI_AMD_RESET
|
||||
#define CFG_FLASH_PROTECTION
|
||||
|
||||
/*
|
||||
* Environment settings
|
||||
*/
|
||||
#define CFG_ENV_IS_IN_FLASH 1
|
||||
#define CFG_ENV_SIZE 0x4000
|
||||
#define CFG_ENV_SECT_SIZE 0x20000
|
||||
|
||||
/*
|
||||
* Memory map
|
||||
*/
|
||||
#define CFG_MBAR 0xF0000000
|
||||
#define CFG_SDRAM_BASE 0x00000000
|
||||
#define CFG_DEFAULT_MBAR 0x80000000
|
||||
|
||||
/* Settings for XLB = 132 MHz */
|
||||
#define SDRAM_DDR 1
|
||||
#define SDRAM_MODE 0x018D0000
|
||||
#define SDRAM_EMODE 0x40090000
|
||||
#define SDRAM_CONTROL 0x714f0f00
|
||||
#define SDRAM_CONFIG1 0x73722930
|
||||
#define SDRAM_CONFIG2 0x47770000
|
||||
#define SDRAM_TAPDELAY 0x10000000
|
||||
|
||||
/* Use ON-Chip SRAM until RAM will be available */
|
||||
#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
|
||||
#ifdef CONFIG_POST
|
||||
/* preserve space for the post_word at end of on-chip SRAM */
|
||||
#define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
|
||||
#else
|
||||
#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE
|
||||
#endif
|
||||
|
||||
|
||||
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
|
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
|
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
|
||||
|
||||
#define CFG_MONITOR_BASE TEXT_BASE
|
||||
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
|
||||
# define CFG_RAMBOOT 1
|
||||
#endif
|
||||
|
||||
#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
|
||||
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
|
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
|
||||
/*
|
||||
* Ethernet configuration
|
||||
*/
|
||||
#define CONFIG_MPC5xxx_FEC 1
|
||||
#define CONFIG_PHY_ADDR 0x00
|
||||
|
||||
/*
|
||||
* GPIO configuration
|
||||
*/
|
||||
#define CFG_GPS_PORT_CONFIG 0x01051004
|
||||
|
||||
/*
|
||||
* RTC configuration
|
||||
*/
|
||||
#define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CFG_LONGHELP /* undef to save memory */
|
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CFG_MAXARGS 16 /* max number of command args */
|
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
/* Enable an alternate, more extensive memory test */
|
||||
#define CFG_ALT_MEMTEST
|
||||
|
||||
#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
|
||||
#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
|
||||
|
||||
#define CFG_LOAD_ADDR 0x100000 /* default load address */
|
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
|
||||
|
||||
/*
|
||||
* Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
|
||||
* which is normally part of the default commands (CFV_CMD_DFL)
|
||||
*/
|
||||
#define CONFIG_LOOPW
|
||||
|
||||
/*
|
||||
* Various low-level settings
|
||||
*/
|
||||
#if defined(CONFIG_MPC5200)
|
||||
#define CFG_HID0_INIT HID0_ICE | HID0_ICFI
|
||||
#define CFG_HID0_FINAL HID0_ICE
|
||||
#else
|
||||
#define CFG_HID0_INIT 0
|
||||
#define CFG_HID0_FINAL 0
|
||||
#endif
|
||||
|
||||
#define CFG_BOOTCS_START CFG_FLASH_BASE
|
||||
#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
|
||||
#define CFG_BOOTCS_CFG 0x0004FB00
|
||||
#define CFG_CS0_START CFG_FLASH_BASE
|
||||
#define CFG_CS0_SIZE CFG_FLASH_SIZE
|
||||
|
||||
/* 8Mbit SRAM @0x80100000 */
|
||||
#define CFG_CS1_START 0x80100000
|
||||
#define CFG_CS1_SIZE 0x00100000
|
||||
#define CFG_CS1_CFG 0x19B00
|
||||
|
||||
/* FRAM 32Kbyte @0x80700000 */
|
||||
#define CFG_CS2_START 0x80700000
|
||||
#define CFG_CS2_SIZE 0x00008000
|
||||
#define CFG_CS2_CFG 0x19800
|
||||
|
||||
/* Display H1, Status Inputs, EPLD @0x80600000 */
|
||||
#define CFG_CS3_START 0x80600000
|
||||
#define CFG_CS3_SIZE 0x00000210
|
||||
#define CFG_CS3_CFG 0x9800
|
||||
|
||||
#define CFG_CS_BURST 0x00000000
|
||||
#define CFG_CS_DEADCYCLE 0x33333333
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in New Issue