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Merge with /home/wd/git/u-boot/custodian/u-boot-mpc86xx

This commit is contained in:
Wolfgang Denk 2007-04-18 17:20:22 +02:00
parent 1d10b9e99d 3d98b85800
commit a8227b66fa
6 changed files with 198 additions and 126 deletions
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161
board/mpc8641hpcn/pixis.c → board/freescale/common/pixis.c
View File

@ -23,14 +23,25 @@
*/
#include <common.h>
#include <watchdog.h>
#include <command.h>
#include <watchdog.h>
#include <asm/cache.h>
#include <mpc86xx.h>
#include "pixis.h"
static ulong strfractoint(uchar *strptr);
/*
* Simple board reset.
*/
void pixis_reset(void)
{
out8(PIXIS_BASE + PIXIS_RST, 0);
}
/*
* Per table 27, page 58 of MPC8641HPCN spec.
*/
@ -235,7 +246,8 @@ void set_px_go_with_watchdog(void)
}
int disable_watchdog(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
int pixis_disable_watchdog_cmd(cmd_tbl_t *cmdtp,
int flag, int argc, char *argv[])
{
u8 tmp;
@ -252,7 +264,7 @@ int disable_watchdog(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
U_BOOT_CMD(
diswd, 1, 0, disable_watchdog,
diswd, 1, 0, pixis_disable_watchdog_cmd,
"diswd - Disable watchdog timer \n",
NULL);
@ -263,7 +275,7 @@ U_BOOT_CMD(
* input: strptr i.e. argv[2]
*/
ulong strfractoint(uchar *strptr)
static ulong strfractoint(uchar *strptr)
{
int i, j, retval;
int mulconst;
@ -319,3 +331,142 @@ ulong strfractoint(uchar *strptr)
return retval;
}
int
pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
ulong val;
ulong corepll;
/*
* No args is a simple reset request.
*/
if (argc <= 1) {
pixis_reset();
/* not reached */
}
if (strcmp(argv[1], "cf") == 0) {
/*
* Reset with frequency changed:
* cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
*/
if (argc < 5) {
puts(cmdtp->usage);
return 1;
}
read_from_px_regs(0);
val = set_px_sysclk(simple_strtoul(argv[2], NULL, 10));
corepll = strfractoint(argv[3]);
val = val + set_px_corepll(corepll);
val = val + set_px_mpxpll(simple_strtoul(argv[4], NULL, 10));
if (val == 3) {
puts("Setting registers VCFGEN0 and VCTL\n");
read_from_px_regs(1);
puts("Resetting board with values from ");
puts("VSPEED0, VSPEED1, VCLKH, and VCLKL \n");
set_px_go();
} else {
puts(cmdtp->usage);
return 1;
}
while (1) ; /* Not reached */
} else if (strcmp(argv[1], "altbank") == 0) {
/*
* Reset using alternate flash bank:
*/
if (argv[2] == 0) {
/*
* Reset from alternate bank without changing
* frequency and without watchdog timer enabled.
* altbank
*/
read_from_px_regs(0);
read_from_px_regs_altbank(0);
if (argc > 2) {
puts(cmdtp->usage);
return 1;
}
puts("Setting registers VCFGNE1, VBOOT, and VCTL\n");
set_altbank();
read_from_px_regs_altbank(1);
puts("Resetting board to boot from the other bank.\n");
set_px_go();
} else if (strcmp(argv[2], "cf") == 0) {
/*
* Reset with frequency changed
* altbank cf <SYSCLK freq> <COREPLL ratio>
* <MPXPLL ratio>
*/
read_from_px_regs(0);
read_from_px_regs_altbank(0);
val = set_px_sysclk(simple_strtoul(argv[3], NULL, 10));
corepll = strfractoint(argv[4]);
val = val + set_px_corepll(corepll);
val = val + set_px_mpxpll(simple_strtoul(argv[5],
NULL, 10));
if (val == 3) {
puts("Setting registers VCFGEN0, VCFGEN1, VBOOT, and VCTL\n");
set_altbank();
read_from_px_regs(1);
read_from_px_regs_altbank(1);
puts("Enabling watchdog timer on the FPGA\n");
puts("Resetting board with values from ");
puts("VSPEED0, VSPEED1, VCLKH and VCLKL ");
puts("to boot from the other bank.\n");
set_px_go_with_watchdog();
} else {
puts(cmdtp->usage);
return 1;
}
while (1) ; /* Not reached */
} else if (strcmp(argv[2], "wd") == 0) {
/*
* Reset from alternate bank without changing
* frequencies but with watchdog timer enabled:
* altbank wd
*/
read_from_px_regs(0);
read_from_px_regs_altbank(0);
puts("Setting registers VCFGEN1, VBOOT, and VCTL\n");
set_altbank();
read_from_px_regs_altbank(1);
puts("Enabling watchdog timer on the FPGA\n");
puts("Resetting board to boot from the other bank.\n");
set_px_go_with_watchdog();
while (1) ; /* Not reached */
} else {
puts(cmdtp->usage);
return 1;
}
} else {
puts(cmdtp->usage);
return 1;
}
return 0;
}
U_BOOT_CMD(
pixis_reset, CFG_MAXARGS, 1, pixis_reset_cmd,
"pixis_reset - Reset the board using the FPGA sequencer\n",
" pixis_reset\n"
" pixis_reset [altbank]\n"
" pixis_reset altbank wd\n"
" pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n"
" pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n"
);

4
board/mpc8641hpcn/pixis.h → board/freescale/common/pixis.h
View File

@ -20,6 +20,7 @@
* MA 02111-1307 USA
*/
extern void pixis_reset(void);
extern int set_px_sysclk(ulong sysclk);
extern int set_px_mpxpll(ulong mpxpll);
extern int set_px_corepll(ulong corepll);
@ -28,6 +29,3 @@ extern void read_from_px_regs_altbank(int set);
extern void set_altbank(void);
extern void set_px_go(void);
extern void set_px_go_with_watchdog(void);
extern int disable_watchdog(cmd_tbl_t *cmdtp,
int flag, int argc, char *argv[]);
extern ulong strfractoint(uchar *strptr);

4
board/mpc8641hpcn/Makefile
View File

@ -25,7 +25,9 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS := $(BOARD).o pixis.o sys_eeprom.o
COBJS := $(BOARD).o sys_eeprom.o \
../freescale/common/pixis.o
SOBJS := init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)

113
board/mpc8641hpcn/mpc8641hpcn.c
View File

@ -1,9 +1,5 @@
/*
* Copyright 2004 Freescale Semiconductor.
* Jeff Brown
* Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
*
* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
* Copyright 2006, 2007 Freescale Semiconductor.
*
* See file CREDITS for list of people who contributed to this
* project.
@ -25,18 +21,18 @@
*/
#include <common.h>
#include <command.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/immap_86xx.h>
#include <spd.h>
#include <asm/io.h>
#if defined(CONFIG_OF_FLAT_TREE)
#include <ft_build.h>
extern void ft_cpu_setup(void *blob, bd_t *bd);
#endif
#include "pixis.h"
#include "../freescale/common/pixis.h"
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
extern void ddr_enable_ecc(unsigned int dram_size);
@ -258,109 +254,6 @@ ft_board_setup(void *blob, bd_t *bd)
#endif
void
mpc8641_reset_board(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
char cmd;
ulong val;
ulong corepll;
/*
* No args is a simple reset request.
*/
if (argc <= 1) {
out8(PIXIS_BASE + PIXIS_RST, 0);
/* not reached */
}
cmd = argv[1][1];
switch (cmd) {
case 'f': /* reset with frequency changed */
if (argc < 5)
goto my_usage;
read_from_px_regs(0);
val = set_px_sysclk(simple_strtoul(argv[2], NULL, 10));
corepll = strfractoint(argv[3]);
val = val + set_px_corepll(corepll);
val = val + set_px_mpxpll(simple_strtoul(argv[4], NULL, 10));
if (val == 3) {
puts("Setting registers VCFGEN0 and VCTL\n");
read_from_px_regs(1);
puts("Resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL ....\n");
set_px_go();
} else
goto my_usage;
while (1) ; /* Not reached */
case 'l':
if (argv[2][1] == 'f') {
read_from_px_regs(0);
read_from_px_regs_altbank(0);
/* reset with frequency changed */
val = set_px_sysclk(simple_strtoul(argv[3], NULL, 10));
corepll = strfractoint(argv[4]);
val = val + set_px_corepll(corepll);
val = val + set_px_mpxpll(simple_strtoul(argv[5],
NULL, 10));
if (val == 3) {
puts("Setting registers VCFGEN0, VCFGEN1, VBOOT, and VCTL\n");
set_altbank();
read_from_px_regs(1);
read_from_px_regs_altbank(1);
puts("Enabling watchdog timer on the FPGA and resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL to boot from the other bank ....\n");
set_px_go_with_watchdog();
} else
goto my_usage;
while (1) ; /* Not reached */
} else if (argv[2][1] == 'd') {
/*
* Reset from alternate bank without changing
* frequencies but with watchdog timer enabled.
*/
read_from_px_regs(0);
read_from_px_regs_altbank(0);
puts("Setting registers VCFGEN1, VBOOT, and VCTL\n");
set_altbank();
read_from_px_regs_altbank(1);
puts("Enabling watchdog timer on the FPGA and resetting board to boot from the other bank....\n");
set_px_go_with_watchdog();
while (1) ; /* Not reached */
} else {
/*
* Reset from next bank without changing
* frequency and without watchdog timer enabled.
*/
read_from_px_regs(0);
read_from_px_regs_altbank(0);
if (argc > 2)
goto my_usage;
puts("Setting registers VCFGNE1, VBOOT, and VCTL\n");
set_altbank();
read_from_px_regs_altbank(1);
puts("Resetting board to boot from the other bank....\n");
set_px_go();
}
default:
goto my_usage;
}
my_usage:
puts("\nUsage: reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n");
puts(" reset altbank [cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>]\n");
puts(" reset altbank [wd]\n");
puts("For example: reset cf 40 2.5 10\n");
puts("See MPC8641HPCN Design Workbook for valid values of command line parameters.\n");
}
/*
* get_board_sys_clk
* Reads the FPGA on board for CONFIG_SYS_CLK_FREQ

8
cpu/mpc86xx/cpu.c
View File

@ -32,12 +32,6 @@
#include <ft_build.h>
#endif
#ifdef CONFIG_MPC8641HPCN
extern void mpc8641_reset_board(cmd_tbl_t *cmdtp, int flag,
int argc, char *argv[]);
#endif
int
checkcpu(void)
{
@ -185,7 +179,7 @@ do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
#else /* CONFIG_MPC8641HPCN */
mpc8641_reset_board(cmdtp, flag, argc, argv);
out8(PIXIS_BASE + PIXIS_RST, 0);
#endif /* !CONFIG_MPC8641HPCN */

34
doc/README.mpc8641hpcn
View File

@ -121,3 +121,37 @@ To Flash U-boot into the alternative bank (0xFF800000 - 0xFFBFFFFF):
0xe300_0000 0xe3ff_ffff PCI2/PEX2 IO 16M
0xfe00_0000 0xfeff_ffff Flash(alternate)16M
0xff00_0000 0xffff_ffff Flash(boot bank)16M
5. pixis_reset command
--------------------
A new command, "pixis_reset", is introduced to reset mpc8641hpcn board
using the FPGA sequencer. When the board restarts, it has the option
of using either the current or alternate flash bank as the boot
image, with or without the watchdog timer enabled, and finally with
or without frequency changes.
Usage is;
pixis_reset
pixis_reset altbank
pixis_reset altbank wd
pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
Examples;
/* reset to current bank, like "reset" command */
pixis_reset
/* reset board but use the to alternate flash bank */
pixis_reset altbank
/* reset board, use alternate flash bank with watchdog timer enabled*/
pixis_reset altbank wd
/* reset board to alternate bank with frequency changed.
* 40 is SYSCLK, 2.5 is COREPLL ratio, 10 is MPXPLL ratio
*/
pixis-reset altbank cf 40 2.5 10
Valid clock choices are in the 8641 Reference Manuals.