drivers/usb/host/ohci-hcd: rename readl/writel to ohci_readl/ohci_writel
This avoids a build warning that you see if anyone in the header chain has included io.h (which is coming shortly). The previous code redefined readl/writel; this patch renames it to be specific to ohci. The defines are also moved from ohci-hcd.c to ohci.h. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
This commit is contained in:
Becky Bruce
Remy Bohmer
parent
944a4894c0
commit
a5496a180b
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@ -83,17 +83,6 @@
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#define OHCI_CONTROL_INIT \
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(OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE
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/*
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* e.g. PCI controllers need this
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*/
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#ifdef CONFIG_SYS_OHCI_SWAP_REG_ACCESS
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# define readl(a) __swap_32(*((volatile u32 *)(a)))
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# define writel(a, b) (*((volatile u32 *)(b)) = __swap_32((volatile u32)a))
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#else
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# define readl(a) (*((volatile u32 *)(a)))
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# define writel(a, b) (*((volatile u32 *)(b)) = ((volatile u32)a))
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#endif /* CONFIG_SYS_OHCI_SWAP_REG_ACCESS */
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#define min_t(type, x, y) \
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({ type __x = (x); type __y = (y); __x < __y ? __x: __y; })
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@ -147,13 +136,13 @@ struct ohci_device ohci_dev;
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struct usb_device *devgone;
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static inline u32 roothub_a(struct ohci *hc)
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{ return readl(&hc->regs->roothub.a); }
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{ return ohci_readl(&hc->regs->roothub.a); }
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static inline u32 roothub_b(struct ohci *hc)
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{ return readl(&hc->regs->roothub.b); }
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{ return ohci_readl(&hc->regs->roothub.b); }
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static inline u32 roothub_status(struct ohci *hc)
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{ return readl(&hc->regs->roothub.status); }
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{ return ohci_readl(&hc->regs->roothub.status); }
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static inline u32 roothub_portstatus(struct ohci *hc, int i)
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{ return readl(&hc->regs->roothub.portstatus[i]); }
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{ return ohci_readl(&hc->regs->roothub.portstatus[i]); }
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/* forward declaration */
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static int hc_interrupt(void);
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@ -302,11 +291,11 @@ static void ohci_dump_status(ohci_t *controller)
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struct ohci_regs *regs = controller->regs;
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__u32 temp;
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temp = readl(®s->revision) & 0xff;
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temp = ohci_readl(®s->revision) & 0xff;
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if (temp != 0x10)
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dbg("spec %d.%d", (temp >> 4), (temp & 0x0f));
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temp = readl(®s->control);
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temp = ohci_readl(®s->control);
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dbg("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp,
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(temp & OHCI_CTRL_RWE) ? " RWE" : "",
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(temp & OHCI_CTRL_RWC) ? " RWC" : "",
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@ -319,7 +308,7 @@ static void ohci_dump_status(ohci_t *controller)
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temp & OHCI_CTRL_CBSR
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);
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temp = readl(®s->cmdstatus);
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temp = ohci_readl(®s->cmdstatus);
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dbg("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp,
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(temp & OHCI_SOC) >> 16,
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(temp & OHCI_OCR) ? " OCR" : "",
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@ -328,18 +317,20 @@ static void ohci_dump_status(ohci_t *controller)
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(temp & OHCI_HCR) ? " HCR" : ""
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);
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ohci_dump_intr_mask("intrstatus", readl(®s->intrstatus));
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ohci_dump_intr_mask("intrenable", readl(®s->intrenable));
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ohci_dump_intr_mask("intrstatus", ohci_readl(®s->intrstatus));
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ohci_dump_intr_mask("intrenable", ohci_readl(®s->intrenable));
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maybe_print_eds("ed_periodcurrent", readl(®s->ed_periodcurrent));
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maybe_print_eds("ed_periodcurrent",
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ohci_readl(®s->ed_periodcurrent));
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maybe_print_eds("ed_controlhead", readl(®s->ed_controlhead));
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maybe_print_eds("ed_controlcurrent", readl(®s->ed_controlcurrent));
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maybe_print_eds("ed_controlhead", ohci_readl(®s->ed_controlhead));
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maybe_print_eds("ed_controlcurrent",
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ohci_readl(®s->ed_controlcurrent));
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maybe_print_eds("ed_bulkhead", readl(®s->ed_bulkhead));
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maybe_print_eds("ed_bulkcurrent", readl(®s->ed_bulkcurrent));
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maybe_print_eds("ed_bulkhead", ohci_readl(®s->ed_bulkhead));
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maybe_print_eds("ed_bulkcurrent", ohci_readl(®s->ed_bulkcurrent));
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maybe_print_eds("donehead", readl(®s->donehead));
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maybe_print_eds("donehead", ohci_readl(®s->donehead));
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}
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static void ohci_dump_roothub(ohci_t *controller, int verbose)
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@ -518,11 +509,11 @@ static inline int sohci_return_job(struct ohci *hc, urb_priv_t *urb)
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/* implicitly requeued */
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if (urb->dev->irq_handle &&
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(urb->dev->irq_act_len = urb->actual_length)) {
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writel(OHCI_INTR_WDH, ®s->intrenable);
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readl(®s->intrenable); /* PCI posting flush */
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ohci_writel(OHCI_INTR_WDH, ®s->intrenable);
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ohci_readl(®s->intrenable); /* PCI posting flush */
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urb->dev->irq_handle(urb->dev);
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writel(OHCI_INTR_WDH, ®s->intrdisable);
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readl(®s->intrdisable); /* PCI posting flush */
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ohci_writel(OHCI_INTR_WDH, ®s->intrdisable);
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ohci_readl(®s->intrdisable); /* PCI posting flush */
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}
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urb->actual_length = 0;
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td_submit_job(
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@ -631,7 +622,7 @@ static int ep_link(ohci_t *ohci, ed_t *edi)
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case PIPE_CONTROL:
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ed->hwNextED = 0;
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if (ohci->ed_controltail == NULL)
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writel(ed, &ohci->regs->ed_controlhead);
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ohci_writel(ed, &ohci->regs->ed_controlhead);
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else
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ohci->ed_controltail->hwNextED =
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m32_swap((unsigned long)ed);
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@ -640,7 +631,7 @@ static int ep_link(ohci_t *ohci, ed_t *edi)
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if (!ohci->ed_controltail && !ohci->ed_rm_list[0] &&
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!ohci->ed_rm_list[1] && !ohci->sleeping) {
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ohci->hc_control |= OHCI_CTRL_CLE;
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writel(ohci->hc_control, &ohci->regs->control);
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ohci_writel(ohci->hc_control, &ohci->regs->control);
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}
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ohci->ed_controltail = edi;
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break;
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@ -648,7 +639,7 @@ static int ep_link(ohci_t *ohci, ed_t *edi)
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case PIPE_BULK:
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ed->hwNextED = 0;
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if (ohci->ed_bulktail == NULL)
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writel(ed, &ohci->regs->ed_bulkhead);
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ohci_writel(ed, &ohci->regs->ed_bulkhead);
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else
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ohci->ed_bulktail->hwNextED =
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m32_swap((unsigned long)ed);
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@ -657,7 +648,7 @@ static int ep_link(ohci_t *ohci, ed_t *edi)
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if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] &&
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!ohci->ed_rm_list[1] && !ohci->sleeping) {
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ohci->hc_control |= OHCI_CTRL_BLE;
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writel(ohci->hc_control, &ohci->regs->control);
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ohci_writel(ohci->hc_control, &ohci->regs->control);
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}
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ohci->ed_bulktail = edi;
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break;
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@ -725,9 +716,10 @@ static int ep_unlink(ohci_t *ohci, ed_t *edi)
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if (ed->ed_prev == NULL) {
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if (!ed->hwNextED) {
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ohci->hc_control &= ~OHCI_CTRL_CLE;
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writel(ohci->hc_control, &ohci->regs->control);
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ohci_writel(ohci->hc_control,
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&ohci->regs->control);
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}
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writel(m32_swap(*((__u32 *)&ed->hwNextED)),
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ohci_writel(m32_swap(*((__u32 *)&ed->hwNextED)),
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&ohci->regs->ed_controlhead);
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} else {
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ed->ed_prev->hwNextED = ed->hwNextED;
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@ -744,9 +736,10 @@ static int ep_unlink(ohci_t *ohci, ed_t *edi)
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if (ed->ed_prev == NULL) {
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if (!ed->hwNextED) {
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ohci->hc_control &= ~OHCI_CTRL_BLE;
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writel(ohci->hc_control, &ohci->regs->control);
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ohci_writel(ohci->hc_control,
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&ohci->regs->control);
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}
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writel(m32_swap(*((__u32 *)&ed->hwNextED)),
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ohci_writel(m32_swap(*((__u32 *)&ed->hwNextED)),
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&ohci->regs->ed_bulkhead);
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} else {
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ed->ed_prev->hwNextED = ed->hwNextED;
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@ -923,7 +916,7 @@ static void td_submit_job(struct usb_device *dev, unsigned long pipe,
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if (!ohci->sleeping) {
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/* start bulk list */
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writel(OHCI_BLF, &ohci->regs->cmdstatus);
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ohci_writel(OHCI_BLF, &ohci->regs->cmdstatus);
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}
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break;
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@ -949,7 +942,7 @@ static void td_submit_job(struct usb_device *dev, unsigned long pipe,
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if (!ohci->sleeping) {
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/* start Control list */
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writel(OHCI_CLF, &ohci->regs->cmdstatus);
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ohci_writel(OHCI_CLF, &ohci->regs->cmdstatus);
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}
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break;
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@ -1224,13 +1217,13 @@ static unsigned char root_hub_str_index1[] =
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#define OK(x) len = (x); break
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#ifdef DEBUG
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#define WR_RH_STAT(x) {info("WR:status %#8x", (x)); writel((x), \
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#define WR_RH_STAT(x) {info("WR:status %#8x", (x)); ohci_writel((x), \
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&gohci.regs->roothub.status); }
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#define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, \
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(x)); writel((x), &gohci.regs->roothub.portstatus[wIndex-1]); }
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(x)); ohci_writel((x), &gohci.regs->roothub.portstatus[wIndex-1]); }
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#else
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#define WR_RH_STAT(x) writel((x), &gohci.regs->roothub.status)
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#define WR_RH_PORTSTAT(x) writel((x), \
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#define WR_RH_STAT(x) ohci_writel((x), &gohci.regs->roothub.status)
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#define WR_RH_PORTSTAT(x) ohci_writel((x), \
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&gohci.regs->roothub.portstatus[wIndex-1])
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#endif
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#define RD_RH_STAT roothub_status(&gohci)
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@ -1661,10 +1654,10 @@ static int hc_reset(ohci_t *ohci)
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int timeout = 1000;
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pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &base);
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writel(readl(base + EHCI_USBCMD_OFF) | EHCI_USBCMD_HCRESET,
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base + EHCI_USBCMD_OFF);
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base += EHCI_USBCMD_OFF;
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ohci_writel(ohci_readl(base) | EHCI_USBCMD_HCRESET, base);
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while (readl(base + EHCI_USBCMD_OFF) & EHCI_USBCMD_HCRESET) {
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while (ohci_readl(base) & EHCI_USBCMD_HCRESET) {
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if (timeout-- <= 0) {
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printf("USB RootHub reset timed out!");
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break;
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@ -1674,11 +1667,11 @@ static int hc_reset(ohci_t *ohci)
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} else
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printf("No EHCI func at %d index!\n", CONFIG_PCI_EHCI_DEVNO);
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#endif
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if (readl(&ohci->regs->control) & OHCI_CTRL_IR) {
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/* SMM owns the HC */
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writel(OHCI_OCR, &ohci->regs->cmdstatus);/* request ownership */
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if (ohci_readl(&ohci->regs->control) & OHCI_CTRL_IR) {
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/* SMM owns the HC, request ownership */
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ohci_writel(OHCI_OCR, &ohci->regs->cmdstatus);
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info("USB HC TakeOver from SMM");
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while (readl(&ohci->regs->control) & OHCI_CTRL_IR) {
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while (ohci_readl(&ohci->regs->control) & OHCI_CTRL_IR) {
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wait_ms(10);
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if (--smm_timeout == 0) {
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err("USB HC TakeOver failed!");
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@ -1688,19 +1681,19 @@ static int hc_reset(ohci_t *ohci)
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}
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/* Disable HC interrupts */
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writel(OHCI_INTR_MIE, &ohci->regs->intrdisable);
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ohci_writel(OHCI_INTR_MIE, &ohci->regs->intrdisable);
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dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;\n",
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ohci->slot_name,
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readl(&ohci->regs->control));
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ohci_readl(&ohci->regs->control));
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/* Reset USB (needed by some controllers) */
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ohci->hc_control = 0;
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writel(ohci->hc_control, &ohci->regs->control);
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ohci_writel(ohci->hc_control, &ohci->regs->control);
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/* HC Reset requires max 10 us delay */
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writel(OHCI_HCR, &ohci->regs->cmdstatus);
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while ((readl(&ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
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ohci_writel(OHCI_HCR, &ohci->regs->cmdstatus);
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while ((ohci_readl(&ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
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if (--timeout == 0) {
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err("USB HC reset timed out!");
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return -1;
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@ -1726,39 +1719,40 @@ static int hc_start(ohci_t *ohci)
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/* Tell the controller where the control and bulk lists are
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* The lists are empty now. */
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writel(0, &ohci->regs->ed_controlhead);
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writel(0, &ohci->regs->ed_bulkhead);
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ohci_writel(0, &ohci->regs->ed_controlhead);
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ohci_writel(0, &ohci->regs->ed_bulkhead);
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writel((__u32)ohci->hcca, &ohci->regs->hcca); /* a reset clears this */
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ohci_writel((__u32)ohci->hcca,
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&ohci->regs->hcca); /* reset clears this */
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fminterval = 0x2edf;
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writel((fminterval * 9) / 10, &ohci->regs->periodicstart);
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ohci_writel((fminterval * 9) / 10, &ohci->regs->periodicstart);
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fminterval |= ((((fminterval - 210) * 6) / 7) << 16);
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writel(fminterval, &ohci->regs->fminterval);
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writel(0x628, &ohci->regs->lsthresh);
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ohci_writel(fminterval, &ohci->regs->fminterval);
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ohci_writel(0x628, &ohci->regs->lsthresh);
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/* start controller operations */
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ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER;
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ohci->disabled = 0;
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writel(ohci->hc_control, &ohci->regs->control);
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ohci_writel(ohci->hc_control, &ohci->regs->control);
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/* disable all interrupts */
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mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD |
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OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC |
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OHCI_INTR_OC | OHCI_INTR_MIE);
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writel(mask, &ohci->regs->intrdisable);
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ohci_writel(mask, &ohci->regs->intrdisable);
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/* clear all interrupts */
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mask &= ~OHCI_INTR_MIE;
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writel(mask, &ohci->regs->intrstatus);
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ohci_writel(mask, &ohci->regs->intrstatus);
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/* Choose the interrupts we care about now - but w/o MIE */
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mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO;
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writel(mask, &ohci->regs->intrenable);
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ohci_writel(mask, &ohci->regs->intrenable);
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#ifdef OHCI_USE_NPS
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/* required for AMD-756 and some Mac platforms */
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writel((roothub_a(ohci) | RH_A_NPS) & ~RH_A_PSM,
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ohci_writel((roothub_a(ohci) | RH_A_NPS) & ~RH_A_PSM,
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&ohci->regs->roothub.a);
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writel(RH_HS_LPSC, &ohci->regs->roothub.status);
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ohci_writel(RH_HS_LPSC, &ohci->regs->roothub.status);
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#endif /* OHCI_USE_NPS */
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#define mdelay(n) ({unsigned long msec = (n); while (msec--) udelay(1000); })
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@ -1792,13 +1786,13 @@ static int hc_interrupt(void)
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!(m32_swap(ohci->hcca->done_head) & 0x01)) {
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ints = OHCI_INTR_WDH;
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} else {
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ints = readl(®s->intrstatus);
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ints = ohci_readl(®s->intrstatus);
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if (ints == ~(u32)0) {
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ohci->disabled++;
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err("%s device removed!", ohci->slot_name);
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return -1;
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} else {
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ints &= readl(®s->intrenable);
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ints &= ohci_readl(®s->intrenable);
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if (ints == 0) {
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dbg("hc_interrupt: returning..\n");
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return 0xff;
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@ -1833,16 +1827,16 @@ static int hc_interrupt(void)
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if (ints & OHCI_INTR_WDH) {
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wait_ms(1);
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writel(OHCI_INTR_WDH, ®s->intrdisable);
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(void)readl(®s->intrdisable); /* flush */
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ohci_writel(OHCI_INTR_WDH, ®s->intrdisable);
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(void)ohci_readl(®s->intrdisable); /* flush */
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stat = dl_done_list(&gohci);
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writel(OHCI_INTR_WDH, ®s->intrenable);
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(void)readl(®s->intrdisable); /* flush */
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ohci_writel(OHCI_INTR_WDH, ®s->intrenable);
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(void)ohci_readl(®s->intrdisable); /* flush */
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}
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if (ints & OHCI_INTR_SO) {
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dbg("USB Schedule overrun\n");
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writel(OHCI_INTR_SO, ®s->intrenable);
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ohci_writel(OHCI_INTR_SO, ®s->intrenable);
|
||||
stat = -1;
|
||||
}
|
||||
|
||||
|
|
@ -1850,13 +1844,13 @@ static int hc_interrupt(void)
|
|||
if (ints & OHCI_INTR_SF) {
|
||||
unsigned int frame = m16_swap(ohci->hcca->frame_no) & 1;
|
||||
wait_ms(1);
|
||||
writel(OHCI_INTR_SF, ®s->intrdisable);
|
||||
ohci_writel(OHCI_INTR_SF, ®s->intrdisable);
|
||||
if (ohci->ed_rm_list[frame] != NULL)
|
||||
writel(OHCI_INTR_SF, ®s->intrenable);
|
||||
ohci_writel(OHCI_INTR_SF, ®s->intrenable);
|
||||
stat = 0xff;
|
||||
}
|
||||
|
||||
writel(ints, ®s->intrstatus);
|
||||
ohci_writel(ints, ®s->intrstatus);
|
||||
return stat;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -7,6 +7,17 @@
|
|||
* usb-ohci.h
|
||||
*/
|
||||
|
||||
/*
|
||||
* e.g. PCI controllers need this
|
||||
*/
|
||||
#ifdef CONFIG_SYS_OHCI_SWAP_REG_ACCESS
|
||||
# define ohci_readl(a) __swap_32(*((volatile u32 *)(a)))
|
||||
# define ohci_writel(a, b) (*((volatile u32 *)(b)) = __swap_32((volatile u32)a))
|
||||
#else
|
||||
# define ohci_readl(a) (*((volatile u32 *)(a)))
|
||||
# define ohci_writel(a, b) (*((volatile u32 *)(b)) = ((volatile u32)a))
|
||||
#endif /* CONFIG_SYS_OHCI_SWAP_REG_ACCESS */
|
||||
|
||||
/* functions for doing board or CPU specific setup/cleanup */
|
||||
extern int usb_board_init(void);
|
||||
extern int usb_board_stop(void);
|
||||
|
|
@ -196,8 +207,8 @@ struct ohci_hcca {
|
|||
|
||||
/*
|
||||
* This is the structure of the OHCI controller's memory mapped I/O
|
||||
* region. This is Memory Mapped I/O. You must use the readl() and
|
||||
* writel() macros defined in asm/io.h to access these!!
|
||||
* region. This is Memory Mapped I/O. You must use the ohci_readl() and
|
||||
* ohci_writel() macros defined in this file to access these!!
|
||||
*/
|
||||
struct ohci_regs {
|
||||
/* control and status registers */
|
||||
|
|
|
|||
Loading…
Reference in New Issue