sciphone_g2: Added support for Sciphone G2

Added support for Sciphone G2 mobile phone based on MT6235.

Signed-off-by: Marcin Mielczarczyk <marcin.mielczarczyk@gmail.com>
master
Marcin Mielczarczyk 12 years ago committed by Marcin Mielczarczyk
parent efb063390d
commit a4361519f6
  1. 5
      Makefile
  2. 45
      arch/arm/cpu/arm926ejs/mtk/Makefile
  3. 33
      arch/arm/cpu/arm926ejs/mtk/reset.c
  4. 105
      arch/arm/cpu/arm926ejs/mtk/timer.c
  5. 42
      arch/arm/include/asm/arch-mtk/emi.h
  6. 74
      arch/arm/include/asm/arch-mtk/mt6235.h
  7. 96
      arch/arm/include/asm/arch-mtk/nfi.h
  8. 90
      arch/arm/include/asm/arch-mtk/serial.h
  9. 195
      arch/arm/include/asm/arch-mtk/system.h
  10. 54
      board/mtk/sciphone_g2/Makefile
  11. 1
      board/mtk/sciphone_g2/config.mk
  12. 119
      board/mtk/sciphone_g2/sciphone_g2.c
  13. 1
      drivers/mtd/nand/Makefile
  14. 107
      drivers/mtd/nand/mt62xx_nand.c
  15. 1
      drivers/serial/Makefile
  16. 139
      drivers/serial/serial_mt62xx.c
  17. 107
      include/configs/sciphone_g2.h

@ -970,6 +970,11 @@ omap730p2_cs3boot_config : unconfig
fi;
@$(MKCONFIG) -n $@ -a omap730p2 arm arm926ejs omap730p2 ti omap
sciphone_g2_config: unconfig
@mkdir -p $(obj)include
@ > $(obj)include/config.h
@$(MKCONFIG) -n $@ -a sciphone_g2 arm arm926ejs sciphone_g2 mtk mtk
spear300_config \
spear310_config \
spear320_config : unconfig

@ -0,0 +1,45 @@
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(SOC).o
COBJS = timer.o reset.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS)) $(addprefix $(obj),$(SOBJS))
all: $(obj).depend $(LIB)
$(LIB): $(OBJS)
$(call cmd_link_o_target, $(OBJS))
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

@ -0,0 +1,33 @@
/*
* (C) 2010 by Tieto <www.tieto.com>
* Marcin Mielczarczyk <marcin.mielczarczyk@tieto.com>
*
* All Rights Reserved
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch-mtk/system.h>
void reset_cpu(ulong ignored)
{
writew(BBPU_MAGIC | RTC_BBPU_WRITE_EN | RTC_BBPU_AUTO, MTK_RTC_BASE);
/* never reached */
while (1)
;
}

@ -0,0 +1,105 @@
/*
* (C) 2010 by Tieto <www.tieto.com>
* Marcin Mielczarczyk <marcin.mielczarczyk@tieto.com>
*
* All Rights Reserved
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
*/
#include <common.h>
#include <asm/io.h>
/*
* Timers in MT62xx are just 16-bit counters and
* maximum clock is 16384Hz. This gives tick every 61ms
* and overrun in about 4s.
* GPT3 timer is working as free-runninng timer in incrementing mode.
*/
#define TIMER_CLOCK (16384)
#define TIMER_MAX_LOAD (0xFFFF)
#define COUNT_TO_USEC(x) ((x) * 1000000 / TIMER_CLOCK)
#define USEC_TO_COUNT(x) ((x) * TIMER_CLOCK / 1000000 + 1)
#define TICKS_PER_HZ (TIMER_CLOCK / CONFIG_SYS_HZ)
#define TICKS_TO_HZ(x) ((x) / TICKS_PER_HZ)
/* Reads GPT3 timer counter */
#define READ_TIMER() readw(CONFIG_SYS_TIMERBASE + 0x20)
/*
* tcounter is helper variable which increases overflow
* of built-in timer's counter from 4s to 72h.
*/
ulong tcounter;
ulong last_value;
int timer_init(void)
{
tcounter = 0;
last_value = 0;
/* Set 16384Hz clock */
writew(0x00, CONFIG_SYS_TIMERBASE + 0x24);
/* Enable free-running timer */
writew(0x01, CONFIG_SYS_TIMERBASE + 0x1C);
return 0;
}
void reset_timer(void)
{
/* Enable and disable timer ro reset counter */
writew(0x00, CONFIG_SYS_TIMERBASE + 0x1C);
/*
* Unfortunatelly this busy loop has to be here, otherwise
* counter won't be zeroed. After immediate disable/enable cycle,
* GPT3 counter doesn't reset its value.
*/
while(READ_TIMER() != 0)
;
timer_init();
}
static ulong get_counter(void)
{
unsigned int now = READ_TIMER();
if (now < last_value)
/* Overflow occured, increase tcounter properly */
tcounter += TIMER_MAX_LOAD - last_value + now;
else
tcounter += now - last_value;
last_value = now;
return tcounter;
}
ulong get_timer(ulong base)
{
/* Return how many HZ passed since start */
return TICKS_TO_HZ(get_counter()) - base;
}
void __udelay(unsigned long usec)
{
ulong end, start;
start = get_counter();
end = start + USEC_TO_COUNT((uint64_t)usec);
while (get_counter() < end)
;
}

@ -0,0 +1,42 @@
/*
* (C) 2010 by Tieto <www.tieto.com>
* Marcin Mielczarczyk <marcin.mielczarczyk@tieto.com>
*
* All Rights Reserved
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
*/
#ifndef __MTK_EMI_H_
#define __MTK_EMI_H_
/* External Memory Interface register definitions */
#define MTK_EMI_CONA (MTK_EMI_BASE + 0x00)
#define MTK_EMI_CONB (MTK_EMI_BASE + 0x08)
#define MTK_EMI_CONC (MTK_EMI_BASE + 0x10)
#define MTK_EMI_COND (MTK_EMI_BASE + 0x18)
#define MTK_EMI_CONI (MTK_EMI_BASE + 0x40)
#define MTK_EMI_CONJ (MTK_EMI_BASE + 0x48)
#define MTK_EMI_CONK (MTK_EMI_BASE + 0x50)
#define MTK_EMI_CONL (MTK_EMI_BASE + 0x58)
#define MTK_EMI_CONM (MTK_EMI_BASE + 0x60)
#define MTK_EMI_CONN (MTK_EMI_BASE + 0x68)
#define MTK_EMI_GENA (MTK_EMI_BASE + 0x70)
#define MTK_EMI_GENB (MTK_EMI_BASE + 0x78)
#define MTK_EMI_GENC (MTK_EMI_BASE + 0x80)
#define MTK_EMI_GEND (MTK_EMI_BASE + 0x88)
#endif

@ -0,0 +1,74 @@
/*
* (C) 2010 by Tieto <www.tieto.com>
* Marcin Mielczarczyk <marcin.mielczarczyk@tieto.com>
*
* All Rights Reserved
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
*/
#ifndef __MT6235_H
#define __MT6235_H
/* Peripheral base addresses */
#define MTK_EFUSE_BASE 0x80000000
#define MTK_CONFG_BASE 0x80010000
#define MTK_GPIO_BASE 0x80020000
#define MTK_RGU_BASE 0x80030000
#define MTK_EMI_BASE 0x81000000
#define MTK_CIRQ_BASE 0x81010000
#define MTK_DMA_BASE 0x81020000
#define MTK_UART1_BASE 0x81030000
#define MTK_UART2_BASE 0x81040000
#define MTK_UART3_BASE 0x81050000
#define MTK_GPT_BASE 0x81060000
#define MTK_KP_BASE 0x81080000
#define MTK_PWM_BASE 0x81090000
#define MTK_SIM_BASE 0x810A0000
#define MTK_RTC_BASE 0x810C0000
#define MTK_SEJ_BASE 0x810D0000
#define MTK_BM_BASE 0x810E0000
#define MTK_IRDA_BASE 0x810F0000
#define MTK_I2C_BASE 0x81100000
#define MTK_MSDC_BASE 0x81110000
#define MTK_NFI_BASE 0x81120000
#define MTK_MSSDC2_BASE 0x81140000
#define MTK_TDMA_BASE 0x82000000
#define MTK_BSI_BASE 0x82010000
#define MTK_BPI_BASE 0x82020000
#define MTK_AFC_BASE 0x82030000
#define MTK_APC_BASE 0x82040000
#define MTK_AUXADC_BASE 0x82050000
#define MTK_DIVIDER_BASE 0x82060000
#define MTK_FSC_BASE 0x82070000
#define MTK_GCU_BASE 0x82080000
#define MTK_CSD_ACC_BASE 0x82090000
#define MTK_SHARE1_BASE 0x820A0000
#define MTK_IRDBG1_BASE 0x820B0000
#define MTK_SHARE2_BASE 0x820C0000
#define MTK_IRDBG2_BASE 0x820D0000
#define MTK_PATCH_BASE 0x820E0000
#define MTK_AFE_BASE 0x820F0000
#define MTK_BFE_BASE 0x82100000
#define MTK_PLL_BASE 0x83000000
#define MTK_ACIF_BASE 0x83010000
#define MTK_GMC_BASE 0x84000000
#define MTK_G2D_BASE 0x84010000
#define MTK_GCMQ_BASE 0x84020000
#define MTK_CAM_BASE 0x840B0000
#define MTK_CRZ_BASE 0x840E0000
#endif

@ -0,0 +1,96 @@
/*
* (C) 2010 by Tieto <www.tieto.com>
* Marcin Mielczarczyk <marcin.mielczarczyk@tieto.com>
*
* All Rights Reserved
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
*/
#ifndef __MTK_NFI_H_
#define __MTK_NFI_H_
/* Nand Flash Interface register definitions */
#define MTK_NFI_ACCCON (MTK_NFI_BASE + 0x00)
#define MTK_NFI_PAGEFMT (MTK_NFI_BASE + 0x04)
#define MTK_NFI_OPCON (MTK_NFI_BASE + 0x08)
#define MTK_NFI_CMD (MTK_NFI_BASE + 0x10)
#define MTK_NFI_ADDRNOB (MTK_NFI_BASE + 0x20)
#define MTK_NFI_ADDRL (MTK_NFI_BASE + 0x24)
#define MTK_NFI_ADDRM (MTK_NFI_BASE + 0x28)
#define MTK_NFI_DATAW (MTK_NFI_BASE + 0x30)
#define MTK_NFI_DATAWB (MTK_NFI_BASE + 0x34)
#define MTK_NFI_DATAR (MTK_NFI_BASE + 0x38)
#define MTK_NFI_DATARB (MTK_NFI_BASE + 0x3C)
#define MTK_NFI_PSTA (MTK_NFI_BASE + 0x40)
#define MTK_NFI_FIFOSTA (MTK_NFI_BASE + 0x44)
#define MTK_NFI_CON (MTK_NFI_BASE + 0x60)
/* NFI_ACCCON bit fields definitions */
#define NFI_ACCCON_RLT_SHIFT (0)
#define NFI_ACCCON_WST_SHIFT (4)
#define NFI_ACCCON_WH_SHIFT (8)
#define NFI_ACCCON_W2R_SHIFT (12)
#define NFI_ACCCON_C2R_SHIFT (16)
#define NFI_ACCCON_LCD2NAND_SHIFT (28)
/* NFI_PAGEFMT bit fields definitions */
#define NFI_PAGEFMT_PSIZE_512 (0)
#define NFI_PAGEFMT_PSIZE_2048 (1 << 0)
#define NFI_PAGEFMT_ADRMODE_NORMAL (0 << 2)
#define NFI_PAGEFMT_ADRMODE_LARGE_8IO (1 << 2)
#define NFI_PAGEFMT_ADRMODE_LARGE_16IO (2 << 2)
#define NFI_PAGEFMT_ECCBLKSIZE_128 (0 << 4)
#define NFI_PAGEFMT_ECCBLKSIZE_256 (1 << 4)
#define NFI_PAGEFMT_ECCBLKSIZE_512 (2 << 4)
#define NFI_PAGEFMT_ECCBLKSIZE_1024 (3 << 4)
#define NFI_PAGEFMT_B16EN (1 << 8)
/* NFI_OPCON bit fields definitions */
#define NFI_OPCON_BRD (1 << 0)
#define NFI_OPCON_BWR (1 << 1)
#define NFI_OPCON_SRD (1 << 8)
#define NFI_OPCON_FIFO_FLUSH (1 << 10)
#define NFI_OPCON_FIFO_RST (1 << 11)
#define NFI_OPCON_NOB (1 << 12)
/* NFI_PSTA bit fields definitions */
#define NFI_PSTA_CMD (1 << 0)
#define NFI_PSTA_ADDR (1 << 1)
#define NFI_PSTA_DATAR (1 << 2)
#define NFI_PSTA_DATAW (1 << 3)
#define NFI_PSTA_BUSY (1 << 8)
#define NFI_PSTA_NAND_BUSY (1 << 9)
/* NFI_FIFOSTA bit fields definitions */
#define NFI_FIFOSTA_RD_EMPTY (1 << 6)
#define NFI_FIFOSTA_RD_FULL (1 << 7)
#define NFI_FIFOSTA_WR_EMPTY (1 << 14)
#define NFI_FIFOSTA_WR_FULL (1 << 15)
/* NFI_CON bit fields definitions */
#define NFI_CON_DMA_RD_EN (1 << 0)
#define NFI_CON_DMA_WR_EN (1 << 1)
#define NFI_CON_AUTO_ECC_DEC_EN (1 << 2)
#define NFI_CON_AUTO_ECC_ENC_EN (1 << 3)
#define NFI_CON_MULTI_PAGE_RD_EN (1 << 4)
#define NFI_CON_SPARE_EN (1 << 5)
#define NFI_CON_DMA_PAUSE_EN (1 << 6)
#define NFI_CON_SPARE_ECC_EN (1 << 8)
#define NFI_CON_MAIN_ECC_EN (1 << 9)
#define NFI_CON_BYTE_RW (1 << 15)
#endif

@ -0,0 +1,90 @@
/*
* (C) 2010 by Tieto <www.tieto.com>
* Marcin Mielczarczyk <marcin.mielczarczyk@tieto.com>
*
* All Rights Reserved
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
*/
#ifndef __MT62XX_SERIAL_H_
#define __MT62XX_SERIAL_H_
/* MT62XX UART register definitions */
#define MTK_UART_DR 0x00 /* RX or TX buffer register */
#define MTK_UART_IER 0x04 /* Interrupt enable register */
#define MTK_UART_FCR 0x08 /* FIFO control register */
#define MTK_UART_LCR 0x0C /* Line control register */
#define MTK_UART_MCR 0x10 /* Modem control register */
#define MTK_UART_LSR 0x14 /* Line status register */
#define MTK_UART_MSR 0x14 /* Modem status register */
#define MTK_UART_SCR 0x1C /* Scratch register */
#define MTK_UART_AUTOBAUD_EN 0x20 /* Autobaud enable */
#define MTK_UART_HIGHSPEED 0x24 /* High speed UART */
#define MTK_UART_SAMPLE_COUNT 0x28
#define MTK_UART_SAMPLE_POINT 0x2C
#define MTK_UART_AUTOBAUD_REG 0x30
#define MTK_UART_RATEFIX_AD 0x34 /* Rate fix address */
#define MTK_UART_AUTOBAUD_SAMPLE 0x38
#define MTK_UART_GUARD 0x3C /* Guard time added */
#define MTK_UART_ESCAPE_DAT 0x40 /* Escape character */
#define MTK_UART_ESCAPE_EN 0x44 /* Escape enable */
#define MTK_UART_SLEEP_EN 0x48 /* Sleep enable */
#define MTK_UART_VFIFO_EN 0x4C /* Virtual FIFO enable */
#define MTK_UART_RXTRI_AD 0x50 /* RX trigger address */
/* Registers available when LCR[7] = 1 (bit DLAB) */
#define MTK_UART_DLL 0x00 /* Divisor latch (LS) */
#define MTK_UART_DLM 0x04 /* Divisor latch (MS) */
/* Registers available when LCR = 0xBF */
#define MTK_UART_EFR 0x08 /* Enhanced feature register */
#define MTK_UART_XON1 0x10
#define MTK_UART_XON2 0x14
#define MTK_UART_XOFF1 0x18
#define MTK_UART_XOFF2 0x1C
/* UART_FCR bit fields definitions */
#define UART_FCR_FIFOE (1 << 0)
#define UART_FCR_CLRR (1 << 1)
#define UART_FCR_CLRT (1 << 2)
#define UART_FCR_DMA1 (1 << 3)
#define UART_FCR_TFTL0 (1 << 4)
#define UART_FCR_TFTL1 (1 << 5)
#define UART_FCR_RTFL0 (1 << 6)
#define UART_FCR_RTFL1 (1 << 7)
/* UART_LCR bit fields definitions */
#define UART_LCR_WLS0 (1 << 0)
#define UART_LCR_WLS1 (1 << 1)
#define UART_LCR_STB (1 << 2)
#define UART_LCR_PEN (1 << 3)
#define UART_LCR_EPS (1 << 4)
#define UART_LCR_SP (1 << 5)
#define UART_LCR_SB (1 << 6)
#define UART_LCR_DLAB (1 << 7)
/* UART_LSR bit fields definitions */
#define UART_LSR_DR (1 << 0)
#define UART_LSR_OE (1 << 1)
#define UART_LSR_PE (1 << 2)
#define UART_LSR_FE (1 << 3)
#define UART_LSR_BI (1 << 4)
#define UART_LSR_THRE (1 << 5)
#define UART_LSR_TEMT (1 << 6)
#define UART_LSR_FIFOERR (1 << 7)
#endif

@ -0,0 +1,195 @@
/*
* (C) 2010 by Tieto <www.tieto.com>
* Marcin Mielczarczyk <marcin.mielczarczyk@tieto.com>
*
* All Rights Reserved
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
*/
#ifndef __MTK_SYSTEM_H_
#define __MTK_SYSTEM_H_
/*
* Configuration block section (Clock, Power Down, Version and Reset
*/
/* Register definitions */
#define MTK_CONFG_HW_VERSION (MTK_CONFG_BASE + 0x000)
#define MTK_CONFG_FW_VERSION (MTK_CONFG_BASE + 0x004)
#define MTK_CONFG_HW_CODE (MTK_CONFG_BASE + 0x008)
#define MTK_CONFG_SLEEP_CON (MTK_CONFG_BASE + 0x114)
#define MTK_CONFG_MCUCLK_CON (MTK_CONFG_BASE + 0x118)
#define MTK_CONFG_DSPCLK_CON (MTK_CONFG_BASE + 0x11C)
#define MTK_CONFG_IDN_SEL (MTK_CONFG_BASE + 0x200)
#define MTK_CONFG_PDN_CON0 (MTK_CONFG_BASE + 0x300)
#define MTK_CONFG_PDN_CON1 (MTK_CONFG_BASE + 0x304)
#define MTK_CONFG_PDN_CON2 (MTK_CONFG_BASE + 0x308)
#define MTK_CONFG_PDN_CON3 (MTK_CONFG_BASE + 0x30C)
#define MTK_CONFG_PDN_SET0 (MTK_CONFG_BASE + 0x310)
#define MTK_CONFG_PDN_SET1 (MTK_CONFG_BASE + 0x314)
#define MTK_CONFG_PDN_SET2 (MTK_CONFG_BASE + 0x318)
#define MTK_CONFG_PDN_SET3 (MTK_CONFG_BASE + 0x31C)
#define MTK_CONFG_PDN_CLR0 (MTK_CONFG_BASE + 0x320)
#define MTK_CONFG_PDN_CLR1 (MTK_CONFG_BASE + 0x324)
#define MTK_CONFG_PDN_CLR2 (MTK_CONFG_BASE + 0x328)
#define MTK_CONFG_PDN_CLR3 (MTK_CONFG_BASE + 0x32C)
/* CONFG_MCUCLK_CON bit fields definitions */
#define MCUCLK_CON_AHBX8CLK_SHIFT (0)
#define MCUCLK_CON_AHBX4CLK_SHIFT (4)
#define MCUCLK_CON_ARMCLK_SHIFT (8)
#define MCUCLK_CON_EMICLK_SHIFT (12)
/* PDN_CON0 bit fields definitions */
#define PDN_CON0_CON0_DMA (1 << 0)
#define PDN_CON0_USB (1 << 1)
#define PDN_CON0_GCU (1 << 2)
#define PDN_CON0_WAVE (1 << 3)
#define PDN_CON0_SEJ (1 << 4)
#define PDN_CON0_IR (1 << 6)
#define PDN_CON0_PWM3 (1 << 7)
#define PDN_CON0_PWM (1 << 8)
#define PDN_CON0_SIM2 (1 << 10)
#define PDN_CON0_IRDBG1 (1 << 12)
#define PDN_CON0_IRDBG2 (1 << 13)
/* PDN_CON1 bit fields definitions */
#define PDN_CON1_GPT (1 << 0)
#define PDN_CON1_KP (1 << 1)
#define PDN_CON1_GPIO (1 << 2)
#define PDN_CON1_UART1 (1 << 3)
#define PDN_CON1_SIM (1 << 4)
#define PDN_CON1_PWM1 (1 << 5)
#define PDN_CON1_LCD (1 << 7)
#define PDN_CON1_UART2 (1 << 8)
#define PDN_CON1_MSDC (1 << 9)
#define PDN_CON1_TP (1 << 10)
#define PDN_CON1_PWM2 (1 << 11)
#define PDN_CON1_NFI (1 << 12)
#define PDN_CON1_UART3 (1 << 14)
#define PDN_CON1_IRDA (1 << 15)
/* PDN_CON2 bit fields definitions */
#define PDN_CON2_TDMA (1 << 0)
#define PDN_CON2_RTC (1 << 1)
#define PDN_CON2_BSI (1 << 2)
#define PDN_CON2_BPI (1 << 3)
#define PDN_CON2_AFC (1 << 4)
#define PDN_CON2_APC (1 << 5)
/*
* Reset Generation Unit block section
*/
#define MTK_RGU_WDT_MODE (MTK_RGU_BASE + 0x00)
#define MTK_RGU_WDT_LENGTH (MTK_RGU_BASE + 0x04)
#define MTK_RGU_WDT_RESTART (MTK_RGU_BASE + 0x08)
#define MTK_RGU_WDT_STA (MTK_RGU_BASE + 0x0C)
#define MTK_RGU_SW_PERIPH_RSTN (MTK_RGU_BASE + 0x10)
#define MTK_RGU_SW_DSP_RSTN (MTK_RGU_BASE + 0x14)
#define MTK_RGU_WDT_RSTINTERVAL (MTK_RGU_BASE + 0x18)
#define MTK_RGU_WDT_SWRST (MTK_RGU_BASE + 0x1C)
#define WDT_MODE_KEY 0x2200
#define WDT_LENGTH_KEY 0x0008
#define WDT_RESTART_KEY 0x1971
#define SW_PERIPH_RSTN_KEY 0x0037
#define WDT_SWRST_KEY 0x1209
/*
* RTC block section
*/
/* RTC registers definition */
#define MTK_RTC_BBPU (MTK_RTC_BASE + 0x00)
#define MTK_RTC_IRQ_STA (MTK_RTC_BASE + 0x04)
#define MTK_RTC_IRQ_EN (MTK_RTC_BASE + 0x08)
#define MTK_RTC_CII_EN (MTK_RTC_BASE + 0x0C)
#define MTK_RTC_AL_MASK (MTK_RTC_BASE + 0x10)
#define MTK_RTC_TC_SEC (MTK_RTC_BASE + 0x14)
#define MTK_RTC_TC_MIN (MTK_RTC_BASE + 0x18)
#define MTK_RTC_TC_HOU (MTK_RTC_BASE + 0x1C)
#define MTK_RTC_TC_DOM (MTK_RTC_BASE + 0x20)
#define MTK_RTC_TC_DOW (MTK_RTC_BASE + 0x24)
#define MTK_RTC_TC_MTH (MTK_RTC_BASE + 0x28)
#define MTK_RTC_TC_YEA (MTK_RTC_BASE + 0x2C)
#define MTK_RTC_AL_SEC (MTK_RTC_BASE + 0x30)
#define MTK_RTC_AL_MIN (MTK_RTC_BASE + 0x34)
#define MTK_RTC_AL_HOU (MTK_RTC_BASE + 0x38)
#define MTK_RTC_AL_DOM (MTK_RTC_BASE + 0x3C)
#define MTK_RTC_AL_DOW (MTK_RTC_BASE + 0x40)
#define MTK_RTC_AL_MTH (MTK_RTC_BASE + 0x44)
#define MTK_RTC_AL_YEA (MTK_RTC_BASE + 0x48)
#define MTK_RTC_XOSCCALI (MTK_RTC_BASE + 0x4C)
#define MTK_RTC_POWERKEY1 (MTK_RTC_BASE + 0x50)
#define MTK_RTC_POWERKEY2 (MTK_RTC_BASE + 0x54)
#define MTK_RTC_PDN1 (MTK_RTC_BASE + 0x58)
#define MTK_RTC_PDN2 (MTK_RTC_BASE + 0x5C)
#define MTK_RTC_SPAR1 (MTK_RTC_BASE + 0x64)
#define MTK_RTC_DIFF (MTK_RTC_BASE + 0x6C)
#define MTK_RTC_CALI (MTK_RTC_BASE + 0x70)
#define MTK_RTC_WRTGR (MTK_RTC_BASE + 0x74)
#define POWERKEY1_MAGIC 0xA357
#define POWERKEY2_MAGIC 0x67D2
/* RTC_BBPU bit fields definitions */
#define RTC_BBPU_PWREN (1 << 0)
#define RTC_BBPU_WRITE_EN (1 << 1)
#define RTC_BBPU_BBPU (1 << 2)
#define RTC_BBPU_AUTO (1 << 3)
#define RTC_BBPU_CLRPKY (1 << 4)
#define RTC_BBPU_RELOAD (1 << 5)
#define RTC_BBPU_CBUSY (1 << 6)
#define RTC_BBPU_DBING (1 << 7)
#define RTC_BBPU_KEY_BBPU (1 << 8)
/* RTC_BBPU write is only acceptable when KEY_BBPU=0x43 */
#define BBPU_MAGIC 0x4300
/*
* PLL block section
*/
/* PLL registers definition */
#define MTK_PLL_PLL (MTK_PLL_BASE + 0x00)
#define MTK_PLL_PLL2 (MTK_PLL_BASE + 0x04)
#define MTK_PLL_CLK_CON (MTK_PLL_BASE + 0x18)
#define MTK_PLL_PDN_CON (MTK_PLL_BASE + 0x1C)
/* MTK_PLL_PLL bit fields definitions */
#define PLL_PLLVCOSEL (0 << 0)
#define PLL_MPLLSEL_SYSCLK (1 << 3)
#define PLL_MPLLSEL_PLL (2 << 3)
#define PLL_DPLLSEL (1 << 5)
#define PLL_UPLLSEL (1 << 6)
#define PLL_RST (1 << 7)
#define PLL_CALI (1 << 8)
/* MTK_PLL_CLK_CON bit fields definitions */
#define PLL_CLKSQ_DIV2_DSP (1 << 0)
#define PLL_CLKSQ_DIV2_MCU (1 << 1)
#define PLL_CLKSQ_PLD (1 << 2)
#define PLL_SRCCLK (1 << 7)
#define PLL_CLKSQ_TEST (1 << 15)
/* MTK_PLL_PDN_CON bit fields definitions */
#define PLL_PDN_CON_CLKSQ (1 << 11)
#define PLL_PDN_CON_MCU_DIV2 (1 << 12)
#define PLL_PDN_CON_PLL (1 << 13)
#define PLL_PDN_CON_DSP_DIV2 (1 << 15)
#endif

@ -0,0 +1,54 @@
#
# (C) Copyright 2000-2004
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2004
# ARM Ltd.
# Philippe Robin, <philippe.robin@arm.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
COBJS := sciphone_g2.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

@ -0,0 +1 @@
CONFIG_SYS_TEXT_BASE = 0x8000

@ -0,0 +1,119 @@
/*
* (C) 2010 by Tieto <www.tieto.com>
* Marcin Mielczarczyk <marcin.mielczarczyk@tieto.com>
*
* All Rights Reserved
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch-mtk/emi.h>
#include <asm/arch-mtk/system.h>
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_SHOW_BOOT_PROGRESS
void show_boot_progress(int progress)
{
printf("%i\n", progress);
}
#endif
int board_init(void)
{
gd->bd->bi_arch_number = MACH_TYPE_SCIPHONE_G2;
gd->bd->bi_boot_params = 0x00000100;
/* Powerup BB */
writew(POWERKEY1_MAGIC, MTK_RTC_POWERKEY1);
writew(POWERKEY2_MAGIC, MTK_RTC_POWERKEY2);
writew(BBPU_MAGIC | RTC_BBPU_WRITE_EN |
RTC_BBPU_BBPU | RTC_BBPU_AUTO,
MTK_RTC_BBPU);
writew(1, MTK_RTC_WRTGR);
/* Disable watchdog */
writew(WDT_MODE_KEY, MTK_RGU_WDT_MODE);
writew(WDT_MODE_KEY, MTK_RGU_WDT_MODE);
/*
* PLL configuration influents JTAG clock.
* Currently it's disabled to avoid problems with JTAG.
*/
#if 0
/* Power on PLL */
writew(0, MTK_PLL_PDN_CON);
/* Turn on MCU and DSP dividers, mark that SYSCLK is 26MHz */
writew(PLL_CLKSQ_DIV2_DSP | PLL_CLKSQ_DIV2_MCU | PLL_SRCCLK,
MTK_PLL_CLK_CON);
/* Reset PLL */
writew(PLL_RST, MTK_PLL_PLL);
writew(0, MTK_PLL_PLL);
udelay(100);
/* Turn on PLL for MCU, DSP and USB */
writew(PLL_MPLLSEL_PLL | PLL_DPLLSEL | PLL_UPLLSEL, MTK_PLL_PLL);
/*
* Setup MCU clock register:
* ARMCLK = 208MHz, AHBx4CLK = 52MHz, AHBx8CLK = 104MHz
* we have to write to the read-only part (EMICLK) as well, otherwise
* the EMI won't work! (datasheet lies)
*/
writew(7 << MCUCLK_CON_AHBX8CLK_SHIFT |
3 << MCUCLK_CON_AHBX4CLK_SHIFT |
15 << MCUCLK_CON_ARMCLK_SHIFT |
7 << MCUCLK_CON_EMICLK_SHIFT,
MTK_CONFG_MCUCLK_CON);
#endif
return 0;
}
int dram_init(void)
{
gd->ram_size = get_ram_size(PHYS_SDRAM_1, CONFIG_MAX_RAM_BANK_SIZE);
/*
* Currently UBoot is executed from external RAM and below configuration
* will make it to stop working. This code will be uncommented when
* UBoot will be placed in NAND memory.
*/
#if 0
/* Configure DRAM controller */
writel(0x0001000E, MTK_EMI_GEND);
writel(0x00088E3A, MTK_EMI_GENA);
writel(0x000000C0, MTK_EMI_GENB);
writel(0x18C618C6, MTK_EMI_GENC);
writel(0x18007505, MTK_EMI_CONL);
writel(0x00002828, MTK_EMI_CONM);
writel(0x00332000, MTK_EMI_CONI);
writel(0x3CD24431, MTK_EMI_CONJ);
writel(0x02000000, MTK_EMI_CONK);
for (i = 0; i < 5; ++i) {
/* Setup five single bits, one by one for DRAM init */
writel((1 << (24 + i)) | (0x500013), MTK_EMI_CONN);
udelay(1);
writel(0x500013, MTK_EMI_CONN);
udelay(1);
}
#endif
return 0;
}

@ -42,6 +42,7 @@ COBJS-$(CONFIG_NAND_KB9202) += kb9202_nand.o
COBJS-$(CONFIG_NAND_KIRKWOOD) += kirkwood_nand.o
COBJS-$(CONFIG_NAND_KMETER1) += kmeter1_nand.o
COBJS-$(CONFIG_NAND_MPC5121_NFC) += mpc5121_nfc.o
COBJS-$(CONFIG_NAND_MT62XX) += mt62xx_nand.o
COBJS-$(CONFIG_NAND_MXC) += mxc_nand.o
COBJS-$(CONFIG_NAND_NDFC) += ndfc.o
COBJS-$(CONFIG_NAND_NOMADIK) += nomadik.o

@ -0,0 +1,107 @@
/*
* (C) 2010 by Tieto <www.tieto.com>
* Marcin Mielczarczyk <marcin.mielczarczyk@tieto.com>
*
* All Rights Reserved
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
*/
#include <common.h>
#include <nand.h>
#include <asm/io.h>
#include <asm/arch-mtk/nfi.h>
#include <asm/arch-mtk/system.h>
static void mtk_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
struct nand_chip *chip = mtd->priv;
static int addr_bit = 0;
static int address = 0;
static int command = 0;
if (ctrl == (NAND_CTRL_CHANGE | NAND_NCE)) {
chip->IO_ADDR_R = (void *)MTK_NFI_DATARB;
if (addr_bit) {
/*
while(!((readw(MTK_NFI_FIFOSTA) & 0xFF) == NFI_FIFOSTA_RD_EMPTY))
readb(MTK_NFI_DATARB);*/
writel(address, MTK_NFI_ADDRL);
if (command == NAND_CMD_READID ||
command == NAND_CMD_STATUS) {
writeb(1, MTK_NFI_ADDRNOB);
while(readl(MTK_NFI_PSTA) & NFI_PSTA_ADDR)
;
writel(NFI_OPCON_SRD, MTK_NFI_OPCON);
} else {
writeb(addr_bit >> 3, MTK_NFI_ADDRNOB);
while(readl(MTK_NFI_PSTA) & NFI_PSTA_ADDR)
;
writel(NFI_OPCON_BRD, MTK_NFI_OPCON);
}
addr_bit = 0;
}
} else if ((ctrl & NAND_CLE) && (cmd != NAND_CMD_NONE)) {
command = cmd;
writel(cmd, MTK_NFI_CMD);
while(readl(MTK_NFI_PSTA) & NFI_PSTA_CMD)
;
} else if (ctrl & NAND_ALE) {
if (!addr_bit)
address = cmd;
else
address |= cmd << addr_bit;
addr_bit += 8;
}
}
static int mtk_dev_ready(struct mtd_info *mtd)
{
return !(readl(MTK_NFI_PSTA) & NFI_PSTA_NAND_BUSY);
}
int board_nand_init(struct nand_chip *nand)
{
/* Power on NFI controller */
writel(PDN_CON1_NFI, MTK_CONFG_PDN_CLR1);
/* Configure for max wait times */
writel(3 << NFI_ACCCON_RLT_SHIFT |
3 << NFI_ACCCON_WST_SHIFT |
3 << NFI_ACCCON_WH_SHIFT |
3 << NFI_ACCCON_W2R_SHIFT |
3 << NFI_ACCCON_C2R_SHIFT |
7 << NFI_ACCCON_LCD2NAND_SHIFT,
MTK_NFI_ACCCON);
/* Flush and reset NFI FIFO */
writel(NFI_OPCON_FIFO_FLUSH | NFI_OPCON_FIFO_RST, MTK_NFI_OPCON);
while(readl(MTK_NFI_OPCON))
;
writel(NFI_PAGEFMT_PSIZE_2048 |
NFI_PAGEFMT_ADRMODE_LARGE_8IO |
NFI_PAGEFMT_ECCBLKSIZE_1024,
MTK_NFI_PAGEFMT);
writel(NFI_CON_SPARE_EN, MTK_NFI_CON);
nand->cmd_ctrl = mtk_cmd_ctrl;
nand->dev_ready = mtk_dev_ready;
nand->ecc.mode = NAND_ECC_SOFT;
return 0;
}

@ -45,6 +45,7 @@ COBJS-$(CONFIG_KS8695_SERIAL) += serial_ks8695.o
COBJS-$(CONFIG_LPC2292_SERIAL) += serial_lpc2292.o
COBJS-$(CONFIG_LH7A40X_SERIAL) += serial_lh7a40x.o
COBJS-$(CONFIG_MAX3100_SERIAL) += serial_max3100.o
COBJS-$(CONFIG_MT62XX_SERIAL) += serial_mt62xx.o
COBJS-$(CONFIG_MXC_UART) += serial_mxc.o
COBJS-$(CONFIG_NETARM_SERIAL) += serial_netarm.o
COBJS-$(CONFIG_PL010_SERIAL) += serial_pl01x.o

@ -0,0 +1,139 @@
/*
* (C) 2010 by Tieto <www.tieto.com>
* Marcin Mielczarczyk <marcin.mielczarczyk@tieto.com>
*
* All Rights Reserved
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
*/
#include <common.h>
#include <watchdog.h>
#include <asm/io.h>
#include <asm/arch-mtk/serial.h>
static volatile unsigned char *const port[] = CONFIG_MT62XX_PORTS;
#define NUM_PORTS (sizeof(port)/sizeof(port[0]))
struct baud_div {
unsigned int baud;
unsigned int div;
};
/* Divisor needed to generate given baudrate (52MHz clock) */
static struct baud_div baud_table[] = {
{110, 29545},
{300, 10833},
{1200, 2708},
{2400, 1354},
{4800, 677},
{9600, 339},
{19200, 169},
{38400, 85},
{57600, 56},
{115200,28},
};
unsigned int baudrate = CONFIG_BAUDRATE;
DECLARE_GLOBAL_DATA_PTR;
int serial_init(void)
{
int i;
/* First, clear and setup FIFOs */
writew(UART_FCR_FIFOE | UART_FCR_CLRR | UART_FCR_CLRT,
port[CONSOLE_PORT] + MTK_UART_FCR);
/* Set baud rate */
writew(UART_LCR_DLAB, port[CONSOLE_PORT] + MTK_UART_LCR);
for (i = 0; i < sizeof(baud_table)/sizeof(baud_table[0]); ++i) {
if (baud_table[i].baud == baudrate) {
writew(baud_table[i].div & 0xFFFF,
port[CONSOLE_PORT] + MTK_UART_DLL);
writew(baud_table[i].div >> 16,
port[CONSOLE_PORT] + MTK_UART_DLM);
break;
}
}
if (i >= sizeof(baud_table)/sizeof(baud_table[0]))
printf("Warning! Not supported baudrate: %d\n", baudrate);
writew(0, port[CONSOLE_PORT] + MTK_UART_LCR);
/* Set the UART to be 8 bits, 1 stop bit, no parity */
writew(UART_LCR_WLS0 | UART_LCR_WLS1,
port[CONSOLE_PORT] + MTK_UART_LCR);
return 0;
}
static void mt62xx_putc(int portnum, char c)
{
/* Wait until there is space in the FIFO */
while(!(readw(port[portnum] + MTK_UART_LSR) & UART_LSR_THRE))
WATCHDOG_RESET();
/* Send the character */
writew(c, port[portnum] + MTK_UART_DR);
}
static int mt62xx_getc(int portnum)
{
/* Wait until there is data in the FIFO */
while (!(readl(port[portnum] + MTK_UART_LSR) & UART_LSR_DR))
WATCHDOG_RESET();
return readl(port[portnum] + MTK_UART_DR);
}
static int mt62xx_tstc(int portnum)
{
WATCHDOG_RESET();
return (readl(port[portnum] + MTK_UART_LSR) & UART_LSR_DR);
}
void serial_putc(const char c)
{
if (c == '\n')
mt62xx_putc(CONSOLE_PORT, '\r');
mt62xx_putc(CONSOLE_PORT, c);
}
void serial_puts (const char *s)
{
while(*s)
serial_putc(*s++);
}
int serial_getc (void)
{
return mt62xx_getc(CONSOLE_PORT);
}
int serial_tstc (void)
{
return mt62xx_tstc(CONSOLE_PORT);
}
void serial_setbrg(void)
{
baudrate = gd->baudrate;
serial_init();
}

@ -0,0 +1,107 @@
/*
* (C) 2010 by Tieto <www.tieto.com>
* Marcin Mielczarczyk <marcin.mielczarczyk@tieto.com>
*
* All Rights Reserved
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#include "asm/arch-mtk/mt6235.h"
#define CONFIG_ARM926EJS
/* We have already been loaded to RAM */
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_CMDLINE_TAG
/* Serial port configuration */
#define CONFIG_MT62XX_SERIAL
#define CONFIG_MT62XX_PORTS {0x81030000, 0x81040000, 0x81050000}
#define CONSOLE_PORT 0
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
/* There is no NOR flash, so undefine these commands */
#undef CONFIG_CMD_FLASH
#undef CONFIG_CMD_IMLS
#define CONFIG_SYS_NO_FLASH
/* Configure NAND storage */
#define CONFIG_NAND_MT62XX
#define CONFIG_CMD_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE MTK_NFI_BASE
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_LOADB
#define CONFIG_CMD_RUN
/* Timing configuration */
#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_TIMERBASE MTK_GPT_BASE
/* Support for command auto completion */
#define CONFIG_AUTO_COMPLETE
/* User interface */
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT "Sciphone> "
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_CBSIZE 256
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_SYS_LOAD_ADDR 0x800000
#define CONFIG_SYS_LOADS_BAUD_CHANGE
#define CONFIG_ENV_SIZE 0x20000 /* 128 Kb - one sector */
#define CONFIG_ENV_ADDR (0x00280000 - CONFIG_ENV_SIZE)
#define CONFIG_BOOTDELAY 1
#define CONFIG_BOOTARGS "console=ttyMTK0,115200n8 mem=64M@0"
#define CONFIG_BOOTCOMMAND "bootm 0x800000"
/* Memory related information */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM_1 0x00000000
#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000)
#define CONFIG_MAX_RAM_BANK_SIZE 0x10000000
#define CONFIG_STACKSIZE (128 * 1024)
#ifdef CONFIG_USE_IRQ
# define CONFIG_STACKSIZE_IRQ (4 * 1024) /* IRQ stack */
# define CONFIG_STACKSIZE_FIQ (4 * 1024) /* FIQ stack */
#endif
#define CONFIG_SYS_MEMTEST_START 0x00000000
#define CONFIG_SYS_MEMTEST_END 0x02FFFFFF
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 256 * 1024)
#define CONFIG_SYS_GBL_DATA_SIZE 128
/* This is needed to make hello_world.c happy */
#define CONFIG_SYS_MAX_FLASH_SECT 512
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#endif
Loading…
Cancel
Save