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Merge branch 'master' of git://www.denx.de/git/u-boot-at91

This commit is contained in:
Wolfgang Denk 2008-04-08 00:16:36 +02:00
parent f9eabcb357 b5873f1732
commit a1b215e2a2
54 changed files with 2492 additions and 995 deletions
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5
MAINTAINERS
View File

@ -530,6 +530,11 @@ Dave Peverley <dpeverley@mpc-data.co.uk>
omap730p2 ARM926EJS
Stelian Pop <stelian.pop@leadtechdesign.com>
at91cap9adk ARM926EJS (AT91CAP9 SoC)
at91sam9260ek ARM926EJS (AT91SAM9260 SoC)
Stefan Roese <sr@denx.de>
ixdpg425 xscale

4
MAKEALL
View File

@ -452,6 +452,7 @@ LIST_ARM7=" \
LIST_ARM9=" \
at91cap9adk \
at91rm9200dk \
at91sam9260ek \
cmc_pu2 \
ap920t \
ap922_XA10 \
@ -463,6 +464,8 @@ LIST_ARM9=" \
cp926ejs \
cp946es \
cp966 \
csb637 \
kb9202 \
lpd7a400 \
m501sk \
mp2usb \
@ -472,6 +475,7 @@ LIST_ARM9=" \
omap1510inn \
omap1610h2 \
omap1610inn \
omap5912osk \
omap730p2 \
sbc2410x \
scb9328 \

5
Makefile
View File

@ -2308,11 +2308,14 @@ xtract_omap1610xxx = $(subst _cs0boot,,$(subst _cs3boot,,$(subst _cs_autoboot,,$
xtract_omap730p2 = $(subst _cs0boot,,$(subst _cs3boot,, $(subst _config,,$1)))
at91cap9adk_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm926ejs at91cap9adk atmel at91cap9
@$(MKCONFIG) $(@:_config=) arm arm926ejs at91cap9adk atmel at91sam9
at91rm9200dk_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm920t at91rm9200dk atmel at91rm9200
at91sam9260ek_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm926ejs at91sam9260ek atmel at91sam9
cmc_pu2_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm920t cmc_pu2 NULL at91rm9200

8
board/atmel/at91cap9adk/Makefile
View File

@ -25,10 +25,12 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS := at91cap9adk.o led.o nand.o
COBJS-y += at91cap9adk.o
COBJS-y += led.o
COBJS-$(CONFIG_CMD_NAND) += nand.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)

223
board/atmel/at91cap9adk/at91cap9adk.c
View File

@ -23,7 +23,13 @@
*/
#include <common.h>
#include <asm/arch/AT91CAP9.h>
#include <asm/arch/at91cap9.h>
#include <asm/arch/at91cap9_matrix.h>
#include <asm/arch/at91sam926x_mc.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_rstc.h>
#include <asm/arch/gpio.h>
#include <asm/arch/io.h>
#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
#include <net.h>
#endif
@ -40,126 +46,106 @@ DECLARE_GLOBAL_DATA_PTR;
static void at91cap9_serial_hw_init(void)
{
#ifdef CONFIG_USART0
AT91C_BASE_PIOA->PIO_PDR = AT91C_PA22_TXD0 | AT91C_PA23_RXD0;
AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_US0;
at91_set_A_periph(AT91_PIN_PA22, 1); /* TXD0 */
at91_set_A_periph(AT91_PIN_PA23, 0); /* RXD0 */
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US0);
#endif
#ifdef CONFIG_USART1
AT91C_BASE_PIOD->PIO_PDR = AT91C_PD0_TXD1 | AT91C_PD1_RXD1;
AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_US1;
at91_set_A_periph(AT91_PIN_PD0, 1); /* TXD1 */
at91_set_A_periph(AT91_PIN_PD1, 0); /* RXD1 */
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US1);
#endif
#ifdef CONFIG_USART2
AT91C_BASE_PIOD->PIO_PDR = AT91C_PD2_TXD2 | AT91C_PD3_RXD2;
AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_US2;
at91_set_A_periph(AT91_PIN_PD2, 1); /* TXD2 */
at91_set_A_periph(AT91_PIN_PD3, 0); /* RXD2 */
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US2);
#endif
#ifdef CONFIG_USART3 /* DBGU */
AT91C_BASE_PIOC->PIO_PDR = AT91C_PC31_DTXD | AT91C_PC30_DRXD;
AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_SYS;
at91_set_A_periph(AT91_PIN_PC30, 0); /* DRXD */
at91_set_A_periph(AT91_PIN_PC31, 1); /* DTXD */
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
#endif
}
static void at91cap9_nor_hw_init(void)
{
unsigned long csa;
/* Ensure EBI supply is 3.3V */
AT91C_BASE_CCFG->CCFG_EBICSA |= AT91C_EBI_SUP_3V3;
csa = at91_sys_read(AT91_MATRIX_EBICSA);
at91_sys_write(AT91_MATRIX_EBICSA,
csa | AT91_MATRIX_EBI_VDDIOMSEL_3_3V);
/* Configure SMC CS0 for parallel flash */
AT91C_BASE_SMC->SMC_SETUP0 = AT91C_FLASH_NWE_SETUP |
AT91C_FLASH_NCS_WR_SETUP |
AT91C_FLASH_NRD_SETUP |
AT91C_FLASH_NCS_RD_SETUP;
AT91C_BASE_SMC->SMC_PULSE0 = AT91C_FLASH_NWE_PULSE |
AT91C_FLASH_NCS_WR_PULSE |
AT91C_FLASH_NRD_PULSE |
AT91C_FLASH_NCS_RD_PULSE;
AT91C_BASE_SMC->SMC_CYCLE0 = AT91C_FLASH_NWE_CYCLE |
AT91C_FLASH_NRD_CYCLE;
AT91C_BASE_SMC->SMC_CTRL0 = AT91C_SMC_READMODE |
AT91C_SMC_WRITEMODE |
AT91C_SMC_NWAITM_NWAIT_DISABLE |
AT91C_SMC_BAT_BYTE_WRITE |
AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS |
(AT91C_SMC_TDF & (1 << 16));
at91_sys_write(AT91_SMC_SETUP(0),
AT91_SMC_NWESETUP_(4) | AT91_SMC_NCS_WRSETUP_(2) |
AT91_SMC_NRDSETUP_(4) | AT91_SMC_NCS_RDSETUP_(2));
at91_sys_write(AT91_SMC_PULSE(0),
AT91_SMC_NWEPULSE_(8) | AT91_SMC_NCS_WRPULSE_(10) |
AT91_SMC_NRDPULSE_(8) | AT91_SMC_NCS_RDPULSE_(10));
at91_sys_write(AT91_SMC_CYCLE(0),
AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16));
at91_sys_write(AT91_SMC_MODE(0),
AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_WRITE |
AT91_SMC_DBW_16 | AT91_SMC_TDF_(1));
}
#ifdef CONFIG_CMD_NAND
static void at91cap9_nand_hw_init(void)
{
unsigned long csa;
/* Enable CS3 */
AT91C_BASE_CCFG->CCFG_EBICSA |= AT91C_EBI_CS3A_SM | AT91C_EBI_SUP_3V3;
csa = at91_sys_read(AT91_MATRIX_EBICSA);
at91_sys_write(AT91_MATRIX_EBICSA,
csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA |
AT91_MATRIX_EBI_VDDIOMSEL_3_3V);
/* Configure SMC CS3 for NAND/SmartMedia */
AT91C_BASE_SMC->SMC_SETUP3 = AT91C_SM_NWE_SETUP |
AT91C_SM_NCS_WR_SETUP |
AT91C_SM_NRD_SETUP |
AT91C_SM_NCS_RD_SETUP;
at91_sys_write(AT91_SMC_SETUP(3),
AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(1) |
AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(1));
at91_sys_write(AT91_SMC_PULSE(3),
AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(6) |
AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(6));
at91_sys_write(AT91_SMC_CYCLE(3),
AT91_SMC_NWECYCLE_(8) | AT91_SMC_NRDCYCLE_(8));
at91_sys_write(AT91_SMC_MODE(3),
AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
AT91_SMC_EXNWMODE_DISABLE |
AT91_SMC_DBW_8 | AT91_SMC_TDF_(1));
AT91C_BASE_SMC->SMC_PULSE3 = AT91C_SM_NWE_PULSE |
AT91C_SM_NCS_WR_PULSE |
AT91C_SM_NRD_PULSE |
AT91C_SM_NCS_RD_PULSE;
AT91C_BASE_SMC->SMC_CYCLE3 = AT91C_SM_NWE_CYCLE |
AT91C_SM_NRD_CYCLE;
AT91C_BASE_SMC->SMC_CTRL3 = AT91C_SMC_READMODE |
AT91C_SMC_WRITEMODE |
AT91C_SMC_NWAITM_NWAIT_DISABLE |
AT91C_SMC_DBW_WIDTH_EIGTH_BITS |
AT91C_SM_TDF;
AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOABCD;
at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_PIOABCD);
/* RDY/BSY is not connected */
/* Enable NandFlash */
AT91C_BASE_PIOD->PIO_PER = AT91C_PIO_PD15;
AT91C_BASE_PIOD->PIO_OER = AT91C_PIO_PD15;
at91_set_gpio_output(AT91_PIN_PD15, 1);
}
#endif
#ifdef CONFIG_HAS_DATAFLASH
static void at91cap9_spi_hw_init(void)
{
AT91C_BASE_PIOD->PIO_BSR = AT91C_PD0_SPI0_NPCS2D |
AT91C_PD1_SPI0_NPCS3D;
AT91C_BASE_PIOD->PIO_PDR = AT91C_PD0_SPI0_NPCS2D |
AT91C_PD1_SPI0_NPCS3D;
at91_set_B_periph(AT91_PIN_PA5, 0); /* SPI0_NPCS0 */
AT91C_BASE_PIOA->PIO_ASR = AT91C_PA28_SPI0_NPCS3A;
AT91C_BASE_PIOA->PIO_BSR = AT91C_PA4_SPI0_NPCS2A |
AT91C_PA1_SPI0_MOSI |
AT91C_PA0_SPI0_MISO |
AT91C_PA3_SPI0_NPCS1 |
AT91C_PA5_SPI0_NPCS0 |
AT91C_PA2_SPI0_SPCK;
AT91C_BASE_PIOA->PIO_PDR = AT91C_PA28_SPI0_NPCS3A |
AT91C_PA4_SPI0_NPCS2A |
AT91C_PA1_SPI0_MOSI |
AT91C_PA0_SPI0_MISO |
AT91C_PA3_SPI0_NPCS1 |
AT91C_PA5_SPI0_NPCS0 |
AT91C_PA2_SPI0_SPCK;
at91_set_B_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */
at91_set_B_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */
at91_set_B_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */
/* Enable Clock */
AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_SPI0;
/* Enable clock */
at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_SPI0);
}
#endif
#ifdef CONFIG_MACB
static void at91cap9_macb_hw_init(void)
{
unsigned int gpio;
/* Enable clock */
AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_EMAC;
at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_EMAC);
/*
* Disable pull-up on:
@ -169,54 +155,59 @@ static void at91cap9_macb_hw_init(void)
*
* PHY has internal pull-down
*/
AT91C_BASE_PIOB->PIO_PPUDR = AT91C_PB22_E_RXDV |
AT91C_PB25_E_RX0 |
AT91C_PB26_E_RX1;
writel(pin_to_mask(AT91_PIN_PB22) |
pin_to_mask(AT91_PIN_PB25) |
pin_to_mask(AT91_PIN_PB26),
pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);
/* Need to reset PHY -> 500ms reset */
AT91C_BASE_RSTC->RSTC_RMR = (AT91C_RSTC_KEY & (0xA5 << 24)) |
(AT91C_RSTC_ERSTL & (0x0D << 8)) |
AT91C_RSTC_URSTEN;
AT91C_BASE_RSTC->RSTC_RCR = (AT91C_RSTC_KEY & (0xA5 << 24)) |
AT91C_RSTC_EXTRST;
at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
AT91_RSTC_ERSTL | (0x0D << 8) |
AT91_RSTC_URSTEN);
at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
/* Wait for end hardware reset */
while (!(AT91C_BASE_RSTC->RSTC_RSR & AT91C_RSTC_NRSTL));
while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
/* Re-enable pull-up */
AT91C_BASE_PIOB->PIO_PPUER = AT91C_PB22_E_RXDV |
AT91C_PB25_E_RX0 |
AT91C_PB26_E_RX1;
writel(pin_to_mask(AT91_PIN_PB22) |
pin_to_mask(AT91_PIN_PB25) |
pin_to_mask(AT91_PIN_PB26),
pin_to_controller(AT91_PIN_PA0) + PIO_PUER);
#ifdef CONFIG_RMII
gpio = AT91C_PB30_E_MDIO |
AT91C_PB29_E_MDC |
AT91C_PB21_E_TXCK |
AT91C_PB27_E_RXER |
AT91C_PB25_E_RX0 |
AT91C_PB22_E_RXDV |
AT91C_PB26_E_RX1 |
AT91C_PB28_E_TXEN |
AT91C_PB23_E_TX0 |
AT91C_PB24_E_TX1;
AT91C_BASE_PIOB->PIO_ASR = gpio;
AT91C_BASE_PIOB->PIO_BSR = 0;
AT91C_BASE_PIOB->PIO_PDR = gpio;
#else
#error AT91CAP9A-DK works only in RMII mode
at91_set_A_periph(AT91_PIN_PB21, 0); /* ETXCK_EREFCK */
at91_set_A_periph(AT91_PIN_PB22, 0); /* ERXDV */
at91_set_A_periph(AT91_PIN_PB25, 0); /* ERX0 */
at91_set_A_periph(AT91_PIN_PB26, 0); /* ERX1 */
at91_set_A_periph(AT91_PIN_PB27, 0); /* ERXER */
at91_set_A_periph(AT91_PIN_PB28, 0); /* ETXEN */
at91_set_A_periph(AT91_PIN_PB23, 0); /* ETX0 */
at91_set_A_periph(AT91_PIN_PB24, 0); /* ETX1 */
at91_set_A_periph(AT91_PIN_PB30, 0); /* EMDIO */
at91_set_A_periph(AT91_PIN_PB29, 0); /* EMDC */
#ifndef CONFIG_RMII
at91_set_B_periph(AT91_PIN_PC25, 0); /* ECRS */
at91_set_B_periph(AT91_PIN_PC26, 0); /* ECOL */
at91_set_B_periph(AT91_PIN_PC22, 0); /* ERX2 */
at91_set_B_periph(AT91_PIN_PC23, 0); /* ERX3 */
at91_set_B_periph(AT91_PIN_PC27, 0); /* ERXCK */
at91_set_B_periph(AT91_PIN_PC20, 0); /* ETX2 */
at91_set_B_periph(AT91_PIN_PC21, 0); /* ETX3 */
at91_set_B_periph(AT91_PIN_PC24, 0); /* ETXER */
#endif
/* Unlock EMAC, 3 0 2 1 sequence */
#define MP_MAC_KEY0 0x5969cb2a
#define MP_MAC_KEY1 0xb4a1872e
#define MP_MAC_KEY2 0x05683fbc
#define MP_MAC_KEY3 0x3634fba4
#define UNLOCK_MAC 0x00000008
*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x3c)) = MP_MAC_KEY3;
*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x30)) = MP_MAC_KEY0;
*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x38)) = MP_MAC_KEY2;
*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x34)) = MP_MAC_KEY1;
*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x40)) = UNLOCK_MAC;
writel(MP_MAC_KEY3, MP_BLOCK_3_BASE + 0x3c);
writel(MP_MAC_KEY0, MP_BLOCK_3_BASE + 0x30);
writel(MP_MAC_KEY2, MP_BLOCK_3_BASE + 0x38);
writel(MP_MAC_KEY1, MP_BLOCK_3_BASE + 0x34);
writel(UNLOCK_MAC, MP_BLOCK_3_BASE + 0x40);
}
#endif
@ -229,11 +220,11 @@ static void at91cap9_uhp_hw_init(void)
#define MP_OHCI_KEY2 0x4823efbc
#define MP_OHCI_KEY3 0x8651aae4
#define UNLOCK_OHCI 0x00000010
*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x3c)) = MP_OHCI_KEY3;
*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x38)) = MP_OHCI_KEY2;
*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x30)) = MP_OHCI_KEY0;
*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x34)) = MP_OHCI_KEY1;
*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x40)) = UNLOCK_OHCI;
writel(MP_OHCI_KEY3, MP_BLOCK_3_BASE + 0x3c);
writel(MP_OHCI_KEY2, MP_BLOCK_3_BASE + 0x38);
writel(MP_OHCI_KEY0, MP_BLOCK_3_BASE + 0x30);
writel(MP_OHCI_KEY1, MP_BLOCK_3_BASE + 0x34);
writel(UNLOCK_OHCI, MP_BLOCK_3_BASE + 0x40);
}
#endif

43
board/atmel/at91cap9adk/led.c
View File

@ -23,58 +23,55 @@
*/
#include <common.h>
#include <asm/arch/AT91CAP9.h>
#include <asm/arch/at91cap9.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/gpio.h>
#include <asm/arch/io.h>
#define RED_LED AT91C_PIO_PC29 /* this is the power led */
#define GREEN_LED AT91C_PIO_PA10 /* this is the user1 led */
#define YELLOW_LED AT91C_PIO_PA11 /* this is the user1 led */
#define RED_LED AT91_PIN_PC29 /* this is the power led */
#define GREEN_LED AT91_PIN_PA10 /* this is the user1 led */
#define YELLOW_LED AT91_PIN_PA11 /* this is the user1 led */
void red_LED_on(void)
{
AT91C_BASE_PIOC->PIO_SODR = RED_LED;
at91_set_gpio_value(RED_LED, 1);
}
void red_LED_off(void)
{
AT91C_BASE_PIOC->PIO_CODR = RED_LED;
at91_set_gpio_value(RED_LED, 0);
}
void green_LED_on(void)
{
AT91C_BASE_PIOA->PIO_CODR = GREEN_LED;
at91_set_gpio_value(GREEN_LED, 0);
}
void green_LED_off(void)
{
AT91C_BASE_PIOA->PIO_SODR = GREEN_LED;
at91_set_gpio_value(GREEN_LED, 1);
}
void yellow_LED_on(void)
{
AT91C_BASE_PIOA->PIO_CODR = YELLOW_LED;
at91_set_gpio_value(YELLOW_LED, 0);
}
void yellow_LED_off(void)
{
AT91C_BASE_PIOA->PIO_SODR = YELLOW_LED;
at91_set_gpio_value(YELLOW_LED, 1);
}
void coloured_LED_init(void)
{
/* Enable clock */
AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOABCD;
at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_PIOABCD);
/* Disable peripherals on LEDs */
AT91C_BASE_PIOA->PIO_PER = GREEN_LED | YELLOW_LED;
/* Enable pins as outputs */
AT91C_BASE_PIOA->PIO_OER = GREEN_LED | YELLOW_LED;
/* Turn all LEDs OFF */
AT91C_BASE_PIOA->PIO_SODR = GREEN_LED | YELLOW_LED;
at91_set_gpio_output(RED_LED, 1);
at91_set_gpio_output(GREEN_LED, 1);
at91_set_gpio_output(YELLOW_LED, 1);
/* Disable peripherals on LEDs */
AT91C_BASE_PIOC->PIO_PER = RED_LED;
/* Enable pins as outputs */
AT91C_BASE_PIOC->PIO_OER = RED_LED;
/* Turn all LEDs OFF */
AT91C_BASE_PIOC->PIO_CODR = RED_LED;
at91_set_gpio_output(RED_LED, 0);
at91_set_gpio_output(GREEN_LED, 1);
at91_set_gpio_output(YELLOW_LED, 1);
}

11
board/atmel/at91cap9adk/nand.c
View File

@ -25,9 +25,9 @@
*/
#include <common.h>
#include <asm/arch/hardware.h>
#ifdef CONFIG_CMD_NAND
#include <asm/arch/at91cap9.h>
#include <asm/arch/gpio.h>
#include <asm/arch/at91_pio.h>
#include <nand.h>
@ -51,10 +51,10 @@ static void at91cap9adk_nand_hwcontrol(struct mtd_info *mtd, int cmd)
IO_ADDR_W |= MASK_ALE;
break;
case NAND_CTL_CLRNCE:
AT91C_BASE_PIOD->PIO_SODR = AT91C_PIO_PD15;
at91_set_gpio_value(AT91_PIN_PD15, 1);
break;
case NAND_CTL_SETNCE:
AT91C_BASE_PIOD->PIO_CODR = AT91C_PIO_PD15;
at91_set_gpio_value(AT91_PIN_PD15, 0);
break;
}
this->IO_ADDR_W = (void *) IO_ADDR_W;
@ -68,4 +68,3 @@ int board_nand_init(struct nand_chip *nand)
return 0;
}
#endif

52
board/atmel/at91sam9260ek/Makefile Normal file
View File

@ -0,0 +1,52 @@
#
# (C) Copyright 2003-2008
# Wolfgang Denk, DENX Software Engineering, wd <at> denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS-y += at91sam9260ek.o
COBJS-y += led.o
COBJS-$(CONFIG_CMD_NAND) += nand.o
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

236
board/atmel/at91sam9260ek/at91sam9260ek.c Normal file
View File

@ -0,0 +1,236 @@
/*
* (C) Copyright 2007-2008
* Stelian Pop <stelian.pop <at> leadtechdesign.com>
* Lead Tech Design <www.leadtechdesign.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/arch/at91sam9260.h>
#include <asm/arch/at91sam9260_matrix.h>
#include <asm/arch/at91sam926x_mc.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_rstc.h>
#include <asm/arch/gpio.h>
#include <asm/arch/io.h>
#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
#include <net.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
/* ------------------------------------------------------------------------- */
/*
* Miscelaneous platform dependent initialisations
*/
static void at91sam9260ek_serial_hw_init(void)
{
#ifdef CONFIG_USART0
at91_set_A_periph(AT91_PIN_PB4, 1); /* TXD0 */
at91_set_A_periph(AT91_PIN_PB5, 0); /* RXD0 */
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US0);
#endif
#ifdef CONFIG_USART1
at91_set_A_periph(AT91_PIN_PB6, 1); /* TXD1 */
at91_set_A_periph(AT91_PIN_PB7, 0); /* RXD1 */
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US1);
#endif
#ifdef CONFIG_USART2
at91_set_A_periph(AT91_PIN_PB8, 1); /* TXD2 */
at91_set_A_periph(AT91_PIN_PB9, 0); /* RXD2 */
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US2);
#endif
#ifdef CONFIG_USART3 /* DBGU */
at91_set_A_periph(AT91_PIN_PB14, 0); /* DRXD */
at91_set_A_periph(AT91_PIN_PB15, 1); /* DTXD */
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
#endif
}
#ifdef CONFIG_CMD_NAND
static void at91sam9260ek_nand_hw_init(void)
{
unsigned long csa;
/* Enable CS3 */
csa = at91_sys_read(AT91_MATRIX_EBICSA);
at91_sys_write(AT91_MATRIX_EBICSA,
csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
/* Configure SMC CS3 for NAND/SmartMedia */
at91_sys_write(AT91_SMC_SETUP(3),
AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) |
AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
at91_sys_write(AT91_SMC_PULSE(3),
AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
at91_sys_write(AT91_SMC_CYCLE(3),
AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
at91_sys_write(AT91_SMC_MODE(3),
AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
AT91_SMC_EXNWMODE_DISABLE |
AT91_SMC_DBW_8 | AT91_SMC_TDF_(2));
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC);
/* Configure RDY/BSY */
at91_set_gpio_input(AT91_PIN_PC13, 1);
/* Enable NandFlash */
at91_set_gpio_output(AT91_PIN_PC14, 1);
}
#endif
#ifdef CONFIG_HAS_DATAFLASH
static void at91sam9260ek_spi_hw_init(void)
{
at91_set_A_periph(AT91_PIN_PA3, 0); /* SPI0_NPCS0 */
at91_set_B_periph(AT91_PIN_PC11, 0); /* SPI0_NPCS1 */
at91_set_A_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */
at91_set_A_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */
at91_set_A_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */
/* Enable clock */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_SPI0);
}
#endif
#ifdef CONFIG_MACB
static void at91sam9260ek_macb_hw_init(void)
{
/* Enable clock */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC);
/*
* Disable pull-up on:
* RXDV (PA17) => PHY normal mode (not Test mode)
* ERX0 (PA14) => PHY ADDR0
* ERX1 (PA15) => PHY ADDR1
* ERX2 (PA25) => PHY ADDR2
* ERX3 (PA26) => PHY ADDR3
* ECRS (PA28) => PHY ADDR4 => PHYADDR = 0x0
*
* PHY has internal pull-down
*/
writel(pin_to_mask(AT91_PIN_PA14) |
pin_to_mask(AT91_PIN_PA15) |
pin_to_mask(AT91_PIN_PA17) |
pin_to_mask(AT91_PIN_PA25) |
pin_to_mask(AT91_PIN_PA26) |
pin_to_mask(AT91_PIN_PA28),
pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);
/* Need to reset PHY -> 500ms reset */
at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
AT91_RSTC_ERSTL | (0x0D << 8) |
AT91_RSTC_URSTEN);
at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
/* Wait for end hardware reset */
while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
/* Restore NRST value */
at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
AT91_RSTC_ERSTL | (0x0 << 8) |
AT91_RSTC_URSTEN);
/* Re-enable pull-up */
writel(pin_to_mask(AT91_PIN_PA14) |
pin_to_mask(AT91_PIN_PA15) |
pin_to_mask(AT91_PIN_PA17) |
pin_to_mask(AT91_PIN_PA25) |
pin_to_mask(AT91_PIN_PA26) |
pin_to_mask(AT91_PIN_PA28),
pin_to_controller(AT91_PIN_PA0) + PIO_PUER);
at91_set_A_periph(AT91_PIN_PA19, 0); /* ETXCK_EREFCK */
at91_set_A_periph(AT91_PIN_PA17, 0); /* ERXDV */
at91_set_A_periph(AT91_PIN_PA14, 0); /* ERX0 */
at91_set_A_periph(AT91_PIN_PA15, 0); /* ERX1 */
at91_set_A_periph(AT91_PIN_PA18, 0); /* ERXER */
at91_set_A_periph(AT91_PIN_PA16, 0); /* ETXEN */
at91_set_A_periph(AT91_PIN_PA12, 0); /* ETX0 */
at91_set_A_periph(AT91_PIN_PA13, 0); /* ETX1 */
at91_set_A_periph(AT91_PIN_PA21, 0); /* EMDIO */
at91_set_A_periph(AT91_PIN_PA20, 0); /* EMDC */
#ifndef CONFIG_RMII
at91_set_B_periph(AT91_PIN_PA28, 0); /* ECRS */
at91_set_B_periph(AT91_PIN_PA29, 0); /* ECOL */
at91_set_B_periph(AT91_PIN_PA25, 0); /* ERX2 */
at91_set_B_periph(AT91_PIN_PA26, 0); /* ERX3 */
at91_set_B_periph(AT91_PIN_PA27, 0); /* ERXCK */
at91_set_B_periph(AT91_PIN_PA23, 0); /* ETX2 */
at91_set_B_periph(AT91_PIN_PA24, 0); /* ETX3 */
at91_set_B_periph(AT91_PIN_PA22, 0); /* ETXER */
#endif
}
#endif
int board_init(void)
{
/* Enable Ctrlc */
console_init_f();
/* arch number of AT91SAM9260EK-Board */
gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9260EK;
/* adress of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
at91sam9260ek_serial_hw_init();
#ifdef CONFIG_CMD_NAND
at91sam9260ek_nand_hw_init();
#endif
#ifdef CONFIG_HAS_DATAFLASH
at91sam9260ek_spi_hw_init();
#endif
#ifdef CONFIG_MACB
at91sam9260ek_macb_hw_init();
#endif
return 0;
}
int dram_init(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM;
gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
return 0;
}
#ifdef CONFIG_RESET_PHY_R
void reset_phy(void)
{
#ifdef CONFIG_MACB
/*
* Initialize ethernet HW addr prior to starting Linux,
* needed for nfsroot
*/
eth_init(gd->bd);
#endif
}
#endif

1
board/atmel/at91sam9260ek/config.mk Normal file
View File

@ -0,0 +1 @@
TEXT_BASE = 0x23f00000

64
board/atmel/at91sam9260ek/led.c Normal file
View File

@ -0,0 +1,64 @@
/*
* (C) Copyright 2007-2008
* Stelian Pop <stelian.pop <at> leadtechdesign.com>
* Lead Tech Design <www.leadtechdesign.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/arch/at91sam9260.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/gpio.h>
#include <asm/arch/io.h>
#define RED_LED AT91_PIN_PA9 /* this is the power led */
#define GREEN_LED AT91_PIN_PA6 /* this is the user led */
void red_LED_on(void)
{
at91_set_gpio_value(RED_LED, 1);
}
void red_LED_off(void)
{
at91_set_gpio_value(RED_LED, 0);
}
void green_LED_on(void)
{
at91_set_gpio_value(GREEN_LED, 0);
}
void green_LED_off(void)
{
at91_set_gpio_value(GREEN_LED, 1);
}
void coloured_LED_init(void)
{
/* Enable clock */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOA);
at91_set_gpio_output(RED_LED, 1);
at91_set_gpio_output(GREEN_LED, 1);
at91_set_gpio_value(RED_LED, 0);
at91_set_gpio_value(GREEN_LED, 1);
}

76
board/atmel/at91sam9260ek/nand.c Normal file
View File

@ -0,0 +1,76 @@
/*
* (C) Copyright 2007-2008
* Stelian Pop <stelian.pop <at> leadtechdesign.com>
* Lead Tech Design <www.leadtechdesign.com>
*
* (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/arch/at91sam9260.h>
#include <asm/arch/gpio.h>
#include <asm/arch/at91_pio.h>
#include <nand.h>
/*
* hardware specific access to control-lines
*/
#define MASK_ALE (1 << 21) /* our ALE is AD21 */
#define MASK_CLE (1 << 22) /* our CLE is AD22 */
static void at91sam9260ek_nand_hwcontrol(struct mtd_info *mtd, int cmd)
{
struct nand_chip *this = mtd->priv;
ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);
switch (cmd) {
case NAND_CTL_SETCLE:
IO_ADDR_W |= MASK_CLE;
break;
case NAND_CTL_SETALE:
IO_ADDR_W |= MASK_ALE;
break;
case NAND_CTL_CLRNCE:
at91_set_gpio_value(AT91_PIN_PC14, 1);
break;
case NAND_CTL_SETNCE:
at91_set_gpio_value(AT91_PIN_PC14, 0);
break;
}
this->IO_ADDR_W = (void *) IO_ADDR_W;
}
static int at91sam9260ek_nand_ready(struct mtd_info *mtd)
{
return at91_get_gpio_value(AT91_PIN_PC13);
}
int board_nand_init(struct nand_chip *nand)
{
nand->eccmode = NAND_ECC_SOFT;
nand->hwcontrol = at91sam9260ek_nand_hwcontrol;
nand->dev_ready = at91sam9260ek_nand_ready;
nand->chip_delay = 20;
return 0;
}

57
board/atmel/at91sam9260ek/u-boot.lds Normal file
View File

@ -0,0 +1,57 @@
/*
* (C) Copyright 2002
* Gary Jennejohn, DENX Software Engineering, <gj <at> denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/
OUTPUT_ARCH(arm)
ENTRY(_start)
SECTIONS
{
. = 0x00000000;
. = ALIGN(4);
.text :
{
cpu/arm926ejs/start.o (.text)
*(.text)
}
. = ALIGN(4);
.rodata : { *(.rodata) }
. = ALIGN(4);
.data : { *(.data) }
. = ALIGN(4);
.got : { *(.got) }
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = ALIGN(4);
__bss_start = .;
.bss : { *(.bss) }
_end = .;
}

8
board/m501sk/memsetup.S
View File

@ -52,8 +52,8 @@
#define MC_AASR_VAL 0x00000000
#define EBI_CFGR 0xFFFFFF64
#define EBI_CFGR_VAL 0x00000000
#define SMC2_CSR 0xFFFFFF70
#define SMC2_CSR_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
#define SMC_CSR0 0xFFFFFF70
#define SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
/* clocks */
#define PLLAR 0xFFFFFC28
@ -141,8 +141,8 @@ SMRDATA:
.word MC_AASR_VAL
.word EBI_CFGR
.word EBI_CFGR_VAL
.word SMC2_CSR
.word SMC2_CSR_VAL
.word SMC_CSR0
.word SMC_CSR0_VAL
.word PLLAR
.word PLLAR_VAL
.word PLLBR

25
common/cmd_flash.c
View File

@ -41,6 +41,7 @@ int find_dev_and_part(const char *id, struct mtd_device **dev,
u8 *part_num, struct part_info **part);
#endif
#ifndef CFG_NO_FLASH
extern flash_info_t flash_info[]; /* info for FLASH chips */
/*
@ -275,15 +276,19 @@ flash_fill_sect_ranges (ulong addr_first, ulong addr_last,
return rcode;
}
#endif /* CFG_NO_FLASH */
int do_flinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
#ifndef CFG_NO_FLASH
ulong bank;
#endif
#ifdef CONFIG_HAS_DATAFLASH
dataflash_print_info();
#endif
#ifndef CFG_NO_FLASH
if (argc == 1) { /* print info for all FLASH banks */
for (bank=0; bank <CFG_MAX_FLASH_BANKS; ++bank) {
printf ("\nBank # %ld: ", bank+1);
@ -301,11 +306,13 @@ int do_flinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
printf ("\nBank # %ld: ", bank);
flash_print_info (&flash_info[bank-1]);
#endif /* CFG_NO_FLASH */
return 0;
}
int do_flerase (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
#ifndef CFG_NO_FLASH
flash_info_t *info;
ulong bank, addr_first, addr_last;
int n, sect_first, sect_last;
@ -397,8 +404,12 @@ int do_flerase (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
rcode = flash_sect_erase(addr_first, addr_last);
return rcode;
#else
return 0;
#endif /* CFG_NO_FLASH */
}
#ifndef CFG_NO_FLASH
int flash_sect_erase (ulong addr_first, ulong addr_last)
{
flash_info_t *info;
@ -439,12 +450,17 @@ int flash_sect_erase (ulong addr_first, ulong addr_last)
}
return rcode;
}
#endif /* CFG_NO_FLASH */
int do_protect (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
#ifndef CFG_NO_FLASH
flash_info_t *info;
ulong bank, addr_first, addr_last;
int i, p, n, sect_first, sect_last;
ulong bank;
int i, n, sect_first, sect_last;
#endif /* CFG_NO_FLASH */
ulong addr_first, addr_last;
int p;
#if defined(CONFIG_CMD_JFFS2) && defined(CONFIG_JFFS2_CMDLINE)
struct mtd_device *dev;
struct part_info *part;
@ -487,6 +503,7 @@ int do_protect (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
#endif
#ifndef CFG_NO_FLASH
if (strcmp(argv[2], "all") == 0) {
for (bank=1; bank<=CFG_MAX_FLASH_BANKS; ++bank) {
info = &flash_info[bank-1];
@ -611,10 +628,11 @@ int do_protect (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
return 1;
}
rcode = flash_sect_protect (p, addr_first, addr_last);
#endif /* CFG_NO_FLASH */
return rcode;
}
#ifndef CFG_NO_FLASH
int flash_sect_protect (int p, ulong addr_first, ulong addr_last)
{
flash_info_t *info;
@ -667,6 +685,7 @@ int flash_sect_protect (int p, ulong addr_first, ulong addr_last)
}
return rcode;
}
#endif /* CFG_NO_FLASH */
/**************************************************/

6
common/cmd_mem.c
View File

@ -492,7 +492,11 @@ int do_mem_cp ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
/* Check if we are copying from DataFlash to RAM */
if (addr_dataflash(addr) && !addr_dataflash(dest) && (addr2info(dest)==NULL) ){
if (addr_dataflash(addr) && !addr_dataflash(dest)
#ifndef CFG_NO_FLASH
&& (addr2info(dest) == NULL)
#endif
){
int rc;
rc = read_dataflash(addr, count * size, (char *) dest);
if (rc != 1) {

6
cpu/arm920t/at91rm9200/lowlevel_init.S
View File

@ -46,7 +46,7 @@
#define MC_ASR 0xFFFFFF04
#define MC_AASR 0xFFFFFF08
#define EBI_CFGR 0xFFFFFF64
#define SMC2_CSR 0xFFFFFF70
#define SMC_CSR0 0xFFFFFF70
/* clocks */
#define PLLAR 0xFFFFFC28
@ -146,8 +146,8 @@ SMRDATA:
.word MC_AASR_VAL
.word EBI_CFGR
.word EBI_CFGR_VAL
.word SMC2_CSR
.word SMC2_CSR_VAL
.word SMC_CSR0
.word SMC_CSR0_VAL
.word PLLAR
.word PLLAR_VAL
.word PLLBR

119
cpu/arm926ejs/at91cap9/spi.c
View File

@ -1,119 +0,0 @@
/*
* Driver for ATMEL DataFlash support
* Author : Hamid Ikdoumi (Atmel)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#include <config.h>
#include <common.h>
#include <asm/hardware.h>
#ifdef CONFIG_HAS_DATAFLASH
#include <dataflash.h>
/* Max Value = 10MHz to be compliant to the Continuous Array Read function */
#define AT91C_SPI_CLK 10000000
/* AC Characteristics: DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns */
#define DATAFLASH_TCSS (0xFA << 16)
#define DATAFLASH_TCHS (0x8 << 24)
#define AT91C_TIMEOUT_WRDY 200000
#define AT91C_SPI_PCS0_DATAFLASH_CARD 0xE /* Chip Select 0: NPCS0%1110 */
#define AT91C_SPI_PCS3_DATAFLASH_CARD 0x7 /* Chip Select 3: NPCS3%0111 */
void AT91F_SpiInit(void)
{
/* Reset the SPI */
AT91C_BASE_SPI0->SPI_CR = AT91C_SPI_SWRST;
/* Configure SPI in Master Mode with No CS selected !!! */
AT91C_BASE_SPI0->SPI_MR =
AT91C_SPI_MSTR | AT91C_SPI_MODFDIS | AT91C_SPI_PCS;
/* Configure CS0 */
AT91C_BASE_SPI0->SPI_CSR[0] =
AT91C_SPI_CPOL |
(AT91C_SPI_DLYBS & DATAFLASH_TCSS) |
(AT91C_SPI_DLYBCT & DATAFLASH_TCHS) |
((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8);
}
void AT91F_SpiEnable(int cs)
{
switch (cs) {
case 0: /* Configure SPI CS0 for Serial DataFlash AT45DBxx */
AT91C_BASE_SPI0->SPI_MR &= 0xFFF0FFFF;
AT91C_BASE_SPI0->SPI_MR |=
((AT91C_SPI_PCS0_DATAFLASH_CARD<<16) & AT91C_SPI_PCS);
break;
case 3:
AT91C_BASE_SPI0->SPI_MR &= 0xFFF0FFFF;
AT91C_BASE_SPI0->SPI_MR |=
((AT91C_SPI_PCS3_DATAFLASH_CARD<<16) & AT91C_SPI_PCS);
break;
}
/* SPI_Enable */
AT91C_BASE_SPI0->SPI_CR = AT91C_SPI_SPIEN;
}
unsigned int AT91F_SpiWrite(AT91PS_DataflashDesc pDesc)
{
unsigned int timeout;
pDesc->state = BUSY;
AT91C_BASE_SPI0->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS;
/* Initialize the Transmit and Receive Pointer */
AT91C_BASE_SPI0->SPI_RPR = (unsigned int)pDesc->rx_cmd_pt;
AT91C_BASE_SPI0->SPI_TPR = (unsigned int)pDesc->tx_cmd_pt;
/* Intialize the Transmit and Receive Counters */
AT91C_BASE_SPI0->SPI_RCR = pDesc->rx_cmd_size;
AT91C_BASE_SPI0->SPI_TCR = pDesc->tx_cmd_size;
if (pDesc->tx_data_size != 0) {
/* Initialize the Next Transmit and Next Receive Pointer */
AT91C_BASE_SPI0->SPI_RNPR = (unsigned int)pDesc->rx_data_pt;
AT91C_BASE_SPI0->SPI_TNPR = (unsigned int)pDesc->tx_data_pt;
/* Intialize the Next Transmit and Next Receive Counters */
AT91C_BASE_SPI0->SPI_RNCR = pDesc->rx_data_size;
AT91C_BASE_SPI0->SPI_TNCR = pDesc->tx_data_size;
}
/* arm simple, non interrupt dependent timer */
reset_timer_masked();
timeout = 0;
AT91C_BASE_SPI0->SPI_PTCR = AT91C_PDC_TXTEN + AT91C_PDC_RXTEN;
while (!(AT91C_BASE_SPI0->SPI_SR & AT91C_SPI_RXBUFF) &&
((timeout = get_timer_masked()) < CFG_SPI_WRITE_TOUT));
AT91C_BASE_SPI0->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS;
pDesc->state = IDLE;
if (timeout >= CFG_SPI_WRITE_TOUT) {
printf("Error Timeout\n\r");
return DATAFLASH_ERROR;
}
return DATAFLASH_OK;
}
#endif

9
cpu/arm926ejs/at91cap9/Makefile → cpu/arm926ejs/at91sam9/Makefile
View File

@ -25,11 +25,14 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(SOC).a
COBJS = ether.o timer.o spi.o usb.o
COBJS-y += ether.o
COBJS-y += timer.o
COBJS-$(CONFIG_HAS_DATAFLASH) +=spi.o
COBJS-y += usb.o
SOBJS = lowlevel_init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y))
all: $(obj).depend $(LIB)

0
cpu/arm926ejs/at91cap9/config.mk → cpu/arm926ejs/at91sam9/config.mk
View File

6
cpu/arm926ejs/at91cap9/ether.c → cpu/arm926ejs/at91sam9/ether.c
View File

@ -23,13 +23,13 @@
*/
#include <common.h>
#include <asm/arch/AT91CAP9.h>
#include <asm/arch/hardware.h>
extern int macb_eth_initialize(int id, void *regs, unsigned int phy_addr);
#if defined(CONFIG_MACB) && defined(CONFIG_CMD_NET)
void at91cap9_eth_initialize(bd_t *bi)
void at91sam9_eth_initialize(bd_t *bi)
{
macb_eth_initialize(0, (void *)AT91C_BASE_MACB, 0x00);
macb_eth_initialize(0, (void *)AT91_BASE_EMAC, 0x00);
}
#endif

2
cpu/arm926ejs/at91cap9/lowlevel_init.S → cpu/arm926ejs/at91sam9/lowlevel_init.S
View File

@ -1,5 +1,5 @@
/*
* AT91CAP9 setup stuff
* AT91CAP9/SAM9 setup stuff
*
* (C) Copyright 2007-2008
* Stelian Pop <stelian.pop <at> leadtechdesign.com>

157
cpu/arm926ejs/at91sam9/spi.c Normal file
View File

@ -0,0 +1,157 @@
/*
* Driver for ATMEL DataFlash support
* Author : Hamid Ikdoumi (Atmel)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#include <common.h>
#include <asm/arch/hardware.h>
#include <asm/arch/gpio.h>
#include <asm/arch/io.h>
#include <asm/arch/at91_pio.h>
#include <asm/arch/at91_spi.h>
#include <dataflash.h>
#define AT91_SPI_PCS0_DATAFLASH_CARD 0xE /* Chip Select 0: NPCS0%1110 */
#define AT91_SPI_PCS1_DATAFLASH_CARD 0xD /* Chip Select 0: NPCS0%1101 */
#define AT91_SPI_PCS3_DATAFLASH_CARD 0x7 /* Chip Select 3: NPCS3%0111 */
void AT91F_SpiInit(void)
{
/* Reset the SPI */
writel(AT91_SPI_SWRST, AT91_BASE_SPI + AT91_SPI_CR);
/* Configure SPI in Master Mode with No CS selected !!! */
writel(AT91_SPI_MSTR | AT91_SPI_MODFDIS | AT91_SPI_PCS,
AT91_BASE_SPI + AT91_SPI_MR);
/* Configure CS0 */
writel(AT91_SPI_NCPHA |
(AT91_SPI_DLYBS & DATAFLASH_TCSS) |
(AT91_SPI_DLYBCT & DATAFLASH_TCHS) |
((AT91_MASTER_CLOCK / AT91_SPI_CLK) << 8),
AT91_BASE_SPI + AT91_SPI_CSR(0));
#ifdef CFG_DATAFLASH_LOGIC_ADDR_CS1
/* Configure CS1 */
writel(AT91_SPI_NCPHA |
(AT91_SPI_DLYBS & DATAFLASH_TCSS) |
(AT91_SPI_DLYBCT & DATAFLASH_TCHS) |
((AT91_MASTER_CLOCK / AT91_SPI_CLK) << 8),
AT91_BASE_SPI + AT91_SPI_CSR(1));
#endif
#ifdef CFG_DATAFLASH_LOGIC_ADDR_CS3
/* Configure CS3 */
writel(AT91_SPI_NCPHA |
(AT91_SPI_DLYBS & DATAFLASH_TCSS) |
(AT91_SPI_DLYBCT & DATAFLASH_TCHS) |
((AT91_MASTER_CLOCK / AT91_SPI_CLK) << 8),
AT91_BASE_SPI + AT91_SPI_CSR(3));
#endif
/* SPI_Enable */
writel(AT91_SPI_SPIEN, AT91_BASE_SPI + AT91_SPI_CR);
while (!(readl(AT91_BASE_SPI + AT91_SPI_SR) & AT91_SPI_SPIENS));
/*
* Add tempo to get SPI in a safe state.
* Should not be needed for new silicon (Rev B)
*/
udelay(500000);
readl(AT91_BASE_SPI + AT91_SPI_SR);
readl(AT91_BASE_SPI + AT91_SPI_RDR);
}
void AT91F_SpiEnable(int cs)
{
unsigned long mode;
switch (cs) {
case 0: /* Configure SPI CS0 for Serial DataFlash AT45DBxx */
mode = readl(AT91_BASE_SPI + AT91_SPI_MR);
mode &= 0xFFF0FFFF;
writel(mode | ((AT91_SPI_PCS0_DATAFLASH_CARD<<16) & AT91_SPI_PCS),
AT91_BASE_SPI + AT91_SPI_MR);
break;
case 1: /* Configure SPI CS1 for Serial DataFlash AT45DBxx */
mode = readl(AT91_BASE_SPI + AT91_SPI_MR);
mode &= 0xFFF0FFFF;
writel(mode | ((AT91_SPI_PCS1_DATAFLASH_CARD<<16) & AT91_SPI_PCS),
AT91_BASE_SPI + AT91_SPI_MR);
break;
case 3:
mode = readl(AT91_BASE_SPI + AT91_SPI_MR);
mode &= 0xFFF0FFFF;
writel(mode | ((AT91_SPI_PCS3_DATAFLASH_CARD<<16) & AT91_SPI_PCS),
AT91_BASE_SPI + AT91_SPI_MR);
break;
}
/* SPI_Enable */
writel(AT91_SPI_SPIEN, AT91_BASE_SPI + AT91_SPI_CR);
}
unsigned int AT91F_SpiWrite1(AT91PS_DataflashDesc pDesc);
unsigned int AT91F_SpiWrite(AT91PS_DataflashDesc pDesc)
{
unsigned int timeout;
pDesc->state = BUSY;
writel(AT91_SPI_TXTDIS + AT91_SPI_RXTDIS, AT91_BASE_SPI + AT91_SPI_PTCR);
/* Initialize the Transmit and Receive Pointer */
writel((unsigned int)pDesc->rx_cmd_pt, AT91_BASE_SPI + AT91_SPI_RPR);
writel((unsigned int)pDesc->tx_cmd_pt, AT91_BASE_SPI + AT91_SPI_TPR);
/* Intialize the Transmit and Receive Counters */
writel(pDesc->rx_cmd_size, AT91_BASE_SPI + AT91_SPI_RCR);
writel(pDesc->tx_cmd_size, AT91_BASE_SPI + AT91_SPI_TCR);
if (pDesc->tx_data_size != 0) {
/* Initialize the Next Transmit and Next Receive Pointer */
writel((unsigned int)pDesc->rx_data_pt, AT91_BASE_SPI + AT91_SPI_RNPR);
writel((unsigned int)pDesc->tx_data_pt, AT91_BASE_SPI + AT91_SPI_TNPR);
/* Intialize the Next Transmit and Next Receive Counters */
writel(pDesc->rx_data_size, AT91_BASE_SPI + AT91_SPI_RNCR);
writel(pDesc->tx_data_size, AT91_BASE_SPI + AT91_SPI_TNCR);
}
/* arm simple, non interrupt dependent timer */
reset_timer_masked();
timeout = 0;
writel(AT91_SPI_TXTEN + AT91_SPI_RXTEN, AT91_BASE_SPI + AT91_SPI_PTCR);
while (!(readl(AT91_BASE_SPI + AT91_SPI_SR) & AT91_SPI_RXBUFF) &&
((timeout = get_timer_masked()) < CFG_SPI_WRITE_TOUT));
writel(AT91_SPI_TXTDIS + AT91_SPI_RXTDIS, AT91_BASE_SPI + AT91_SPI_PTCR);
pDesc->state = IDLE;
if (timeout >= CFG_SPI_WRITE_TOUT) {
printf("Error Timeout\n\r");
return DATAFLASH_ERROR;
}
return DATAFLASH_OK;
}

32
cpu/arm926ejs/at91cap9/timer.c → cpu/arm926ejs/at91sam9/timer.c
View File

@ -24,36 +24,35 @@
#include <common.h>
#include <asm/arch/hardware.h>
#include <asm/arch/at91_pit.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_rstc.h>
#include <asm/arch/io.h>
/*
* We're using the AT91CAP9 PITC in 32 bit mode, by
* We're using the AT91CAP9/SAM9 PITC in 32 bit mode, by
* setting the 20 bit counter period to its maximum (0xfffff).
*/
#define TIMER_LOAD_VAL 0xfffff
#define READ_RESET_TIMER (AT91C_BASE_PITC->PITC_PIVR)
#define READ_TIMER (AT91C_BASE_PITC->PITC_PIIR)
#define READ_RESET_TIMER at91_sys_read(AT91_PIT_PIVR)
#define READ_TIMER at91_sys_read(AT91_PIT_PIIR)
#define TIMER_FREQ (AT91C_MASTER_CLOCK << 4)
#define TICKS_TO_USEC(ticks) ((ticks) / 6)
ulong get_timer_masked(void);
ulong resettime;
AT91PS_PITC p_pitc;
/* nothing really to do with interrupts, just starts up a counter. */
int interrupt_init(void)
int timer_init(void)
{
/*
* Enable PITC Clock
* The clock is already enabled for system controller in boot
*/
AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_SYS;
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
/* Enable PITC */
AT91C_BASE_PITC->PITC_PIMR = AT91C_PITC_PITEN;
/* Load PITC_PIMR with the right timer value */
AT91C_BASE_PITC->PITC_PIMR |= TIMER_LOAD_VAL;
at91_sys_write(AT91_PIT_MR, TIMER_LOAD_VAL | AT91_PIT_PITEN);
reset_timer_masked();
@ -67,6 +66,7 @@ int interrupt_init(void)
static inline ulong get_timer_raw(void)
{
ulong now = READ_TIMER;
if (now >= resettime)
return now - resettime;
else
@ -129,20 +129,20 @@ unsigned long long get_ticks(void)
ulong get_tbclk(void)
{
ulong tbclk;
tbclk = CFG_HZ;
return tbclk;
}
/*
* Reset the cpu by setting up the watchdog timer and let him time out
* on the AT91CAP9ADK board
* Reset the cpu by setting up the watchdog timer and let him time out.
*/
void reset_cpu(ulong ignored)
{
/* this is the way Linux does it */
AT91C_BASE_RSTC->RSTC_RCR = (0xA5 << 24) |
AT91C_RSTC_PROCRST |
AT91C_RSTC_PERRST;
at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY |
AT91_RSTC_PROCRST |
AT91_RSTC_PERRST);
while (1);
/* Never reached */

12
cpu/arm926ejs/at91cap9/usb.c → cpu/arm926ejs/at91sam9/usb.c
View File

@ -24,15 +24,16 @@
#include <common.h>
#if defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_CPU_INIT)
#ifdef CONFIG_AT91CAP9
#include <asm/arch/hardware.h>
#include <asm/arch/io.h>
#include <asm/arch/at91_pmc.h>
int usb_cpu_init(void)
{
/* Enable USB host clock. */
AT91C_BASE_PMC->PMC_SCER = AT91C_PMC_UHP;
AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_UHP;
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_UHP);
at91_sys_write(AT91_PMC_SCER, AT91_PMC_UHP);
return 0;
}
@ -40,8 +41,8 @@ int usb_cpu_init(void)
int usb_cpu_stop(void)
{
/* Disable USB host clock. */
AT91C_BASE_PMC->PMC_PCDR = 1 << AT91C_ID_UHP;
AT91C_BASE_PMC->PMC_SCDR = AT91C_PMC_UHP;
at91_sys_write(AT91_PMC_PCDR, 1 << AT91_ID_UHP);
at91_sys_write(AT91_PMC_SCDR, AT91_PMC_UHP);
return 0;
}
@ -50,5 +51,4 @@ int usb_cpu_init_fail(void)
return usb_cpu_stop();
}
#endif /* CONFIG_AT91CAP9 */
#endif /* defined(CONFIG_USB_OHCI) && defined(CFG_USB_OHCI_CPU_INIT) */

2
cpu/arm926ejs/interrupts.c
View File

@ -38,7 +38,7 @@
#include <common.h>
#include <arm926ejs.h>
#if defined(CONFIG_INTEGRATOR) || defined(CONFIG_AT91CAP9ADK)
#ifdef CONFIG_INTEGRATOR
/* Timer functionality supplied by Integrator board (AP or CP) */

8
drivers/mtd/Makefile
View File

@ -23,17 +23,17 @@
include $(TOPDIR)/config.mk
LIB := $(obj)libmtd.a
LIB := $(obj)libmtd.a
COBJS-y += at45.o
COBJS-y += cfi_flash.o
COBJS-y += dataflash.o
COBJS-$(CONFIG_HAS_DATAFLASH) += dataflash.o
COBJS-y += mw_eeprom.o
COBJS-$(CONFIG_FLASH_CFI_LEGACY) += jedec_flash.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
all: $(LIB)

83
drivers/mtd/dataflash.c
View File

@ -19,7 +19,6 @@
*/
#include <common.h>
#include <config.h>
#ifdef CONFIG_HAS_DATAFLASH
#include <asm/hardware.h>
#include <dataflash.h>
@ -31,7 +30,7 @@ struct dataflash_addr {
int cs;
};
#ifdef CONFIG_AT91SAM9260EK
#if defined(CONFIG_AT91SAM9260EK)
struct dataflash_addr cs[CFG_MAX_DATAFLASH_BANKS] = {
{CFG_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */
{CFG_DATAFLASH_LOGIC_ADDR_CS1, 1}
@ -48,51 +47,13 @@ struct dataflash_addr cs[CFG_MAX_DATAFLASH_BANKS] = {
#endif
/*define the area offsets*/
#if defined(CONFIG_AT91SAM9261EK) || defined(CONFIG_AT91SAM9260EK) || \
defined(CONFIG_AT91SAM9263EK) || defined(CONFIG_AT91CAP9ADK)
#if defined(CONFIG_NEW_PARTITION)
dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
{0x00000000, 0x00003FFF, FLAG_PROTECT_SET, 0, "Bootstrap"}, /* ROM code */
{0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"}, /* u-boot environment */
{0x00008400, 0x0003DDFF, FLAG_PROTECT_SET, 0, "U-Boot"}, /* u-boot code */
{0x0003DE00, 0x00041FFF, FLAG_PROTECT_CLEAR, FLAG_SETENV, "MON"}, /* Room for alternative boot monitor */
{0x00042000, 0x0018BFFF, FLAG_PROTECT_CLEAR, FLAG_SETENV, "OS"}, /* data area size to tune */
{0x0018C000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, FLAG_SETENV, "FS"}, /* data area size to tune */
{0x00000000, 0x000041FF, FLAG_PROTECT_SET, 0, "Bootstrap"},
{0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
{0x00008400, 0x0003DDFF, FLAG_PROTECT_SET, 0, "U-Boot"},
{0x0003DE00, 0x0023DE3F, FLAG_PROTECT_CLEAR, 0, "Kernel"},
{0x0023DE40, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "FS"},
};
#else
dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
{0, 0x3fff, FLAG_PROTECT_SET}, /* ROM code */
{0x4000, 0x7fff, FLAG_PROTECT_CLEAR}, /* u-boot environment */
{0x8000, 0x37fff, FLAG_PROTECT_SET}, /* u-boot code */
{0x38000, 0x1fffff, FLAG_PROTECT_CLEAR}, /* data area size to tune */
};
#endif
#elif defined(CONFIG_NEW_PARTITION)
/*define the area offsets*/
/* Invalid partitions should be defined with start > end */
dataflash_protect_t area_list[NB_DATAFLASH_AREA*CFG_MAX_DATAFLASH_BANKS] = {
{0x00000000, 0x000083ff, FLAG_PROTECT_SET, 0, "Bootstrap"}, /* ROM code */
{0x00008400, 0x00020fff, FLAG_PROTECT_SET, 0, "U-Boot"}, /* u-boot code */
{0x00021000, 0x000293ff, FLAG_PROTECT_CLEAR, 0, "Environment"}, /* u-boot environment 8Kb */
{0x00029400, 0x00041fff, FLAG_PROTECT_INVALID, 0, "<Unused>"}, /* Rest of Sector 1 */
{0x00042000, 0x0018Bfff, FLAG_PROTECT_CLEAR, FLAG_SETENV, "OS"}, /* data area size to tune */
{0x0018C000, 0xffffffff, FLAG_PROTECT_CLEAR, FLAG_SETENV, "FS"}, /* data area size to tune */
{0x00000000, 0xffffffff, FLAG_PROTECT_CLEAR, FLAG_SETENV, "Data"}, /* data area */
{0xffffffff, 0x00000000, FLAG_PROTECT_INVALID, 0, "<Invalid>"}, /* Invalid */
{0xffffffff, 0x00000000, FLAG_PROTECT_INVALID, 0, "<Invalid>"}, /* Invalid */
{0xffffffff, 0x00000000, FLAG_PROTECT_INVALID, 0, "<Invalid>"}, /* Invalid */
{0xffffffff, 0x00000000, FLAG_PROTECT_INVALID, 0, "<Invalid>"}, /* Invalid */
{0xffffffff, 0x00000000, FLAG_PROTECT_INVALID, 0, "<Invalid>"}, /* Invalid */
};
#else
dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
{0, 0x7fff, FLAG_PROTECT_SET}, /* ROM code */
{0x8000, 0x1ffff, FLAG_PROTECT_SET}, /* u-boot code */
{0x20000, 0x27fff, FLAG_PROTECT_CLEAR}, /* u-boot environment */
{0x28000, 0x1fffff, FLAG_PROTECT_CLEAR}, /* data area size to tune */
};
#endif
extern void AT91F_SpiInit (void);
extern int AT91F_DataflashProbe (int i, AT91PS_DataflashDesc pDesc);
@ -108,7 +69,7 @@ int AT91F_DataflashInit (void)
{
int i, j;
int dfcode;
int part = 0;
int part;
int last_part;
int found[CFG_MAX_DATAFLASH_BANKS];
unsigned char protected;
@ -181,7 +142,8 @@ int AT91F_DataflashInit (void)
(dataflash_info[i].Device.pages_number *
dataflash_info[i].Device.pages_size)-1;
last_part=0;
part = 0;
last_part = 0;
/* set the area addresses */
for(j = 0; j<NB_DATAFLASH_AREA; j++) {
if(found[i]!=0) {
@ -224,6 +186,7 @@ int AT91F_DataflashSetEnv (void)
unsigned char env;
unsigned char s[32]; /* Will fit a long int in hex */
unsigned long start;
for (i = 0, part= 0; i < CFG_MAX_DATAFLASH_BANKS; i++) {
for(j = 0; j<NB_DATAFLASH_AREA; j++) {
env = area_list[part].setenv;
@ -297,9 +260,8 @@ void dataflash_print_info (void)
}
}
/*---------------------------------------------------------------------------*/
/* Function Name : AT91F_DataflashSelect */
/* Function Name : AT91F_DataflashSelect */
/* Object : Select the correct device */
/*---------------------------------------------------------------------------*/
AT91PS_DataFlash AT91F_DataflashSelect (AT91PS_DataFlash pFlash,
@ -326,7 +288,7 @@ AT91PS_DataFlash AT91F_DataflashSelect (AT91PS_DataFlash pFlash,
}
/*---------------------------------------------------------------------------*/
/* Function Name : addr_dataflash */
/* Function Name : addr_dataflash */
/* Object : Test if address is valid */
/*---------------------------------------------------------------------------*/
int addr_dataflash (unsigned long addr)
@ -344,8 +306,9 @@ int addr_dataflash (unsigned long addr)
return addr_valid;
}
/*---------------------------------------------------------------------------*/
/* Function Name : size_dataflash */
/* Function Name : size_dataflash */
/* Object : Test if address is valid regarding the size */
/*---------------------------------------------------------------------------*/
int size_dataflash (AT91PS_DataFlash pdataFlash, unsigned long addr,
@ -361,13 +324,15 @@ int size_dataflash (AT91PS_DataFlash pdataFlash, unsigned long addr,
return 1;
}
/*---------------------------------------------------------------------------*/
/* Function Name : prot_dataflash */
/* Function Name : prot_dataflash */
/* Object : Test if destination area is protected */
/*---------------------------------------------------------------------------*/
int prot_dataflash (AT91PS_DataFlash pdataFlash, unsigned long addr)
{
int area;
int area;
/* find area */
for (area=0; area < NB_DATAFLASH_AREA; area++) {
if ((addr >= pdataFlash->pDevice->area_list[area].start) &&
@ -385,6 +350,7 @@ int area;
return 1;
}
/*--------------------------------------------------------------------------*/
/* Function Name : dataflash_real_protect */
/* Object : protect/unprotect area */
@ -392,7 +358,8 @@ int area;
int dataflash_real_protect (int flag, unsigned long start_addr,
unsigned long end_addr)
{
int i,j, area1, area2, addr_valid = 0;
int i,j, area1, area2, addr_valid = 0;
/* find dataflash */
for (i = 0; i < CFG_MAX_DATAFLASH_BANKS; i++) {
if ((((int) start_addr) & 0xF0000000) ==
@ -435,7 +402,7 @@ int i,j, area1, area2, addr_valid = 0;
}
/*---------------------------------------------------------------------------*/
/* Function Name : read_dataflash */
/* Function Name : read_dataflash */
/* Object : dataflash memory read */
/*---------------------------------------------------------------------------*/
int read_dataflash (unsigned long addr, unsigned long size, char *result)
@ -454,9 +421,8 @@ int read_dataflash (unsigned long addr, unsigned long size, char *result)
return (AT91F_DataFlashRead (pFlash, AddrToRead, size, result));
}
/*---------------------------------------------------------------------------*/
/* Function Name : write_dataflash */
/* Function Name : write_dataflash */
/* Object : write a block in dataflash */
/*---------------------------------------------------------------------------*/
int write_dataflash (unsigned long addr_dest, unsigned long addr_src,
@ -483,7 +449,6 @@ int write_dataflash (unsigned long addr_dest, unsigned long addr_src,
AddrToWrite, size);
}
void dataflash_perror (int err)
{
switch (err) {
@ -509,5 +474,3 @@ void dataflash_perror (int err)
break;
}
}
#endif

4
drivers/net/macb.c
View File

@ -417,13 +417,13 @@ static int macb_init(struct eth_device *netdev, bd_t *bd)
/* choose RMII or MII mode. This depends on the board */
#ifdef CONFIG_RMII
#ifdef CONFIG_AT91CAP9ADK
#if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260)
macb_writel(macb, USRIO, MACB_BIT(RMII) | MACB_BIT(CLKEN));
#else
macb_writel(macb, USRIO, 0);
#endif
#else
#ifdef CONFIG_AT91CAP9ADK
#if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260)
macb_writel(macb, USRIO, MACB_BIT(CLKEN));
#else
macb_writel(macb, USRIO, MACB_BIT(MII));

518
include/asm-arm/arch-at91cap9/AT91CAP9.h
View File

@ -1,518 +0,0 @@
/*
* (C) Copyright 2008
* AT91CAP9 definitions
* Author : ATMEL AT91 application group
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef AT91CAP9_H
#define AT91CAP9_H
typedef volatile unsigned int AT91_REG;
/* Static Memory Controller */
typedef struct _AT91S_SMC {
AT91_REG SMC_SETUP0; /* Setup Register for CS 0 */
AT91_REG SMC_PULSE0; /* Pulse Register for CS 0 */
AT91_REG SMC_CYCLE0; /* Cycle Register for CS 0 */
AT91_REG SMC_CTRL0; /* Control Register for CS 0 */
AT91_REG SMC_SETUP1; /* Setup Register for CS 1 */
AT91_REG SMC_PULSE1; /* Pulse Register for CS 1 */
AT91_REG SMC_CYCLE1; /* Cycle Register for CS 1 */
AT91_REG SMC_CTRL1; /* Control Register for CS 1 */
AT91_REG SMC_SETUP2; /* Setup Register for CS 2 */
AT91_REG SMC_PULSE2; /* Pulse Register for CS 2 */
AT91_REG SMC_CYCLE2; /* Cycle Register for CS 2 */
AT91_REG SMC_CTRL2; /* Control Register for CS 2 */
AT91_REG SMC_SETUP3; /* Setup Register for CS 3 */
AT91_REG SMC_PULSE3; /* Pulse Register for CS 3 */
AT91_REG SMC_CYCLE3; /* Cycle Register for CS 3 */
AT91_REG SMC_CTRL3; /* Control Register for CS 3 */
AT91_REG SMC_SETUP4; /* Setup Register for CS 4 */
AT91_REG SMC_PULSE4; /* Pulse Register for CS 4 */
AT91_REG SMC_CYCLE4; /* Cycle Register for CS 4 */
AT91_REG SMC_CTRL4; /* Control Register for CS 4 */
AT91_REG SMC_SETUP5; /* Setup Register for CS 5 */
AT91_REG SMC_PULSE5; /* Pulse Register for CS 5 */
AT91_REG SMC_CYCLE5; /* Cycle Register for CS 5 */
AT91_REG SMC_CTRL5; /* Control Register for CS 5 */
AT91_REG SMC_SETUP6; /* Setup Register for CS 6 */
AT91_REG SMC_PULSE6; /* Pulse Register for CS 6 */
AT91_REG SMC_CYCLE6; /* Cycle Register for CS 6 */
AT91_REG SMC_CTRL6; /* Control Register for CS 6 */
AT91_REG SMC_SETUP7; /* Setup Register for CS 7 */
AT91_REG SMC_PULSE7; /* Pulse Register for CS 7 */
AT91_REG SMC_CYCLE7; /* Cycle Register for CS 7 */
AT91_REG SMC_CTRL7; /* Control Register for CS 7 */
} AT91S_SMC, *AT91PS_SMC;
/* SMC_SETUP : (SMC Offset: 0x0) Setup Register for CS x */
#define AT91C_SMC_NWESETUP (0x3F << 0) /* NWE Setup Length */
#define AT91C_SMC_NCSSETUPWR (0x3F << 8) /* NCS Setup Length for WRite */
#define AT91C_SMC_NRDSETUP (0x3F << 16) /* NRD Setup Length */
#define AT91C_SMC_NCSSETUPRD (0x3F << 24) /* NCS Setup Length for ReaD */
/* SMC_PULSE : (SMC Offset: 0x4) Pulse Register for CS x */
#define AT91C_SMC_NWEPULSE (0x7F << 0) /* NWE Pulse Length */
#define AT91C_SMC_NCSPULSEWR (0x7F << 8) /* NCS Pulse Length for WRite */
#define AT91C_SMC_NRDPULSE (0x7F << 16) /* NRD Pulse Length */
#define AT91C_SMC_NCSPULSERD (0x7F << 24) /* NCS Pulse Length for ReaD */
/* SMC_CYC : (SMC Offset: 0x8) Cycle Register for CS x */
#define AT91C_SMC_NWECYCLE (0x1FF << 0) /* Total Write Cycle Length */
#define AT91C_SMC_NRDCYCLE (0x1FF << 16) /* Total Read Cycle Length */
/* SMC_CTRL : (SMC Offset: 0xc) Control Register for CS x */
#define AT91C_SMC_READMODE (0x1 << 0) /* Read Mode */
#define AT91C_SMC_WRITEMODE (0x1 << 1) /* Write Mode */
#define AT91C_SMC_NWAITM (0x3 << 5) /* NWAIT Mode */
/* External NWAIT disabled */
#define AT91C_SMC_NWAITM_NWAIT_DISABLE (0x0 << 5)
/* External NWAIT enabled in frozen mode */
#define AT91C_SMC_NWAITM_NWAIT_ENABLE_FROZEN (0x2 << 5)
/* External NWAIT enabled in ready mode */
#define AT91C_SMC_NWAITM_NWAIT_ENABLE_READY (0x3 << 5)
#define AT91C_SMC_BAT (0x1 << 8) /* Byte Access Type */
/*
* Write controled by ncs, nbs0, nbs1, nbs2, nbs3.
* Read controled by ncs, nrd, nbs0, nbs1, nbs2, nbs3.
*/
#define AT91C_SMC_BAT_BYTE_SELECT (0x0 << 8)
/*
* Write controled by ncs, nwe0, nwe1, nwe2, nwe3.
* Read controled by ncs and nrd.
*/
#define AT91C_SMC_BAT_BYTE_WRITE (0x1 << 8)
#define AT91C_SMC_DBW (0x3 << 12) /* Data Bus Width */
#define AT91C_SMC_DBW_WIDTH_EIGTH_BITS (0x0 << 12)
#define AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS (0x1 << 12)
#define AT91C_SMC_DBW_WIDTH_THIRTY_TWO_BITS (0x2 << 12)
#define AT91C_SMC_TDF (0xF << 16) /* Data Float Time */
#define AT91C_SMC_TDFEN (0x1 << 20) /* TDF Enabled */
#define AT91C_SMC_PMEN (0x1 << 24) /* Page Mode Enabled */
#define AT91C_SMC_PS (0x3 << 28) /* Page Size */
#define AT91C_SMC_PS_SIZE_FOUR_BYTES (0x0 << 28)
#define AT91C_SMC_PS_SIZE_EIGHT_BYTES (0x1 << 28)
#define AT91C_SMC_PS_SIZE_SIXTEEN_BYTES (0x2 << 28)
#define AT91C_SMC_PS_SIZE_THIRTY_TWO_BYTES (0x3 << 28)
/* SMC_SETUP : (SMC Offset: 0x10) Setup Register for CS x */
/* SMC_PULSE : (SMC Offset: 0x14) Pulse Register for CS x */
/* SMC_CYC : (SMC Offset: 0x18) Cycle Register for CS x */
/* SMC_CTRL : (SMC Offset: 0x1c) Control Register for CS x */
/* SMC_SETUP : (SMC Offset: 0x20) Setup Register for CS x */
/* SMC_PULSE : (SMC Offset: 0x24) Pulse Register for CS x */
/* SMC_CYC : (SMC Offset: 0x28) Cycle Register for CS x */
/* SMC_CTRL : (SMC Offset: 0x2c) Control Register for CS x */
/* SMC_SETUP : (SMC Offset: 0x30) Setup Register for CS x */
/* SMC_PULSE : (SMC Offset: 0x34) Pulse Register for CS x */
/* SMC_CYC : (SMC Offset: 0x38) Cycle Register for CS x */
/* SMC_CTRL : (SMC Offset: 0x3c) Control Register for CS x */
/* SMC_SETUP : (SMC Offset: 0x40) Setup Register for CS x */
/* SMC_PULSE : (SMC Offset: 0x44) Pulse Register for CS x */
/* SMC_CYC : (SMC Offset: 0x48) Cycle Register for CS x */
/* SMC_CTRL : (SMC Offset: 0x4c) Control Register for CS x */
/* SMC_SETUP : (SMC Offset: 0x50) Setup Register for CS x */
/* SMC_PULSE : (SMC Offset: 0x54) Pulse Register for CS x */
/* SMC_CYC : (SMC Offset: 0x58) Cycle Register for CS x */
/* SMC_CTRL : (SMC Offset: 0x5c) Control Register for CS x */
/* SMC_SETUP : (SMC Offset: 0x60) Setup Register for CS x */
/* SMC_PULSE : (SMC Offset: 0x64) Pulse Register for CS x */
/* SMC_CYC : (SMC Offset: 0x68) Cycle Register for CS x */
/* SMC_CTRL : (SMC Offset: 0x6c) Control Register for CS x */
/* SMC_SETUP : (SMC Offset: 0x70) Setup Register for CS x */
/* SMC_PULSE : (SMC Offset: 0x74) Pulse Register for CS x */
/* SMC_CYC : (SMC Offset: 0x78) Cycle Register for CS x */
/* SMC_CTRL : (SMC Offset: 0x7c) Control Register for CS x */
/* AHB CCFG */
typedef struct _AT91S_CCFG {
AT91_REG Reserved0[1];
AT91_REG CCFG_MPBS0; /* MPB Slave 0 */
AT91_REG CCFG_UDPHS; /* AHB Periphs */
AT91_REG CCFG_MPBS1; /* MPB Slave 1 */
AT91_REG CCFG_EBICSA; /* EBI Chip Select Assignement */
AT91_REG Reserved1[2];
AT91_REG CCFG_MPBS2; /* MPB Slave 2 */
AT91_REG CCFG_MPBS3; /* MPB Slave 3 */
AT91_REG CCFG_BRIDGE; /* APB Bridge */
AT91_REG Reserved2[49];
AT91_REG CCFG_MATRIXVERSION;/* Version */
} AT91S_CCFG, *AT91PS_CCFG;
/* CCFG_UDPHS : (CCFG Offset: 0x8) UDPHS Configuration */
#define AT91C_CCFG_UDPHS_UDP_SELECT (0x1 << 31) /* UDPHS or UDP */
#define AT91C_CCFG_UDPHS_UDP_SELECT_UDPHS (0x0 << 31)
#define AT91C_CCFG_UDPHS_UDP_SELECT_UDP (0x1 << 31)
/* CCFG_EBICSA : (CCFG Offset: 0x10) EBI Chip Select Assignement Register */
#define AT91C_EBI_CS1A (0x1 << 1) /* CS1 Assignment */
#define AT91C_EBI_CS1A_SMC (0x0 << 1)
#define AT91C_EBI_CS1A_BCRAMC (0x1 << 1)
#define AT91C_EBI_CS3A (0x1 << 3) /* CS 3 Assignment */
#define AT91C_EBI_CS3A_SMC (0x0 << 3)
#define AT91C_EBI_CS3A_SM (0x1 << 3)
#define AT91C_EBI_CS4A (0x1 << 4) /* CS4 Assignment */
#define AT91C_EBI_CS4A_SMC (0x0 << 4)
#define AT91C_EBI_CS4A_CF (0x1 << 4)
#define AT91C_EBI_CS5A (0x1 << 5) /* CS 5 Assignment */
#define AT91C_EBI_CS5A_SMC (0x0 << 5)
#define AT91C_EBI_CS5A_CF (0x1 << 5)
#define AT91C_EBI_DBPUC (0x1 << 8) /* Data Bus Pull-up */
#define AT91C_EBI_DDRPUC (0x1 << 9) /* DDDR DQS Pull-up */
#define AT91C_EBI_SUP (0x1 << 16) /* EBI Supply */
#define AT91C_EBI_SUP_1V8 (0x0 << 16)
#define AT91C_EBI_SUP_3V3 (0x1 << 16)
#define AT91C_EBI_LP (0x1 << 17) /* EBI Low Power */
#define AT91C_EBI_LP_LOW_DRIVE (0x0 << 17)
#define AT91C_EBI_LP_STD_DRIVE (0x1 << 17)
#define AT91C_CCFG_DDR_SDR_SELECT (0x1 << 31) /* DDR or SDR */
#define AT91C_CCFG_DDR_SDR_SELECT_DDR (0x0 << 31)
#define AT91C_CCFG_DDR_SDR_SELECT_SDR (0x1 << 31)
/* CCFG_BRIDGE : (CCFG Offset: 0x24) BRIDGE Configuration */
#define AT91C_CCFG_AES_TDES_SELECT (0x1 << 31) /* AES or TDES */
#define AT91C_CCFG_AES_TDES_SELECT_AES (0x0 << 31)
#define AT91C_CCFG_AES_TDES_SELECT_TDES (0x1 << 31)
/* PIO controller */
typedef struct _AT91S_PIO {
AT91_REG PIO_PER; /* PIO Enable Register */
AT91_REG PIO_PDR; /* PIO Disable Register */
AT91_REG PIO_PSR; /* PIO Status Register */
AT91_REG Reserved0[1];
AT91_REG PIO_OER; /* Output Enable Register */
AT91_REG PIO_ODR; /* Output Disable Register */
AT91_REG PIO_OSR; /* Output Status Register */
AT91_REG Reserved1[1];
AT91_REG PIO_IFER; /* Input Filter Enable Register */
AT91_REG PIO_IFDR; /* Input Filter Disable Register */
AT91_REG PIO_IFSR; /* Input Filter Status Register */
AT91_REG Reserved2[1];
AT91_REG PIO_SODR; /* Set Output Data Register */
AT91_REG PIO_CODR; /* Clear Output Data Register */
AT91_REG PIO_ODSR; /* Output Data Status Register */
AT91_REG PIO_PDSR; /* Pin Data Status Register */
AT91_REG PIO_IER; /* Interrupt Enable Register */
AT91_REG PIO_IDR; /* Interrupt Disable Register */
AT91_REG PIO_IMR; /* Interrupt Mask Register */
AT91_REG PIO_ISR; /* Interrupt Status Register */
AT91_REG PIO_MDER; /* Multi-driver Enable Register */
AT91_REG PIO_MDDR; /* Multi-driver Disable Register */
AT91_REG PIO_MDSR; /* Multi-driver Status Register */
AT91_REG Reserved3[1];
AT91_REG PIO_PPUDR; /* Pull-up Disable Register */
AT91_REG PIO_PPUER; /* Pull-up Enable Register */
AT91_REG PIO_PPUSR; /* Pull-up Status Register */
AT91_REG Reserved4[1];
AT91_REG PIO_ASR; /* Select A Register */
AT91_REG PIO_BSR; /* Select B Register */
AT91_REG PIO_ABSR; /* AB Select Status Register */
AT91_REG Reserved5[9];
AT91_REG PIO_OWER; /* Output Write Enable Register */
AT91_REG PIO_OWDR; /* Output Write Disable Register */
AT91_REG PIO_OWSR; /* Output Write Status Register */
} AT91S_PIO, *AT91PS_PIO;
/* Power Management Controller */
typedef struct _AT91S_PMC {
AT91_REG PMC_SCER; /* System Clock Enable Register */
AT91_REG PMC_SCDR; /* System Clock Disable Register */
AT91_REG PMC_SCSR; /* System Clock Status Register */
AT91_REG Reserved0[1];
AT91_REG PMC_PCER; /* Peripheral Clock Enable Register */
AT91_REG PMC_PCDR; /* Peripheral Clock Disable Register */
AT91_REG PMC_PCSR; /* Peripheral Clock Status Register */
AT91_REG PMC_UCKR; /* UTMI Clock Configuration Register */
AT91_REG PMC_MOR; /* Main Oscillator Register */
AT91_REG PMC_MCFR; /* Main Clock Frequency Register */
AT91_REG PMC_PLLAR; /* PLL A Register */
AT91_REG PMC_PLLBR; /* PLL B Register */
AT91_REG PMC_MCKR; /* Master Clock Register */
AT91_REG Reserved1[3];
AT91_REG PMC_PCKR[8]; /* Programmable Clock Register */
AT91_REG PMC_IER; /* Interrupt Enable Register */
AT91_REG PMC_IDR; /* Interrupt Disable Register */
AT91_REG PMC_SR; /* Status Register */
AT91_REG PMC_IMR; /* Interrupt Mask Register */
} AT91S_PMC, *AT91PS_PMC;
/* PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register */
#define AT91C_PMC_PCK (0x1 << 0) /* Processor Clock */
#define AT91C_PMC_OTG (0x1 << 5) /* USB OTG Clock */
#define AT91C_PMC_UHP (0x1 << 6) /* USB Host Port Clock */
#define AT91C_PMC_UDP (0x1 << 7) /* USB Device Port Clock */
#define AT91C_PMC_PCK0 (0x1 << 8) /* Programmable Clock Output */
#define AT91C_PMC_PCK1 (0x1 << 9) /* Programmable Clock Output */
#define AT91C_PMC_PCK2 (0x1 << 10) /* Programmable Clock Output */
#define AT91C_PMC_PCK3 (0x1 << 11) /* Programmable Clock Output */
/* PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register */
/* PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register */
/* CKGR_UCKR : (PMC Offset: 0x1c) UTMI Clock Configuration Register */
/* CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register */
/* CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register */
/* CKGR_PLLAR : (PMC Offset: 0x28) PLL A Register */
/* CKGR_PLLBR : (PMC Offset: 0x2c) PLL B Register */
/* PMC_MCKR : (PMC Offset: 0x30) Master Clock Register */
#define AT91C_PMC_CSS (0x3 << 0) /* Clock Selection */
#define AT91C_PMC_CSS_SLOW_CLK (0x0 << 0) /* Slow Clk */
#define AT91C_PMC_CSS_MAIN_CLK (0x1 << 0) /* Main Clk */
#define AT91C_PMC_CSS_PLLA_CLK (0x2 << 0) /* PLL A Clk */
#define AT91C_PMC_CSS_PLLB_CLK (0x3 << 0) /* PLL B Clk */
#define AT91C_PMC_PRES (0x7 << 2) /* Clock Prescaler */
#define AT91C_PMC_PRES_CLK (0x0 << 2)
#define AT91C_PMC_PRES_CLK_2 (0x1 << 2)
#define AT91C_PMC_PRES_CLK_4 (0x2 << 2)
#define AT91C_PMC_PRES_CLK_8 (0x3 << 2)
#define AT91C_PMC_PRES_CLK_16 (0x4 << 2)
#define AT91C_PMC_PRES_CLK_32 (0x5 << 2)
#define AT91C_PMC_PRES_CLK_64 (0x6 << 2)
#define AT91C_PMC_MDIV (0x3 << 8) /* Master Clock Division */
#define AT91C_PMC_MDIV_1 (0x0 << 8)
#define AT91C_PMC_MDIV_2 (0x1 << 8)
#define AT91C_PMC_MDIV_4 (0x2 << 8)
/* PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register */
/* PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register */
#define AT91C_PMC_MOSCS (0x1 << 0) /* MOSC mask */
#define AT91C_PMC_LOCKA (0x1 << 1) /* PLL A mask */
#define AT91C_PMC_LOCKB (0x1 << 2) /* PLL B mask */
#define AT91C_PMC_MCKRDY (0x1 << 3) /* Master mask */
#define AT91C_PMC_LOCKU (0x1 << 6) /* PLL UTMI mask */
#define AT91C_PMC_PCK0RDY (0x1 << 8) /* PCK0_RDY mask */
#define AT91C_PMC_PCK1RDY (0x1 << 9) /* PCK1_RDY mask */
#define AT91C_PMC_PCK2RDY (0x1 << 10) /* PCK2_RDY mask */
#define AT91C_PMC_PCK3RDY (0x1 << 11) /* PCK3_RDY mask */
/* PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register */
/* PMC_SR : (PMC Offset: 0x68) PMC Status Register */
/* PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register */
/* Reset controller */
typedef struct _AT91S_RSTC {
AT91_REG RSTC_RCR; /* Reset Control Register */
AT91_REG RSTC_RSR; /* Reset Status Register */
AT91_REG RSTC_RMR; /* Reset Mode Register */
} AT91S_RSTC, *AT91PS_RSTC;
/* RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register */
#define AT91C_RSTC_PROCRST (0x1 << 0) /* Processor Reset */
#define AT91C_RSTC_ICERST (0x1 << 1) /* ICE Interface Reset */
#define AT91C_RSTC_PERRST (0x1 << 2) /* Peripheral Reset */
#define AT91C_RSTC_EXTRST (0x1 << 3) /* External Reset */
#define AT91C_RSTC_KEY (0xFF << 24) /* Password */
/* RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register */
#define AT91C_RSTC_URSTS (0x1 << 0) /* User Reset Status */
#define AT91C_RSTC_RSTTYP (0x7 << 8) /* Reset Type */
#define AT91C_RSTC_RSTTYP_GENERAL (0x0 << 8)
#define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8)
#define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8)
#define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8)
#define AT91C_RSTC_RSTTYP_USER (0x4 << 8)
#define AT91C_RSTC_NRSTL (0x1 << 16) /* NRST pin level */
#define AT91C_RSTC_SRCMP (0x1 << 17) /* Software Rst in Progress. */
/* RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register */
#define AT91C_RSTC_URSTEN (0x1 << 0) /* User Reset Enable */
#define AT91C_RSTC_URSTIEN (0x1 << 4) /* User Reset Int. Enable */
#define AT91C_RSTC_ERSTL (0xF << 8) /* User Reset Enable */
/* Periodic Timer Controller */
typedef struct _AT91S_PITC {
AT91_REG PITC_PIMR; /* Period Interval Mode Register */
AT91_REG PITC_PISR; /* Period Interval Status Register */
AT91_REG PITC_PIVR; /* Period Interval Value Register */
AT91_REG PITC_PIIR; /* Period Interval Image Register */
} AT91S_PITC, *AT91PS_PITC;
/* PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register */
#define AT91C_PITC_PIV (0xFFFFF << 0) /* Periodic Interval Value */
#define AT91C_PITC_PITEN (0x1 << 24) /* PIT Enable */
#define AT91C_PITC_PITIEN (0x1 << 25) /* PIT Interrupt Enable */
/* PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register */
#define AT91C_PITC_PITS (0x1 << 0) /* PIT Status */
/* PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register */
#define AT91C_PITC_CPIV (0xFFFFF << 0) /* Current Value */
#define AT91C_PITC_PICNT (0xFFF << 20) /* Periodic Interval Counter */
/* PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register */
/* Serial Paraller Interface */
typedef struct _AT91S_SPI {
AT91_REG SPI_CR; /* Control Register */
AT91_REG SPI_MR; /* Mode Register */
AT91_REG SPI_RDR; /* Receive Data Register */
AT91_REG SPI_TDR; /* Transmit Data Register */
AT91_REG SPI_SR; /* Status Register */
AT91_REG SPI_IER; /* Interrupt Enable Register */
AT91_REG SPI_IDR; /* Interrupt Disable Register */
AT91_REG SPI_IMR; /* Interrupt Mask Register */
AT91_REG Reserved0[4];
AT91_REG SPI_CSR[4]; /* Chip Select Register */
AT91_REG Reserved1[48];
AT91_REG SPI_RPR; /* Receive Pointer Register */
AT91_REG SPI_RCR; /* Receive Counter Register */
AT91_REG SPI_TPR; /* Transmit Pointer Register */
AT91_REG SPI_TCR; /* Transmit Counter Register */
AT91_REG SPI_RNPR; /* Receive Next Pointer Register */
AT91_REG SPI_RNCR; /* Receive Next Counter Register */
AT91_REG SPI_TNPR; /* Transmit Next Pointer Register */
AT91_REG SPI_TNCR; /* Transmit Next Counter Register */
AT91_REG SPI_PTCR; /* PDC Transfer Control Register */
AT91_REG SPI_PTSR; /* PDC Transfer Status Register */
} AT91S_SPI, *AT91PS_SPI;
/* SPI_CR : (SPI Offset: 0x0) SPI Control Register */
#define AT91C_SPI_SPIEN (0x1 << 0) /* SPI Enable */
#define AT91C_SPI_SPIDIS (0x1 << 1) /* SPI Disable */
#define AT91C_SPI_SWRST (0x1 << 7) /* SPI Software reset */
#define AT91C_SPI_LASTXFER (0x1 << 24) /* SPI Last Transfer */
/* SPI_MR : (SPI Offset: 0x4) SPI Mode Register */
#define AT91C_SPI_MSTR (0x1 << 0) /* Master/Slave Mode */
#define AT91C_SPI_PS (0x1 << 1) /* Peripheral Select */
#define AT91C_SPI_PS_FIXED (0x0 << 1)
#define AT91C_SPI_PS_VARIABLE (0x1 << 1)
#define AT91C_SPI_PCSDEC (0x1 << 2) /* Chip Select Decode */
#define AT91C_SPI_FDIV (0x1 << 3) /* Clock Selection */
#define AT91C_SPI_MODFDIS (0x1 << 4) /* Mode Fault Detection */
#define AT91C_SPI_LLB (0x1 << 7) /* Clock Selection */
#define AT91C_SPI_PCS (0xF << 16) /* Peripheral Chip Select */
#define AT91C_SPI_DLYBCS (0xFF << 24) /* Delay Between Chip Selects */
/* SPI_RDR : (SPI Offset: 0x8) Receive Data Register */
#define AT91C_SPI_RD (0xFFFF << 0) /* Receive Data */
#define AT91C_SPI_RPCS (0xF << 16) /* Peripheral CS Status */
/* SPI_TDR : (SPI Offset: 0xc) Transmit Data Register */
#define AT91C_SPI_TD (0xFFFF << 0) /* Transmit Data */
#define AT91C_SPI_TPCS (0xF << 16) /* Peripheral CS Status */
/* SPI_SR : (SPI Offset: 0x10) Status Register */
#define AT91C_SPI_RDRF (0x1 << 0) /* Receive Data Register Full */
#define AT91C_SPI_TDRE (0x1 << 1) /* Trans. Data Register Empty */
#define AT91C_SPI_MODF (0x1 << 2) /* Mode Fault Error */
#define AT91C_SPI_OVRES (0x1 << 3) /* Overrun Error Status */
#define AT91C_SPI_ENDRX (0x1 << 4) /* End of Receiver Transfer */
#define AT91C_SPI_ENDTX (0x1 << 5) /* End of Receiver Transfer */
#define AT91C_SPI_RXBUFF (0x1 << 6) /* RXBUFF Interrupt */
#define AT91C_SPI_TXBUFE (0x1 << 7) /* TXBUFE Interrupt */
#define AT91C_SPI_NSSR (0x1 << 8) /* NSSR Interrupt */
#define AT91C_SPI_TXEMPTY (0x1 << 9) /* TXEMPTY Interrupt */
#define AT91C_SPI_SPIENS (0x1 << 16) /* Enable Status */
/* SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register */
/* SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register */
/* SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register */
/* SPI_CSR : (SPI Offset: 0x30) Chip Select Register */
#define AT91C_SPI_CPOL (0x1 << 0) /* Clock Polarity */
#define AT91C_SPI_NCPHA (0x1 << 1) /* Clock Phase */
#define AT91C_SPI_CSAAT (0x1 << 3) /* CS Active After Transfer */
#define AT91C_SPI_BITS (0xF << 4) /* Bits Per Transfer */
#define AT91C_SPI_BITS_8 (0x0 << 4) /* 8 Bits */
#define AT91C_SPI_BITS_9 (0x1 << 4) /* 9 Bits */
#define AT91C_SPI_BITS_10 (0x2 << 4) /* 10 Bits */
#define AT91C_SPI_BITS_11 (0x3 << 4) /* 11 Bits */
#define AT91C_SPI_BITS_12 (0x4 << 4) /* 12 Bits */
#define AT91C_SPI_BITS_13 (0x5 << 4) /* 13 Bits */
#define AT91C_SPI_BITS_14 (0x6 << 4) /* 14 Bits */
#define AT91C_SPI_BITS_15 (0x7 << 4) /* 15 Bits */
#define AT91C_SPI_BITS_16 (0x8 << 4) /* 16 Bits */
#define AT91C_SPI_SCBR (0xFF << 8) /* Serial Clock Baud Rate */
#define AT91C_SPI_DLYBS (0xFF << 16) /* Delay Before SPCK */
#define AT91C_SPI_DLYBCT (0xFF << 24) /* Delay Between Transfers */
/* SPI_PTCR : PDC Transfer Control Register */
#define AT91C_PDC_RXTEN (0x1 << 0) /* Receiver Transfer Enable */
#define AT91C_PDC_RXTDIS (0x1 << 1) /* Receiver Transfer Disable */
#define AT91C_PDC_TXTEN (0x1 << 8) /* Transm. Transfer Enable */
#define AT91C_PDC_TXTDIS (0x1 << 9) /* Transm. Transfer Disable */
/* PIO definitions */
#define AT91C_PIO_PA0 (1 << 0) /* Pin Controlled by PA0 */
#define AT91C_PA0_SPI0_MISO AT91C_PIO_PA0
#define AT91C_PIO_PA1 (1 << 1) /* Pin Controlled by PA1 */
#define AT91C_PA1_SPI0_MOSI AT91C_PIO_PA1
#define AT91C_PIO_PA2 (1 << 2) /* Pin Controlled by PA2 */
#define AT91C_PA2_SPI0_SPCK AT91C_PIO_PA2
#define AT91C_PIO_PA3 (1 << 3) /* Pin Controlled by PA3 */
#define AT91C_PA3_SPI0_NPCS1 AT91C_PIO_PA3
#define AT91C_PIO_PA4 (1 << 4) /* Pin Controlled by PA4 */
#define AT91C_PA4_SPI0_NPCS2A AT91C_PIO_PA4
#define AT91C_PIO_PA5 (1 << 5) /* Pin Controlled by PA5 */
#define AT91C_PA5_SPI0_NPCS0 AT91C_PIO_PA5
#define AT91C_PIO_PA10 (1 << 10) /* Pin Controlled by PA10 */
#define AT91C_PIO_PA11 (1 << 11) /* Pin Controlled by PA11 */
#define AT91C_PIO_PA22 (1 << 22) /* Pin Controlled by PA22 */
#define AT91C_PA22_TXD0 AT91C_PIO_PA22
#define AT91C_PIO_PA23 (1 << 23) /* Pin Controlled by PA23 */
#define AT91C_PA23_RXD0 AT91C_PIO_PA23
#define AT91C_PIO_PA28 (1 << 28) /* Pin Controlled by PA28 */
#define AT91C_PA28_SPI0_NPCS3A AT91C_PIO_PA28
#define AT91C_PIO_PB21 (1 << 21) /* Pin Controlled by PB21 */
#define AT91C_PB21_E_TXCK AT91C_PIO_PB21
#define AT91C_PIO_PB22 (1 << 22) /* Pin Controlled by PB22 */
#define AT91C_PB22_E_RXDV AT91C_PIO_PB22
#define AT91C_PIO_PB23 (1 << 23) /* Pin Controlled by PB23 */
#define AT91C_PB23_E_TX0 AT91C_PIO_PB23
#define AT91C_PIO_PB24 (1 << 24) /* Pin Controlled by PB24 */
#define AT91C_PB24_E_TX1 AT91C_PIO_PB24
#define AT91C_PIO_PB25 (1 << 25) /* Pin Controlled by PB25 */
#define AT91C_PB25_E_RX0 AT91C_PIO_PB25
#define AT91C_PIO_PB26 (1 << 26) /* Pin Controlled by PB26 */
#define AT91C_PB26_E_RX1 AT91C_PIO_PB26
#define AT91C_PIO_PB27 (1 << 27) /* Pin Controlled by PB27 */
#define AT91C_PB27_E_RXER AT91C_PIO_PB27
#define AT91C_PIO_PB28 (1 << 28) /* Pin Controlled by PB28 */
#define AT91C_PB28_E_TXEN AT91C_PIO_PB28
#define AT91C_PIO_PB29 (1 << 29) /* Pin Controlled by PB29 */
#define AT91C_PB29_E_MDC AT91C_PIO_PB29
#define AT91C_PIO_PB30 (1 << 30) /* Pin Controlled by PB30 */
#define AT91C_PB30_E_MDIO AT91C_PIO_PB30
#define AT91C_PIO_PB31 (1 << 31) /* Pin Controlled by PB31 */
#define AT91C_PIO_PC29 (1 << 29) /* Pin Controlled by PC29 */
#define AT91C_PIO_PC30 (1 << 30) /* Pin Controlled by PC30 */
#define AT91C_PC30_DRXD AT91C_PIO_PC30
#define AT91C_PIO_PC31 (1 << 31) /* Pin Controlled by PC31 */
#define AT91C_PC31_DTXD AT91C_PIO_PC31
#define AT91C_PIO_PD0 (1 << 0) /* Pin Controlled by PD0 */
#define AT91C_PD0_TXD1 AT91C_PIO_PD0
#define AT91C_PD0_SPI0_NPCS2D AT91C_PIO_PD0
#define AT91C_PIO_PD1 (1 << 1) /* Pin Controlled by PD1 */
#define AT91C_PD1_RXD1 AT91C_PIO_PD1
#define AT91C_PD1_SPI0_NPCS3D AT91C_PIO_PD1
#define AT91C_PIO_PD2 (1 << 2) /* Pin Controlled by PD2 */
#define AT91C_PD2_TXD2 AT91C_PIO_PD2
#define AT91C_PIO_PD3 (1 << 3) /* Pin Controlled by PD3 */
#define AT91C_PD3_RXD2 AT91C_PIO_PD3
#define AT91C_PIO_PD15 (1 << 15) /* Pin Controlled by PD15 */
/* Peripheral ID */
#define AT91C_ID_SYS 1 /* System Controller */
#define AT91C_ID_PIOABCD 2 /* Parallel IO Controller A, B, C, D */
#define AT91C_ID_US0 8 /* USART 0 */
#define AT91C_ID_US1 9 /* USART 1 */
#define AT91C_ID_US2 10 /* USART 2 */
#define AT91C_ID_SPI0 15 /* Serial Peripheral Interface 0 */
#define AT91C_ID_EMAC 22 /* Ethernet Mac */
#define AT91C_ID_UHP 29 /* USB Host Port */
/* Base addresses */
#define AT91C_BASE_SMC ((AT91PS_SMC) 0xFFFFE800) /* SMC */
#define AT91C_BASE_CCFG ((AT91PS_CCFG) 0xFFFFEB10) /* CCFG */
#define AT91C_BASE_DBGU ((unsigned long)0xFFFFEE00) /* DBGU */
#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF200) /* PIOA */
#define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF400) /* PIOB */
#define AT91C_BASE_PIOC ((AT91PS_PIO) 0xFFFFF600) /* PIOC */
#define AT91C_BASE_PIOD ((AT91PS_PIO) 0xFFFFF800) /* PIOD */
#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) /* PMC */
#define AT91C_BASE_RSTC ((AT91PS_RSTC) 0xFFFFFD00) /* RSTC */
#define AT91C_BASE_PITC ((AT91PS_PITC) 0xFFFFFD30) /* PITC */
#define AT91C_BASE_US0 ((unsigned long)0xFFF8C000) /* US0 */
#define AT91C_BASE_US1 ((unsigned long)0xFFF90000) /* US1 */
#define AT91C_BASE_US2 ((unsigned long)0xFFF94000) /* US2 */
#define AT91C_BASE_SPI0 ((AT91PS_SPI) 0xFFFA4000) /* SPI0 */
#define AT91C_BASE_MACB ((unsigned long)0xFFFBC000) /* MACB */
#endif

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include/asm-arm/arch-at91cap9/hardware.h
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/*
* (C) Copyright 2007
* Stelian Pop <stelian.pop <at> leadtechdesign.com>
* Lead Tech Design <www.leadtechdesign.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_HARDWARE_H
#define __ASM_ARCH_HARDWARE_H
#include <asm/sizes.h>
#include <asm/arch/AT91CAP9.h>
/*
* container_of - cast a member of a structure out to the containing structure
*
* @ptr: the pointer to the member.
* @type: the type of the container struct this is embedded in.
* @member: the name of the member within the struct.
*/
#define container_of(ptr, type, member) ({ \
const typeof(((type *)0)->member) *__mptr = (ptr); \
(type *)((char *)__mptr - offsetof(type, member)); })
#endif

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/*
* include/asm-arm/arch-at91/at91_pio.h
*
* Copyright (C) 2005 Ivan Kokshaysky
* Copyright (C) SAN People
*
* Parallel I/O Controller (PIO) - System peripherals registers.
* Based on AT91RM9200 datasheet revision E.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91_PIO_H
#define AT91_PIO_H
#define PIO_PER 0x00 /* Enable Register */
#define PIO_PDR 0x04 /* Disable Register */
#define PIO_PSR 0x08 /* Status Register */
#define PIO_OER 0x10 /* Output Enable Register */
#define PIO_ODR 0x14 /* Output Disable Register */
#define PIO_OSR 0x18 /* Output Status Register */
#define PIO_IFER 0x20 /* Glitch Input Filter Enable */
#define PIO_IFDR 0x24 /* Glitch Input Filter Disable */
#define PIO_IFSR 0x28 /* Glitch Input Filter Status */
#define PIO_SODR 0x30 /* Set Output Data Register */
#define PIO_CODR 0x34 /* Clear Output Data Register */
#define PIO_ODSR 0x38 /* Output Data Status Register */
#define PIO_PDSR 0x3c /* Pin Data Status Register */
#define PIO_IER 0x40 /* Interrupt Enable Register */
#define PIO_IDR 0x44 /* Interrupt Disable Register */
#define PIO_IMR 0x48 /* Interrupt Mask Register */
#define PIO_ISR 0x4c /* Interrupt Status Register */
#define PIO_MDER 0x50 /* Multi-driver Enable Register */
#define PIO_MDDR 0x54 /* Multi-driver Disable Register */
#define PIO_MDSR 0x58 /* Multi-driver Status Register */
#define PIO_PUDR 0x60 /* Pull-up Disable Register */
#define PIO_PUER 0x64 /* Pull-up Enable Register */
#define PIO_PUSR 0x68 /* Pull-up Status Register */
#define PIO_ASR 0x70 /* Peripheral A Select Register */
#define PIO_BSR 0x74 /* Peripheral B Select Register */
#define PIO_ABSR 0x78 /* AB Status Register */
#define PIO_OWER 0xa0 /* Output Write Enable Register */
#define PIO_OWDR 0xa4 /* Output Write Disable Register */
#define PIO_OWSR 0xa8 /* Output Write Status Register */
#endif

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/*
* include/asm-arm/arch-at91/at91_pit.h
*
* Periodic Interval Timer (PIT) - System peripherals regsters.
* Based on AT91SAM9261 datasheet revision D.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91_PIT_H
#define AT91_PIT_H
#define AT91_PIT_MR (AT91_PIT + 0x00) /* Mode Register */
#define AT91_PIT_PITIEN (1 << 25) /* Timer Interrupt Enable */
#define AT91_PIT_PITEN (1 << 24) /* Timer Enabled */
#define AT91_PIT_PIV (0xfffff) /* Periodic Interval Value */
#define AT91_PIT_SR (AT91_PIT + 0x04) /* Status Register */
#define AT91_PIT_PITS (1 << 0) /* Timer Status */
#define AT91_PIT_PIVR (AT91_PIT + 0x08) /* Periodic Interval Value Register */
#define AT91_PIT_PIIR (AT91_PIT + 0x0c) /* Periodic Interval Image Register */
#define AT91_PIT_PICNT (0xfff << 20) /* Interval Counter */
#define AT91_PIT_CPIV (0xfffff) /* Inverval Value */
#endif

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/*
* include/asm-arm/arch-at91/at91_pmc.h
*
* Copyright (C) 2005 Ivan Kokshaysky
* Copyright (C) SAN People
*
* Power Management Controller (PMC) - System peripherals registers.
* Based on AT91RM9200 datasheet revision E.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91_PMC_H
#define AT91_PMC_H
#define AT91_PMC_SCER (AT91_PMC + 0x00) /* System Clock Enable Register */
#define AT91_PMC_SCDR (AT91_PMC + 0x04) /* System Clock Disable Register */
#define AT91_PMC_SCSR (AT91_PMC + 0x08) /* System Clock Status Register */
#define AT91_PMC_PCK (1 << 0) /* Processor Clock */
#define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */
#define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
#define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */
#define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */
#define AT91CAP9_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91CAP9 only] */
#define AT91SAM926x_PMC_UDP (1 << 7) /* USB Devcice Port Clock [AT91SAM926x only] */
#define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */
#define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */
#define AT91_PMC_PCK2 (1 << 10) /* Programmable Clock 2 */
#define AT91_PMC_PCK3 (1 << 11) /* Programmable Clock 3 */
#define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */
#define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */
#define AT91_PMC_PCER (AT91_PMC + 0x10) /* Peripheral Clock Enable Register */
#define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */
#define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */
#define AT91_CKGR_UCKR (AT91_PMC + 0x1C) /* UTMI Clock Register [SAM9RL, CAP9] */
#define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register [not on SAM9RL] */
#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */
#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [AT91SAM926x only] */
#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */
#define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */
#define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */
#define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */
#define AT91_CKGR_PLLAR (AT91_PMC + 0x28) /* PLL A Register */
#define AT91_CKGR_PLLBR (AT91_PMC + 0x2c) /* PLL B Register */
#define AT91_PMC_DIV (0xff << 0) /* Divider */
#define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */
#define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */
#define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */
#define AT91_PMC_USBDIV (3 << 28) /* USB Divisor (PLLB only) */
#define AT91_PMC_USBDIV_1 (0 << 28)
#define AT91_PMC_USBDIV_2 (1 << 28)
#define AT91_PMC_USBDIV_4 (2 << 28)
#define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */
#define AT91_PMC_MCKR (AT91_PMC + 0x30) /* Master Clock Register */
#define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */
#define AT91_PMC_CSS_SLOW (0 << 0)
#define AT91_PMC_CSS_MAIN (1 << 0)
#define AT91_PMC_CSS_PLLA (2 << 0)
#define AT91_PMC_CSS_PLLB (3 << 0)
#define AT91_PMC_PRES (7 << 2) /* Master Clock Prescaler */
#define AT91_PMC_PRES_1 (0 << 2)
#define AT91_PMC_PRES_2 (1 << 2)
#define AT91_PMC_PRES_4 (2 << 2)
#define AT91_PMC_PRES_8 (3 << 2)
#define AT91_PMC_PRES_16 (4 << 2)
#define AT91_PMC_PRES_32 (5 << 2)
#define AT91_PMC_PRES_64 (6 << 2)
#define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */
#define AT91_PMC_MDIV_1 (0 << 8)
#define AT91_PMC_MDIV_2 (1 << 8)
#define AT91_PMC_MDIV_3 (2 << 8)
#define AT91_PMC_MDIV_4 (3 << 8)
#define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-3 Registers */
#define AT91_PMC_IER (AT91_PMC + 0x60) /* Interrupt Enable Register */
#define AT91_PMC_IDR (AT91_PMC + 0x64) /* Interrupt Disable Register */
#define AT91_PMC_SR (AT91_PMC + 0x68) /* Status Register */
#define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */
#define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */
#define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */
#define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */
#define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */
#define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */
#define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */
#define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */
#define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */
#endif

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/*
* include/asm-arm/arch-at91/at91_rstc.h
*
* Reset Controller (RSTC) - System peripherals regsters.
* Based on AT91SAM9261 datasheet revision D.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91_RSTC_H
#define AT91_RSTC_H
#define AT91_RSTC_CR (AT91_RSTC + 0x00) /* Reset Controller Control Register */
#define AT91_RSTC_PROCRST (1 << 0) /* Processor Reset */
#define AT91_RSTC_PERRST (1 << 2) /* Peripheral Reset */
#define AT91_RSTC_EXTRST (1 << 3) /* External Reset */
#define AT91_RSTC_KEY (0xa5 << 24) /* KEY Password */
#define AT91_RSTC_SR (AT91_RSTC + 0x04) /* Reset Controller Status Register */
#define AT91_RSTC_URSTS (1 << 0) /* User Reset Status */
#define AT91_RSTC_RSTTYP (7 << 8) /* Reset Type */
#define AT91_RSTC_RSTTYP_GENERAL (0 << 8)
#define AT91_RSTC_RSTTYP_WAKEUP (1 << 8)
#define AT91_RSTC_RSTTYP_WATCHDOG (2 << 8)
#define AT91_RSTC_RSTTYP_SOFTWARE (3 << 8)
#define AT91_RSTC_RSTTYP_USER (4 << 8)
#define AT91_RSTC_NRSTL (1 << 16) /* NRST Pin Level */
#define AT91_RSTC_SRCMP (1 << 17) /* Software Reset Command in Progress */
#define AT91_RSTC_MR (AT91_RSTC + 0x08) /* Reset Controller Mode Register */
#define AT91_RSTC_URSTEN (1 << 0) /* User Reset Enable */
#define AT91_RSTC_URSTIEN (1 << 4) /* User Reset Interrupt Enable */
#define AT91_RSTC_ERSTL (0xf << 8) /* External Reset Length */
#endif

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/*
* include/asm-arm/arch-at91/at91_spi.h
*
* Copyright (C) 2005 Ivan Kokshaysky
* Copyright (C) SAN People
*
* Serial Peripheral Interface (SPI) registers.
* Based on AT91RM9200 datasheet revision E.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91_SPI_H
#define AT91_SPI_H
#define AT91_SPI_CR 0x00 /* Control Register */
#define AT91_SPI_SPIEN (1 << 0) /* SPI Enable */
#define AT91_SPI_SPIDIS (1 << 1) /* SPI Disable */
#define AT91_SPI_SWRST (1 << 7) /* SPI Software Reset */
#define AT91_SPI_LASTXFER (1 << 24) /* Last Transfer [SAM9261 only] */
#define AT91_SPI_MR 0x04 /* Mode Register */
#define AT91_SPI_MSTR (1 << 0) /* Master/Slave Mode */
#define AT91_SPI_PS (1 << 1) /* Peripheral Select */
#define AT91_SPI_PS_FIXED (0 << 1)
#define AT91_SPI_PS_VARIABLE (1 << 1)
#define AT91_SPI_PCSDEC (1 << 2) /* Chip Select Decode */
#define AT91_SPI_DIV32 (1 << 3) /* Clock Selection [AT91RM9200 only] */
#define AT91_SPI_MODFDIS (1 << 4) /* Mode Fault Detection */
#define AT91_SPI_LLB (1 << 7) /* Local Loopback Enable */
#define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */
#define AT91_SPI_DLYBCS (0xff << 24) /* Delay Between Chip Selects */
#define AT91_SPI_RDR 0x08 /* Receive Data Register */
#define AT91_SPI_RD (0xffff << 0) /* Receive Data */
#define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */
#define AT91_SPI_TDR 0x0c /* Transmit Data Register */
#define AT91_SPI_TD (0xffff << 0) /* Transmit Data */
#define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */
#define AT91_SPI_LASTXFER (1 << 24) /* Last Transfer [SAM9261 only] */
#define AT91_SPI_SR 0x10 /* Status Register */
#define AT91_SPI_RDRF (1 << 0) /* Receive Data Register Full */
#define AT91_SPI_TDRE (1 << 1) /* Transmit Data Register Full */
#define AT91_SPI_MODF (1 << 2) /* Mode Fault Error */
#define AT91_SPI_OVRES (1 << 3) /* Overrun Error Status */
#define AT91_SPI_ENDRX (1 << 4) /* End of RX buffer */
#define AT91_SPI_ENDTX (1 << 5) /* End of TX buffer */
#define AT91_SPI_RXBUFF (1 << 6) /* RX Buffer Full */
#define AT91_SPI_TXBUFE (1 << 7) /* TX Buffer Empty */
#define AT91_SPI_NSSR (1 << 8) /* NSS Rising [SAM9261 only] */
#define AT91_SPI_TXEMPTY (1 << 9) /* Transmission Register Empty [SAM9261 only] */
#define AT91_SPI_SPIENS (1 << 16) /* SPI Enable Status */
#define AT91_SPI_IER 0x14 /* Interrupt Enable Register */
#define AT91_SPI_IDR 0x18 /* Interrupt Disable Register */
#define AT91_SPI_IMR 0x1c /* Interrupt Mask Register */
#define AT91_SPI_CSR(n) (0x30 + ((n) * 4)) /* Chip Select Registers 0-3 */
#define AT91_SPI_CPOL (1 << 0) /* Clock Polarity */
#define AT91_SPI_NCPHA (1 << 1) /* Clock Phase */
#define AT91_SPI_CSAAT (1 << 3) /* Chip Select Active After Transfer [SAM9261 only] */
#define AT91_SPI_BITS (0xf << 4) /* Bits Per Transfer */
#define AT91_SPI_BITS_8 (0 << 4)
#define AT91_SPI_BITS_9 (1 << 4)
#define AT91_SPI_BITS_10 (2 << 4)
#define AT91_SPI_BITS_11 (3 << 4)
#define AT91_SPI_BITS_12 (4 << 4)
#define AT91_SPI_BITS_13 (5 << 4)
#define AT91_SPI_BITS_14 (6 << 4)
#define AT91_SPI_BITS_15 (7 << 4)
#define AT91_SPI_BITS_16 (8 << 4)
#define AT91_SPI_SCBR (0xff << 8) /* Serial Clock Baud Rate */
#define AT91_SPI_DLYBS (0xff << 16) /* Delay before SPCK */
#define AT91_SPI_DLYBCT (0xff << 24) /* Delay between Consecutive Transfers */
#define AT91_SPI_RPR 0x0100 /* Receive Pointer Register */
#define AT91_SPI_RCR 0x0104 /* Receive Counter Register */
#define AT91_SPI_TPR 0x0108 /* Transmit Pointer Register */
#define AT91_SPI_TCR 0x010c /* Transmit Counter Register */
#define AT91_SPI_RNPR 0x0110 /* Receive Next Pointer Register */
#define AT91_SPI_RNCR 0x0114 /* Receive Next Counter Register */
#define AT91_SPI_TNPR 0x0118 /* Transmit Next Pointer Register */
#define AT91_SPI_TNCR 0x011c /* Transmit Next Counter Register */
#define AT91_SPI_PTCR 0x0120 /* PDC Transfer Control Register */
#define AT91_SPI_RXTEN (0x1 << 0) /* Receiver Transfer Enable */
#define AT91_SPI_RXTDIS (0x1 << 1) /* Receiver Transfer Disable */
#define AT91_SPI_TXTEN (0x1 << 8) /* Transmitter Transfer Enable */
#define AT91_SPI_TXTDIS (0x1 << 9) /* Transmitter Transfer Disable */
#define AT91_SPI_PTSR 0x0124 /* PDC Transfer Status Register */
#endif

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/*
* include/asm-arm/arch-at91/at91cap9.h
*
* Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
* Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
* Copyright (C) 2007 Atmel Corporation.
*
* Common definitions.
* Based on AT91CAP9 datasheet revision B (Preliminary).
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91CAP9_H
#define AT91CAP9_H
/*
* Peripheral identifiers/interrupts.
*/
#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
#define AT91_ID_SYS 1 /* System Peripherals */
#define AT91CAP9_ID_PIOABCD 2 /* Parallel IO Controller A, B, C and D */
#define AT91CAP9_ID_MPB0 3 /* MP Block Peripheral 0 */
#define AT91CAP9_ID_MPB1 4 /* MP Block Peripheral 1 */
#define AT91CAP9_ID_MPB2 5 /* MP Block Peripheral 2 */
#define AT91CAP9_ID_MPB3 6 /* MP Block Peripheral 3 */
#define AT91CAP9_ID_MPB4 7 /* MP Block Peripheral 4 */
#define AT91CAP9_ID_US0 8 /* USART 0 */
#define AT91CAP9_ID_US1 9 /* USART 1 */
#define AT91CAP9_ID_US2 10 /* USART 2 */
#define AT91CAP9_ID_MCI0 11 /* Multimedia Card Interface 0 */
#define AT91CAP9_ID_MCI1 12 /* Multimedia Card Interface 1 */
#define AT91CAP9_ID_CAN 13 /* CAN */
#define AT91CAP9_ID_TWI 14 /* Two-Wire Interface */
#define AT91CAP9_ID_SPI0 15 /* Serial Peripheral Interface 0 */
#define AT91CAP9_ID_SPI1 16 /* Serial Peripheral Interface 0 */
#define AT91CAP9_ID_SSC0 17 /* Serial Synchronous Controller 0 */
#define AT91CAP9_ID_SSC1 18 /* Serial Synchronous Controller 1 */
#define AT91CAP9_ID_AC97C 19 /* AC97 Controller */
#define AT91CAP9_ID_TCB 20 /* Timer Counter 0, 1 and 2 */
#define AT91CAP9_ID_PWMC 21 /* Pulse Width Modulation Controller */
#define AT91CAP9_ID_EMAC 22 /* Ethernet */
#define AT91CAP9_ID_AESTDES 23 /* Advanced Encryption Standard, Triple DES */
#define AT91CAP9_ID_ADC 24 /* Analog-to-Digital Converter */
#define AT91CAP9_ID_ISI 25 /* Image Sensor Interface */
#define AT91CAP9_ID_LCDC 26 /* LCD Controller */
#define AT91CAP9_ID_DMA 27 /* DMA Controller */
#define AT91CAP9_ID_UDPHS 28 /* USB High Speed Device Port */
#define AT91CAP9_ID_UHP 29 /* USB Host Port */
#define AT91CAP9_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */
#define AT91CAP9_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */
/*
* User Peripheral physical base addresses.
*/
#define AT91CAP9_BASE_UDPHS 0xfff78000
#define AT91CAP9_BASE_TCB0 0xfff7c000
#define AT91CAP9_BASE_TC0 0xfff7c000
#define AT91CAP9_BASE_TC1 0xfff7c040
#define AT91CAP9_BASE_TC2 0xfff7c080
#define AT91CAP9_BASE_MCI0 0xfff80000
#define AT91CAP9_BASE_MCI1 0xfff84000
#define AT91CAP9_BASE_TWI 0xfff88000
#define AT91CAP9_BASE_US0 0xfff8c000
#define AT91CAP9_BASE_US1 0xfff90000
#define AT91CAP9_BASE_US2 0xfff94000
#define AT91CAP9_BASE_SSC0 0xfff98000
#define AT91CAP9_BASE_SSC1 0xfff9c000
#define AT91CAP9_BASE_AC97C 0xfffa0000
#define AT91CAP9_BASE_SPI0 0xfffa4000
#define AT91CAP9_BASE_SPI1 0xfffa8000
#define AT91CAP9_BASE_CAN 0xfffac000
#define AT91CAP9_BASE_PWMC 0xfffb8000
#define AT91CAP9_BASE_EMAC 0xfffbc000
#define AT91CAP9_BASE_ADC 0xfffc0000
#define AT91CAP9_BASE_ISI 0xfffc4000
#define AT91_BASE_SYS 0xffffe200
/*
* System Peripherals (offset from AT91_BASE_SYS)
*/
#define AT91_ECC (0xffffe200 - AT91_BASE_SYS)
#define AT91_BCRAMC (0xffffe400 - AT91_BASE_SYS)
#define AT91_DDRSDRC (0xffffe600 - AT91_BASE_SYS)
#define AT91_SMC (0xffffe800 - AT91_BASE_SYS)
#define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS)
#define AT91_CCFG (0xffffeb10 - AT91_BASE_SYS)
#define AT91_DMA (0xffffec00 - AT91_BASE_SYS)
#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)
#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
#define AT91_PIOA (0xfffff200 - AT91_BASE_SYS)
#define AT91_PIOB (0xfffff400 - AT91_BASE_SYS)
#define AT91_PIOC (0xfffff600 - AT91_BASE_SYS)
#define AT91_PIOD (0xfffff800 - AT91_BASE_SYS)
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
#define AT91_USART0 AT91CAP9_BASE_US0
#define AT91_USART1 AT91CAP9_BASE_US1
#define AT91_USART2 AT91CAP9_BASE_US2
/*
* Internal Memory.
*/
#define AT91CAP9_SRAM_BASE 0x00100000 /* Internal SRAM base address */
#define AT91CAP9_SRAM_SIZE (32 * SZ_1K) /* Internal SRAM size (32Kb) */
#define AT91CAP9_ROM_BASE 0x00400000 /* Internal ROM base address */
#define AT91CAP9_ROM_SIZE (32 * SZ_1K) /* Internal ROM size (32Kb) */
#define AT91CAP9_LCDC_BASE 0x00500000 /* LCD Controller */
#define AT91CAP9_UDPHS_BASE 0x00600000 /* USB High Speed Device Port */
#define AT91CAP9_UHP_BASE 0x00700000 /* USB Host controller */
#define CONFIG_DRAM_BASE AT91_CHIPSELECT_6
#endif

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/*
* include/asm-arm/arch-at91/at91cap9_matrix.h
*
* Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
* Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
* Copyright (C) 2006 Atmel Corporation.
*
* Memory Controllers (MATRIX, EBI) - System peripherals registers.
* Based on AT91CAP9 datasheet revision B (Preliminary).
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91CAP9_MATRIX_H
#define AT91CAP9_MATRIX_H
#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */
#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */
#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */
#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */
#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */
#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */
#define AT91_MATRIX_MCFG6 (AT91_MATRIX + 0x18) /* Master Configuration Register 6 */
#define AT91_MATRIX_MCFG7 (AT91_MATRIX + 0x1C) /* Master Configuration Register 7 */
#define AT91_MATRIX_MCFG8 (AT91_MATRIX + 0x20) /* Master Configuration Register 8 */
#define AT91_MATRIX_MCFG9 (AT91_MATRIX + 0x24) /* Master Configuration Register 9 */
#define AT91_MATRIX_MCFG10 (AT91_MATRIX + 0x28) /* Master Configuration Register 10 */
#define AT91_MATRIX_MCFG11 (AT91_MATRIX + 0x2C) /* Master Configuration Register 11 */
#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
#define AT91_MATRIX_ULBT_FOUR (2 << 0)
#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */
#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */
#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */
#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */
#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */
#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */
#define AT91_MATRIX_SCFG6 (AT91_MATRIX + 0x58) /* Slave Configuration Register 6 */
#define AT91_MATRIX_SCFG7 (AT91_MATRIX + 0x5C) /* Slave Configuration Register 7 */
#define AT91_MATRIX_SCFG8 (AT91_MATRIX + 0x60) /* Slave Configuration Register 8 */
#define AT91_MATRIX_SCFG9 (AT91_MATRIX + 0x64) /* Slave Configuration Register 9 */
#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */
#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */
#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */
#define AT91_MATRIX_PRBS0 (AT91_MATRIX + 0x84) /* Priority Register B for Slave 0 */
#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */
#define AT91_MATRIX_PRBS1 (AT91_MATRIX + 0x8C) /* Priority Register B for Slave 1 */
#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */
#define AT91_MATRIX_PRBS2 (AT91_MATRIX + 0x94) /* Priority Register B for Slave 2 */
#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */
#define AT91_MATRIX_PRBS3 (AT91_MATRIX + 0x9C) /* Priority Register B for Slave 3 */
#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */
#define AT91_MATRIX_PRBS4 (AT91_MATRIX + 0xA4) /* Priority Register B for Slave 4 */
#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */
#define AT91_MATRIX_PRBS5 (AT91_MATRIX + 0xAC) /* Priority Register B for Slave 5 */
#define AT91_MATRIX_PRAS6 (AT91_MATRIX + 0xB0) /* Priority Register A for Slave 6 */
#define AT91_MATRIX_PRBS6 (AT91_MATRIX + 0xB4) /* Priority Register B for Slave 6 */
#define AT91_MATRIX_PRAS7 (AT91_MATRIX + 0xB8) /* Priority Register A for Slave 7 */
#define AT91_MATRIX_PRBS7 (AT91_MATRIX + 0xBC) /* Priority Register B for Slave 7 */
#define AT91_MATRIX_PRAS8 (AT91_MATRIX + 0xC0) /* Priority Register A for Slave 8 */
#define AT91_MATRIX_PRBS8 (AT91_MATRIX + 0xC4) /* Priority Register B for Slave 8 */
#define AT91_MATRIX_PRAS9 (AT91_MATRIX + 0xC8) /* Priority Register A for Slave 9 */
#define AT91_MATRIX_PRBS9 (AT91_MATRIX + 0xCC) /* Priority Register B for Slave 9 */
#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
#define AT91_MATRIX_M6PR (3 << 24) /* Master 6 Priority */
#define AT91_MATRIX_M7PR (3 << 28) /* Master 7 Priority */
#define AT91_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */
#define AT91_MATRIX_M9PR (3 << 4) /* Master 9 Priority (in Register B) */
#define AT91_MATRIX_M10PR (3 << 8) /* Master 10 Priority (in Register B) */
#define AT91_MATRIX_M11PR (3 << 12) /* Master 11 Priority (in Register B) */
#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */
#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
#define AT91_MATRIX_RCB2 (1 << 2)
#define AT91_MATRIX_RCB3 (1 << 3)
#define AT91_MATRIX_RCB4 (1 << 4)
#define AT91_MATRIX_RCB5 (1 << 5)
#define AT91_MATRIX_RCB6 (1 << 6)
#define AT91_MATRIX_RCB7 (1 << 7)
#define AT91_MATRIX_RCB8 (1 << 8)
#define AT91_MATRIX_RCB9 (1 << 9)
#define AT91_MATRIX_RCB10 (1 << 10)
#define AT91_MATRIX_RCB11 (1 << 11)
#define AT91_MPBS0_SFR (AT91_MATRIX + 0x114) /* MPBlock Slave 0 Special Function Register */
#define AT91_MPBS1_SFR (AT91_MATRIX + 0x11C) /* MPBlock Slave 1 Special Function Register */
#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x120) /* EBI Chip Select Assignment Register */
#define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1)
#define AT91_MATRIX_EBI_CS1A_BCRAMC (1 << 1)
#define AT91_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */
#define AT91_MATRIX_EBI_CS3A_SMC (0 << 3)
#define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA (1 << 3)
#define AT91_MATRIX_EBI_CS4A (1 << 4) /* Chip Select 4 Assignment */
#define AT91_MATRIX_EBI_CS4A_SMC (0 << 4)
#define AT91_MATRIX_EBI_CS4A_SMC_CF1 (1 << 4)
#define AT91_MATRIX_EBI_CS5A (1 << 5) /* Chip Select 5 Assignment */
#define AT91_MATRIX_EBI_CS5A_SMC (0 << 5)
#define AT91_MATRIX_EBI_CS5A_SMC_CF2 (1 << 5)
#define AT91_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
#define AT91_MATRIX_EBI_DQSPDC (1 << 9) /* Data Qualifier Strobe Pull-Down Configuration */
#define AT91_MATRIX_EBI_VDDIOMSEL (1 << 16) /* Memory voltage selection */
#define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16)
#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16)
#define AT91_MPBS2_SFR (AT91_MATRIX + 0x12C) /* MPBlock Slave 2 Special Function Register */
#define AT91_MPBS3_SFR (AT91_MATRIX + 0x130) /* MPBlock Slave 3 Special Function Register */
#define AT91_APB_SFR (AT91_MATRIX + 0x134) /* APB Bridge Special Function Register */
#endif

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/*
* include/asm-arm/arch-at91/at91sam9260.h
*
* (C) 2006 Andrew Victor
*
* Common definitions.
* Based on AT91SAM9260 datasheet revision A (Preliminary).
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91SAM9260_H
#define AT91SAM9260_H
/*
* Peripheral identifiers/interrupts.
*/
#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
#define AT91_ID_SYS 1 /* System Peripherals */
#define AT91SAM9260_ID_PIOA 2 /* Parallel IO Controller A */
#define AT91SAM9260_ID_PIOB 3 /* Parallel IO Controller B */
#define AT91SAM9260_ID_PIOC 4 /* Parallel IO Controller C */
#define AT91SAM9260_ID_ADC 5 /* Analog-to-Digital Converter */
#define AT91SAM9260_ID_US0 6 /* USART 0 */
#define AT91SAM9260_ID_US1 7 /* USART 1 */
#define AT91SAM9260_ID_US2 8 /* USART 2 */
#define AT91SAM9260_ID_MCI 9 /* Multimedia Card Interface */
#define AT91SAM9260_ID_UDP 10 /* USB Device Port */
#define AT91SAM9260_ID_TWI 11 /* Two-Wire Interface */
#define AT91SAM9260_ID_SPI0 12 /* Serial Peripheral Interface 0 */
#define AT91SAM9260_ID_SPI1 13 /* Serial Peripheral Interface 1 */
#define AT91SAM9260_ID_SSC 14 /* Serial Synchronous Controller */
#define AT91SAM9260_ID_TC0 17 /* Timer Counter 0 */
#define AT91SAM9260_ID_TC1 18 /* Timer Counter 1 */
#define AT91SAM9260_ID_TC2 19 /* Timer Counter 2 */
#define AT91SAM9260_ID_UHP 20 /* USB Host port */
#define AT91SAM9260_ID_EMAC 21 /* Ethernet */
#define AT91SAM9260_ID_ISI 22 /* Image Sensor Interface */
#define AT91SAM9260_ID_US3 23 /* USART 3 */
#define AT91SAM9260_ID_US4 24 /* USART 4 */
#define AT91SAM9260_ID_US5 25 /* USART 5 */
#define AT91SAM9260_ID_TC3 26 /* Timer Counter 3 */
#define AT91SAM9260_ID_TC4 27 /* Timer Counter 4 */
#define AT91SAM9260_ID_TC5 28 /* Timer Counter 5 */
#define AT91SAM9260_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */
#define AT91SAM9260_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */
#define AT91SAM9260_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */
/*
* User Peripheral physical base addresses.
*/
#define AT91SAM9260_BASE_TCB0 0xfffa0000
#define AT91SAM9260_BASE_TC0 0xfffa0000
#define AT91SAM9260_BASE_TC1 0xfffa0040
#define AT91SAM9260_BASE_TC2 0xfffa0080
#define AT91SAM9260_BASE_UDP 0xfffa4000
#define AT91SAM9260_BASE_MCI 0xfffa8000
#define AT91SAM9260_BASE_TWI 0xfffac000
#define AT91SAM9260_BASE_US0 0xfffb0000
#define AT91SAM9260_BASE_US1 0xfffb4000
#define AT91SAM9260_BASE_US2 0xfffb8000
#define AT91SAM9260_BASE_SSC 0xfffbc000
#define AT91SAM9260_BASE_ISI 0xfffc0000
#define AT91SAM9260_BASE_EMAC 0xfffc4000
#define AT91SAM9260_BASE_SPI0 0xfffc8000
#define AT91SAM9260_BASE_SPI1 0xfffcc000
#define AT91SAM9260_BASE_US3 0xfffd0000
#define AT91SAM9260_BASE_US4 0xfffd4000
#define AT91SAM9260_BASE_US5 0xfffd8000
#define AT91SAM9260_BASE_TCB1 0xfffdc000
#define AT91SAM9260_BASE_TC3 0xfffdc000
#define AT91SAM9260_BASE_TC4 0xfffdc040
#define AT91SAM9260_BASE_TC5 0xfffdc080
#define AT91SAM9260_BASE_ADC 0xfffe0000
#define AT91_BASE_SYS 0xffffe800
/*
* System Peripherals (offset from AT91_BASE_SYS)
*/
#define AT91_ECC (0xffffe800 - AT91_BASE_SYS)
#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS)
#define AT91_SMC (0xffffec00 - AT91_BASE_SYS)
#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
#define AT91_CCFG (0xffffef10 - AT91_BASE_SYS)
#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS)
#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS)
#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS)
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
#define AT91_USART0 AT91SAM9260_BASE_US0
#define AT91_USART1 AT91SAM9260_BASE_US1
#define AT91_USART2 AT91SAM9260_BASE_US2
#define AT91_USART3 AT91SAM9260_BASE_US3
#define AT91_USART4 AT91SAM9260_BASE_US4
#define AT91_USART5 AT91SAM9260_BASE_US5
/*
* Internal Memory.
*/
#define AT91SAM9260_ROM_BASE 0x00100000 /* Internal ROM base address */
#define AT91SAM9260_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */
#define AT91SAM9260_SRAM0_BASE 0x00200000 /* Internal SRAM 0 base address */
#define AT91SAM9260_SRAM0_SIZE SZ_4K /* Internal SRAM 0 size (4Kb) */
#define AT91SAM9260_SRAM1_BASE 0x00300000 /* Internal SRAM 1 base address */
#define AT91SAM9260_SRAM1_SIZE SZ_4K /* Internal SRAM 1 size (4Kb) */
#define AT91SAM9260_UHP_BASE 0x00500000 /* USB Host controller */
#define AT91SAM9XE_FLASH_BASE 0x00200000 /* Internal FLASH base address */
#define AT91SAM9XE_SRAM_BASE 0x00300000 /* Internal SRAM base address */
#endif

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include/asm-arm/arch-at91sam9/at91sam9260_matrix.h Normal file
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/*
* include/asm-arm/arch-at91/at91sam9260_matrix.h
*
* Memory Controllers (MATRIX, EBI) - System peripherals registers.
* Based on AT91SAM9260 datasheet revision B.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91SAM9260_MATRIX_H
#define AT91SAM9260_MATRIX_H
#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */
#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */
#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */
#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */
#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */
#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */
#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
#define AT91_MATRIX_ULBT_FOUR (2 << 0)
#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */
#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */
#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */
#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */
#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */
#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */
#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */
#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */
#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */
#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */
#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */
#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */
#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */
#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x11C) /* EBI Chip Select Assignment Register */
#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */
#define AT91_MATRIX_CS1A_SMC (0 << 1)
#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */
#define AT91_MATRIX_CS3A_SMC (0 << 3)
#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */
#define AT91_MATRIX_CS4A_SMC (0 << 4)
#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4)
#define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */
#define AT91_MATRIX_CS5A_SMC (0 << 5)
#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5)
#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
#define AT91_MATRIX_VDDIOMSEL (1 << 16) /* Memory voltage selection */
#define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16)
#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16)
#endif

140
include/asm-arm/arch-at91sam9/at91sam926x_mc.h Normal file
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/*
* include/asm-arm/arch-at91/at91sam926x_mc.h
*
* Memory Controllers (SMC, SDRAMC) - System peripherals registers.
* Based on AT91SAM9261 datasheet revision D.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91SAM926x_MC_H
#define AT91SAM926x_MC_H
/* SDRAM Controller (SDRAMC) registers */
#define AT91_SDRAMC_MR (AT91_SDRAMC + 0x00) /* SDRAM Controller Mode Register */
#define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */
#define AT91_SDRAMC_MODE_NORMAL 0
#define AT91_SDRAMC_MODE_NOP 1
#define AT91_SDRAMC_MODE_PRECHARGE 2
#define AT91_SDRAMC_MODE_LMR 3
#define AT91_SDRAMC_MODE_REFRESH 4
#define AT91_SDRAMC_MODE_EXT_LMR 5
#define AT91_SDRAMC_MODE_DEEP 6
#define AT91_SDRAMC_TR (AT91_SDRAMC + 0x04) /* SDRAM Controller Refresh Timer Register */
#define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Counter */
#define AT91_SDRAMC_CR (AT91_SDRAMC + 0x08) /* SDRAM Controller Configuration Register */
#define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */
#define AT91_SDRAMC_NC_8 (0 << 0)
#define AT91_SDRAMC_NC_9 (1 << 0)
#define AT91_SDRAMC_NC_10 (2 << 0)
#define AT91_SDRAMC_NC_11 (3 << 0)
#define AT91_SDRAMC_NR (3 << 2) /* Number of Row Bits */
#define AT91_SDRAMC_NR_11 (0 << 2)
#define AT91_SDRAMC_NR_12 (1 << 2)
#define AT91_SDRAMC_NR_13 (2 << 2)
#define AT91_SDRAMC_NB (1 << 4) /* Number of Banks */
#define AT91_SDRAMC_NB_2 (0 << 4)
#define AT91_SDRAMC_NB_4 (1 << 4)
#define AT91_SDRAMC_CAS (3 << 5) /* CAS Latency */
#define AT91_SDRAMC_CAS_1 (1 << 5)
#define AT91_SDRAMC_CAS_2 (2 << 5)
#define AT91_SDRAMC_CAS_3 (3 << 5)
#define AT91_SDRAMC_DBW (1 << 7) /* Data Bus Width */
#define AT91_SDRAMC_DBW_32 (0 << 7)
#define AT91_SDRAMC_DBW_16 (1 << 7)
#define AT91_SDRAMC_TWR (0xf << 8) /* Write Recovery Delay */
#define AT91_SDRAMC_TRC (0xf << 12) /* Row Cycle Delay */
#define AT91_SDRAMC_TRP (0xf << 16) /* Row Precharge Delay */
#define AT91_SDRAMC_TRCD (0xf << 20) /* Row to Column Delay */
#define AT91_SDRAMC_TRAS (0xf << 24) /* Active to Precharge Delay */
#define AT91_SDRAMC_TXSR (0xf << 28) /* Exit Self Refresh to Active Delay */
#define AT91_SDRAMC_LPR (AT91_SDRAMC + 0x10) /* SDRAM Controller Low Power Register */
#define AT91_SDRAMC_LPCB (3 << 0) /* Low-power Configurations */
#define AT91_SDRAMC_LPCB_DISABLE 0
#define AT91_SDRAMC_LPCB_SELF_REFRESH 1
#define AT91_SDRAMC_LPCB_POWER_DOWN 2
#define AT91_SDRAMC_LPCB_DEEP_POWER_DOWN 3
#define AT91_SDRAMC_PASR (7 << 4) /* Partial Array Self Refresh */
#define AT91_SDRAMC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */
#define AT91_SDRAMC_DS (3 << 10) /* Drive Strenght */
#define AT91_SDRAMC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */
#define AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES (0 << 12)
#define AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES (1 << 12)
#define AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES (2 << 12)
#define AT91_SDRAMC_IER (AT91_SDRAMC + 0x14) /* SDRAM Controller Interrupt Enable Register */
#define AT91_SDRAMC_IDR (AT91_SDRAMC + 0x18) /* SDRAM Controller Interrupt Disable Register */
#define AT91_SDRAMC_IMR (AT91_SDRAMC + 0x1C) /* SDRAM Controller Interrupt Mask Register */
#define AT91_SDRAMC_ISR (AT91_SDRAMC + 0x20) /* SDRAM Controller Interrupt Status Register */
#define AT91_SDRAMC_RES (1 << 0) /* Refresh Error Status */
#define AT91_SDRAMC_MDR (AT91_SDRAMC + 0x24) /* SDRAM Memory Device Register */
#define AT91_SDRAMC_MD (3 << 0) /* Memory Device Type */
#define AT91_SDRAMC_MD_SDRAM 0
#define AT91_SDRAMC_MD_LOW_POWER_SDRAM 1
/* Static Memory Controller (SMC) registers */
#define AT91_SMC_SETUP(n) (AT91_SMC + 0x00 + ((n)*0x10)) /* Setup Register for CS n */
#define AT91_SMC_NWESETUP (0x3f << 0) /* NWE Setup Length */
#define AT91_SMC_NWESETUP_(x) ((x) << 0)
#define AT91_SMC_NCS_WRSETUP (0x3f << 8) /* NCS Setup Length in Write Access */
#define AT91_SMC_NCS_WRSETUP_(x) ((x) << 8)
#define AT91_SMC_NRDSETUP (0x3f << 16) /* NRD Setup Length */
#define AT91_SMC_NRDSETUP_(x) ((x) << 16)
#define AT91_SMC_NCS_RDSETUP (0x3f << 24) /* NCS Setup Length in Read Access */
#define AT91_SMC_NCS_RDSETUP_(x) ((x) << 24)
#define AT91_SMC_PULSE(n) (AT91_SMC + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */
#define AT91_SMC_NWEPULSE (0x7f << 0) /* NWE Pulse Length */
#define AT91_SMC_NWEPULSE_(x) ((x) << 0)
#define AT91_SMC_NCS_WRPULSE (0x7f << 8) /* NCS Pulse Length in Write Access */
#define AT91_SMC_NCS_WRPULSE_(x)((x) << 8)
#define AT91_SMC_NRDPULSE (0x7f << 16) /* NRD Pulse Length */
#define AT91_SMC_NRDPULSE_(x) ((x) << 16)
#define AT91_SMC_NCS_RDPULSE (0x7f << 24) /* NCS Pulse Length in Read Access */
#define AT91_SMC_NCS_RDPULSE_(x)((x) << 24)
#define AT91_SMC_CYCLE(n) (AT91_SMC + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */
#define AT91_SMC_NWECYCLE (0x1ff << 0 ) /* Total Write Cycle Length */
#define AT91_SMC_NWECYCLE_(x) ((x) << 0)
#define AT91_SMC_NRDCYCLE (0x1ff << 16) /* Total Read Cycle Length */
#define AT91_SMC_NRDCYCLE_(x) ((x) << 16)
#define AT91_SMC_MODE(n) (AT91_SMC + 0x0c + ((n)*0x10)) /* Mode Register for CS n */
#define AT91_SMC_READMODE (1 << 0) /* Read Mode */
#define AT91_SMC_WRITEMODE (1 << 1) /* Write Mode */
#define AT91_SMC_EXNWMODE (3 << 4) /* NWAIT Mode */
#define AT91_SMC_EXNWMODE_DISABLE (0 << 4)
#define AT91_SMC_EXNWMODE_FROZEN (2 << 4)
#define AT91_SMC_EXNWMODE_READY (3 << 4)
#define AT91_SMC_BAT (1 << 8) /* Byte Access Type */
#define AT91_SMC_BAT_SELECT (0 << 8)
#define AT91_SMC_BAT_WRITE (1 << 8)
#define AT91_SMC_DBW (3 << 12) /* Data Bus Width */
#define AT91_SMC_DBW_8 (0 << 12)
#define AT91_SMC_DBW_16 (1 << 12)
#define AT91_SMC_DBW_32 (2 << 12)
#define AT91_SMC_TDF (0xf << 16) /* Data Float Time. */
#define AT91_SMC_TDF_(x) ((x) << 16)
#define AT91_SMC_TDFMODE (1 << 20) /* TDF Optimization - Enabled */
#define AT91_SMC_PMEN (1 << 24) /* Page Mode Enabled */
#define AT91_SMC_PS (3 << 28) /* Page Size */
#define AT91_SMC_PS_4 (0 << 28)
#define AT91_SMC_PS_8 (1 << 28)
#define AT91_SMC_PS_16 (2 << 28)
#define AT91_SMC_PS_32 (3 << 28)
#if defined(AT91_SMC1) /* The AT91SAM9263 has 2 Static Memory contollers */
#define AT91_SMC1_SETUP(n) (AT91_SMC1 + 0x00 + ((n)*0x10)) /* Setup Register for CS n */
#define AT91_SMC1_PULSE(n) (AT91_SMC1 + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */
#define AT91_SMC1_CYCLE(n) (AT91_SMC1 + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */
#define AT91_SMC1_MODE(n) (AT91_SMC1 + 0x0c + ((n)*0x10)) /* Mode Register for CS n */
#endif
#endif

4
include/asm-arm/arch-at91cap9/clk.h → include/asm-arm/arch-at91sam9/clk.h
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@ -28,12 +28,12 @@
static inline unsigned long get_macb_pclk_rate(unsigned int dev_id)
{
return AT91C_MASTER_CLOCK;
return AT91_MASTER_CLOCK;
}
static inline unsigned long get_usart_clk_rate(unsigned int dev_id)
{
return AT91C_MASTER_CLOCK;
return AT91_MASTER_CLOCK;
}
#endif /* __ASM_ARM_ARCH_CLK_H__ */

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include/asm-arm/arch-at91sam9/gpio.h Normal file
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/*
* include/asm-arm/arch-at91/gpio.h
*
* Copyright (C) 2005 HP Labs
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
*/
#ifndef __ASM_ARCH_AT91_GPIO_H
#define __ASM_ARCH_AT91_GPIO_H
#include <asm/io.h>
#include <asm/errno.h>
#include <asm/arch/at91_pio.h>
#define PIN_BASE 32
#define MAX_GPIO_BANKS 5
/* these pin numbers double as IRQ numbers, like AT91xxx_ID_* values */
#define AT91_PIN_PA0 (PIN_BASE + 0x00 + 0)
#define AT91_PIN_PA1 (PIN_BASE + 0x00 + 1)
#define AT91_PIN_PA2 (PIN_BASE + 0x00 + 2)
#define AT91_PIN_PA3 (PIN_BASE + 0x00 + 3)
#define AT91_PIN_PA4 (PIN_BASE + 0x00 + 4)
#define AT91_PIN_PA5 (PIN_BASE + 0x00 + 5)
#define AT91_PIN_PA6 (PIN_BASE + 0x00 + 6)
#define AT91_PIN_PA7 (PIN_BASE + 0x00 + 7)
#define AT91_PIN_PA8 (PIN_BASE + 0x00 + 8)
#define AT91_PIN_PA9 (PIN_BASE + 0x00 + 9)
#define AT91_PIN_PA10 (PIN_BASE + 0x00 + 10)
#define AT91_PIN_PA11 (PIN_BASE + 0x00 + 11)
#define AT91_PIN_PA12 (PIN_BASE + 0x00 + 12)
#define AT91_PIN_PA13 (PIN_BASE + 0x00 + 13)
#define AT91_PIN_PA14 (PIN_BASE + 0x00 + 14)
#define AT91_PIN_PA15 (PIN_BASE + 0x00 + 15)
#define AT91_PIN_PA16 (PIN_BASE + 0x00 + 16)
#define AT91_PIN_PA17 (PIN_BASE + 0x00 + 17)
#define AT91_PIN_PA18 (PIN_BASE + 0x00 + 18)
#define AT91_PIN_PA19 (PIN_BASE + 0x00 + 19)
#define AT91_PIN_PA20 (PIN_BASE + 0x00 + 20)
#define AT91_PIN_PA21 (PIN_BASE + 0x00 + 21)
#define AT91_PIN_PA22 (PIN_BASE + 0x00 + 22)
#define AT91_PIN_PA23 (PIN_BASE + 0x00 + 23)
#define AT91_PIN_PA24 (PIN_BASE + 0x00 + 24)
#define AT91_PIN_PA25 (PIN_BASE + 0x00 + 25)
#define AT91_PIN_PA26 (PIN_BASE + 0x00 + 26)
#define AT91_PIN_PA27 (PIN_BASE + 0x00 + 27)
#define AT91_PIN_PA28 (PIN_BASE + 0x00 + 28)
#define AT91_PIN_PA29 (PIN_BASE + 0x00 + 29)
#define AT91_PIN_PA30 (PIN_BASE + 0x00 + 30)
#define AT91_PIN_PA31 (PIN_BASE + 0x00 + 31)
#define AT91_PIN_PB0 (PIN_BASE + 0x20 + 0)
#define AT91_PIN_PB1 (PIN_BASE + 0x20 + 1)
#define AT91_PIN_PB2 (PIN_BASE + 0x20 + 2)
#define AT91_PIN_PB3 (PIN_BASE + 0x20 + 3)
#define AT91_PIN_PB4 (PIN_BASE + 0x20 + 4)
#define AT91_PIN_PB5 (PIN_BASE + 0x20 + 5)
#define AT91_PIN_PB6 (PIN_BASE + 0x20 + 6)
#define AT91_PIN_PB7 (PIN_BASE + 0x20 + 7)
#define AT91_PIN_PB8 (PIN_BASE + 0x20 + 8)
#define AT91_PIN_PB9 (PIN_BASE + 0x20 + 9)
#define AT91_PIN_PB10 (PIN_BASE + 0x20 + 10)
#define AT91_PIN_PB11 (PIN_BASE + 0x20 + 11)
#define AT91_PIN_PB12 (PIN_BASE + 0x20 + 12)
#define AT91_PIN_PB13 (PIN_BASE + 0x20 + 13)
#define AT91_PIN_PB14 (PIN_BASE + 0x20 + 14)
#define AT91_PIN_PB15 (PIN_BASE + 0x20 + 15)
#define AT91_PIN_PB16 (PIN_BASE + 0x20 + 16)
#define AT91_PIN_PB17 (PIN_BASE + 0x20 + 17)
#define AT91_PIN_PB18 (PIN_BASE + 0x20 + 18)
#define AT91_PIN_PB19 (PIN_BASE + 0x20 + 19)
#define AT91_PIN_PB20 (PIN_BASE + 0x20 + 20)
#define AT91_PIN_PB21 (PIN_BASE + 0x20 + 21)
#define AT91_PIN_PB22 (PIN_BASE + 0x20 + 22)
#define AT91_PIN_PB23 (PIN_BASE + 0x20 + 23)
#define AT91_PIN_PB24 (PIN_BASE + 0x20 + 24)
#define AT91_PIN_PB25 (PIN_BASE + 0x20 + 25)
#define AT91_PIN_PB26 (PIN_BASE + 0x20 + 26)
#define AT91_PIN_PB27 (PIN_BASE + 0x20 + 27)
#define AT91_PIN_PB28 (PIN_BASE + 0x20 + 28)
#define AT91_PIN_PB29 (PIN_BASE + 0x20 + 29)
#define AT91_PIN_PB30 (PIN_BASE + 0x20 + 30)
#define AT91_PIN_PB31 (PIN_BASE + 0x20 + 31)
#define AT91_PIN_PC0 (PIN_BASE + 0x40 + 0)
#define AT91_PIN_PC1 (PIN_BASE + 0x40 + 1)
#define AT91_PIN_PC2 (PIN_BASE + 0x40 + 2)
#define AT91_PIN_PC3 (PIN_BASE + 0x40 + 3)
#define AT91_PIN_PC4 (PIN_BASE + 0x40 + 4)
#define AT91_PIN_PC5 (PIN_BASE + 0x40 + 5)
#define AT91_PIN_PC6 (PIN_BASE + 0x40 + 6)
#define AT91_PIN_PC7 (PIN_BASE + 0x40 + 7)
#define AT91_PIN_PC8 (PIN_BASE + 0x40 + 8)
#define AT91_PIN_PC9 (PIN_BASE + 0x40 + 9)
#define AT91_PIN_PC10 (PIN_BASE + 0x40 + 10)
#define AT91_PIN_PC11 (PIN_BASE + 0x40 + 11)
#define AT91_PIN_PC12 (PIN_BASE + 0x40 + 12)
#define AT91_PIN_PC13 (PIN_BASE + 0x40 + 13)
#define AT91_PIN_PC14 (PIN_BASE + 0x40 + 14)
#define AT91_PIN_PC15 (PIN_BASE + 0x40 + 15)
#define AT91_PIN_PC16 (PIN_BASE + 0x40 + 16)
#define AT91_PIN_PC17 (PIN_BASE + 0x40 + 17)
#define AT91_PIN_PC18 (PIN_BASE + 0x40 + 18)
#define AT91_PIN_PC19 (PIN_BASE + 0x40 + 19)
#define AT91_PIN_PC20 (PIN_BASE + 0x40 + 20)
#define AT91_PIN_PC21 (PIN_BASE + 0x40 + 21)
#define AT91_PIN_PC22 (PIN_BASE + 0x40 + 22)
#define AT91_PIN_PC23 (PIN_BASE + 0x40 + 23)
#define AT91_PIN_PC24 (PIN_BASE + 0x40 + 24)
#define AT91_PIN_PC25 (PIN_BASE + 0x40 + 25)
#define AT91_PIN_PC26 (PIN_BASE + 0x40 + 26)
#define AT91_PIN_PC27 (PIN_BASE + 0x40 + 27)
#define AT91_PIN_PC28 (PIN_BASE + 0x40 + 28)
#define AT91_PIN_PC29 (PIN_BASE + 0x40 + 29)
#define AT91_PIN_PC30 (PIN_BASE + 0x40 + 30)
#define AT91_PIN_PC31 (PIN_BASE + 0x40 + 31)
#define AT91_PIN_PD0 (PIN_BASE + 0x60 + 0)
#define AT91_PIN_PD1 (PIN_BASE + 0x60 + 1)
#define AT91_PIN_PD2 (PIN_BASE + 0x60 + 2)
#define AT91_PIN_PD3 (PIN_BASE + 0x60 + 3)
#define AT91_PIN_PD4 (PIN_BASE + 0x60 + 4)
#define AT91_PIN_PD5 (PIN_BASE + 0x60 + 5)
#define AT91_PIN_PD6 (PIN_BASE + 0x60 + 6)
#define AT91_PIN_PD7 (PIN_BASE + 0x60 + 7)
#define AT91_PIN_PD8 (PIN_BASE + 0x60 + 8)
#define AT91_PIN_PD9 (PIN_BASE + 0x60 + 9)
#define AT91_PIN_PD10 (PIN_BASE + 0x60 + 10)
#define AT91_PIN_PD11 (PIN_BASE + 0x60 + 11)
#define AT91_PIN_PD12 (PIN_BASE + 0x60 + 12)
#define AT91_PIN_PD13 (PIN_BASE + 0x60 + 13)
#define AT91_PIN_PD14 (PIN_BASE + 0x60 + 14)
#define AT91_PIN_PD15 (PIN_BASE + 0x60 + 15)
#define AT91_PIN_PD16 (PIN_BASE + 0x60 + 16)
#define AT91_PIN_PD17 (PIN_BASE + 0x60 + 17)
#define AT91_PIN_PD18 (PIN_BASE + 0x60 + 18)
#define AT91_PIN_PD19 (PIN_BASE + 0x60 + 19)
#define AT91_PIN_PD20 (PIN_BASE + 0x60 + 20)
#define AT91_PIN_PD21 (PIN_BASE + 0x60 + 21)
#define AT91_PIN_PD22 (PIN_BASE + 0x60 + 22)
#define AT91_PIN_PD23 (PIN_BASE + 0x60 + 23)
#define AT91_PIN_PD24 (PIN_BASE + 0x60 + 24)
#define AT91_PIN_PD25 (PIN_BASE + 0x60 + 25)
#define AT91_PIN_PD26 (PIN_BASE + 0x60 + 26)
#define AT91_PIN_PD27 (PIN_BASE + 0x60 + 27)
#define AT91_PIN_PD28 (PIN_BASE + 0x60 + 28)
#define AT91_PIN_PD29 (PIN_BASE + 0x60 + 29)
#define AT91_PIN_PD30 (PIN_BASE + 0x60 + 30)
#define AT91_PIN_PD31 (PIN_BASE + 0x60 + 31)
#define AT91_PIN_PE0 (PIN_BASE + 0x80 + 0)
#define AT91_PIN_PE1 (PIN_BASE + 0x80 + 1)
#define AT91_PIN_PE2 (PIN_BASE + 0x80 + 2)
#define AT91_PIN_PE3 (PIN_BASE + 0x80 + 3)
#define AT91_PIN_PE4 (PIN_BASE + 0x80 + 4)
#define AT91_PIN_PE5 (PIN_BASE + 0x80 + 5)
#define AT91_PIN_PE6 (PIN_BASE + 0x80 + 6)
#define AT91_PIN_PE7 (PIN_BASE + 0x80 + 7)
#define AT91_PIN_PE8 (PIN_BASE + 0x80 + 8)
#define AT91_PIN_PE9 (PIN_BASE + 0x80 + 9)
#define AT91_PIN_PE10 (PIN_BASE + 0x80 + 10)
#define AT91_PIN_PE11 (PIN_BASE + 0x80 + 11)
#define AT91_PIN_PE12 (PIN_BASE + 0x80 + 12)
#define AT91_PIN_PE13 (PIN_BASE + 0x80 + 13)
#define AT91_PIN_PE14 (PIN_BASE + 0x80 + 14)
#define AT91_PIN_PE15 (PIN_BASE + 0x80 + 15)
#define AT91_PIN_PE16 (PIN_BASE + 0x80 + 16)
#define AT91_PIN_PE17 (PIN_BASE + 0x80 + 17)
#define AT91_PIN_PE18 (PIN_BASE + 0x80 + 18)
#define AT91_PIN_PE19 (PIN_BASE + 0x80 + 19)
#define AT91_PIN_PE20 (PIN_BASE + 0x80 + 20)
#define AT91_PIN_PE21 (PIN_BASE + 0x80 + 21)
#define AT91_PIN_PE22 (PIN_BASE + 0x80 + 22)
#define AT91_PIN_PE23 (PIN_BASE + 0x80 + 23)
#define AT91_PIN_PE24 (PIN_BASE + 0x80 + 24)
#define AT91_PIN_PE25 (PIN_BASE + 0x80 + 25)
#define AT91_PIN_PE26 (PIN_BASE + 0x80 + 26)
#define AT91_PIN_PE27 (PIN_BASE + 0x80 + 27)
#define AT91_PIN_PE28 (PIN_BASE + 0x80 + 28)
#define AT91_PIN_PE29 (PIN_BASE + 0x80 + 29)
#define AT91_PIN_PE30 (PIN_BASE + 0x80 + 30)
#define AT91_PIN_PE31 (PIN_BASE + 0x80 + 31)
static unsigned long at91_pios[] = {
AT91_PIOA,
AT91_PIOB,
AT91_PIOC,
#ifdef AT91_PIOD
AT91_PIOD,
#ifdef AT91_PIOE
AT91_PIOE
#endif
#endif
};
static inline void *pin_to_controller(unsigned pin)
{
pin -= PIN_BASE;
pin /= 32;
return (void *)(AT91_BASE_SYS + at91_pios[pin]);
}
static inline unsigned pin_to_mask(unsigned pin)
{
pin -= PIN_BASE;
return 1 << (pin % 32);
}
/*
* mux the pin to the "GPIO" peripheral role.
*/
static inline int at91_set_GPIO_periph(unsigned pin, int use_pullup)
{
void *pio = pin_to_controller(pin);
unsigned mask = pin_to_mask(pin);
__raw_writel(mask, pio + PIO_IDR);
__raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
__raw_writel(mask, pio + PIO_PER);
return 0;
}
/*
* mux the pin to the "A" internal peripheral role.
*/
static inline int at91_set_A_periph(unsigned pin, int use_pullup)
{
void *pio = pin_to_controller(pin);
unsigned mask = pin_to_mask(pin);
__raw_writel(mask, pio + PIO_IDR);
__raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
__raw_writel(mask, pio + PIO_ASR);
__raw_writel(mask, pio + PIO_PDR);
return 0;
}
/*
* mux the pin to the "B" internal peripheral role.
*/
static inline int at91_set_B_periph(unsigned pin, int use_pullup)
{
void *pio = pin_to_controller(pin);
unsigned mask = pin_to_mask(pin);
__raw_writel(mask, pio + PIO_IDR);
__raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
__raw_writel(mask, pio + PIO_BSR);
__raw_writel(mask, pio + PIO_PDR);
return 0;
}
/*
* mux the pin to the gpio controller (instead of "A" or "B" peripheral), and
* configure it for an input.
*/
static inline int at91_set_gpio_input(unsigned pin, int use_pullup)
{
void *pio = pin_to_controller(pin);
unsigned mask = pin_to_mask(pin);
__raw_writel(mask, pio + PIO_IDR);
__raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
__raw_writel(mask, pio + PIO_ODR);
__raw_writel(mask, pio + PIO_PER);
return 0;
}
/*
* mux the pin to the gpio controller (instead of "A" or "B" peripheral),
* and configure it for an output.
*/
static inline int at91_set_gpio_output(unsigned pin, int value)
{
void *pio = pin_to_controller(pin);
unsigned mask = pin_to_mask(pin);
__raw_writel(mask, pio + PIO_IDR);
__raw_writel(mask, pio + PIO_PUDR);
__raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
__raw_writel(mask, pio + PIO_OER);
__raw_writel(mask, pio + PIO_PER);
return 0;
}
/*
* enable/disable the glitch filter; mostly used with IRQ handling.
*/
static inline int at91_set_deglitch(unsigned pin, int is_on)
{
void *pio = pin_to_controller(pin);
unsigned mask = pin_to_mask(pin);
__raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
return 0;
}
/*
* enable/disable the multi-driver; This is only valid for output and
* allows the output pin to run as an open collector output.
*/
static inline int at91_set_multi_drive(unsigned pin, int is_on)
{
void *pio = pin_to_controller(pin);
unsigned mask = pin_to_mask(pin);
__raw_writel(mask, pio + (is_on ? PIO_MDER : PIO_MDDR));
return 0;
}
static inline int gpio_direction_input(unsigned pin)
{
void *pio = pin_to_controller(pin);
unsigned mask = pin_to_mask(pin);
if (!(__raw_readl(pio + PIO_PSR) & mask))
return -EINVAL;
__raw_writel(mask, pio + PIO_ODR);
return 0;
}
static inline int gpio_direction_output(unsigned pin, int value)
{
void *pio = pin_to_controller(pin);
unsigned mask = pin_to_mask(pin);
if (!(__raw_readl(pio + PIO_PSR) & mask))
return -EINVAL;
__raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
__raw_writel(mask, pio + PIO_OER);
return 0;
}
/*
* assuming the pin is muxed as a gpio output, set its value.
*/
static inline int at91_set_gpio_value(unsigned pin, int value)
{
void *pio = pin_to_controller(pin);
unsigned mask = pin_to_mask(pin);
__raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
return 0;
}
/*
* read the pin's value (works even if it's not muxed as a gpio).
*/
static inline int at91_get_gpio_value(unsigned pin)
{
void *pio = pin_to_controller(pin);
unsigned mask = pin_to_mask(pin);
u32 pdsr;
pdsr = __raw_readl(pio + PIO_PDSR);
return (pdsr & mask) != 0;
}
#endif

56
include/asm-arm/arch-at91sam9/hardware.h Normal file
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@ -0,0 +1,56 @@
/*
* include/asm-arm/arch-at91/hardware.h
*
* Copyright (C) 2003 SAN People
* Copyright (C) 2003 ATMEL
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
*/
#ifndef __ASM_ARCH_HARDWARE_H
#define __ASM_ARCH_HARDWARE_H
#include <asm/sizes.h>
#if defined(CONFIG_AT91RM9200)
#include <asm/arch/at91rm9200.h>
#elif defined(CONFIG_AT91SAM9260)
#include <asm/arch/at91sam9260.h>
#define AT91_BASE_EMAC AT91SAM9260_BASE_EMAC
#define AT91_BASE_SPI AT91SAM9260_BASE_SPI0
#define AT91_ID_UHP AT91SAM9260_ID_UHP
#define AT91_PMC_UHP AT91SAM926x_PMC_UHP
#elif defined(CONFIG_AT91SAM9261)
#include <asm/arch/at91sam9261.h>
#elif defined(CONFIG_AT91SAM9263)
#include <asm/arch/at91sam9263.h>
#elif defined(CONFIG_AT91SAM9RL)
#include <asm/arch/at91sam9rl.h>
#elif defined(CONFIG_AT91CAP9)
#include <asm/arch/at91cap9.h>
#define AT91_BASE_EMAC AT91CAP9_BASE_EMAC
#define AT91_BASE_SPI AT91CAP9_BASE_SPI0
#define AT91_ID_UHP AT91CAP9_ID_UHP
#define AT91_PMC_UHP AT91CAP9_PMC_UHP
#elif defined(CONFIG_AT91X40)
#include <asm/arch/at91x40.h>
#else
#error "Unsupported AT91 processor"
#endif
/*
* container_of - cast a member of a structure out to the containing structure
*
* @ptr: the pointer to the member.
* @type: the type of the container struct this is embedded in.
* @member: the name of the member within the struct.
*/
#define container_of(ptr, type, member) ({ \
const typeof(((type *)0)->member) *__mptr = (ptr); \
(type *)((char *)__mptr - offsetof(type, member)); })
#endif

40
include/asm-arm/arch-at91sam9/io.h Normal file
View File

@ -0,0 +1,40 @@
/*
* include/asm-arm/arch-at91/io.h
*
* Copyright (C) 2003 SAN People
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_IO_H
#define __ASM_ARCH_IO_H
#include <asm/io.h>
static inline unsigned int at91_sys_read(unsigned int reg_offset)
{
void *addr = (void *)AT91_BASE_SYS;
return __raw_readl(addr + reg_offset);
}
static inline void at91_sys_write(unsigned int reg_offset, unsigned long value)
{
void *addr = (void *)AT91_BASE_SYS;
__raw_writel(value, addr + reg_offset);
}
#endif

10
include/asm-arm/arch-at91cap9/memory-map.h → include/asm-arm/arch-at91sam9/memory-map.h
View File

@ -24,11 +24,11 @@
#ifndef __ASM_ARM_ARCH_MEMORYMAP_H__
#define __ASM_ARM_ARCH_MEMORYMAP_H__
#include <asm/arch/AT91CAP9.h>
#include <asm/arch/hardware.h>
#define USART0_BASE AT91C_BASE_US0
#define USART1_BASE AT91C_BASE_US1
#define USART2_BASE AT91C_BASE_US2
#define USART3_BASE AT91C_BASE_DBGU
#define USART0_BASE AT91_USART0
#define USART1_BASE AT91_USART1
#define USART2_BASE AT91_USART2
#define USART3_BASE (AT91_BASE_SYS + AT91_DBGU)
#endif /* __ASM_ARM_ARCH_MEMORYMAP_H__ */

61
include/configs/at91cap9adk.h
View File

@ -1,5 +1,5 @@
/*
* (C) Copyright 2007
* (C) Copyright 2007-2008
* Stelian Pop <stelian.pop <at> leadtechdesign.com>
* Lead Tech Design <www.leadtechdesign.com>
*
@ -28,8 +28,8 @@
#define __CONFIG_H
/* ARM asynchronous clock */
#define AT91C_MAIN_CLOCK 200000000 /* from 12 MHz crystal */
#define AT91C_MASTER_CLOCK 100000000 /* peripheral = main / 2 */
#define AT91_MAIN_CLOCK 200000000 /* from 12 MHz crystal */
#define AT91_MASTER_CLOCK 100000000 /* peripheral = main / 2 */
#define CFG_HZ 1000000 /* 1us resolution */
#define AT91_SLOW_CLOCK 32768 /* slow clock */
@ -46,19 +46,9 @@
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SKIP_RELOCATE_UBOOT
#define ROUND(A, B) (((A) + (B)) & ~((B) - 1))
/*
* Size of malloc() pool
*/
#define CFG_MALLOC_LEN ROUND(CFG_ENV_SIZE + 128*1024, 0x1000)
#define CFG_GBL_DATA_SIZE 128 /* 128 bytes for initial data */
#define CONFIG_BAUDRATE 115200
/*
* Hardware drivers
*/
#define CONFIG_ATMEL_USART 1
#undef CONFIG_USART0
#undef CONFIG_USART1
@ -104,7 +94,9 @@
#define CFG_SPI_WRITE_TOUT (5*CFG_HZ)
#define CFG_MAX_DATAFLASH_BANKS 1
#define CFG_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */
#define CONFIG_NEW_PARTITION 1
#define AT91_SPI_CLK 20000000
#define DATAFLASH_TCSS (0xFA << 16)
#define DATAFLASH_TCHS (0x8 << 24)
/* NOR flash */
#define CFG_FLASH_CFI 1
@ -114,39 +106,11 @@
#define CFG_MAX_FLASH_SECT 256
#define CFG_MAX_FLASH_BANKS 1
#define AT91C_FLASH_NWE_SETUP (4 << 0)
#define AT91C_FLASH_NCS_WR_SETUP (2 << 8)
#define AT91C_FLASH_NRD_SETUP (4 << 16)
#define AT91C_FLASH_NCS_RD_SETUP (2 << 24)
#define AT91C_FLASH_NWE_PULSE (8 << 0)
#define AT91C_FLASH_NCS_WR_PULSE (10 << 8)
#define AT91C_FLASH_NRD_PULSE (8 << 16)
#define AT91C_FLASH_NCS_RD_PULSE (10 << 24)
#define AT91C_FLASH_NWE_CYCLE (16 << 0)
#define AT91C_FLASH_NRD_CYCLE (16 << 16)
/* NAND flash */
#define NAND_MAX_CHIPS 1
#define CFG_MAX_NAND_DEVICE 1
#define CFG_NAND_BASE 0x40000000
#define AT91C_SM_NWE_SETUP (2 << 0)
#define AT91C_SM_NCS_WR_SETUP (1 << 8)
#define AT91C_SM_NRD_SETUP (2 << 16)
#define AT91C_SM_NCS_RD_SETUP (1 << 24)
#define AT91C_SM_NWE_PULSE (4 << 0)
#define AT91C_SM_NCS_WR_PULSE (6 << 8)
#define AT91C_SM_NRD_PULSE (4 << 16)
#define AT91C_SM_NCS_RD_PULSE (6 << 24)
#define AT91C_SM_NWE_CYCLE (8 << 0)
#define AT91C_SM_NRD_CYCLE (8 << 16)
#define AT91C_SM_TDF (1 << 16)
/* Ethernet */
#define CONFIG_MACB 1
#define CONFIG_RMII 1
@ -159,15 +123,14 @@
#define LITTLEENDIAN 1
#define CONFIG_DOS_PARTITION 1
#define CFG_USB_OHCI_CPU_INIT 1
#define CFG_USB_OHCI_REGS_BASE 0x00700000 /* AT91C_BASE_UHP */
#define CFG_USB_OHCI_REGS_BASE 0x00700000 /* AT91_BASE_UHP */
#define CFG_USB_OHCI_SLOT_NAME "at91cap9"
#define CFG_USB_OHCI_MAX_ROOT_PORTS 2
#define CFG_LOAD_ADDR 0x72000000 /* load address */
#define CFG_MEMTEST_START PHYS_SDRAM
#define CFG_MEMTEST_END 0x73000000
#define CFG_MEMTEST_END 0x73e00000
#define CFG_USE_DATAFLASH 1
#undef CFG_USE_NORFLASH
@ -194,6 +157,7 @@
#endif
#define CONFIG_BAUDRATE 115200
#define CFG_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
#define CFG_PROMPT "U-Boot> "
@ -203,6 +167,13 @@
#define CFG_LONGHELP 1
#define CONFIG_CMDLINE_EDITING 1
#define ROUND(A, B) (((A) + (B)) & ~((B) - 1))
/*
* Size of malloc() pool
*/
#define CFG_MALLOC_LEN ROUND(CFG_ENV_SIZE + 128*1024, 0x1000)
#define CFG_GBL_DATA_SIZE 128 /* 128 bytes for initial data */
#define CONFIG_STACKSIZE (32*1024) /* regular stack */
#ifdef CONFIG_USE_IRQ

2
include/configs/at91rm9200dk.h
View File

@ -51,7 +51,7 @@
#define MC_ASR_VAL 0x00000000
#define MC_AASR_VAL 0x00000000
#define EBI_CFGR_VAL 0x00000000
#define SMC2_CSR_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
#define SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
/* clocks */
#define PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */

191
include/configs/at91sam9260ek.h Normal file
View File

@ -0,0 +1,191 @@
/*
* (C) Copyright 2007-2008
* Stelian Pop <stelian.pop <at> leadtechdesign.com>
* Lead Tech Design <www.leadtechdesign.com>
*
* Configuation settings for the AT91SAM9260EK board.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/* ARM asynchronous clock */
#define AT91_MAIN_CLOCK 198656000 /* from 18.432 MHz crystal */
#define AT91_MASTER_CLOCK 99328000 /* peripheral = main / 2 */
#define CFG_HZ 1000000 /* 1us resolution */
#define AT91_SLOW_CLOCK 32768 /* slow clock */
#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
#define CONFIG_AT91SAM9260 1 /* It's an Atmel AT91SAM9260 SoC*/
#define CONFIG_AT91SAM9260EK 1 /* on an AT91SAM9260EK Board */
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG 1
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SKIP_RELOCATE_UBOOT
/*
* Hardware drivers
*/
#define CONFIG_ATMEL_USART 1
#undef CONFIG_USART0
#undef CONFIG_USART1
#undef CONFIG_USART2
#define CONFIG_USART3 1 /* USART 3 is DBGU */
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
"root=/dev/mtdblock0 rw rootfstype=jffs2"
/* #define CONFIG_ENV_OVERWRITE 1 */
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE 1
#define CONFIG_BOOTP_BOOTPATH 1
#define CONFIG_BOOTP_GATEWAY 1
#define CONFIG_BOOTP_HOSTNAME 1
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#undef CONFIG_CMD_BDI
#undef CONFIG_CMD_IMI
#undef CONFIG_CMD_AUTOSCRIPT
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_LOADS
#undef CONFIG_CMD_IMLS
#define CONFIG_CMD_PING 1
#define CONFIG_CMD_DHCP 1
#define CONFIG_CMD_NAND 1
#define CONFIG_CMD_USB 1
/* SDRAM */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM 0x20000000
#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */
/* DataFlash */
#define CONFIG_HAS_DATAFLASH 1
#define CFG_SPI_WRITE_TOUT (5*CFG_HZ)
#define CFG_MAX_DATAFLASH_BANKS 2
#define CFG_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */
#define CFG_DATAFLASH_LOGIC_ADDR_CS1 0xD0000000 /* CS1 */
#define AT91_SPI_CLK 33000000
#define DATAFLASH_TCSS (0x1a << 16)
#define DATAFLASH_TCHS (0x1 << 24)
/* NAND flash */
#define NAND_MAX_CHIPS 1
#define CFG_MAX_NAND_DEVICE 1
#define CFG_NAND_BASE 0x40000000
/* NOR flash - no real flash on this board */
#define CFG_NO_FLASH 1
/* Ethernet */
#define CONFIG_MACB 1
#define CONFIG_RMII 1
#define CONFIG_NET_MULTI 1
#define CONFIG_NET_RETRY_COUNT 20
#define CONFIG_RESET_PHY_R 1
/* USB */
#define CONFIG_USB_OHCI_NEW 1
#define LITTLEENDIAN 1
#define CONFIG_DOS_PARTITION 1
#define CFG_USB_OHCI_CPU_INIT 1
#define CFG_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9260_UHP_BASE */
#define CFG_USB_OHCI_SLOT_NAME "at91sam9260"
#define CFG_USB_OHCI_MAX_ROOT_PORTS 2
#define CONFIG_USB_STORAGE 1
#define CFG_LOAD_ADDR 0x22000000 /* load address */
#define CFG_MEMTEST_START PHYS_SDRAM
#define CFG_MEMTEST_END 0x23e00000
#undef CFG_USE_DATAFLASH_CS0
#define CFG_USE_DATAFLASH_CS1 1
#undef CFG_USE_NANDFLASH
#ifdef CFG_USE_DATAFLASH_CS0
/* bootstrap + u-boot + env + linux in dataflash on CS0 */
#define CFG_ENV_IS_IN_DATAFLASH 1
#define CFG_MONITOR_BASE (CFG_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
#define CFG_ENV_OFFSET 0x4200
#define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET)
#define CFG_ENV_SIZE 0x4200
#define CONFIG_BOOTCOMMAND "cp.b 0xC003DE00 0x22000000 0x200040; bootm"
#elif CFG_USE_DATAFLASH_CS1
/* bootstrap + u-boot + env + linux in dataflash on CS1 */
#define CFG_ENV_IS_IN_DATAFLASH 1
#define CFG_MONITOR_BASE (CFG_DATAFLASH_LOGIC_ADDR_CS1 + 0x8400)
#define CFG_ENV_OFFSET 0x4200
#define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS1 + CFG_ENV_OFFSET)
#define CFG_ENV_SIZE 0x4200
#define CONFIG_BOOTCOMMAND "cp.b 0xD003DE00 0x22000000 0x200040; bootm"
#else /* CFG_USE_NANDFLASH */
/* bootstrap + u-boot + env + linux in nandflash */
#define CFG_ENV_IS_IN_NAND 1
#define CFG_ENV_OFFSET 0x60000
#define CFG_ENV_OFFSET_REDUND 0x80000
#define CFG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm"
#endif
#define CONFIG_BAUDRATE 115200
#define CFG_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
#define CFG_PROMPT "U-Boot> "
#define CFG_CBSIZE 256
#define CFG_MAXARGS 16
#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
#define CFG_LONGHELP 1
#define CONFIG_CMDLINE_EDITING 1
#define ROUND(A, B) (((A) + (B)) & ~((B) - 1))
/*
* Size of malloc() pool
*/
#define CFG_MALLOC_LEN ROUND(3 * CFG_ENV_SIZE + 128*1024, 0x1000)
#define CFG_GBL_DATA_SIZE 128 /* 128 bytes for initial data */
#define CONFIG_STACKSIZE (32*1024) /* regular stack */
#ifdef CONFIG_USE_IRQ
#error CONFIG_USE_IRQ not supported
#endif
#endif

2
include/configs/cmc_pu2.h
View File

@ -50,7 +50,7 @@
#define MC_ASR_VAL 0x00000000
#define MC_AASR_VAL 0x00000000
#define EBI_CFGR_VAL 0x00000000
#define SMC2_CSR_VAL 0x100032ad /* 16bit, 2 TDF, 4 WS */
#define SMC_CSR0_VAL 0x100032ad /* 16bit, 2 TDF, 4 WS */
/* clocks */
#define PLLAR_VAL 0x2026BE04 /* 179,712 MHz for PCK */

2
include/configs/csb637.h
View File

@ -51,7 +51,7 @@
#define MC_ASR_VAL 0x00000000
#define MC_AASR_VAL 0x00000000
#define EBI_CFGR_VAL 0x00000000
#define SMC2_CSR_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
#define SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
/* clocks */
#define PLLAR_VAL 0x2031BE01 /* 184.320000 MHz for PCK */

2
include/configs/mp2usb.h
View File

@ -55,7 +55,7 @@
#define MC_ASR_VAL 0x00000000
#define MC_AASR_VAL 0x00000000
#define EBI_CFGR_VAL 0x00000000
#define SMC2_CSR_VAL 0x00003084 /* 16bit, 2 TDF, 4 WS */
#define SMC_CSR0_VAL 0x00003084 /* 16bit, 2 TDF, 4 WS */
/* clocks */
#define PLLAR_VAL 0x20263E04 /* 180 MHz for PCK */

6
include/dataflash.h
View File

@ -38,11 +38,7 @@
#include "config.h"
/*number of protected area*/
#ifdef CONFIG_NEW_PARTITION
# define NB_DATAFLASH_AREA 6
#else
# define NB_DATAFLASH_AREA 4
#endif
#define NB_DATAFLASH_AREA 5
#ifdef CFG_NO_FLASH

6
net/eth.c
View File

@ -64,7 +64,7 @@ extern int greth_initialize(bd_t *);
extern int atngw100_eth_initialize(bd_t *);
extern int mcffec_initialize(bd_t*);
extern int mcdmafec_initialize(bd_t*);
extern int at91cap9_eth_initialize(bd_t *);
extern int at91sam9_eth_initialize(bd_t *);
#ifdef CONFIG_API
extern void (*push_packet)(volatile void *, int);
@ -288,8 +288,8 @@ int eth_initialize(bd_t *bis)
#if defined(CONFIG_FSLDMAFEC)
mcdmafec_initialize(bis);
#endif
#if defined(CONFIG_AT91CAP9)
at91cap9_eth_initialize(bis);
#if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260)
at91sam9_eth_initialize(bis);
#endif
if (!eth_devices) {