Extend POST support for PPC440
Added memory, CPU, UART, I2C and SPR POST tests for PPC440. Signed-off-by: Igor Lisitsin <igor@emcraft.com> --
This commit is contained in:
Igor Lisitsin
Wolfgang Denk
parent
02032e8f14
commit
a11e06965e
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@ -586,3 +586,13 @@ int is_pci_host(struct pci_controller *hose)
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return (1);
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}
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#endif /* defined(CONFIG_PCI) */
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#if defined(CONFIG_POST)
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/*
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* Returns 1 if keys pressed to start the power-on long-running tests
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* Called from board_init_f().
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*/
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int post_hotkeys_pressed(void)
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{
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return 0; /* No hotkeys supported */
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}
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#endif /* CONFIG_POST */
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@ -211,6 +211,8 @@ cpu_init_f (void)
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val = mfspr(tcr);
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#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
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val |= 0xb8000000; /* generate system reset after 1.34 seconds */
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#elif defined(CONFIG_440EPX)
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val |= 0xb0000000; /* generate system reset after 1.34 seconds */
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#else
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val |= 0xf0000000; /* generate system reset after 2.684 seconds */
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#endif
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@ -59,6 +59,7 @@
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#define CFG_MONITOR_BASE TEXT_BASE
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#define CFG_NAND_ADDR 0xd0000000 /* NAND Flash */
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#define CFG_OCM_BASE 0xe0010000 /* ocm */
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#define CFG_OCM_DATA_ADDR CFG_OCM_BASE
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#define CFG_PCI_BASE 0xe0000000 /* Internal PCI regs */
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#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
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#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
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@ -81,7 +82,7 @@
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#define CFG_INIT_RAM_END (4 << 10)
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#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR
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/*-----------------------------------------------------------------------
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* Serial Port
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@ -328,6 +329,18 @@
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CFG_CMD_SDRAM | \
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CMD_USB)
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/* POST support */
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#define CONFIG_POST (CFG_POST_MEMORY | \
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CFG_POST_CPU | \
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CFG_POST_UART | \
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CFG_POST_I2C | \
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CFG_POST_SPR)
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#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
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#define CONFIG_LOGBUFFER
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#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
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#define CONFIG_SUPPORT_VFAT
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
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@ -91,6 +91,7 @@ extern int post_hotkeys_pressed(void);
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#define CFG_POST_SYSMON 0x00000800
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#define CFG_POST_DSP 0x00001000
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#define CFG_POST_CODEC 0x00002000
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#define CFG_POST_FPU 0x00004000
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#endif /* CONFIG_POST */
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@ -282,6 +282,32 @@
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#define sdr_sdstp3 0x4003
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#endif /* CONFIG_440GX */
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#ifdef CONFIG_440
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/*----------------------------------------------------------------------------+
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| Core Configuration/MMU configuration for 440 (CCR1 for 440x5 only).
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+----------------------------------------------------------------------------*/
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#define CCR0_PRE 0x40000000
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#define CCR0_CRPE 0x08000000
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#define CCR0_DSTG 0x00200000
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#define CCR0_DAPUIB 0x00100000
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#define CCR0_DTB 0x00008000
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#define CCR0_GICBT 0x00004000
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#define CCR0_GDCBT 0x00002000
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#define CCR0_FLSTA 0x00000100
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#define CCR0_ICSLC_MASK 0x0000000C
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#define CCR0_ICSLT_MASK 0x00000003
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#define CCR1_TCS_MASK 0x00000080
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#define CCR1_TCS_INTCLK 0x00000000
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#define CCR1_TCS_EXTCLK 0x00000080
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#define MMUCR_SWOA 0x01000000
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#define MMUCR_U1TE 0x00400000
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#define MMUCR_U2SWOAE 0x00200000
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#define MMUCR_DULXE 0x00800000
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#define MMUCR_IULXE 0x00400000
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#define MMUCR_STS 0x00100000
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#define MMUCR_STID_MASK 0x000000FF
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#endif /* CONFIG_440 */
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#ifdef CONFIG_440SPE
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#undef sdr_sdstp2
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#define sdr_sdstp2 0x0022
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@ -307,30 +333,6 @@
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#define sdr_sdstp6 0x4005
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#define sdr_sdstp7 0x4007
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/*----------------------------------------------------------------------------+
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| Core Configuration/MMU configuration for 440 (CCR1 for 440x5 only).
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+----------------------------------------------------------------------------*/
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#define CCR0_PRE 0x40000000
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#define CCR0_CRPE 0x08000000
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#define CCR0_DSTG 0x00200000
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#define CCR0_DAPUIB 0x00100000
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#define CCR0_DTB 0x00008000
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#define CCR0_GICBT 0x00004000
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#define CCR0_GDCBT 0x00002000
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#define CCR0_FLSTA 0x00000100
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#define CCR0_ICSLC_MASK 0x0000000C
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#define CCR0_ICSLT_MASK 0x00000003
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#define CCR1_TCS_MASK 0x00000080
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#define CCR1_TCS_INTCLK 0x00000000
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#define CCR1_TCS_EXTCLK 0x00000080
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#define MMUCR_SEOA 0x01000000
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#define MMUCR_U1TE 0x00400000
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#define MMUCR_U2SWOAE 0x00200000
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#define MMUCR_DULXE 0x00800000
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#define MMUCR_IULXE 0x00400000
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#define MMUCR_STS 0x00100000
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#define MMUCR_STID_MASK 0x000000FF
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#define SDR0_CFGADDR 0x00E
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#define SDR0_CFGDATA 0x00F
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@ -0,0 +1,28 @@
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#
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# (C) Copyright 2002-2007
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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LIB = libpostppc4xx.a
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COBJS = fpu.o spr.o uart.o watchdog.o
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include $(TOPDIR)/post/rules.mk
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@ -0,0 +1,55 @@
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/*
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* Copyright (C) 2007 Wolfgang Denk <wd@denx.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#ifdef CONFIG_POST
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#if defined(CONFIG_440EP) || \
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defined(CONFIG_440EPX)
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#include <ppc4xx.h>
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#include <asm/processor.h>
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int fpu_status(void)
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{
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if (mfspr(ccr0) & CCR0_DAPUIB)
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return 0; /* Disabled */
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else
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return 1; /* Enabled */
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}
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void fpu_disable(void)
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{
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mtspr(ccr0, mfspr(ccr0) | CCR0_DAPUIB);
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mtmsr(mfmsr() & ~MSR_FP);
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}
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void fpu_enable(void)
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{
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mtspr(ccr0, mfspr(ccr0) & ~CCR0_DAPUIB);
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mtmsr(mfmsr() | MSR_FP);
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}
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#endif
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#endif
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@ -0,0 +1,176 @@
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/*
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* (C) Copyright 2007
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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/*
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* SPR test
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*
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* The test checks the contents of Special Purpose Registers (SPR) listed
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* in the spr_test_list array below.
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* Each SPR value is read using mfspr instruction, some bits are masked
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* according to the table and the resulting value is compared to the
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* corresponding table value.
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*/
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#ifdef CONFIG_POST
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#include <post.h>
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#if CONFIG_POST & CFG_POST_SPR
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static struct
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{
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int number;
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char * name;
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unsigned long mask;
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unsigned long value;
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} spr_test_list [] = {
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/* Standard Special-Purpose Registers */
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{0x001, "XER", 0x00000000, 0x00000000},
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{0x008, "LR", 0x00000000, 0x00000000},
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{0x009, "CTR", 0x00000000, 0x00000000},
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{0x016, "DEC", 0x00000000, 0x00000000},
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{0x01a, "SRR0", 0x00000000, 0x00000000},
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{0x01b, "SRR1", 0x00000000, 0x00000000},
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{0x110, "SPRG0", 0x00000000, 0x00000000},
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{0x111, "SPRG1", 0x00000000, 0x00000000},
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{0x112, "SPRG2", 0x00000000, 0x00000000},
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{0x113, "SPRG3", 0x00000000, 0x00000000},
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{0x11f, "PVR", 0x00000000, 0x00000000},
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/* Additional Special-Purpose Registers */
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{0x30, "PID", 0x00000000, 0x00000000},
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{0x3a, "CSRR0", 0x00000000, 0x00000000},
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{0x3b, "CSRR1", 0x00000000, 0x00000000},
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{0x3d, "DEAR", 0x00000000, 0x00000000},
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{0x3e, "ESR", 0x00000000, 0x00000000},
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{0x3f, "IVPR", 0xffff0000, 0x00000000},
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{0x100, "USPRG0", 0x00000000, 0x00000000},
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{0x104, "SPRG4", 0x00000000, 0x00000000},
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{0x105, "SPRG5", 0x00000000, 0x00000000},
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{0x106, "SPRG6", 0x00000000, 0x00000000},
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{0x107, "SPRG7", 0x00000000, 0x00000000},
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{0x10c, "TBL", 0x00000000, 0x00000000},
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{0x10d, "TBU", 0x00000000, 0x00000000},
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{0x11e, "PIR", 0x0000000f, 0x00000000},
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{0x130, "DBSR", 0x00000000, 0x00000000},
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{0x134, "DBCR0", 0x00000000, 0x00000000},
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{0x135, "DBCR1", 0x00000000, 0x00000000},
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{0x136, "DBCR2", 0x00000000, 0x00000000},
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{0x138, "IAC1", 0x00000000, 0x00000000},
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{0x139, "IAC2", 0x00000000, 0x00000000},
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{0x13a, "IAC3", 0x00000000, 0x00000000},
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{0x13b, "IAC4", 0x00000000, 0x00000000},
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{0x13c, "DAC1", 0x00000000, 0x00000000},
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{0x13d, "DAC2", 0x00000000, 0x00000000},
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{0x13e, "DVC1", 0x00000000, 0x00000000},
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{0x13f, "DVC2", 0x00000000, 0x00000000},
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{0x150, "TSR", 0x00000000, 0x00000000},
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{0x154, "TCR", 0x00000000, 0x00000000},
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{0x190, "IVOR0", 0x00000000, 0x00000000},
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{0x191, "IVOR1", 0x00000000, 0x00000000},
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{0x192, "IVOR2", 0x00000000, 0x00000000},
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{0x193, "IVOR3", 0x00000000, 0x00000000},
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{0x194, "IVOR4", 0x00000000, 0x00000000},
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{0x195, "IVOR5", 0x00000000, 0x00000000},
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{0x196, "IVOR6", 0x00000000, 0x00000000},
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{0x197, "IVOR7", 0x00000000, 0x00000000},
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{0x198, "IVOR8", 0x00000000, 0x00000000},
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{0x199, "IVOR9", 0x00000000, 0x00000000},
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{0x19a, "IVOR10", 0x00000000, 0x00000000},
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{0x19b, "IVOR11", 0x00000000, 0x00000000},
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{0x19c, "IVOR12", 0x00000000, 0x00000000},
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{0x19d, "IVOR13", 0x00000000, 0x00000000},
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{0x19e, "IVOR14", 0x00000000, 0x00000000},
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{0x19f, "IVOR15", 0x00000000, 0x00000000},
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{0x23a, "MCSRR0", 0x00000000, 0x00000000},
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{0x23b, "MCSRR1", 0x00000000, 0x00000000},
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{0x23c, "MCSR", 0x00000000, 0x00000000},
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{0x370, "INV0", 0x00000000, 0x00000000},
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{0x371, "INV1", 0x00000000, 0x00000000},
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{0x372, "INV2", 0x00000000, 0x00000000},
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{0x373, "INV3", 0x00000000, 0x00000000},
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{0x374, "ITV0", 0x00000000, 0x00000000},
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{0x375, "ITV1", 0x00000000, 0x00000000},
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{0x376, "ITV2", 0x00000000, 0x00000000},
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{0x377, "ITV3", 0x00000000, 0x00000000},
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{0x378, "CCR1", 0x00000000, 0x00000000},
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{0x390, "DNV0", 0x00000000, 0x00000000},
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{0x391, "DNV1", 0x00000000, 0x00000000},
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{0x392, "DNV2", 0x00000000, 0x00000000},
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{0x393, "DNV3", 0x00000000, 0x00000000},
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{0x394, "DTV0", 0x00000000, 0x00000000},
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{0x395, "DTV1", 0x00000000, 0x00000000},
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{0x396, "DTV2", 0x00000000, 0x00000000},
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{0x397, "DTV3", 0x00000000, 0x00000000},
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{0x398, "DVLIM", 0x00000000, 0x00000000},
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{0x399, "IVLIM", 0x00000000, 0x00000000},
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{0x39b, "RSTCFG", 0x00000000, 0x00000000},
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{0x39c, "DCDBTRL", 0x00000000, 0x00000000},
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{0x39d, "DCDBTRH", 0x00000000, 0x00000000},
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{0x39e, "ICDBTRL", 0x00000000, 0x00000000},
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{0x39f, "ICDBTRH", 0x00000000, 0x00000000},
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{0x3b2, "MMUCR", 0x00000000, 0x00000000},
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{0x3b3, "CCR0", 0x00000000, 0x00000000},
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{0x3d3, "ICDBDR", 0x00000000, 0x00000000},
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{0x3f3, "DBDR", 0x00000000, 0x00000000},
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};
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static int spr_test_list_size =
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sizeof (spr_test_list) / sizeof (spr_test_list[0]);
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int spr_post_test (int flags)
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{
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int ret = 0;
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int i;
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unsigned long code[] = {
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0x7c6002a6, /* mfspr r3,SPR */
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0x4e800020 /* blr */
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};
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unsigned long (*get_spr) (void) = (void *) code;
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for (i = 0; i < spr_test_list_size; i++) {
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int num = spr_test_list[i].number;
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/* mfspr r3,num */
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code[0] = 0x7c6002a6 | ((num & 0x1F) << 16) | ((num & 0x3E0) << 6);
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asm volatile ("isync");
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if ((get_spr () & spr_test_list[i].mask) !=
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(spr_test_list[i].value & spr_test_list[i].mask)) {
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post_log ("The value of %s special register "
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"is incorrect: 0x%08X\n",
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spr_test_list[i].name, get_spr ());
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ret = -1;
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}
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}
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return ret;
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}
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#endif /* CONFIG_POST & CFG_POST_SPR */
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#endif /* CONFIG_POST */
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@ -0,0 +1,214 @@
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/*
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* (C) Copyright 2007
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
|
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* project.
|
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*
|
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* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
|
||||
/*
|
||||
* UART test
|
||||
*
|
||||
* The controllers are configured to loopback mode and several
|
||||
* characters are transmitted.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_POST
|
||||
|
||||
#include <post.h>
|
||||
|
||||
#if CONFIG_POST & CFG_POST_UART
|
||||
|
||||
#include <asm/processor.h>
|
||||
#include <serial.h>
|
||||
|
||||
#define UART0_BASE CFG_PERIPHERAL_BASE + 0x00000300
|
||||
#define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000400
|
||||
#define UART2_BASE CFG_PERIPHERAL_BASE + 0x00000500
|
||||
#define UART3_BASE CFG_PERIPHERAL_BASE + 0x00000600
|
||||
|
||||
#define CR0_MASK 0xdfffffff
|
||||
#define CR0_EXTCLK_ENA 0x00800000
|
||||
#define CR0_UDIV_POS 0
|
||||
#define UDIV_SUBTRACT 0
|
||||
#define UART0_SDR sdr_uart0
|
||||
#define UART1_SDR sdr_uart1
|
||||
#define UART2_SDR sdr_uart2
|
||||
#define UART3_SDR sdr_uart3
|
||||
#define MFREG(a, d) mfsdr(a, d)
|
||||
#define MTREG(a, d) mtsdr(a, d)
|
||||
|
||||
#define UART_RBR 0x00
|
||||
#define UART_THR 0x00
|
||||
#define UART_IER 0x01
|
||||
#define UART_IIR 0x02
|
||||
#define UART_FCR 0x02
|
||||
#define UART_LCR 0x03
|
||||
#define UART_MCR 0x04
|
||||
#define UART_LSR 0x05
|
||||
#define UART_MSR 0x06
|
||||
#define UART_SCR 0x07
|
||||
#define UART_DLL 0x00
|
||||
#define UART_DLM 0x01
|
||||
|
||||
/*
|
||||
Line Status Register.
|
||||
*/
|
||||
#define asyncLSRDataReady1 0x01
|
||||
#define asyncLSROverrunError1 0x02
|
||||
#define asyncLSRParityError1 0x04
|
||||
#define asyncLSRFramingError1 0x08
|
||||
#define asyncLSRBreakInterrupt1 0x10
|
||||
#define asyncLSRTxHoldEmpty1 0x20
|
||||
#define asyncLSRTxShiftEmpty1 0x40
|
||||
#define asyncLSRRxFifoError1 0x80
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
static int uart_post_init (unsigned long dev_base)
|
||||
{
|
||||
unsigned long reg;
|
||||
unsigned long udiv;
|
||||
unsigned short bdiv;
|
||||
volatile char val;
|
||||
#ifdef CFG_EXT_SERIAL_CLOCK
|
||||
unsigned long tmp;
|
||||
#endif
|
||||
int i;
|
||||
|
||||
for (i = 0; i < 3500; i++) {
|
||||
if (in8 (dev_base + UART_LSR) & asyncLSRTxHoldEmpty1)
|
||||
break;
|
||||
udelay (100);
|
||||
}
|
||||
MFREG(UART0_SDR, reg);
|
||||
reg &= ~CR0_MASK;
|
||||
|
||||
#ifdef CFG_EXT_SERIAL_CLOCK
|
||||
reg |= CR0_EXTCLK_ENA;
|
||||
udiv = 1;
|
||||
tmp = gd->baudrate * 16;
|
||||
bdiv = (CFG_EXT_SERIAL_CLOCK + tmp / 2) / tmp;
|
||||
#else
|
||||
/* For 440, the cpu clock is on divider chain A, UART on divider
|
||||
* chain B ... so cpu clock is irrelevant. Get the "optimized"
|
||||
* values that are subject to the 1/2 opb clock constraint
|
||||
*/
|
||||
serial_divs (gd->baudrate, &udiv, &bdiv);
|
||||
#endif
|
||||
|
||||
reg |= (udiv - UDIV_SUBTRACT) << CR0_UDIV_POS; /* set the UART divisor */
|
||||
|
||||
/*
|
||||
* Configure input clock to baudrate generator for all
|
||||
* available serial ports here
|
||||
*/
|
||||
MTREG(UART0_SDR, reg);
|
||||
#if defined(UART1_SDR)
|
||||
MTREG(UART1_SDR, reg);
|
||||
#endif
|
||||
#if defined(UART2_SDR)
|
||||
MTREG(UART2_SDR, reg);
|
||||
#endif
|
||||
#if defined(UART3_SDR)
|
||||
MTREG(UART3_SDR, reg);
|
||||
#endif
|
||||
|
||||
out8(dev_base + UART_LCR, 0x80); /* set DLAB bit */
|
||||
out8(dev_base + UART_DLL, bdiv); /* set baudrate divisor */
|
||||
out8(dev_base + UART_DLM, bdiv >> 8); /* set baudrate divisor */
|
||||
out8(dev_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
|
||||
out8(dev_base + UART_FCR, 0x00); /* disable FIFO */
|
||||
out8(dev_base + UART_MCR, 0x10); /* enable loopback mode */
|
||||
val = in8(dev_base + UART_LSR); /* clear line status */
|
||||
val = in8(dev_base + UART_RBR); /* read receive buffer */
|
||||
out8(dev_base + UART_SCR, 0x00); /* set scratchpad */
|
||||
out8(dev_base + UART_IER, 0x00); /* set interrupt enable reg */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void uart_post_putc (unsigned long dev_base, char c)
|
||||
{
|
||||
int i;
|
||||
|
||||
out8 (dev_base + UART_THR, c); /* put character out */
|
||||
|
||||
/* Wait for transfer completion */
|
||||
for (i = 0; i < 3500; i++) {
|
||||
if (in8 (dev_base + UART_LSR) & asyncLSRTxHoldEmpty1)
|
||||
break;
|
||||
udelay (100);
|
||||
}
|
||||
}
|
||||
|
||||
static int uart_post_getc (unsigned long dev_base)
|
||||
{
|
||||
int i;
|
||||
|
||||
/* Wait for character available */
|
||||
for (i = 0; i < 3500; i++) {
|
||||
if (in8 (dev_base + UART_LSR) & asyncLSRDataReady1)
|
||||
break;
|
||||
udelay (100);
|
||||
}
|
||||
return 0xff & in8 (dev_base + UART_RBR);
|
||||
}
|
||||
|
||||
static int test_ctlr (unsigned long dev_base, int index)
|
||||
{
|
||||
int res = -1;
|
||||
char test_str[] = "*** UART Test String ***\r\n";
|
||||
int i;
|
||||
|
||||
uart_post_init (dev_base);
|
||||
|
||||
for (i = 0; i < sizeof (test_str) - 1; i++) {
|
||||
uart_post_putc (dev_base, test_str[i]);
|
||||
if (uart_post_getc (dev_base) != test_str[i])
|
||||
goto done;
|
||||
}
|
||||
res = 0;
|
||||
done:
|
||||
if (res)
|
||||
post_log ("uart%d test failed\n", index);
|
||||
|
||||
return res;
|
||||
}
|
||||
|
||||
int uart_post_test (int flags)
|
||||
{
|
||||
int i, res = 0;
|
||||
static unsigned long base[] = {
|
||||
UART0_BASE, UART1_BASE, UART2_BASE, UART3_BASE
|
||||
};
|
||||
|
||||
for (i = 0; i < sizeof (base) / sizeof (base[0]); i++) {
|
||||
if (test_ctlr (base[i], i))
|
||||
res = -1;
|
||||
}
|
||||
serial_reinit_all ();
|
||||
|
||||
return res;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_POST & CFG_POST_UART */
|
||||
|
||||
#endif /* CONFIG_POST */
|
||||
|
|
@ -0,0 +1,68 @@
|
|||
/*
|
||||
* (C) Copyright 2007
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
|
||||
/*
|
||||
* Watchdog test
|
||||
*
|
||||
* The test verifies the watchdog timer operation.
|
||||
* On the first iteration, the test routine disables interrupts and
|
||||
* makes a 10-second delay. If the system does not reboot during this delay,
|
||||
* the watchdog timer is not operational and the test fails. If the system
|
||||
* reboots, on the second iteration the test routine reports a success.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_POST
|
||||
|
||||
#include <post.h>
|
||||
#include <watchdog.h>
|
||||
|
||||
#if CONFIG_POST & CFG_POST_WATCHDOG
|
||||
|
||||
int watchdog_post_test (int flags)
|
||||
{
|
||||
if (flags & POST_REBOOT) {
|
||||
/* Test passed */
|
||||
|
||||
return 0;
|
||||
} else {
|
||||
/* 10-second delay */
|
||||
int ints = disable_interrupts ();
|
||||
ulong base = post_time_ms (0);
|
||||
|
||||
while (post_time_ms (base) < 10000)
|
||||
;
|
||||
if (ints)
|
||||
enable_interrupts ();
|
||||
|
||||
/*
|
||||
* If we have reached this point, the watchdog timer
|
||||
* does not work
|
||||
*/
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
#endif /* CONFIG_POST & CFG_POST_WATCHDOG */
|
||||
#endif /* CONFIG_POST */
|
||||
|
|
@ -34,6 +34,7 @@
|
|||
/* void cpu_post_exec_02 (ulong *code, ulong op1, ulong op2); */
|
||||
.global cpu_post_exec_02
|
||||
cpu_post_exec_02:
|
||||
isync
|
||||
mflr r0
|
||||
stwu r0, -4(r1)
|
||||
|
||||
|
|
@ -56,6 +57,7 @@ cpu_post_exec_02:
|
|||
/* void cpu_post_exec_04 (ulong *code, ulong op1, ulong op2, ulong op3, ulong op4); */
|
||||
.global cpu_post_exec_04
|
||||
cpu_post_exec_04:
|
||||
isync
|
||||
mflr r0
|
||||
stwu r0, -4(r1)
|
||||
|
||||
|
|
@ -80,6 +82,7 @@ cpu_post_exec_04:
|
|||
/* void cpu_post_exec_12 (ulong *code, ulong *res, ulong op1, ulong op2); */
|
||||
.global cpu_post_exec_12
|
||||
cpu_post_exec_12:
|
||||
isync
|
||||
mflr r0
|
||||
stwu r0, -4(r1)
|
||||
stwu r4, -4(r1)
|
||||
|
|
@ -100,6 +103,7 @@ cpu_post_exec_12:
|
|||
/* void cpu_post_exec_11 (ulong *code, ulong *res, ulong op1); */
|
||||
.global cpu_post_exec_11
|
||||
cpu_post_exec_11:
|
||||
isync
|
||||
mflr r0
|
||||
stwu r0, -4(r1)
|
||||
stwu r4, -4(r1)
|
||||
|
|
@ -119,6 +123,7 @@ cpu_post_exec_11:
|
|||
/* void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op1); */
|
||||
.global cpu_post_exec_21
|
||||
cpu_post_exec_21:
|
||||
isync
|
||||
mflr r0
|
||||
stwu r0, -4(r1)
|
||||
stwu r4, -4(r1)
|
||||
|
|
@ -148,6 +153,7 @@ cpu_post_exec_21:
|
|||
ulong op2); */
|
||||
.global cpu_post_exec_22
|
||||
cpu_post_exec_22:
|
||||
isync
|
||||
mflr r0
|
||||
stwu r0, -4(r1)
|
||||
stwu r4, -4(r1)
|
||||
|
|
@ -177,6 +183,7 @@ cpu_post_exec_22:
|
|||
/* void cpu_post_exec_12w (ulong *code, ulong *op1, ulong op2, ulong op3); */
|
||||
.global cpu_post_exec_12w
|
||||
cpu_post_exec_12w:
|
||||
isync
|
||||
mflr r0
|
||||
stwu r0, -4(r1)
|
||||
stwu r4, -4(r1)
|
||||
|
|
@ -198,6 +205,7 @@ cpu_post_exec_12w:
|
|||
/* void cpu_post_exec_11w (ulong *code, ulong *op1, ulong op2); */
|
||||
.global cpu_post_exec_11w
|
||||
cpu_post_exec_11w:
|
||||
isync
|
||||
mflr r0
|
||||
stwu r0, -4(r1)
|
||||
stwu r4, -4(r1)
|
||||
|
|
@ -218,6 +226,7 @@ cpu_post_exec_11w:
|
|||
/* void cpu_post_exec_22w (ulong *code, ulong *op1, ulong op2, ulong *op3); */
|
||||
.global cpu_post_exec_22w
|
||||
cpu_post_exec_22w:
|
||||
isync
|
||||
mflr r0
|
||||
stwu r0, -4(r1)
|
||||
stwu r4, -4(r1)
|
||||
|
|
@ -241,6 +250,7 @@ cpu_post_exec_22w:
|
|||
/* void cpu_post_exec_21w (ulong *code, ulong *op1, ulong *op2); */
|
||||
.global cpu_post_exec_21w
|
||||
cpu_post_exec_21w:
|
||||
isync
|
||||
mflr r0
|
||||
stwu r0, -4(r1)
|
||||
stwu r4, -4(r1)
|
||||
|
|
@ -263,6 +273,7 @@ cpu_post_exec_21w:
|
|||
/* void cpu_post_exec_21x (ulong *code, ulong *op1, ulong *op2, ulong op3); */
|
||||
.global cpu_post_exec_21x
|
||||
cpu_post_exec_21x:
|
||||
isync
|
||||
mflr r0
|
||||
stwu r0, -4(r1)
|
||||
stwu r4, -4(r1)
|
||||
|
|
@ -286,6 +297,7 @@ cpu_post_exec_21x:
|
|||
ulong cr); */
|
||||
.global cpu_post_exec_31
|
||||
cpu_post_exec_31:
|
||||
isync
|
||||
mflr r0
|
||||
stwu r0, -4(r1)
|
||||
stwu r4, -4(r1)
|
||||
|
|
|
|||
|
|
@ -49,7 +49,7 @@ extern void cpu_post_exec_31 (ulong *code, ulong *ctr, ulong *lr, ulong *jump,
|
|||
ulong cr);
|
||||
|
||||
static int cpu_post_test_bc (ulong cmd, ulong bo, ulong bi,
|
||||
int pjump, int dec, int link, ulong pctr, ulong cr)
|
||||
int pjump, int decr, int link, ulong pctr, ulong cr)
|
||||
{
|
||||
int ret = 0;
|
||||
ulong lr = 0;
|
||||
|
|
@ -77,7 +77,7 @@ static int cpu_post_test_bc (ulong cmd, ulong bo, ulong bi,
|
|||
ret = pjump == jump ? 0 : -1;
|
||||
if (ret == 0)
|
||||
{
|
||||
if (dec)
|
||||
if (decr)
|
||||
ret = pctr == ctr + 1 ? 0 : -1;
|
||||
else
|
||||
ret = pctr == ctr ? 0 : -1;
|
||||
|
|
@ -163,7 +163,7 @@ int cpu_post_test_b (void)
|
|||
{
|
||||
for (ctr = 1; ctr <= 2 && ret == 0; ctr++)
|
||||
{
|
||||
int dec = cd < 2;
|
||||
int decr = cd < 2;
|
||||
int cr = cond ? 0x80000000 : 0x00000000;
|
||||
int jumpc = cc >= 2 ||
|
||||
(cc == 0 && !cond) ||
|
||||
|
|
@ -174,7 +174,7 @@ int cpu_post_test_b (void)
|
|||
int jump = jumpc && jumpd;
|
||||
|
||||
ret = cpu_post_test_bc (link ? OP_BCL : OP_BC,
|
||||
(cc << 3) + (cd << 1), 0, jump, dec, link,
|
||||
(cc << 3) + (cd << 1), 0, jump, decr, link,
|
||||
ctr, cr);
|
||||
|
||||
if (ret != 0)
|
||||
|
|
|
|||
|
|
@ -428,7 +428,7 @@ void post_reloc (void)
|
|||
unsigned long post_time_ms (unsigned long base)
|
||||
{
|
||||
#ifdef CONFIG_PPC
|
||||
return (unsigned long)get_ticks () / (get_tbclk () / CFG_HZ) - base;
|
||||
return (unsigned long)(get_ticks () / (get_tbclk () / CFG_HZ)) - base;
|
||||
#else
|
||||
#warning "Not implemented yet"
|
||||
return 0; /* Not implemented yet */
|
||||
|
|
|
|||
14
post/tests.c
14
post/tests.c
|
|
@ -37,6 +37,7 @@ extern int i2c_post_test (int flags);
|
|||
extern int rtc_post_test (int flags);
|
||||
extern int memory_post_test (int flags);
|
||||
extern int cpu_post_test (int flags);
|
||||
extern int fpu_post_test (int flags);
|
||||
extern int uart_post_test (int flags);
|
||||
extern int ether_post_test (int flags);
|
||||
extern int spi_post_test (int flags);
|
||||
|
|
@ -126,6 +127,19 @@ struct post_test post_list[] =
|
|||
CFG_POST_CPU
|
||||
},
|
||||
#endif
|
||||
#if CONFIG_POST & CFG_POST_FPU
|
||||
{
|
||||
"FPU test",
|
||||
"fpu",
|
||||
"This test verifies the arithmetic logic unit of"
|
||||
" FPU.",
|
||||
POST_RAM | POST_ALWAYS,
|
||||
&fpu_post_test,
|
||||
NULL,
|
||||
NULL,
|
||||
CFG_POST_FPU
|
||||
},
|
||||
#endif
|
||||
#if CONFIG_POST & CFG_POST_UART
|
||||
{
|
||||
"UART test",
|
||||
|
|
|
|||
Loading…
Reference in New Issue