powerpc/8xxx: Refactor SRIO initialization into common code

Moved the SRIO init out of corenet_ds and into common code for 8xxx/QorIQ processors that have SRIO. We mimic what we do with PCIe controllers for SRIO. We utilize the fact that SRIO is over serdes to determine if its configured or not and thus can setup the LAWs needed for it dynamically. We additionally update the device tree (to remove the SRIO nodes) if the board doesn't have SRIO enabled. Introduced the following standard defines for board config.h: CONFIG_SYS_SRIO - Chip has SRIO or not CONFIG_SRIO1 - Board has SRIO 1 port available CONFIG_SRIO2 - Board has SRIO 2 port available (where 'n' is the port #) CONFIG_SYS_SRIOn_MEM_VIRT - virtual address in u-boot CONFIG_SYS_SRIOn_MEM_PHYS - physical address (for law setup) CONFIG_SYS_SRIOn_MEM_SIZE - size of window (for law setup) [ These mimic what we have for PCI and PCIe controllers ] Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Wolfgang Denk <wd@denx.de>
2010-12-30 12:09:53 -06:00 · 2010-12-30 12:09:53 -06:00 · a09b9b68d4
parent 213ac73e2c
commit a09b9b68d4
9 changed files with 151 additions and 56 deletions
--- a/18
+++ b/18
@ -2783,6 +2783,24 @@ Low Level (hardware related) configuration options:
 		Disable PCI-Express on systems where it is supported but not
 		required.

+- CONFIG_SYS_SRIO:
+		Chip has SRIO or not
+
+- CONFIG_SRIO1:
+		Board has SRIO 1 port available
+
+- CONFIG_SRIO2:
+		Board has SRIO 2 port available
+
+- CONFIG_SYS_SRIOn_MEM_VIRT:
+		Virtual Address of SRIO port 'n' memory region
+
+- CONFIG_SYS_SRIOn_MEM_PHYS:
+		Physical Address of SRIO port 'n' memory region
+
+- CONFIG_SYS_SRIOn_MEM_SIZE:
+		Size of SRIO port 'n' memory region
+
 - CONFIG_SPD_EEPROM
 		Get DDR timing information from an I2C EEPROM. Common
 		with pluggable memory modules such as SODIMMs
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@ -1,5 +1,5 @@
 /*
- * Copyright 2007-2010 Freescale Semiconductor, Inc.
+ * Copyright 2007-2011 Freescale Semiconductor, Inc.
 *
 * (C) Copyright 2003 Motorola Inc.
 * Modified by Xianghua Xiao, X.Xiao@motorola.com
@ -40,6 +40,8 @@

 DECLARE_GLOBAL_DATA_PTR;

+extern void srio_init(void);
+
 #ifdef CONFIG_QE
 extern qe_iop_conf_t qe_iop_conf_tab[];
 extern void qe_config_iopin(u8 port, u8 pin, int dir,
@ -384,6 +386,10 @@ int cpu_init_r(void)
 	/* needs to be in ram since code uses global static vars */
 	fsl_serdes_init();

+#ifdef CONFIG_SYS_SRIO
+	srio_init();
+#endif
+
 #if defined(CONFIG_MP)
 	setup_mp();
 #endif
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@ -1,5 +1,5 @@
 /*
- * Copyright 2007-2010 Freescale Semiconductor, Inc.
+ * Copyright 2007-2011 Freescale Semiconductor, Inc.
 *
 * (C) Copyright 2000
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@ -38,6 +38,7 @@ DECLARE_GLOBAL_DATA_PTR;

 extern void ft_qe_setup(void *blob);
 extern void ft_fixup_num_cores(void *blob);
+extern void ft_srio_setup(void *blob);

 #ifdef CONFIG_MP
 #include "mp.h"
@ -478,4 +479,8 @@ void ft_cpu_setup(void *blob, bd_t *bd)

 	fdt_fixup_qportals(blob);
 #endif
+
+#ifdef CONFIG_SYS_SRIO
+	ft_srio_setup(blob);
+#endif
 }
--- a/arch/powerpc/cpu/mpc8xxx/Makefile
+++ b/arch/powerpc/cpu/mpc8xxx/Makefile
@ -16,6 +16,7 @@ endif

 COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
 COBJS-$(CONFIG_FSL_LBC) += fsl_lbc.o
+COBJS-$(CONFIG_SYS_SRIO) += srio.o

 SRCS	:= $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
--- a/arch/powerpc/cpu/mpc8xxx/fdt.c
+++ b/arch/powerpc/cpu/mpc8xxx/fdt.c
@ -1,5 +1,5 @@
 /*
- * Copyright 2009-2010 Freescale Semiconductor, Inc.
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
 *
 * This file is derived from arch/powerpc/cpu/mpc85xx/cpu.c and
 * arch/powerpc/cpu/mpc86xx/cpu.c. Basically this file contains
@ -28,6 +28,7 @@
 #include <fdt_support.h>
 #include <asm/mp.h>
 #include <asm/fsl_enet.h>
+#include <asm/fsl_serdes.h>

 #if defined(CONFIG_MP) && (defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx))
 static int ft_del_cpuhandle(void *blob, int cpuhandle)
@ -239,3 +240,23 @@ int fdt_fixup_phy_connection(void *blob, int offset, enum fsl_phy_enet_if phyc)
 	return fdt_setprop_string(blob, offset, "phy-connection-type",
 					 fsl_phy_enet_if_str[phyc]);
 }
+
+#ifdef CONFIG_SYS_SRIO
+void ft_srio_setup(void *blob)
+{
+#ifdef CONFIG_SRIO1
+	if (!is_serdes_configured(SRIO1)) {
+		fdt_del_node_and_alias(blob, "rio0");
+	}
+#else
+	fdt_del_node_and_alias(blob, "rio0");
+#endif
+#ifdef CONFIG_SRIO2
+	if (!is_serdes_configured(SRIO2)) {
+		fdt_del_node_and_alias(blob, "rio1");
+	}
+#else
+	fdt_del_node_and_alias(blob, "rio1");
+#endif
+}
+#endif
--- a/arch/powerpc/cpu/mpc8xxx/srio.c
+++ b/arch/powerpc/cpu/mpc8xxx/srio.c
@ -0,0 +1,86 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+
+#if defined(CONFIG_FSL_CORENET)
+	#define _DEVDISR_SRIO1 FSL_CORENET_DEVDISR_SRIO1
+	#define _DEVDISR_SRIO2 FSL_CORENET_DEVDISR_SRIO2
+	#define _DEVDISR_RMU   FSL_CORENET_DEVDISR_RMU
+	#define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
+#elif defined(CONFIG_MPC85xx)
+	#define _DEVDISR_SRIO1 MPC85xx_DEVDISR_SRIO
+	#define _DEVDISR_SRIO2 MPC85xx_DEVDISR_SRIO
+	#define _DEVDISR_RMU   MPC85xx_DEVDISR_RMSG
+	#define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
+#elif defined(CONFIG_MPC86xx)
+	#define _DEVDISR_SRIO1 MPC86xx_DEVDISR_SRIO
+	#define _DEVDISR_SRIO2 MPC86xx_DEVDISR_SRIO
+	#define _DEVDISR_RMU   MPC86xx_DEVDISR_RMSG
+	#define CONFIG_SYS_MPC8xxx_GUTS_ADDR \
+		(&((immap_t *)CONFIG_SYS_IMMR)->im_gur)
+#else
+#error "No defines for DEVDISR_SRIO"
+#endif
+
+void srio_init(void)
+{
+	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC8xxx_GUTS_ADDR;
+	int srio1_used = 0, srio2_used = 0;
+
+	if (is_serdes_configured(SRIO1)) {
+		set_next_law(CONFIG_SYS_SRIO1_MEM_PHYS,
+				law_size_bits(CONFIG_SYS_SRIO1_MEM_SIZE),
+				LAW_TRGT_IF_RIO_1);
+		srio1_used = 1;
+		printf("SRIO1: enabled\n");
+	} else {
+		printf("SRIO1: disabled\n");
+	}
+
+#ifdef CONFIG_SRIO2
+	if (is_serdes_configured(SRIO2)) {
+		set_next_law(CONFIG_SYS_SRIO2_MEM_PHYS,
+				law_size_bits(CONFIG_SYS_SRIO2_MEM_SIZE),
+				LAW_TRGT_IF_RIO_2);
+		srio2_used = 1;
+		printf("SRIO2: enabled\n");
+	} else {
+		printf("SRIO2: disabled\n");
+	}
+#endif
+
+#ifdef CONFIG_FSL_CORENET
+	/* On FSL_CORENET devices we can disable individual ports */
+	if (!srio1_used)
+		setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO1);
+	if (!srio2_used)
+		setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO2);
+#endif
+
+	/* neither port is used - disable everything */
+	if (!srio1_used && !srio2_used) {
+		setbits_be32(&gur->devdisr, _DEVDISR_SRIO1);
+		setbits_be32(&gur->devdisr, _DEVDISR_SRIO2);
+		setbits_be32(&gur->devdisr, _DEVDISR_RMU);
+	}
+}
--- a/arch/powerpc/include/asm/fsl_law.h
+++ b/arch/powerpc/include/asm/fsl_law.h
@ -90,6 +90,7 @@ enum law_trgt_if {
 #define LAW_TRGT_IF_PCI_1	LAW_TRGT_IF_PCI
 #define LAW_TRGT_IF_PCIX	LAW_TRGT_IF_PCI
 #define LAW_TRGT_IF_PCIE_2	LAW_TRGT_IF_PCI_2
+#define LAW_TRGT_IF_RIO_1	LAW_TRGT_IF_RIO

 #ifdef CONFIG_MPC8641
 #define LAW_TRGT_IF_PCIE_1	LAW_TRGT_IF_PCI
--- a/board/freescale/corenet_ds/corenet_ds.c
+++ b/board/freescale/corenet_ds/corenet_ds.c
@ -157,34 +157,10 @@ static const char *serdes_clock_to_string(u32 clock)
 int misc_init_r(void)
 {
 	serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
-	__maybe_unused ccsr_gur_t *gur;
 	u32 actual[NUM_SRDS_BANKS];
 	unsigned int i;
 	u8 sw3;

-	gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-#ifdef CONFIG_SRIO1
-	if (is_serdes_configured(SRIO1)) {
-		set_next_law(CONFIG_SYS_RIO1_MEM_PHYS, LAW_SIZE_256M,
-				LAW_TRGT_IF_RIO_1);
-	} else {
-		printf ("    SRIO1: disabled\n");
-	}
-#else
-	setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO1); /* disable */
-#endif
-
-#ifdef CONFIG_SRIO2
-	if (is_serdes_configured(SRIO2)) {
-		set_next_law(CONFIG_SYS_RIO2_MEM_PHYS, LAW_SIZE_256M,
-				LAW_TRGT_IF_RIO_2);
-	} else {
-		printf ("    SRIO2: disabled\n");
-	}
-#else
-	setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO2); /* disable */
-#endif
-
 	/* Warn if the expected SERDES reference clocks don't match the
 	 * actual reference clocks.  This needs to be done after calling
 	 * p4080_erratum_serdes8(), since that function may modify the clocks.
@ -217,24 +193,6 @@ void board_lmb_reserve(struct lmb *lmb)
 }
 #endif

-void ft_srio_setup(void *blob)
-{
-#ifdef CONFIG_SRIO1
-	if (!is_serdes_configured(SRIO1)) {
-		fdt_del_node_and_alias(blob, "rio0");
-	}
-#else
-	fdt_del_node_and_alias(blob, "rio0");
-#endif
-#ifdef CONFIG_SRIO2
-	if (!is_serdes_configured(SRIO2)) {
-		fdt_del_node_and_alias(blob, "rio1");
-	}
-#else
-	fdt_del_node_and_alias(blob, "rio1");
-#endif
-}
-
 void ft_board_setup(void *blob, bd_t *bd)
 {
 	phys_addr_t base;
@ -242,8 +200,6 @@ void ft_board_setup(void *blob, bd_t *bd)

 	ft_cpu_setup(blob, bd);

-	ft_srio_setup(blob);
-
 	base = getenv_bootm_low();
 	size = getenv_bootm_size();

--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@ -1,5 +1,5 @@
 /*
- * Copyright 2009-2010 Freescale Semiconductor, Inc.
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
@ -51,6 +51,7 @@
 #define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
 #define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */

+#define CONFIG_SYS_SRIO
 #define CONFIG_SRIO1			/* SRIO port 1 */
 #define CONFIG_SRIO2			/* SRIO port 2 */

@ -265,21 +266,21 @@
 /*
 * RapidIO
 */
-#define CONFIG_SYS_RIO1_MEM_VIRT	0xa0000000
+#define CONFIG_SYS_SRIO1_MEM_VIRT	0xa0000000
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_RIO1_MEM_PHYS	0xc20000000ull
+#define CONFIG_SYS_SRIO1_MEM_PHYS	0xc20000000ull
 #else
-#define CONFIG_SYS_RIO1_MEM_PHYS	0xa0000000
+#define CONFIG_SYS_SRIO1_MEM_PHYS	0xa0000000
 #endif
-#define CONFIG_SYS_RIO1_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_SRIO1_MEM_SIZE	0x10000000	/* 256M */

-#define CONFIG_SYS_RIO2_MEM_VIRT	0xb0000000
+#define CONFIG_SYS_SRIO2_MEM_VIRT	0xb0000000
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_RIO2_MEM_PHYS	0xc30000000ull
+#define CONFIG_SYS_SRIO2_MEM_PHYS	0xc30000000ull
 #else
-#define CONFIG_SYS_RIO2_MEM_PHYS	0xb0000000
+#define CONFIG_SYS_SRIO2_MEM_PHYS	0xb0000000
 #endif
-#define CONFIG_SYS_RIO2_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_SRIO2_MEM_SIZE	0x10000000	/* 256M */

 /*
 * General PCI