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Fix memory init problems on MCC200 board

This commit is contained in:
Wolfgang Denk 2006-06-14 16:48:18 +02:00
parent df02bd1b3f
commit 9e18a4bc6c
3 changed files with 52 additions and 1 deletions
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2
CHANGELOG
View File

@ -2,6 +2,8 @@
Changes since U-Boot 1.1.4:
======================================================================
* Fix memory init problems on MCC200 board
* Fix IxEthDB.h to compile again
Patch by Stefan Roese, 14 Jun 2006

8
board/mcc200/mcc200.c
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@ -28,7 +28,11 @@
#include <mpc5xxx.h>
#include <pci.h>
#include "mt48lc8m32b2-6-7.h"
/* Two MT48LC8M32B2 for 32 MB */
/* #include "mt48lc8m32b2-6-7.h" */
/* One MT48LC16M32S2 for 64 MB */
#include "mt48lc16m32s2-75.h"
DECLARE_GLOBAL_DATA_PTR;
@ -74,6 +78,8 @@ static void sdram_start (int hi_addr)
/* normal operation */
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
__asm__ volatile ("sync");
udelay(10);
}
#endif

43
board/mcc200/mt48lc16m32s2-75.h Normal file
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@ -0,0 +1,43 @@
/*
* (C) Copyright 2004
* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#define SDRAM_DDR 0 /* is SDR */
#if defined(CONFIG_MPC5200)
/* Settings for XLB = 132 MHz */
#define SDRAM_MODE 0x00CD0000
#define SDRAM_CONTROL 0x504F0000
#define SDRAM_CONFIG1 0xD2322800
#define SDRAM_CONFIG2 0x8AD70000
#elif defined(CONFIG_MGT5100)
/* Settings for XLB = 66 MHz */
#define SDRAM_MODE 0x008D0000
#define SDRAM_CONTROL 0x504F0000
#define SDRAM_CONFIG1 0xC2222600
#define SDRAM_CONFIG2 0x88B70004
#define SDRAM_ADDRSEL 0x02000000
#else
#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
#endif