* Patch by Kurt Stremerch, 03 Sep 2004:
Add Xilinx Spartan2E family FPGA support * Patch by Jeff Angielski, 02 Sep 2004: Add Added support for H2 revision of the EP8260 board. Fixed formatting for some of the EP8260 related source files.
This commit is contained in:
parent
a1191902ca
commit
9dd611b8c1
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@ -2,6 +2,13 @@
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Changes for U-Boot 1.1.3:
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Changes for U-Boot 1.1.3:
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======================================================================
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======================================================================
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* Patch by Kurt Stremerch, 03 Sep 2004:
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Add Xilinx Spartan2E family FPGA support
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* Patch by Jeff Angielski, 02 Sep 2004:
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Add Added support for H2 revision of the EP8260 board.
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Fixed formatting for some of the EP8260 related source files.
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* Patch by Jon Loeliger, 02 Sep 2004:
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* Patch by Jon Loeliger, 02 Sep 2004:
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Reset monitor size back to 256 so environment can be written
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Reset monitor size back to 256 so environment can be written
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to flash on MPC85xx ADS and CDS releases.
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to flash on MPC85xx ADS and CDS releases.
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@ -227,6 +227,10 @@ int checkboard (void)
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major = 1;
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major = 1;
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minor = 1;
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minor = 1;
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break;
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break;
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case 0x06:
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major = 1;
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minor = 3;
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break;
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default:
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default:
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break;
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break;
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}
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}
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@ -81,15 +81,28 @@ ulong flash_get_size( ulong baseaddr, flash_info_t *info )
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info->flash_id = FLASH_UNKNOWN;
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info->flash_id = FLASH_UNKNOWN;
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return(0);
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return(0);
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}
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}
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if (flashtest_h == AMD_ID_DL323B) {
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switch((int)flashtest_h) {
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case AMD_ID_DL323B:
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info->flash_id += FLASH_AMDL323B;
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info->flash_id += FLASH_AMDL323B;
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info->sector_count = 71;
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info->sector_count = 71;
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info->size = 0x01000000; /* 4 * 4 MB = 16 MB */
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info->size = 0x01000000; /* 4 * 4 MB = 16 MB */
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} else {
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break;
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case AMD_ID_LV640U: /* AMDLV640 and AMDLV641 have same ID */
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info->flash_id += FLASH_AMLV640U;
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info->sector_count = 128;
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info->size = 0x02000000; /* 4 * 8 MB = 32 MB */
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break;
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default:
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info->flash_id = FLASH_UNKNOWN;
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info->flash_id = FLASH_UNKNOWN;
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return(0); /* no or unknown flash */
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return(0); /* no or unknown flash */
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}
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}
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if(flashtest_h == AMD_ID_LV640U) {
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/* set up sector start adress table (uniform sector type) */
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for (i = 0; i < info->sector_count; i++)
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info->start[i] = baseaddr + (i * 0x00040000);
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} else {
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/* set up sector start adress table (bottom sector type) */
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/* set up sector start adress table (bottom sector type) */
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for (i = 0; i < 8; i++) {
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for (i = 0; i < 8; i++) {
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info->start[i] = baseaddr + (i * 0x00008000);
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info->start[i] = baseaddr + (i * 0x00008000);
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@ -97,7 +110,7 @@ ulong flash_get_size( ulong baseaddr, flash_info_t *info )
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for (i = 8; i < info->sector_count; i++) {
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for (i = 8; i < info->sector_count; i++) {
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info->start[i] = baseaddr + (i * 0x00040000) - 0x001C0000;
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info->start[i] = baseaddr + (i * 0x00040000) - 0x001C0000;
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}
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}
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}
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/* check for protected sectors */
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/* check for protected sectors */
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for (i = 0; i < info->sector_count; i++) {
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for (i = 0; i < info->sector_count; i++) {
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/* read sector protection at sector address, (A7 .. A0) = 0x02 */
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/* read sector protection at sector address, (A7 .. A0) = 0x02 */
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@ -176,6 +189,8 @@ void flash_print_info (flash_info_t *info)
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switch (info->flash_id & FLASH_TYPEMASK) {
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switch (info->flash_id & FLASH_TYPEMASK) {
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case FLASH_AMDL323B: printf ("29DL323B (32 M, bottom sector)\n");
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case FLASH_AMDL323B: printf ("29DL323B (32 M, bottom sector)\n");
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break;
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break;
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case FLASH_AMLV640U: printf ("29LV640U (64 M, uniform sector)\n");
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break;
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default: printf ("Unknown Chip Type\n");
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default: printf ("Unknown Chip Type\n");
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break;
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break;
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}
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}
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@ -27,16 +27,27 @@
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/*
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/*
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* board/config.h - configuration options, board specific
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* board/config.h - configuration options, board specific
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*
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*
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* Note: my board is a "SBC 8260 H, V.1.1"
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* "EP8260 H, V.1.1"
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* - 64M 60x Bus SDRAM
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* - 64M 60x Bus SDRAM
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* - 32M Local Bus SDRAM
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* - 32M Local Bus SDRAM
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* - 16M Flash (4 x AM29DL323DB90WDI)
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* - 16M Flash (4 x AM29DL323DB90WDI)
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* - 128k NVRAM with RTC
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* - 128k NVRAM with RTC
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*
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* "EP8260 H2, V.1.3" (CFG_EP8260_H2)
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* - 300MHz/133MHz/66MHz
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* - 64M 60x Bus SDRAM
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* - 32M Local Bus SDRAM
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* - 32M Flash
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* - 128k NVRAM with RTC
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*/
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*/
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#ifndef __CONFIG_H
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define __CONFIG_H
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/* Define this to enable support the EP8260 H2 version */
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#define CFG_EP8260_H2 1
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/* #undef CFG_EP8260_H2 */
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/* What is the oscillator's (UX2) frequency in Hz? */
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/* What is the oscillator's (UX2) frequency in Hz? */
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#define CONFIG_8260_CLKIN (66 * 1000 * 1000)
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#define CONFIG_8260_CLKIN (66 * 1000 * 1000)
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@ -62,7 +73,11 @@
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* 0x6 0x1 66 133 266
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* 0x6 0x1 66 133 266
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* 0x6 0x2 66 133 300
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* 0x6 0x2 66 133 300
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*/
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*/
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#define CFG_SBC_MODCK_H 0x05
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#ifdef CFG_EP8260_H2
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#define CFG_SBC_MODCK_H (HRCW_MODCK_H0110)
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#else
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#define CFG_SBC_MODCK_H (HRCW_MODCK_H0110)
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#endif
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/* Define this if you want to boot from 0x00000100. If you don't define
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/* Define this if you want to boot from 0x00000100. If you don't define
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* this, you will need to program the bootloader to 0xfff00000, and
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* this, you will need to program the bootloader to 0xfff00000, and
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* The main FLASH is whichever is connected to *CS0. U-Boot expects
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* The main FLASH is whichever is connected to *CS0. U-Boot expects
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* this to be the SIMM.
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* this to be the SIMM.
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*/
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*/
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#ifdef CFG_EP8260_H2
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#define CFG_FLASH0_BASE 0xFE000000
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#define CFG_FLASH0_SIZE 32
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#else
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#define CFG_FLASH0_BASE 0xFF000000
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#define CFG_FLASH0_BASE 0xFF000000
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#define CFG_FLASH0_SIZE 16
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#define CFG_FLASH0_SIZE 16
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#endif
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/* What should the base address of the secondary FLASH be and how big
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/* What should the base address of the secondary FLASH be and how big
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* is it (in Mbytes)? The secondary FLASH is whichever is connected
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* is it (in Mbytes)? The secondary FLASH is whichever is connected
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/* What should be the base address of NVRAM and how big is
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/* What should be the base address of NVRAM and how big is
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* it (in Bytes)
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* it (in Bytes)
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*/
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*/
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#define CFG_NVRAM_BASE_ADDR 0xFa080000
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#define CFG_NVRAM_BASE_ADDR 0xFA080000
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#define CFG_NVRAM_SIZE (128*1024)-16
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#define CFG_NVRAM_SIZE (128*1024)-16
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/* The RTC is a Dallas DS1556
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/* The RTC is a Dallas DS1556
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_ENV_OVERWRITE
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/* What should the console's baud rate be? */
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/* What should the console's baud rate be? */
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/* #define CONFIG_BAUDRATE 57600 */
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#ifdef CFG_EP8260_H2
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#define CONFIG_BAUDRATE 9600
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#else
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_BAUDRATE 115200
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#endif
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/* Ethernet MAC address */
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/* Ethernet MAC address */
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#define CONFIG_ETHADDR 00:10:EC:00:30:8C
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#define CONFIG_ETHADDR 00:10:EC:00:30:8C
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@ -297,6 +320,7 @@
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CFG_CMD_VFD | \
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CFG_CMD_VFD | \
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CFG_CMD_XIMG ) )
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CFG_CMD_XIMG ) )
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/* Where do the internal registers live? */
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/* Where do the internal registers live? */
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#define CFG_IMMR 0xF0000000
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#define CFG_IMMR 0xF0000000
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#define CFG_DEFAULT_IMMR 0x00010000
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#define CFG_DEFAULT_IMMR 0x00010000
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@ -371,21 +395,22 @@
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# define CFG_SBC_HRCW_BOOT_FLAGS (0x00000000)
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# define CFG_SBC_HRCW_BOOT_FLAGS (0x00000000)
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#endif /* defined(CFG_SBC_BOOT_LOW) */
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#endif /* defined(CFG_SBC_BOOT_LOW) */
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/* get the HRCW ISB field from CFG_IMMR */
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#ifdef CFG_EP8260_H2
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/*
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/* get the HRCW ISB field from CFG_DEFAULT_IMMR */
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#define CFG_SBC_HRCW_IMMR ( ((CFG_IMMR & 0x10000000) >> 10) |\
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#define CFG_SBC_HRCW_IMMR ( ((CFG_DEFAULT_IMMR & 0x10000000) >> 10) |\
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((CFG_IMMR & 0x01000000) >> 7) |\
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((CFG_DEFAULT_IMMR & 0x01000000) >> 7) |\
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((CFG_IMMR & 0x00100000) >> 4) )
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((CFG_DEFAULT_IMMR & 0x00100000) >> 4) )
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#define CFG_HRCW_MASTER (HRCW_EBM |\
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#define CFG_HRCW_MASTER (HRCW_EBM |\
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HRCW_L2CPC01 |\
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HRCW_L2CPC01 |\
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CFG_SBC_HRCW_IMMR |\
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CFG_SBC_HRCW_IMMR |\
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HRCW_APPC10 |\
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HRCW_APPC10 |\
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HRCW_CS10PC01 |\
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HRCW_CS10PC01 |\
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HRCW_MODCK_H0101 |\
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CFG_SBC_MODCK_H |\
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CFG_SBC_HRCW_BOOT_FLAGS)
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CFG_SBC_HRCW_BOOT_FLAGS)
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*/
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#else
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#define CFG_HRCW_MASTER 0x10400245
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#define CFG_HRCW_MASTER 0x10400245
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#endif
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/* no slaves */
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/* no slaves */
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#define CFG_HRCW_SLAVE1 0
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#define CFG_HRCW_SLAVE1 0
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@ -432,7 +457,11 @@
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* FLASH and environment organization
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* FLASH and environment organization
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*/
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*/
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#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#ifdef CFG_EP8260_H2
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#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
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#else
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#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
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#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
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#endif
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#define CFG_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */
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#define CFG_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */
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#define CFG_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */
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#define CFG_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */
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@ -504,40 +533,48 @@
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* BCR - Bus Configuration 4-25
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* BCR - Bus Configuration 4-25
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*-----------------------------------------------------------------------
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*-----------------------------------------------------------------------
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*/
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*/
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/*#define CFG_BCR (BCR_EBM |\
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#define CFG_BCR (BCR_EBM |\
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BCR_PLDP |\
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BCR_PLDP |\
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BCR_EAV |\
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BCR_EAV |\
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BCR_NPQM1)
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BCR_NPQM0)
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*/
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#define CFG_BCR 0x80C08000
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/*-----------------------------------------------------------------------
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/*-----------------------------------------------------------------------
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* SIUMCR - SIU Module Configuration 4-31
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* SIUMCR - SIU Module Configuration 4-31
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*-----------------------------------------------------------------------
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*-----------------------------------------------------------------------
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*/
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*/
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#define CFG_SIUMCR (SIUMCR_L2CPC01 |\
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#define CFG_SIUMCR (SIUMCR_L2CPC01 |\
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SIUMCR_APPC10 |\
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SIUMCR_APPC10 |\
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SIUMCR_CS10PC01)
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SIUMCR_CS10PC01)
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/*-----------------------------------------------------------------------
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/*-----------------------------------------------------------------------
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* SYPCR - System Protection Control 11-9
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* SYPCR - System Protection Control 11-9
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* SYPCR can only be written once after reset!
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* SYPCR can only be written once after reset!
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*-----------------------------------------------------------------------
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*-----------------------------------------------------------------------
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* Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
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* Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
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*/
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*/
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#ifdef CFG_EP8260_H2
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/* TBD: Find out why setting the BMT to 0xff causes the FCC to
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* generate TX buffer underrun errors for large packets under
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* Linux
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*/
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#define CFG_SYPCR_BMT 0x00000600
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#else
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#define CFG_SYPCR_BMT SYPCR_BMT
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#endif
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#ifdef CFG_LSDRAM
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#ifdef CFG_LSDRAM
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#define CFG_SYPCR (SYPCR_SWTC |\
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#define CFG_SYPCR (SYPCR_SWTC |\
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SYPCR_BMT |\
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CFG_SYPCR_BMT |\
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SYPCR_PBME |\
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SYPCR_PBME |\
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SYPCR_LBME |\
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SYPCR_LBME |\
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SYPCR_SWP)
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SYPCR_SWP)
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#else
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#else
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#define CFG_SYPCR (SYPCR_SWTC |\
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#define CFG_SYPCR (SYPCR_SWTC |\
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SYPCR_BMT |\
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CFG_SYPCR_BMT |\
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SYPCR_PBME |\
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SYPCR_PBME |\
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SYPCR_SWP)
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SYPCR_SWP)
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#endif
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#endif
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/*-----------------------------------------------------------------------
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/*-----------------------------------------------------------------------
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* TMCNTSC - Time Counter Status and Control 4-40
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* TMCNTSC - Time Counter Status and Control 4-40
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*-----------------------------------------------------------------------
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*-----------------------------------------------------------------------
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@ -555,10 +592,14 @@
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* Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
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* Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
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* Periodic timer
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* Periodic timer
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*/
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*/
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/*#define CFG_PISCR (PISCR_PS |\
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#ifdef CFG_EP8260_H2
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#define CFG_PISCR (PISCR_PS |\
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PISCR_PTF |\
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PISCR_PTF |\
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PISCR_PTE)*/
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PISCR_PTE)
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#else
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#define CFG_PISCR 0
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#define CFG_PISCR 0
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#endif
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|
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/*-----------------------------------------------------------------------
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/*-----------------------------------------------------------------------
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* SCCR - System Clock Control 9-8
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* SCCR - System Clock Control 9-8
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*-----------------------------------------------------------------------
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*-----------------------------------------------------------------------
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@ -616,7 +657,7 @@
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#define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH0_SIZE) |\
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#define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH0_SIZE) |\
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ORxG_CSNT |\
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ORxG_CSNT |\
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ORxG_ACS_DIV1 |\
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ORxG_ACS_DIV1 |\
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ORxG_SCY_6_CLK |\
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ORxG_SCY_8_CLK |\
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ORxG_EHTR)
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ORxG_EHTR)
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|
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/* Bank 1 - SDRAM
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/* Bank 1 - SDRAM
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@ -632,9 +673,13 @@
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ORxS_ROWST_PBI1_A6 |\
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ORxS_ROWST_PBI1_A6 |\
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ORxS_NUMR_12)
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ORxS_NUMR_12)
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|
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#ifdef CFG_EP8260_H2
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#define CFG_PSDMR 0xC34E246E
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#else
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#define CFG_PSDMR 0xC34E2462
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#define CFG_PSDMR 0xC34E2462
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#define CFG_PSRT 0x64
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#endif
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|
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#define CFG_PSRT 0x64
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|
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#ifdef CFG_LSDRAM
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#ifdef CFG_LSDRAM
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/* Bank 2 - SDRAM
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/* Bank 2 - SDRAM
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@ -673,6 +718,7 @@
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*/
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*/
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#define CFG_OR4_PRELIM 0xfff00854
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#define CFG_OR4_PRELIM 0xfff00854
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|
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#ifdef _NOT_USED_SINCE_NOT_WORKING_
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/* Bank 8 - On board registers
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/* Bank 8 - On board registers
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* PCMCIA (currently not working!)
|
* PCMCIA (currently not working!)
|
||||||
*/
|
*/
|
||||||
|
@ -686,6 +732,7 @@
|
||||||
ORxG_ACS_DIV1 |\
|
ORxG_ACS_DIV1 |\
|
||||||
ORxG_SETA |\
|
ORxG_SETA |\
|
||||||
ORxG_SCY_10_CLK)
|
ORxG_SCY_10_CLK)
|
||||||
|
#endif
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Internal Definitions
|
* Internal Definitions
|
||||||
|
|
|
@ -70,6 +70,13 @@ typedef struct {
|
||||||
#define XILINX_XC2S100_SIZE 781248/8
|
#define XILINX_XC2S100_SIZE 781248/8
|
||||||
#define XILINX_XC2S150_SIZE 1040128/8
|
#define XILINX_XC2S150_SIZE 1040128/8
|
||||||
|
|
||||||
|
/* Spartan-IIE (1.8V) */
|
||||||
|
#define XILINX_XC2S50E_SIZE 630048/8
|
||||||
|
#define XILINX_XC2S100E_SIZE 863840/8
|
||||||
|
#define XILINX_XC2S150E_SIZE 1134496/8
|
||||||
|
#define XILINX_XC2S200E_SIZE 1442016/8
|
||||||
|
#define XILINX_XC2S300E_SIZE 1875648/8
|
||||||
|
|
||||||
/* Descriptor Macros
|
/* Descriptor Macros
|
||||||
*********************************************************************/
|
*********************************************************************/
|
||||||
/* Spartan-II devices */
|
/* Spartan-II devices */
|
||||||
|
@ -88,4 +95,19 @@ typedef struct {
|
||||||
#define XILINX_XC2S150_DESC(iface, fn_table, cookie) \
|
#define XILINX_XC2S150_DESC(iface, fn_table, cookie) \
|
||||||
{ Xilinx_Spartan2, iface, XILINX_XC2S150_SIZE, fn_table, cookie }
|
{ Xilinx_Spartan2, iface, XILINX_XC2S150_SIZE, fn_table, cookie }
|
||||||
|
|
||||||
|
#define XILINX_XC2S50E_DESC(iface, fn_table, cookie) \
|
||||||
|
{ Xilinx_Spartan2, iface, XILINX_XC2S50E_SIZE, fn_table, cookie }
|
||||||
|
|
||||||
|
#define XILINX_XC2S100E_DESC(iface, fn_table, cookie) \
|
||||||
|
{ Xilinx_Spartan2, iface, XILINX_XC2S100E_SIZE, fn_table, cookie }
|
||||||
|
|
||||||
|
#define XILINX_XC2S150E_DESC(iface, fn_table, cookie) \
|
||||||
|
{ Xilinx_Spartan2, iface, XILINX_XC2S150E_SIZE, fn_table, cookie }
|
||||||
|
|
||||||
|
#define XILINX_XC2S200E_DESC(iface, fn_table, cookie) \
|
||||||
|
{ Xilinx_Spartan2, iface, XILINX_XC2S200E_SIZE, fn_table, cookie }
|
||||||
|
|
||||||
|
#define XILINX_XC2S300E_DESC(iface, fn_table, cookie) \
|
||||||
|
{ Xilinx_Spartan2, iface, XILINX_XC2S300E_SIZE, fn_table, cookie }
|
||||||
|
|
||||||
#endif /* _SPARTAN2_H_ */
|
#endif /* _SPARTAN2_H_ */
|
||||||
|
|
Loading…
Reference in New Issue