* Patch by Kurt Stremerch, 03 Sep 2004:
Add Xilinx Spartan2E family FPGA support * Patch by Jeff Angielski, 02 Sep 2004: Add Added support for H2 revision of the EP8260 board. Fixed formatting for some of the EP8260 related source files.
This commit is contained in:
wdenk
parent
a1191902ca
commit
9dd611b8c1
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@ -2,6 +2,13 @@
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Changes for U-Boot 1.1.3:
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======================================================================
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* Patch by Kurt Stremerch, 03 Sep 2004:
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Add Xilinx Spartan2E family FPGA support
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* Patch by Jeff Angielski, 02 Sep 2004:
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Add Added support for H2 revision of the EP8260 board.
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Fixed formatting for some of the EP8260 related source files.
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* Patch by Jon Loeliger, 02 Sep 2004:
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Reset monitor size back to 256 so environment can be written
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to flash on MPC85xx ADS and CDS releases.
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@ -227,6 +227,10 @@ int checkboard (void)
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major = 1;
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minor = 1;
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break;
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case 0x06:
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major = 1;
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minor = 3;
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break;
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default:
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break;
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}
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@ -42,250 +42,265 @@ flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
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*/
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void flash_reset(void)
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{
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if( flash_info[0].flash_id != FLASH_UNKNOWN ) {
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V_ULONG( flash_info[0].start[0] ) = 0x00F000F0;
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V_ULONG( flash_info[0].start[0] + 4 ) = 0x00F000F0;
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}
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if( flash_info[0].flash_id != FLASH_UNKNOWN ) {
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V_ULONG( flash_info[0].start[0] ) = 0x00F000F0;
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V_ULONG( flash_info[0].start[0] + 4 ) = 0x00F000F0;
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}
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}
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/*-----------------------------------------------------------------------
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*/
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ulong flash_get_size( ulong baseaddr, flash_info_t *info )
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{
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short i;
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unsigned long flashtest_h, flashtest_l;
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short i;
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unsigned long flashtest_h, flashtest_l;
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/* Write auto select command sequence and test FLASH answer */
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V_ULONG(baseaddr + ((ulong)0x0555 << 3)) = 0x00AA00AA;
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V_ULONG(baseaddr + ((ulong)0x02AA << 3)) = 0x00550055;
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V_ULONG(baseaddr + ((ulong)0x0555 << 3)) = 0x00900090;
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V_ULONG(baseaddr + 4 + ((ulong)0x0555 << 3)) = 0x00AA00AA;
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V_ULONG(baseaddr + 4 + ((ulong)0x02AA << 3)) = 0x00550055;
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V_ULONG(baseaddr + 4 + ((ulong)0x0555 << 3)) = 0x00900090;
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/* Write auto select command sequence and test FLASH answer */
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V_ULONG(baseaddr + ((ulong)0x0555 << 3)) = 0x00AA00AA;
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V_ULONG(baseaddr + ((ulong)0x02AA << 3)) = 0x00550055;
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V_ULONG(baseaddr + ((ulong)0x0555 << 3)) = 0x00900090;
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V_ULONG(baseaddr + 4 + ((ulong)0x0555 << 3)) = 0x00AA00AA;
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V_ULONG(baseaddr + 4 + ((ulong)0x02AA << 3)) = 0x00550055;
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V_ULONG(baseaddr + 4 + ((ulong)0x0555 << 3)) = 0x00900090;
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flashtest_h = V_ULONG(baseaddr); /* manufacturer ID */
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flashtest_l = V_ULONG(baseaddr + 4);
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flashtest_h = V_ULONG(baseaddr); /* manufacturer ID */
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flashtest_l = V_ULONG(baseaddr + 4);
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if ((int)flashtest_h == AMD_MANUFACT) {
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info->flash_id = FLASH_MAN_AMD;
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} else {
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info->flash_id = FLASH_UNKNOWN;
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info->sector_count = 0;
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info->size = 0;
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return (0); /* no or unknown flash */
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}
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if ((int)flashtest_h == AMD_MANUFACT) {
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info->flash_id = FLASH_MAN_AMD;
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} else {
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info->flash_id = FLASH_UNKNOWN;
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info->sector_count = 0;
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info->size = 0;
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return (0); /* no or unknown flash */
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}
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flashtest_h = V_ULONG(baseaddr + 8); /* device ID */
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flashtest_l = V_ULONG(baseaddr + 12);
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if (flashtest_h != flashtest_l) {
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info->flash_id = FLASH_UNKNOWN;
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return(0);
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}
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if (flashtest_h == AMD_ID_DL323B) {
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info->flash_id += FLASH_AMDL323B;
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info->sector_count = 71;
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info->size = 0x01000000; /* 4 * 4 MB = 16 MB */
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} else {
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info->flash_id = FLASH_UNKNOWN;
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return(0); /* no or unknown flash */
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}
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flashtest_h = V_ULONG(baseaddr + 8); /* device ID */
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flashtest_l = V_ULONG(baseaddr + 12);
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if (flashtest_h != flashtest_l) {
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info->flash_id = FLASH_UNKNOWN;
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return(0);
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}
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/* set up sector start adress table (bottom sector type) */
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for (i = 0; i < 8; i++) {
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info->start[i] = baseaddr + (i * 0x00008000);
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}
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for (i = 8; i < info->sector_count; i++) {
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info->start[i] = baseaddr + (i * 0x00040000) - 0x001C0000;
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}
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switch((int)flashtest_h) {
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case AMD_ID_DL323B:
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info->flash_id += FLASH_AMDL323B;
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info->sector_count = 71;
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info->size = 0x01000000; /* 4 * 4 MB = 16 MB */
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break;
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case AMD_ID_LV640U: /* AMDLV640 and AMDLV641 have same ID */
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info->flash_id += FLASH_AMLV640U;
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info->sector_count = 128;
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info->size = 0x02000000; /* 4 * 8 MB = 32 MB */
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break;
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default:
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info->flash_id = FLASH_UNKNOWN;
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return(0); /* no or unknown flash */
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}
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/* check for protected sectors */
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for (i = 0; i < info->sector_count; i++) {
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/* read sector protection at sector address, (A7 .. A0) = 0x02 */
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if ((V_ULONG( info->start[i] + 16 ) & 0x00010001) ||
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(V_ULONG( info->start[i] + 20 ) & 0x00010001)) {
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info->protect[i] = 1; /* D0 = 1 if protected */
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} else {
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info->protect[i] = 0;
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}
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}
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if(flashtest_h == AMD_ID_LV640U) {
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/* set up sector start adress table (uniform sector type) */
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for (i = 0; i < info->sector_count; i++)
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info->start[i] = baseaddr + (i * 0x00040000);
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} else {
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/* set up sector start adress table (bottom sector type) */
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for (i = 0; i < 8; i++) {
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info->start[i] = baseaddr + (i * 0x00008000);
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}
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for (i = 8; i < info->sector_count; i++) {
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info->start[i] = baseaddr + (i * 0x00040000) - 0x001C0000;
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}
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}
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/* check for protected sectors */
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for (i = 0; i < info->sector_count; i++) {
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/* read sector protection at sector address, (A7 .. A0) = 0x02 */
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if ((V_ULONG( info->start[i] + 16 ) & 0x00010001) ||
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(V_ULONG( info->start[i] + 20 ) & 0x00010001)) {
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info->protect[i] = 1; /* D0 = 1 if protected */
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} else {
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info->protect[i] = 0;
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}
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}
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flash_reset();
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return(info->size);
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flash_reset();
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return(info->size);
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}
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/*-----------------------------------------------------------------------
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*/
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unsigned long flash_init (void)
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{
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unsigned long size_b0 = 0;
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int i;
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unsigned long size_b0 = 0;
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int i;
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/* Init: no FLASHes known */
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for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
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flash_info[i].flash_id = FLASH_UNKNOWN;
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}
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/* Init: no FLASHes known */
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for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
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flash_info[i].flash_id = FLASH_UNKNOWN;
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}
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/* Static FLASH Bank configuration here (only one bank) */
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/* Static FLASH Bank configuration here (only one bank) */
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size_b0 = flash_get_size(CFG_FLASH0_BASE, &flash_info[0]);
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if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) {
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printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
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size_b0, size_b0>>20);
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}
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size_b0 = flash_get_size(CFG_FLASH0_BASE, &flash_info[0]);
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if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) {
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printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
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size_b0, size_b0>>20);
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}
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/*
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* protect monitor and environment sectors
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*/
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/*
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* protect monitor and environment sectors
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*/
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#if CFG_MONITOR_BASE >= CFG_FLASH0_BASE
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flash_protect(FLAG_PROTECT_SET,
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CFG_MONITOR_BASE,
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CFG_MONITOR_BASE+monitor_flash_len-1,
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&flash_info[0]);
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flash_protect(FLAG_PROTECT_SET,
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CFG_MONITOR_BASE,
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CFG_MONITOR_BASE+monitor_flash_len-1,
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&flash_info[0]);
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#endif
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#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR)
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# ifndef CFG_ENV_SIZE
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# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE
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# endif
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flash_protect(FLAG_PROTECT_SET,
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CFG_ENV_ADDR,
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CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
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&flash_info[0]);
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flash_protect(FLAG_PROTECT_SET,
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CFG_ENV_ADDR,
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CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
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&flash_info[0]);
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#endif
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return (size_b0);
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return (size_b0);
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}
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/*-----------------------------------------------------------------------
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*/
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void flash_print_info (flash_info_t *info)
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{
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int i;
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int i;
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if (info->flash_id == FLASH_UNKNOWN) {
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printf ("missing or unknown FLASH type\n");
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if (info->flash_id == FLASH_UNKNOWN) {
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printf ("missing or unknown FLASH type\n");
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return;
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}
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switch ((info->flash_id >> 16) & 0xff) {
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case FLASH_MAN_AMD: printf ("AMD "); break;
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default: printf ("Unknown Vendor "); break;
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}
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switch (info->flash_id & FLASH_TYPEMASK) {
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case FLASH_AMDL323B: printf ("29DL323B (32 M, bottom sector)\n");
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break;
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case FLASH_AMLV640U: printf ("29LV640U (64 M, uniform sector)\n");
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break;
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default: printf ("Unknown Chip Type\n");
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break;
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}
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printf (" Size: %ld MB in %d Sectors\n",
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info->size >> 20, info->sector_count);
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printf (" Sector Start Addresses:");
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for (i=0; i<info->sector_count; ++i) {
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if ((i % 5) == 0)
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printf ("\n ");
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printf (" %08lX%s",
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info->start[i],
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info->protect[i] ? " (RO)" : " "
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);
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}
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printf ("\n");
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return;
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}
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switch ((info->flash_id >> 16) & 0xff) {
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case FLASH_MAN_AMD: printf ("AMD "); break;
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default: printf ("Unknown Vendor "); break;
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}
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switch (info->flash_id & FLASH_TYPEMASK) {
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case FLASH_AMDL323B: printf ("29DL323B (32 M, bottom sector)\n");
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break;
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default: printf ("Unknown Chip Type\n");
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break;
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}
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printf (" Size: %ld MB in %d Sectors\n",
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info->size >> 20, info->sector_count);
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printf (" Sector Start Addresses:");
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for (i=0; i<info->sector_count; ++i) {
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if ((i % 5) == 0)
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printf ("\n ");
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printf (" %08lX%s",
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info->start[i],
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info->protect[i] ? " (RO)" : " "
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);
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}
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printf ("\n");
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return;
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}
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|
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/*-----------------------------------------------------------------------
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*/
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int flash_erase (flash_info_t *info, int s_first, int s_last)
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{
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int flag, prot, sect, l_sect;
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ulong start, now, last;
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int flag, prot, sect, l_sect;
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ulong start, now, last;
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if ((s_first < 0) || (s_first > s_last)) {
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if (info->flash_id == FLASH_UNKNOWN) {
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printf ("- missing\n");
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if ((s_first < 0) || (s_first > s_last)) {
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if (info->flash_id == FLASH_UNKNOWN) {
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printf ("- missing\n");
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} else {
|
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printf ("- no sectors to erase\n");
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}
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return 1;
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}
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|
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prot = 0;
|
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for (sect = s_first; sect <= s_last; sect++) {
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if (info->protect[sect])
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prot++;
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}
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|
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if (prot) {
|
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printf ("- Warning: %d protected sectors will not be erased!\n",
|
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prot);
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} else {
|
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printf ("- no sectors to erase\n");
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printf ("\n");
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}
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return 1;
|
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}
|
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|
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prot = 0;
|
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for (sect = s_first; sect <= s_last; sect++) {
|
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if (info->protect[sect])
|
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prot++;
|
||||
}
|
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l_sect = -1;
|
||||
|
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if (prot) {
|
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printf ("- Warning: %d protected sectors will not be erased!\n",
|
||||
prot);
|
||||
} else {
|
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printf ("\n");
|
||||
}
|
||||
/* Disable interrupts which might cause a timeout here */
|
||||
flag = disable_interrupts();
|
||||
|
||||
l_sect = -1;
|
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V_ULONG( info->start[0] + (0x0555 << 3) ) = 0x00AA00AA;
|
||||
V_ULONG( info->start[0] + (0x02AA << 3) ) = 0x00550055;
|
||||
V_ULONG( info->start[0] + (0x0555 << 3) ) = 0x00800080;
|
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V_ULONG( info->start[0] + (0x0555 << 3) ) = 0x00AA00AA;
|
||||
V_ULONG( info->start[0] + (0x02AA << 3) ) = 0x00550055;
|
||||
V_ULONG( info->start[0] + 4 + (0x0555 << 3) ) = 0x00AA00AA;
|
||||
V_ULONG( info->start[0] + 4 + (0x02AA << 3) ) = 0x00550055;
|
||||
V_ULONG( info->start[0] + 4 + (0x0555 << 3) ) = 0x00800080;
|
||||
V_ULONG( info->start[0] + 4 + (0x0555 << 3) ) = 0x00AA00AA;
|
||||
V_ULONG( info->start[0] + 4 + (0x02AA << 3) ) = 0x00550055;
|
||||
udelay (1000);
|
||||
|
||||
/* Disable interrupts which might cause a timeout here */
|
||||
flag = disable_interrupts();
|
||||
|
||||
V_ULONG( info->start[0] + (0x0555 << 3) ) = 0x00AA00AA;
|
||||
V_ULONG( info->start[0] + (0x02AA << 3) ) = 0x00550055;
|
||||
V_ULONG( info->start[0] + (0x0555 << 3) ) = 0x00800080;
|
||||
V_ULONG( info->start[0] + (0x0555 << 3) ) = 0x00AA00AA;
|
||||
V_ULONG( info->start[0] + (0x02AA << 3) ) = 0x00550055;
|
||||
V_ULONG( info->start[0] + 4 + (0x0555 << 3) ) = 0x00AA00AA;
|
||||
V_ULONG( info->start[0] + 4 + (0x02AA << 3) ) = 0x00550055;
|
||||
V_ULONG( info->start[0] + 4 + (0x0555 << 3) ) = 0x00800080;
|
||||
V_ULONG( info->start[0] + 4 + (0x0555 << 3) ) = 0x00AA00AA;
|
||||
V_ULONG( info->start[0] + 4 + (0x02AA << 3) ) = 0x00550055;
|
||||
udelay (1000);
|
||||
|
||||
/* Start erase on unprotected sectors */
|
||||
for (sect = s_first; sect<=s_last; sect++) {
|
||||
if (info->protect[sect] == 0) { /* not protected */
|
||||
V_ULONG( info->start[sect] ) = 0x00300030;
|
||||
V_ULONG( info->start[sect] + 4 ) = 0x00300030;
|
||||
l_sect = sect;
|
||||
/* Start erase on unprotected sectors */
|
||||
for (sect = s_first; sect<=s_last; sect++) {
|
||||
if (info->protect[sect] == 0) { /* not protected */
|
||||
V_ULONG( info->start[sect] ) = 0x00300030;
|
||||
V_ULONG( info->start[sect] + 4 ) = 0x00300030;
|
||||
l_sect = sect;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* re-enable interrupts if necessary */
|
||||
if (flag)
|
||||
enable_interrupts();
|
||||
/* re-enable interrupts if necessary */
|
||||
if (flag)
|
||||
enable_interrupts();
|
||||
|
||||
/* wait at least 80us - let's wait 1 ms */
|
||||
udelay (1000);
|
||||
/* wait at least 80us - let's wait 1 ms */
|
||||
udelay (1000);
|
||||
|
||||
/*
|
||||
* We wait for the last triggered sector
|
||||
*/
|
||||
if (l_sect < 0)
|
||||
goto DONE;
|
||||
/*
|
||||
* We wait for the last triggered sector
|
||||
*/
|
||||
if (l_sect < 0)
|
||||
goto DONE;
|
||||
|
||||
start = get_timer (0);
|
||||
last = start;
|
||||
while ((V_ULONG( info->start[l_sect] ) & 0x00800080) != 0x00800080 ||
|
||||
(V_ULONG( info->start[l_sect] + 4 ) & 0x00800080) != 0x00800080)
|
||||
{
|
||||
if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
|
||||
printf ("Timeout\n");
|
||||
return 1;
|
||||
start = get_timer (0);
|
||||
last = start;
|
||||
while ((V_ULONG( info->start[l_sect] ) & 0x00800080) != 0x00800080 ||
|
||||
(V_ULONG( info->start[l_sect] + 4 ) & 0x00800080) != 0x00800080)
|
||||
{
|
||||
if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
|
||||
printf ("Timeout\n");
|
||||
return 1;
|
||||
}
|
||||
/* show that we're waiting */
|
||||
if ((now - last) > 1000) { /* every second */
|
||||
serial_putc ('.');
|
||||
last = now;
|
||||
}
|
||||
}
|
||||
/* show that we're waiting */
|
||||
if ((now - last) > 1000) { /* every second */
|
||||
serial_putc ('.');
|
||||
last = now;
|
||||
}
|
||||
}
|
||||
|
||||
DONE:
|
||||
/* reset to read mode */
|
||||
flash_reset ();
|
||||
DONE:
|
||||
/* reset to read mode */
|
||||
flash_reset ();
|
||||
|
||||
printf (" done\n");
|
||||
return 0;
|
||||
printf (" done\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int write_dword (flash_info_t *, ulong, unsigned char *);
|
||||
|
|
@ -299,49 +314,49 @@ static int write_dword (flash_info_t *, ulong, unsigned char *);
|
|||
|
||||
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
|
||||
{
|
||||
ulong dp;
|
||||
static unsigned char bb[8];
|
||||
int i, l, rc, cc = cnt;
|
||||
ulong dp;
|
||||
static unsigned char bb[8];
|
||||
int i, l, rc, cc = cnt;
|
||||
|
||||
dp = (addr & ~7); /* get lower dword aligned address */
|
||||
dp = (addr & ~7); /* get lower dword aligned address */
|
||||
|
||||
/*
|
||||
* handle unaligned start bytes
|
||||
*/
|
||||
if ((l = addr - dp) != 0) {
|
||||
for (i = 0; i < 8; i++)
|
||||
bb[i] = (i < l || (i-l) >= cc) ? V_BYTE(dp+i) : *src++;
|
||||
if ((rc = write_dword(info, dp, bb)) != 0)
|
||||
{
|
||||
return (rc);
|
||||
/*
|
||||
* handle unaligned start bytes
|
||||
*/
|
||||
if ((l = addr - dp) != 0) {
|
||||
for (i = 0; i < 8; i++)
|
||||
bb[i] = (i < l || (i-l) >= cc) ? V_BYTE(dp+i) : *src++;
|
||||
if ((rc = write_dword(info, dp, bb)) != 0)
|
||||
{
|
||||
return (rc);
|
||||
}
|
||||
dp += 8;
|
||||
cc -= 8 - l;
|
||||
}
|
||||
dp += 8;
|
||||
cc -= 8 - l;
|
||||
}
|
||||
|
||||
/*
|
||||
* handle word aligned part
|
||||
*/
|
||||
while (cc >= 8) {
|
||||
if ((rc = write_dword(info, dp, src)) != 0) {
|
||||
return (rc);
|
||||
/*
|
||||
* handle word aligned part
|
||||
*/
|
||||
while (cc >= 8) {
|
||||
if ((rc = write_dword(info, dp, src)) != 0) {
|
||||
return (rc);
|
||||
}
|
||||
dp += 8;
|
||||
src += 8;
|
||||
cc -= 8;
|
||||
}
|
||||
dp += 8;
|
||||
src += 8;
|
||||
cc -= 8;
|
||||
}
|
||||
|
||||
if (cc <= 0) {
|
||||
return (0);
|
||||
}
|
||||
if (cc <= 0) {
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*
|
||||
* handle unaligned tail bytes
|
||||
*/
|
||||
for (i = 0; i < 8; i++) {
|
||||
bb[i] = (i < cc) ? *src++ : V_BYTE(dp+i);
|
||||
}
|
||||
return (write_dword(info, dp, bb));
|
||||
/*
|
||||
* handle unaligned tail bytes
|
||||
*/
|
||||
for (i = 0; i < 8; i++) {
|
||||
bb[i] = (i < cc) ? *src++ : V_BYTE(dp+i);
|
||||
}
|
||||
return (write_dword(info, dp, bb));
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
|
|
@ -352,45 +367,45 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
|
|||
*/
|
||||
static int write_dword (flash_info_t *info, ulong dest, unsigned char * pdata)
|
||||
{
|
||||
ulong start;
|
||||
ulong cl = 0, ch =0;
|
||||
int flag, i;
|
||||
ulong start;
|
||||
ulong cl = 0, ch =0;
|
||||
int flag, i;
|
||||
|
||||
for (ch=0, i=0; i < 4; i++)
|
||||
ch = (ch << 8) + *pdata++; /* high word */
|
||||
for (cl=0, i=0; i < 4; i++)
|
||||
cl = (cl << 8) + *pdata++; /* low word */
|
||||
for (ch=0, i=0; i < 4; i++)
|
||||
ch = (ch << 8) + *pdata++; /* high word */
|
||||
for (cl=0, i=0; i < 4; i++)
|
||||
cl = (cl << 8) + *pdata++; /* low word */
|
||||
|
||||
/* Check if Flash is (sufficiently) erased */
|
||||
if ((*((vu_long *)dest) & ch) != ch
|
||||
||(*((vu_long *)(dest + 4)) & cl) != cl)
|
||||
{
|
||||
return (2);
|
||||
}
|
||||
|
||||
/* Disable interrupts which might cause a timeout here */
|
||||
flag = disable_interrupts();
|
||||
|
||||
V_ULONG( info->start[0] + (0x0555 << 3) ) = 0x00AA00AA;
|
||||
V_ULONG( info->start[0] + (0x02AA << 3) ) = 0x00550055;
|
||||
V_ULONG( info->start[0] + (0x0555 << 3) ) = 0x00A000A0;
|
||||
V_ULONG( dest ) = ch;
|
||||
V_ULONG( info->start[0] + 4 + (0x0555 << 3) ) = 0x00AA00AA;
|
||||
V_ULONG( info->start[0] + 4 + (0x02AA << 3) ) = 0x00550055;
|
||||
V_ULONG( info->start[0] + 4 + (0x0555 << 3) ) = 0x00A000A0;
|
||||
V_ULONG( dest + 4 ) = cl;
|
||||
|
||||
/* re-enable interrupts if necessary */
|
||||
if (flag)
|
||||
enable_interrupts();
|
||||
|
||||
/* data polling for D7 */
|
||||
start = get_timer (0);
|
||||
while (((V_ULONG( dest ) & 0x00800080) != (ch & 0x00800080)) ||
|
||||
((V_ULONG( dest + 4 ) & 0x00800080) != (cl & 0x00800080))) {
|
||||
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
|
||||
return (1);
|
||||
/* Check if Flash is (sufficiently) erased */
|
||||
if ((*((vu_long *)dest) & ch) != ch
|
||||
||(*((vu_long *)(dest + 4)) & cl) != cl)
|
||||
{
|
||||
return (2);
|
||||
}
|
||||
}
|
||||
return (0);
|
||||
|
||||
/* Disable interrupts which might cause a timeout here */
|
||||
flag = disable_interrupts();
|
||||
|
||||
V_ULONG( info->start[0] + (0x0555 << 3) ) = 0x00AA00AA;
|
||||
V_ULONG( info->start[0] + (0x02AA << 3) ) = 0x00550055;
|
||||
V_ULONG( info->start[0] + (0x0555 << 3) ) = 0x00A000A0;
|
||||
V_ULONG( dest ) = ch;
|
||||
V_ULONG( info->start[0] + 4 + (0x0555 << 3) ) = 0x00AA00AA;
|
||||
V_ULONG( info->start[0] + 4 + (0x02AA << 3) ) = 0x00550055;
|
||||
V_ULONG( info->start[0] + 4 + (0x0555 << 3) ) = 0x00A000A0;
|
||||
V_ULONG( dest + 4 ) = cl;
|
||||
|
||||
/* re-enable interrupts if necessary */
|
||||
if (flag)
|
||||
enable_interrupts();
|
||||
|
||||
/* data polling for D7 */
|
||||
start = get_timer (0);
|
||||
while (((V_ULONG( dest ) & 0x00800080) != (ch & 0x00800080)) ||
|
||||
((V_ULONG( dest + 4 ) & 0x00800080) != (cl & 0x00800080))) {
|
||||
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
|
||||
return (1);
|
||||
}
|
||||
}
|
||||
return (0);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -26,17 +26,28 @@
|
|||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific
|
||||
*
|
||||
* Note: my board is a "SBC 8260 H, V.1.1"
|
||||
*
|
||||
* "EP8260 H, V.1.1"
|
||||
* - 64M 60x Bus SDRAM
|
||||
* - 32M Local Bus SDRAM
|
||||
* - 16M Flash (4 x AM29DL323DB90WDI)
|
||||
* - 128k NVRAM with RTC
|
||||
*
|
||||
* "EP8260 H2, V.1.3" (CFG_EP8260_H2)
|
||||
* - 300MHz/133MHz/66MHz
|
||||
* - 64M 60x Bus SDRAM
|
||||
* - 32M Local Bus SDRAM
|
||||
* - 32M Flash
|
||||
* - 128k NVRAM with RTC
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/* Define this to enable support the EP8260 H2 version */
|
||||
#define CFG_EP8260_H2 1
|
||||
/* #undef CFG_EP8260_H2 */
|
||||
|
||||
/* What is the oscillator's (UX2) frequency in Hz? */
|
||||
#define CONFIG_8260_CLKIN (66 * 1000 * 1000)
|
||||
|
||||
|
|
@ -62,7 +73,11 @@
|
|||
* 0x6 0x1 66 133 266
|
||||
* 0x6 0x2 66 133 300
|
||||
*/
|
||||
#define CFG_SBC_MODCK_H 0x05
|
||||
#ifdef CFG_EP8260_H2
|
||||
#define CFG_SBC_MODCK_H (HRCW_MODCK_H0110)
|
||||
#else
|
||||
#define CFG_SBC_MODCK_H (HRCW_MODCK_H0110)
|
||||
#endif
|
||||
|
||||
/* Define this if you want to boot from 0x00000100. If you don't define
|
||||
* this, you will need to program the bootloader to 0xfff00000, and
|
||||
|
|
@ -84,8 +99,13 @@
|
|||
* The main FLASH is whichever is connected to *CS0. U-Boot expects
|
||||
* this to be the SIMM.
|
||||
*/
|
||||
#ifdef CFG_EP8260_H2
|
||||
#define CFG_FLASH0_BASE 0xFE000000
|
||||
#define CFG_FLASH0_SIZE 32
|
||||
#else
|
||||
#define CFG_FLASH0_BASE 0xFF000000
|
||||
#define CFG_FLASH0_SIZE 16
|
||||
#define CFG_FLASH0_SIZE 16
|
||||
#endif
|
||||
|
||||
/* What should the base address of the secondary FLASH be and how big
|
||||
* is it (in Mbytes)? The secondary FLASH is whichever is connected
|
||||
|
|
@ -107,7 +127,7 @@
|
|||
* local bus (8260 local bus is NOT cacheable!)
|
||||
*/
|
||||
/* #define CFG_LSDRAM */
|
||||
#undef CFG_LSDRAM
|
||||
#undef CFG_LSDRAM
|
||||
|
||||
#ifdef CFG_LSDRAM
|
||||
/* What should be the base address of SDRAM DIMM (local bus) and how big is
|
||||
|
|
@ -125,7 +145,7 @@
|
|||
/* What should be the base address of NVRAM and how big is
|
||||
* it (in Bytes)
|
||||
*/
|
||||
#define CFG_NVRAM_BASE_ADDR 0xFa080000
|
||||
#define CFG_NVRAM_BASE_ADDR 0xFA080000
|
||||
#define CFG_NVRAM_SIZE (128*1024)-16
|
||||
|
||||
/* The RTC is a Dallas DS1556
|
||||
|
|
@ -237,8 +257,11 @@
|
|||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
/* What should the console's baud rate be? */
|
||||
/* #define CONFIG_BAUDRATE 57600 */
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
#ifdef CFG_EP8260_H2
|
||||
#define CONFIG_BAUDRATE 9600
|
||||
#else
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
#endif
|
||||
|
||||
/* Ethernet MAC address */
|
||||
#define CONFIG_ETHADDR 00:10:EC:00:30:8C
|
||||
|
|
@ -297,6 +320,7 @@
|
|||
CFG_CMD_VFD | \
|
||||
CFG_CMD_XIMG ) )
|
||||
|
||||
|
||||
/* Where do the internal registers live? */
|
||||
#define CFG_IMMR 0xF0000000
|
||||
#define CFG_DEFAULT_IMMR 0x00010000
|
||||
|
|
@ -371,21 +395,22 @@
|
|||
# define CFG_SBC_HRCW_BOOT_FLAGS (0x00000000)
|
||||
#endif /* defined(CFG_SBC_BOOT_LOW) */
|
||||
|
||||
/* get the HRCW ISB field from CFG_IMMR */
|
||||
/*
|
||||
#define CFG_SBC_HRCW_IMMR ( ((CFG_IMMR & 0x10000000) >> 10) |\
|
||||
((CFG_IMMR & 0x01000000) >> 7) |\
|
||||
((CFG_IMMR & 0x00100000) >> 4) )
|
||||
#ifdef CFG_EP8260_H2
|
||||
/* get the HRCW ISB field from CFG_DEFAULT_IMMR */
|
||||
#define CFG_SBC_HRCW_IMMR ( ((CFG_DEFAULT_IMMR & 0x10000000) >> 10) |\
|
||||
((CFG_DEFAULT_IMMR & 0x01000000) >> 7) |\
|
||||
((CFG_DEFAULT_IMMR & 0x00100000) >> 4) )
|
||||
|
||||
#define CFG_HRCW_MASTER (HRCW_EBM |\
|
||||
HRCW_L2CPC01 |\
|
||||
CFG_SBC_HRCW_IMMR |\
|
||||
HRCW_APPC10 |\
|
||||
HRCW_CS10PC01 |\
|
||||
HRCW_MODCK_H0101 |\
|
||||
CFG_SBC_MODCK_H |\
|
||||
CFG_SBC_HRCW_BOOT_FLAGS)
|
||||
*/
|
||||
#else
|
||||
#define CFG_HRCW_MASTER 0x10400245
|
||||
#endif
|
||||
|
||||
/* no slaves */
|
||||
#define CFG_HRCW_SLAVE1 0
|
||||
|
|
@ -432,7 +457,11 @@
|
|||
* FLASH and environment organization
|
||||
*/
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
|
||||
#ifdef CFG_EP8260_H2
|
||||
#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
|
||||
#else
|
||||
#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
|
||||
#endif
|
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */
|
||||
#define CFG_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */
|
||||
|
|
@ -504,40 +533,48 @@
|
|||
* BCR - Bus Configuration 4-25
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
/*#define CFG_BCR (BCR_EBM |\
|
||||
#define CFG_BCR (BCR_EBM |\
|
||||
BCR_PLDP |\
|
||||
BCR_EAV |\
|
||||
BCR_NPQM1)
|
||||
*/
|
||||
#define CFG_BCR 0x80C08000
|
||||
BCR_NPQM0)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SIUMCR - SIU Module Configuration 4-31
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
#define CFG_SIUMCR (SIUMCR_L2CPC01 |\
|
||||
SIUMCR_APPC10 |\
|
||||
SIUMCR_CS10PC01)
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SYPCR - System Protection Control 11-9
|
||||
* SYPCR can only be written once after reset!
|
||||
*-----------------------------------------------------------------------
|
||||
* Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
|
||||
*/
|
||||
#ifdef CFG_EP8260_H2
|
||||
/* TBD: Find out why setting the BMT to 0xff causes the FCC to
|
||||
* generate TX buffer underrun errors for large packets under
|
||||
* Linux
|
||||
*/
|
||||
#define CFG_SYPCR_BMT 0x00000600
|
||||
#else
|
||||
#define CFG_SYPCR_BMT SYPCR_BMT
|
||||
#endif
|
||||
|
||||
#ifdef CFG_LSDRAM
|
||||
#define CFG_SYPCR (SYPCR_SWTC |\
|
||||
SYPCR_BMT |\
|
||||
CFG_SYPCR_BMT |\
|
||||
SYPCR_PBME |\
|
||||
SYPCR_LBME |\
|
||||
SYPCR_SWP)
|
||||
#else
|
||||
#define CFG_SYPCR (SYPCR_SWTC |\
|
||||
SYPCR_BMT |\
|
||||
CFG_SYPCR_BMT |\
|
||||
SYPCR_PBME |\
|
||||
SYPCR_SWP)
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* TMCNTSC - Time Counter Status and Control 4-40
|
||||
*-----------------------------------------------------------------------
|
||||
|
|
@ -555,10 +592,14 @@
|
|||
* Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
|
||||
* Periodic timer
|
||||
*/
|
||||
/*#define CFG_PISCR (PISCR_PS |\
|
||||
#ifdef CFG_EP8260_H2
|
||||
#define CFG_PISCR (PISCR_PS |\
|
||||
PISCR_PTF |\
|
||||
PISCR_PTE)*/
|
||||
PISCR_PTE)
|
||||
#else
|
||||
#define CFG_PISCR 0
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock Control 9-8
|
||||
*-----------------------------------------------------------------------
|
||||
|
|
@ -616,7 +657,7 @@
|
|||
#define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH0_SIZE) |\
|
||||
ORxG_CSNT |\
|
||||
ORxG_ACS_DIV1 |\
|
||||
ORxG_SCY_6_CLK |\
|
||||
ORxG_SCY_8_CLK |\
|
||||
ORxG_EHTR)
|
||||
|
||||
/* Bank 1 - SDRAM
|
||||
|
|
@ -632,9 +673,13 @@
|
|||
ORxS_ROWST_PBI1_A6 |\
|
||||
ORxS_NUMR_12)
|
||||
|
||||
#ifdef CFG_EP8260_H2
|
||||
#define CFG_PSDMR 0xC34E246E
|
||||
#else
|
||||
#define CFG_PSDMR 0xC34E2462
|
||||
#define CFG_PSRT 0x64
|
||||
#endif
|
||||
|
||||
#define CFG_PSRT 0x64
|
||||
|
||||
#ifdef CFG_LSDRAM
|
||||
/* Bank 2 - SDRAM
|
||||
|
|
@ -651,7 +696,7 @@
|
|||
ORxS_ROWST_PBI0_A9 |\
|
||||
ORxS_NUMR_12)
|
||||
|
||||
#define CFG_LSDMR 0x416A2562
|
||||
#define CFG_LSDMR 0x416A2562
|
||||
#define CFG_LSRT 0x64
|
||||
#else
|
||||
#define CFG_LSRT 0x0
|
||||
|
|
@ -673,6 +718,7 @@
|
|||
*/
|
||||
#define CFG_OR4_PRELIM 0xfff00854
|
||||
|
||||
#ifdef _NOT_USED_SINCE_NOT_WORKING_
|
||||
/* Bank 8 - On board registers
|
||||
* PCMCIA (currently not working!)
|
||||
*/
|
||||
|
|
@ -686,6 +732,7 @@
|
|||
ORxG_ACS_DIV1 |\
|
||||
ORxG_SETA |\
|
||||
ORxG_SCY_10_CLK)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Internal Definitions
|
||||
|
|
|
|||
|
|
@ -70,6 +70,13 @@ typedef struct {
|
|||
#define XILINX_XC2S100_SIZE 781248/8
|
||||
#define XILINX_XC2S150_SIZE 1040128/8
|
||||
|
||||
/* Spartan-IIE (1.8V) */
|
||||
#define XILINX_XC2S50E_SIZE 630048/8
|
||||
#define XILINX_XC2S100E_SIZE 863840/8
|
||||
#define XILINX_XC2S150E_SIZE 1134496/8
|
||||
#define XILINX_XC2S200E_SIZE 1442016/8
|
||||
#define XILINX_XC2S300E_SIZE 1875648/8
|
||||
|
||||
/* Descriptor Macros
|
||||
*********************************************************************/
|
||||
/* Spartan-II devices */
|
||||
|
|
@ -88,4 +95,19 @@ typedef struct {
|
|||
#define XILINX_XC2S150_DESC(iface, fn_table, cookie) \
|
||||
{ Xilinx_Spartan2, iface, XILINX_XC2S150_SIZE, fn_table, cookie }
|
||||
|
||||
#define XILINX_XC2S50E_DESC(iface, fn_table, cookie) \
|
||||
{ Xilinx_Spartan2, iface, XILINX_XC2S50E_SIZE, fn_table, cookie }
|
||||
|
||||
#define XILINX_XC2S100E_DESC(iface, fn_table, cookie) \
|
||||
{ Xilinx_Spartan2, iface, XILINX_XC2S100E_SIZE, fn_table, cookie }
|
||||
|
||||
#define XILINX_XC2S150E_DESC(iface, fn_table, cookie) \
|
||||
{ Xilinx_Spartan2, iface, XILINX_XC2S150E_SIZE, fn_table, cookie }
|
||||
|
||||
#define XILINX_XC2S200E_DESC(iface, fn_table, cookie) \
|
||||
{ Xilinx_Spartan2, iface, XILINX_XC2S200E_SIZE, fn_table, cookie }
|
||||
|
||||
#define XILINX_XC2S300E_DESC(iface, fn_table, cookie) \
|
||||
{ Xilinx_Spartan2, iface, XILINX_XC2S300E_SIZE, fn_table, cookie }
|
||||
|
||||
#endif /* _SPARTAN2_H_ */
|
||||
|
|
|
|||
Loading…
Reference in New Issue