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TQM8xx: Fix CAN timing. 

Signed-off-by: Martin Krause <martin.krause@tqs.de>
This commit is contained in:
Jens Gehrlein 2007-09-26 17:55:54 +02:00 committed by Martin Krause
parent d43e489baf
commit 9d29250e2e
1 changed files with 9 additions and 7 deletions
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16
board/tqm8xx/tqm8xx.c
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@ -354,6 +354,8 @@ long int initdram (int board_type)
udelay (10000);
#ifdef CONFIG_CAN_DRIVER
/* UPM initialization for CAN @ CLKOUT <= 66 MHz */
/* Initialize OR3 / BR3 */
memctl->memc_or3 = CFG_OR3_CAN;
memctl->memc_br3 = CFG_BR3_CAN;
@ -362,7 +364,7 @@ long int initdram (int board_type)
memctl->memc_mbmr = MBMR_GPL_B4DIS; /* GPL_B4 ouput line Disable */
/* Initialize UPMB for CAN: single read */
memctl->memc_mdr = 0xFFFFC004;
memctl->memc_mdr = 0xFFFFCC04;
memctl->memc_mcr = 0x0100 | UPMB;
memctl->memc_mdr = 0x0FFFD004;
@ -374,23 +376,23 @@ long int initdram (int board_type)
memctl->memc_mdr = 0x3FFFC004;
memctl->memc_mcr = 0x0103 | UPMB;
memctl->memc_mdr = 0xFFFFDC05;
memctl->memc_mdr = 0xFFFFDC07;
memctl->memc_mcr = 0x0104 | UPMB;
/* Initialize UPMB for CAN: single write */
memctl->memc_mdr = 0xFFFCC004;
memctl->memc_mdr = 0xFFFCCC04;
memctl->memc_mcr = 0x0118 | UPMB;
memctl->memc_mdr = 0xCFFCD004;
memctl->memc_mdr = 0xCFFCDC04;
memctl->memc_mcr = 0x0119 | UPMB;
memctl->memc_mdr = 0x0FFCC000;
memctl->memc_mdr = 0x3FFCC000;
memctl->memc_mcr = 0x011A | UPMB;
memctl->memc_mdr = 0x7FFCC004;
memctl->memc_mdr = 0xFFFCC004;
memctl->memc_mcr = 0x011B | UPMB;
memctl->memc_mdr = 0xFFFDCC05;
memctl->memc_mdr = 0xFFFDC405;
memctl->memc_mcr = 0x011C | UPMB;
#endif /* CONFIG_CAN_DRIVER */