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ARMV7: Restructure omap3 musb driver to allow code sharing between OMAP3 and OMAP4 

Signed-off-by: Steve Sakoman <steve@sakoman.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
This commit is contained in:
Steve Sakoman 2010-06-25 12:42:04 -07:00 committed by Sandeep Paulraj
parent 516799f677
commit 9b16757758
4 changed files with 24 additions and 1 deletions
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3
arch/arm/include/asm/arch-omap3/cpu.h
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@ -483,4 +483,7 @@ struct pm {
#define I2C_BASE2 (OMAP34XX_CORE_L4_IO_BASE + 0x72000)
#define I2C_BASE3 (OMAP34XX_CORE_L4_IO_BASE + 0x60000)
/* MUSB base */
#define MUSB_BASE (OMAP34XX_CORE_L4_IO_BASE + 0xAB000)
#endif /* _CPU_H */

3
arch/arm/include/asm/arch-omap4/cpu.h
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@ -139,4 +139,7 @@ struct watchdog {
#define I2C_BASE2 (OMAP44XX_L4_PER_BASE + 0x72000)
#define I2C_BASE3 (OMAP44XX_L4_PER_BASE + 0x60000)
/* MUSB base */
#define MUSB_BASE (OMAP44XX_L4_CORE_BASE + 0xAB000)
#endif /* _CPU_H */

16
drivers/usb/musb/omap3.c
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@ -31,6 +31,7 @@
*/
#include <twl4030.h>
#include <twl6030.h>
#include "omap3.h"
static int platform_needs_initialization = 1;
@ -65,7 +66,12 @@ static struct omap3_otg_regs *otg;
#define OMAP3_OTG_SYSSTATUS_RESETDONE 0x0001
/* OMAP4430 has an internal PHY, use it */
#ifdef CONFIG_OMAP4430
#define OMAP3_OTG_INTERFSEL_OMAP 0x0000
#else
#define OMAP3_OTG_INTERFSEL_OMAP 0x0001
#endif
#define OMAP3_OTG_FORCESTDBY_STANDBY 0x0001
@ -105,6 +111,11 @@ int musb_platform_init(void)
goto end;
}
#endif
#ifdef CONFIG_TWL6030_POWER
twl6030_usb_device_settings();
#endif
otg = (struct omap3_otg_regs *)OMAP3_OTG_BASE;
/* Set OTG to always be on */
@ -122,6 +133,11 @@ int musb_platform_init(void)
#ifdef CONFIG_OMAP3_EVM
musb_cfg.extvbus = omap3_evm_need_extvbus();
#endif
#ifdef CONFIG_OMAP4430
u32 *usbotghs_control = (u32 *)(CTRL_BASE + 0x33C);
*usbotghs_control = 0x15;
#endif
platform_needs_initialization = 0;
}

3
drivers/usb/musb/omap3.h
View File

@ -31,10 +31,11 @@
#ifndef _MUSB_OMAP3_H_
#define _MUSB_OMAP3_H_
#include <asm/arch/cpu.h>
#include "musb_core.h"
/* Base address of MUSB registers */
#define MENTOR_USB0_BASE (OMAP34XX_CORE_L4_IO_BASE + 0xAB000)
#define MENTOR_USB0_BASE MUSB_BASE
/* Base address of OTG registers */
#define OMAP3_OTG_BASE (MENTOR_USB0_BASE + 0x400)