at91rm9200ek: convert to at91
This patch removes some functionality from at91rm9200ek board but the remaining functionality does now work with newer at91 code and arm-relocation. Currently missing features are: - dataflash booting (due to missing HW for testing) - MMC/SD-Card - first stage bootloader support is completely removed (not needed for NOR) Cause this board was (some days ago) reference for all at91rm9200 based boards this should be a good starting point to convert all remaining at91rm9200 borads to at91 code. Aside from that this is a good base to get some drivers between at91sam/at91rm/avr32 merged. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Signed-off-by: Reinhard Meyer <u-boot@emk-elektronik.de>
This commit is contained in:
Andreas Bießmann
Reinhard Meyer
parent
1ba91ba233
commit
99fa97e955
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@ -573,6 +573,10 @@ Rishi Bhattacharya <rishi@ti.com>
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omap5912osk ARM926EJS
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Andreas Bießmann <andreas.devel@gmail.com>
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at91rm9200ek at91rm9200
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Cliff Brake <cliff.brake@gmail.com>
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pxa255_idp xscale
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@ -27,11 +27,6 @@ LIB = $(obj)lib$(BOARD).a
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COBJS-y += $(BOARD).o
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COBJS-y += led.o
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COBJS-y += misc.o
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ifdef CONFIG_HAS_DATAFLASH
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COBJS-$(CONFIG_DATAFLASH_MMC_SELECT) += mux.o
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COBJS-y += partition.o
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endif
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SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS-y))
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@ -1,4 +1,8 @@
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/*
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* (C) Copyright 2010 Andreas Bießmann <andreas.devel@gmail.com>
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*
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* derived from previous work
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*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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@ -23,78 +27,44 @@
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*/
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#include <common.h>
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#include <exports.h>
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#include <netdev.h>
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#include <asm/arch/AT91RM9200.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/at91_pio.h>
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#include <asm/arch/at91_pmc.h>
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#include <asm/io.h>
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#if defined(CONFIG_DRIVER_ETHER)
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#include <at91rm9200_net.h>
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#include <dm9161.h>
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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/* ------------------------------------------------------------------------- */
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/*
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* Miscelaneous platform dependent initialisations
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*/
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int board_init (void)
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int board_init(void)
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{
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/* Enable Ctrlc */
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console_init_f ();
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at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
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/*
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* Correct IRDA resistor problem
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* Set PA23_TXD in Output
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*/
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writel(AT91C_PA23_TXD2, ((AT91PS_PIO) AT91C_BASE_PIOA)->PIO_OER);
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/*
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* memory and cpu-speed are setup before relocation
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* so we do _nothing_ here
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*/
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writel(AT91_PMX_AA_TXD2, &pio->pioa.oer);
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/* arch number of AT91RM9200EK-Board */
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gd->bd->bi_arch_number = MACH_TYPE_AT91RM9200EK;
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/* adress of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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return 0;
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}
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int dram_init (void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM;
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gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
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/* dram_init must store complete ramsize in gd->ram_size */
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gd->ram_size = get_ram_size((volatile long *)CONFIG_SYS_SDRAM_BASE,
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CONFIG_SYS_SDRAM_SIZE);
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return 0;
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}
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#if defined(CONFIG_DRIVER_ETHER) && defined(CONFIG_CMD_NET)
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/*
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* Name:
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* at91rm9200_GetPhyInterface
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* Description:
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* Initialise the interface functions to the PHY
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* Arguments:
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* None
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* Return value:
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* None
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*/
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void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops)
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{
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p_phyops->Init = dm9161_InitPhy;
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p_phyops->IsPhyConnected = dm9161_IsPhyConnected;
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p_phyops->GetLinkSpeed = dm9161_GetLinkSpeed;
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p_phyops->AutoNegotiate = dm9161_AutoNegotiate;
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}
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#endif
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#ifdef CONFIG_DRIVER_AT91EMAC
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int board_eth_init(bd_t *bis)
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{
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int rc = 0;
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rc = at91emac_register(bis, 0);
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return rc;
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return at91emac_register(bis, (u32) AT91_EMAC_BASE);
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}
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#endif
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@ -1 +1,2 @@
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CONFIG_SYS_TEXT_BASE = 0x21f00000
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# currently only NOR flash booting is supported
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CONFIG_SYS_TEXT_BASE = 0x10000000
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@ -3,6 +3,9 @@
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* Atmel Nordic AB <www.atmel.com>
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* Ulf Samuelsson <ulf@atmel.com>
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*
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* (C) Copyright 2010
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* Andreas Bießmann <andreas.devel@gmail.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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@ -23,67 +26,62 @@
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*/
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#include <common.h>
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#include <asm/arch/AT91RM9200.h>
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#include <asm/io.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/at91_pmc.h>
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#define GREEN_LED AT91C_PIO_PB0
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#define YELLOW_LED AT91C_PIO_PB1
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#define RED_LED AT91C_PIO_PB2
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/* bit mask in PIO port B */
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#define GREEN_LED (1<<0)
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#define YELLOW_LED (1<<1)
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#define RED_LED (1<<2)
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void green_LED_on(void)
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{
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AT91PS_PIO PIOB = AT91C_BASE_PIOB;
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writel(GREEN_LED, PIOB->PIO_CODR);
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at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
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writel(GREEN_LED, &pio->piob.codr);
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}
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void yellow_LED_on(void)
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{
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AT91PS_PIO PIOB = AT91C_BASE_PIOB;
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writel(YELLOW_LED, PIOB->PIO_CODR);
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at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
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writel(YELLOW_LED, &pio->piob.codr);
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}
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void red_LED_on(void)
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{
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AT91PS_PIO PIOB = AT91C_BASE_PIOB;
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writel(RED_LED, PIOB->PIO_CODR);
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at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
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writel(RED_LED, &pio->piob.codr);
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}
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void green_LED_off(void)
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{
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AT91PS_PIO PIOB = AT91C_BASE_PIOB;
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writel(GREEN_LED, PIOB->PIO_SODR);
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at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
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writel(GREEN_LED, &pio->piob.sodr);
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}
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void yellow_LED_off(void)
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{
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AT91PS_PIO PIOB = AT91C_BASE_PIOB;
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writel(YELLOW_LED, PIOB->PIO_SODR);
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at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
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writel(YELLOW_LED, &pio->piob.sodr);
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}
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void red_LED_off(void)
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{
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AT91PS_PIO PIOB = AT91C_BASE_PIOB;
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writel(RED_LED, PIOB->PIO_SODR);
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at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
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writel(RED_LED, &pio->piob.sodr);
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}
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void coloured_LED_init (void)
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{
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AT91PS_PIO PIOB = AT91C_BASE_PIOB;
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AT91PS_PMC PMC = AT91C_BASE_PMC;
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at91_pmc_t *pmc = (at91_pmc_t *)AT91_PMC_BASE;
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at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
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/* Enable PIOB clock */
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writel((1 << AT91C_ID_PIOB), PMC->PMC_PCER);
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writel(1 << AT91_ID_PIOB, &pmc->pcer);
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/* Disable peripherals on LEDs */
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writel(AT91C_PIO_PB2 | AT91C_PIO_PB1 | AT91C_PIO_PB0, PIOB->PIO_PER);
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writel(GREEN_LED | YELLOW_LED | RED_LED, &pio->piob.per);
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/* Enable pins as outputs */
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writel(AT91C_PIO_PB2 | AT91C_PIO_PB1 | AT91C_PIO_PB0, PIOB->PIO_OER);
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writel(GREEN_LED | YELLOW_LED | RED_LED, &pio->piob.oer);
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/* Turn all LEDs OFF */
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writel(AT91C_PIO_PB2 | AT91C_PIO_PB1 | AT91C_PIO_PB0, PIOB->PIO_SODR);
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writel(GREEN_LED | YELLOW_LED | RED_LED, &pio->piob.sodr);
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}
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@ -1,50 +0,0 @@
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/*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/arch/AT91RM9200.h>
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#include <at91rm9200_net.h>
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#include <dm9161.h>
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#include <net.h>
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int board_late_init(void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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/* Fix Ethernet Initialization Bug when starting Linux from U-Boot */
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eth_init(gd->bd);
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return 0;
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}
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/* checks if addr is in RAM */
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int addr2ram(ulong addr)
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{
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int result = 0;
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if((addr >= PHYS_SDRAM) && (addr < (PHYS_SDRAM + PHYS_SDRAM_SIZE)))
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result = 1;
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return result;
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}
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@ -1,38 +0,0 @@
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#include <config.h>
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#include <common.h>
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#include <asm/hardware.h>
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#include <asm/io.h>
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#include <dataflash.h>
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int AT91F_GetMuxStatus(void)
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{
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/* Set in PIO mode */
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writel(CONFIG_SYS_DATAFLASH_MMC_PIO, AT91C_BASE_PIOB->PIO_PER);
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/* Configure in output */
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writel(CONFIG_SYS_DATAFLASH_MMC_PIO, AT91C_BASE_PIOB->PIO_OER);
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if(readl(AT91C_BASE_PIOB->PIO_ODSR) & CONFIG_SYS_DATAFLASH_MMC_PIO)
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return 1;
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return 0;
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}
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void AT91F_SelectMMC(void)
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{
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/* Set in PIO mode */
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writel(CONFIG_SYS_DATAFLASH_MMC_PIO, AT91C_BASE_PIOB->PIO_PER);
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/* Configure in output */
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writel(CONFIG_SYS_DATAFLASH_MMC_PIO, AT91C_BASE_PIOB->PIO_OER);
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/* Set Output */
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writel(CONFIG_SYS_DATAFLASH_MMC_PIO, AT91C_BASE_PIOB->PIO_SODR);
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}
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void AT91F_SelectSPI(void)
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{
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/* Set in PIO mode */
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writel(CONFIG_SYS_DATAFLASH_MMC_PIO, AT91C_BASE_PIOB->PIO_PER);
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/* Configure in output */
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writel(CONFIG_SYS_DATAFLASH_MMC_PIO, AT91C_BASE_PIOB->PIO_OER);
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/* Clear Output */
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writel(CONFIG_SYS_DATAFLASH_MMC_PIO, AT91C_BASE_PIOB->PIO_CODR);
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}
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@ -1,38 +0,0 @@
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/*
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#include <common.h>
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#include <config.h>
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#include <asm/hardware.h>
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#include <dataflash.h>
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AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS];
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struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
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{CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */
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{CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3, 3}
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};
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/*define the area offsets*/
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dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
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{0x00000000, 0x000041FF, FLAG_PROTECT_SET, 0, "Bootstrap"},
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{0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
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{0x00008400, 0x00041FFF, FLAG_PROTECT_SET, 0, "U-Boot"},
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{0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"},
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{0x00252000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "FS"},
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};
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@ -344,7 +344,7 @@ modnet50 arm arm720t
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lpc2292sodimm arm arm720t - - lpc2292
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eb_cpux9k2 arm arm920t - BuS at91
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at91rm9200dk arm arm920t - atmel at91rm9200
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at91rm9200ek arm arm920t - atmel at91rm9200
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at91rm9200ek arm arm920t - atmel at91
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sbc2410x arm arm920t - - s3c24x0
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smdk2400 arm arm920t - samsung s3c24x0
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smdk2410 arm arm920t - samsung s3c24x0
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@ -1,4 +1,8 @@
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/*
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* Copyright (C) 2010 Andreas Bießmann <biessmann.devel@googlemail.com>
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*
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* based on previous work by
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*
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* Ulf Samuelsson <ulf@atmel.com>
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* Rick Bronson <rick@efn.org>
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*
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@ -23,40 +27,52 @@
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#ifndef __AT91RM9200EK_CONFIG_H__
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#define __AT91RM9200EK_CONFIG_H__
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#define CONFIG_AT91_LEGACY
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#include <asm/sizes.h>
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/* ARM asynchronous clock */
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/*
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* from 18.432 MHz crystal
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* (18432000 / 4 * 39)
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* AT91C_XTAL_CLOCK is the frequency of external xtal in hertz
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* AT91C_MAIN_CLOCK is the frequency of PLLA output
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* AT91C_MASTER_CLOCK is the peripherial clock
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* CONFIG_SYS_HZ_CLOCK is the value for CCR in tc0 (divider 2 is implicitely
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* set in arch/arm/cpu/arm920t/at91/timer.c)
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* CONFIG_SYS_HZ is the tick rate for timer tc0
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*/
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#define AT91C_MAIN_CLOCK 179712000
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#define AT91C_XTAL_CLOCK 18432000
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#define AT91C_MAIN_CLOCK ((AT91C_XTAL_CLOCK / 4) * 39)
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#define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK / 3 )
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#define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK / 2)
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#define CONFIG_SYS_HZ 1000
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/* CPU configuration */
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#define CONFIG_ARM920T
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#define CONFIG_AT91RM9200
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#define CONFIG_AT91RM9200EK
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#define CONFIG_CPUAT91
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#define USE_920T_MMU
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#define CONFIG_CMDLINE_TAG
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_INITRD_TAG
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||||
|
||||
/*
|
||||
* peripheral clock
|
||||
* (AT91C_MASTER_CLOCK / 3)
|
||||
* Memory Configuration
|
||||
*/
|
||||
#define AT91C_MASTER_CLOCK 59904000
|
||||
#define CONFIG_NR_DRAM_BANKS 1
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x20000000
|
||||
#define CONFIG_SYS_SDRAM_SIZE SZ_32M
|
||||
|
||||
#define AT91_SLOW_CLOCK 32768 /* slow clock */
|
||||
|
||||
#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
|
||||
#define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */
|
||||
#define CONFIG_AT91RM9200EK 1 /* on an AT91RM9200EK Board */
|
||||
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
|
||||
#define USE_920T_MMU 1
|
||||
|
||||
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
|
||||
#define CONFIG_SETUP_MEMORY_TAGS 1
|
||||
#define CONFIG_INITRD_TAG 1
|
||||
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
|
||||
#define CONFIG_SYS_MEMTEST_END \
|
||||
(CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE - SZ_256K)
|
||||
|
||||
/*
|
||||
* LowLevel Init
|
||||
*/
|
||||
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
||||
#define CONFIG_SYS_USE_MAIN_OSCILLATOR 1
|
||||
#define CONFIG_SYS_USE_MAIN_OSCILLATOR
|
||||
/* flash */
|
||||
#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
|
||||
#define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
|
||||
|
|
@ -73,50 +89,26 @@
|
|||
#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000
|
||||
#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */
|
||||
#define CONFIG_SYS_SDRC_CR_VAL 0x2188c155 /* set up the CONFIG_SYS_SDRAM */
|
||||
#define CONFIG_SYS_SDRAM 0x20000000 /* address of the CONFIG_SYS_SDRAM */
|
||||
#define CONFIG_SYS_SDRAM1 0x20000080 /* address of the CONFIG_SYS_SDRAM */
|
||||
#define CONFIG_SYS_SDRAM CONFIG_SYS_SDRAM_BASE /* address of the SDRAM */
|
||||
#define CONFIG_SYS_SDRAM1 CONFIG_SYS_SDRAM_BASE /* address of the SDRAM */
|
||||
#define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to CONFIG_SYS_SDRAM */
|
||||
#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */
|
||||
#define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */
|
||||
#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
|
||||
#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */
|
||||
#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
|
||||
#else
|
||||
#define CONFIG_SKIP_RELOCATE_UBOOT
|
||||
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
|
||||
|
||||
/* hardcode so no __divsi3 : AT91C_MASTER_CLOCK / baudrate / 16 */
|
||||
#define CONFIG_SYS_AT91C_BRGR_DIVISOR 33
|
||||
|
||||
/*
|
||||
* Memory Configuration
|
||||
*/
|
||||
#define CONFIG_NR_DRAM_BANKS 1
|
||||
#define PHYS_SDRAM 0x20000000
|
||||
#define PHYS_SDRAM_SIZE 0x02000000 /* 32 megs */
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
|
||||
#define CONFIG_SYS_MEMTEST_END \
|
||||
(CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 262144)
|
||||
|
||||
/*
|
||||
* Hardware drivers
|
||||
*/
|
||||
|
||||
/*
|
||||
* UART Configuration
|
||||
*
|
||||
* define one of these to choose the DBGU,
|
||||
* USART0 or USART1 as console
|
||||
* Choose a USART for serial console
|
||||
* CONFIG_DBGU is DBGU unit on J10
|
||||
* CONFIG_USART1 is USART1 on J14
|
||||
*/
|
||||
#define CONFIG_AT91RM9200_USART
|
||||
#define CONFIG_DBGU
|
||||
#undef CONFIG_USART0
|
||||
#undef CONFIG_USART1
|
||||
/* don't include RTS/CTS flow control support */
|
||||
#undef CONFIG_HWFLOW
|
||||
/* disable modem initialization stuff */
|
||||
#undef CONFIG_MODEM_SUPPORT
|
||||
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
|
@ -130,156 +122,60 @@
|
|||
#define CONFIG_CMD_FAT
|
||||
#define CONFIG_CMD_MII
|
||||
#define CONFIG_CMD_PING
|
||||
|
||||
#undef CONFIG_CMD_BDI
|
||||
#undef CONFIG_CMD_IMI
|
||||
#undef CONFIG_CMD_FPGA
|
||||
#undef CONFIG_CMD_MISC
|
||||
#undef CONFIG_CMD_LOADS
|
||||
|
||||
#include <asm/arch/AT91RM9200.h> /* needed for port definitions */
|
||||
/* Options for MMC/SD Card */
|
||||
#define CONFIG_DOS_PARTITION 1
|
||||
#undef CONFIG_MMC
|
||||
#define CONFIG_SYS_MMC_BASE 0xFFFB4000
|
||||
#define CONFIG_SYS_MMC_BLOCKSIZE 512
|
||||
|
||||
/*
|
||||
* Network Driver Setting
|
||||
*/
|
||||
#define CONFIG_NET_MULTI 1
|
||||
#ifdef CONFIG_NET_MULTI
|
||||
#define CONFIG_DRIVER_AT91EMAC 1
|
||||
#define CONFIG_SYS_RX_ETH_BUFFER 8
|
||||
#else
|
||||
#define CONFIG_DRIVER_ETHER 1
|
||||
#endif
|
||||
#define CONFIG_NET_RETRY_COUNT 20
|
||||
#define CONFIG_AT91C_USE_RMII
|
||||
|
||||
/*
|
||||
* AC Characteristics
|
||||
* DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns
|
||||
*/
|
||||
#define DATAFLASH_TCSS (0xC << 16)
|
||||
#define DATAFLASH_TCHS (0x1 << 24)
|
||||
|
||||
#if defined(CONFIG_HAS_DATAFLASH)
|
||||
#define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ)
|
||||
#define CONFIG_SYS_MAX_DATAFLASH_BANKS 2
|
||||
#define CONFIG_SYS_MAX_DATAFLASH_PAGES 16384
|
||||
/* Logical adress for CS0 */
|
||||
#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000
|
||||
/* Logical adress for CS3 */
|
||||
#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000
|
||||
#define CONFIG_SYS_SUPPORT_BLOCK_ERASE 1
|
||||
#define CONFIG_SYS_DATAFLASH_MMC_PIO AT91C_PIO_PB22
|
||||
#endif
|
||||
#define CONFIG_NET_MULTI
|
||||
#define CONFIG_DRIVER_AT91EMAC
|
||||
#define CONFIG_SYS_RX_ETH_BUFFER 16
|
||||
#define CONFIG_RMII
|
||||
#define CONFIG_MII
|
||||
|
||||
/*
|
||||
* NOR Flash
|
||||
*/
|
||||
#define CONFIG_SYS_FLASH_BASE 0x10000000
|
||||
#define PHYS_FLASH_SIZE 0x800000 /* 8MB */
|
||||
#define CONFIG_SYS_FLASH_CFI 1
|
||||
#define CONFIG_FLASH_CFI_DRIVER 1
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 256
|
||||
#define CONFIG_FLASH_CFI_DRIVER
|
||||
#define CONFIG_SYS_FLASH_CFI
|
||||
#define CONFIG_SYS_FLASH_BASE 0x10000000
|
||||
#define PHYS_FLASH_1 CONFIG_SYS_FLASH_BASE
|
||||
#define PHYS_FLASH_SIZE SZ_8M
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 256
|
||||
#define CONFIG_SYS_FLASH_PROTECTION
|
||||
|
||||
/*
|
||||
* Environment Settings
|
||||
*/
|
||||
#ifdef CONFIG_ENV_IS_IN_DATAFLASH
|
||||
/*
|
||||
* Datasflash Environment Settings
|
||||
*/
|
||||
#define CONFIG_ENV_OFFSET 0x4200
|
||||
#define CONFIG_ENV_ADDR \
|
||||
(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
|
||||
/* 8 * 1056 really , but start.s is not OK with this*/
|
||||
#define CONFIG_ENV_SIZE 0x2000
|
||||
#define CONFIG_ENV_IS_IN_FLASH
|
||||
|
||||
#else
|
||||
/*
|
||||
* NOR Flash Environment Settings
|
||||
*/
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1
|
||||
|
||||
#ifdef CONFIG_SKIP_LOWLEVEL_INIT
|
||||
/*
|
||||
* between boot.bin and u-boot.bin.gz
|
||||
*/
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0xe000)
|
||||
#define CONFIG_ENV_SIZE 0x10000 /* sectors are 64K here */
|
||||
#else
|
||||
/*
|
||||
* after u-boot.bin
|
||||
*/
|
||||
#define CONFIG_ENV_ADDR \
|
||||
(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
|
||||
#define CONFIG_ENV_SIZE 0x10000 /* sectors are 64K here */
|
||||
#define CONFIG_ENV_SIZE SZ_64K /* sectors are 64K here */
|
||||
/* The following #defines are needed to get flash environment right */
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
|
||||
#define CONFIG_SYS_MONITOR_LEN \
|
||||
(CONFIG_SYS_BOOT_SIZE + CONFIG_SYS_U_BOOT_SIZE)
|
||||
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
|
||||
|
||||
#endif /* CONFIG_ENV_IS_IN_DATAFLASH */
|
||||
#define CONFIG_SYS_MONITOR_LEN SZ_256K
|
||||
|
||||
/*
|
||||
* Boot option
|
||||
*/
|
||||
#define CONFIG_BOOTDELAY 3
|
||||
|
||||
#ifdef CONFIG_SKIP_LOWLEVEL_INIT
|
||||
/* boot.bin, env, u-boot.bin.gz */
|
||||
#define CONFIG_SYS_BOOT_SIZE 0x6000 /* 24 KBytes */
|
||||
#define CONFIG_SYS_U_BOOT_BASE (CONFIG_SYS_FLASH_BASE + 0x10000)
|
||||
#define CONFIG_SYS_U_BOOT_SIZE 0x10000 /* 64 KBytes */
|
||||
#else
|
||||
/* u-boot.bin */
|
||||
#define CONFIG_SYS_BOOT_SIZE 0x0 /* 0 KBytes */
|
||||
#define CONFIG_SYS_U_BOOT_BASE CONFIG_SYS_FLASH_BASE
|
||||
#define CONFIG_SYS_U_BOOT_SIZE 0x40000 /* 128 KBytes */
|
||||
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */
|
||||
#define CONFIG_ENV_OVERWRITE 1
|
||||
|
||||
/*
|
||||
* USB Config
|
||||
*/
|
||||
#define CONFIG_CMD_USB
|
||||
#define CONFIG_USB_OHCI_NEW 1
|
||||
#define CONFIG_USB_KEYBOARD 1
|
||||
#define CONFIG_USB_STORAGE 1
|
||||
#define CONFIG_DOS_PARTITION 1
|
||||
|
||||
#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
|
||||
#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
|
||||
#define CONFIG_SYS_USB_OHCI_REGS_BASE AT91_USB_HOST_BASE
|
||||
#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91rm9200"
|
||||
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
|
||||
|
||||
/*
|
||||
* I2C
|
||||
*/
|
||||
#define CONFIG_HARD_I2C
|
||||
|
||||
#ifdef CONFIG_HARD_I2C
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_SYS_I2C_SPEED 0 /* not used */
|
||||
#define CONFIG_SYS_I2C_SLAVE 0 /* not used */
|
||||
#endif
|
||||
/* default load address */
|
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_16M
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
/*
|
||||
* Shell Settings
|
||||
*/
|
||||
#define CONFIG_CMDLINE_EDITING 1
|
||||
#define CONFIG_SYS_LONGHELP 1
|
||||
#define CONFIG_AUTO_COMPLETE 1
|
||||
#define CONFIG_SYS_HUSH_PARSER 1
|
||||
#define CONFIG_CMDLINE_EDITING
|
||||
#define CONFIG_SYS_LONGHELP
|
||||
#define CONFIG_AUTO_COMPLETE
|
||||
#define CONFIG_SYS_HUSH_PARSER
|
||||
#define CONFIG_SYS_PROMPT "U-Boot> "
|
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
|
|
@ -288,41 +184,18 @@
|
|||
#define CONFIG_SYS_PBSIZE \
|
||||
(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
/*-----------------------------------------------------------------------
|
||||
* Board specific extension for bd_info
|
||||
*
|
||||
* This structure is embedded in the global bd_info (bd_t) structure
|
||||
* and can be used by the board specific code (eg board/...)
|
||||
*/
|
||||
|
||||
struct bd_info_ext {
|
||||
/* helper variable for board environment handling
|
||||
*
|
||||
* env_crc_valid == 0 => uninitialised
|
||||
* env_crc_valid > 0 => environment crc in flash is valid
|
||||
* env_crc_valid < 0 => environment crc in flash is invalid
|
||||
*/
|
||||
int env_crc_valid;
|
||||
};
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_HZ 1000
|
||||
/*
|
||||
* AT91C_TC0_CMR is implicitly set to
|
||||
* AT91C_TC_TIMER_DIV1_CLOCK
|
||||
*/
|
||||
#define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK / 2)
|
||||
|
||||
/*
|
||||
* Size of malloc() pool
|
||||
*/
|
||||
#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024 \
|
||||
, 0x1000)
|
||||
#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + SZ_128K, \
|
||||
SZ_4K)
|
||||
/* size in bytes reserved for initial data */
|
||||
#define CONFIG_SYS_GBL_DATA_SIZE 128
|
||||
|
||||
#define CONFIG_STACKSIZE (32 * 1024) /* regular stack */
|
||||
#define CONFIG_STACKSIZE_IRQ (4 * 1024) /* Unsure if to big or to small*/
|
||||
#define CONFIG_STACKSIZE_FIQ (4 * 1024) /* Unsure if to big or to small*/
|
||||
#endif
|
||||
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_4K \
|
||||
- CONFIG_SYS_GBL_DATA_SIZE)
|
||||
|
||||
#define CONFIG_STACKSIZE SZ_32K /* regular stack */
|
||||
#define CONFIG_STACKSIZE_IRQ SZ_4K /* Unsure if to big or to small*/
|
||||
#define CONFIG_STACKSIZE_FIQ SZ_4K /* Unsure if to big or to small*/
|
||||
#endif /* __AT91RM9200EK_CONFIG_H__ */
|
||||
|
|
|
|||
Loading…
Reference in New Issue