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Merge branch 'master' of /home/stefan/git/u-boot/u-boot into next

This commit is contained in:
Stefan Roese 2008-08-12 20:39:27 +02:00
parent 1c7015100a cd82919e6c
commit 9939ffd5fb
81 changed files with 3375 additions and 804 deletions
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@ -1,3 +1,579 @@
commit 17e900b8c0f38d922da47073246219dce2a847f2
Author: Wolfgang Denk <wd@denx.de>
Date: Tue Aug 12 14:54:04 2008 +0200
MVBC_P: fix compile problem
Signed-off-by: Wolfgang Denk <wd@denx.de>
commit 52b047ae48219b59bebe37ba743ab103fd4f8316
Author: Wolfgang Denk <wd@denx.de>
Date: Tue Aug 12 12:10:11 2008 +0200
MPC8272ADS: fix build error: 'bd_t' has no member named 'pci_clk'
Signed-off-by: Wolfgang Denk <wd@denx.de>
commit c9c101c660b3d1995045c61c7c6041f52b6cf335
Author: Wolfgang Denk <wd@denx.de>
Date: Tue Aug 12 00:36:53 2008 +0200
ads5121: fix compiler warnings (unused variables)
Signed-off-by: Wolfgang Denk <wd@denx.de>
commit 902ca09246039964d59bbcb519b1e1b5aed01308
Author: Kumar Gala <galak@kernel.crashing.org>
Date: Mon Aug 11 11:29:28 2008 -0500
85xx: Rename CONFIG_NR_CPUS to CONFIG_NUM_CPUS
Use CONFIG_NUM_CPUS to match existing define used by 86xx.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Jon Loeliger <jdl@freescale.com>
commit 3216ca9692ff80d7c638723ef448f3d36301d9e7
Author: Kumar Gala <galak@kernel.crashing.org>
Date: Mon Aug 11 09:20:53 2008 -0500
Fix fallout from autostart revert
The autostart revert caused a bit of duplicated code as well as
code that was using images->autostart that needs to get removed so
we can build again.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
commit 3cf8a234b8e8c02e4da1f23566043bc288b05220
Author: Kumar Gala <galak@kernel.crashing.org>
Date: Mon Aug 11 09:16:25 2008 -0500
Fix compile error related to r8a66597-hcd & usb
When building the 8544DS board we get this error:
In file included from r8a66597-hcd.c:22:
u-boot/include/usb.h:190:2: error: #error USB Lowlevel not defined
make[1]: *** [r8a66597-hcd.o] Error 1
The cleanest fix is to only build r8a66597-hcd.c if CONFIG_USB_R8A66597_HCD
is set.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
commit 2d0daa03612338a813e3c9d22680e54eabfea378
Author: Becky Bruce <becky.bruce@freescale.com>
Date: Mon Aug 4 14:02:26 2008 -0500
POWERPC 86xx: Move BAT setup code to C
This is needed because we will be possibly be locating
devices at physical addresses above 32bits, and the asm
preprocessing does not appear to deal with ULL constants
properly. We now call write_bat in lib_ppc/bat_rw.c.
Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
Acked-by: Jon Loeliger <jdl@freescale.com>
commit 9de67149db576c91b9c2a0a182652331e7e44211
Author: Becky Bruce <becky.bruce@freescale.com>
Date: Mon Aug 4 14:01:53 2008 -0500
POWERPC: Add synchronization to write_bat in lib_ppc/bat_rw.c
Perform sync/isync as required by the architecture.
Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
Acked-by: Jon Loeliger <jdl@freescale.com>
commit 23f935c073e7578c6066804fd2f9ee116cae6ffe
Author: Becky Bruce <becky.bruce@freescale.com>
Date: Mon Aug 4 14:01:16 2008 -0500
POWERPC: 86xx - add missing CONFIG_HIGH_BATS to sbc8641d config
Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
Acked-by: Jon Loeliger <jdl@freescale.com>
commit 5276a3584d26a9533404f0ec00c3b61cf9a97939
Author: Magnus Lilja <lilja.magnus@gmail.com>
Date: Sun Aug 3 21:44:10 2008 +0200
i.MX31: Fix mx31_gpio_mux() function and MUX_-macros.
Correct the mx31_gpio_mux() function to allow changing all i.MX31 IOMUX
contacts instead of only the first 256 ones as is the case prior to
this patch.
Add missing MUX_* macros and update board files to use the new macros.
Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
commit b6b183c5b2fffd4c456b7e3fcb064cceb47fe7ac
Author: Magnus Lilja <lilja.magnus@gmail.com>
Date: Sun Aug 3 21:43:37 2008 +0200
i.MX31: Fix IOMUX related typos
Correct the names of some IOMUX macros.
Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
commit 4d57b0fb2927d4f50d834884b4ec4a7ca01708b0
Author: Steve Sakoman <steve@sakoman.com>
Date: Mon Aug 11 20:26:16 2008 +0200
OneNAND: Remove unused parameters to onenand_verify_page
The block and page parameters of onenand_verify_page() are not used. This causes a compiler error when CONFIG_MTD_ONENAND_VERIFY_WRITE is enabled.
Signed-off-by: Steve Sakoman <steve@sakoman.com>
Signed-off-by: Dirk Behme <dirk.behme@gmail.com>
commit e84d568fa2a9f4ce7888141e71676368ef6b3f25
Author: Anatolij Gustschin <agust@denx.de>
Date: Fri Aug 8 18:00:40 2008 +0200
video: fix bug in cfb_console code
FILL_15BIT_555RGB macro extension for pixel swapping
by commit bed53753dd1d7e6bcbea4339be0fb7760214cc35
introduced a bug in cfb_console:
Bitmaps with odd-numbered width won't be rendered
correctly and even U-Boot crashes are observed on
some platforms while repeated rendering of such
bitmaps with "bmp display". Also if a bitmap is
rendered to an odd-numbered x starting position,
the same problem occurs. This patch is an attempt
to fix it.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
commit d9015f6a50d7258125349ef5c2af836458a0029a
Author: Anatolij Gustschin <agust@denx.de>
Date: Fri Aug 8 18:00:39 2008 +0200
video: fix bug in logo_plot
If logo_plot() should ever be called with x starting
position other than zero and for pixel depths greater
than 8bpp, logo colors distortion will be observed.
This patch fixes the issue.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
commit 406819ae94f79f5b59e01d163380ca7d83709251
Author: Wolfgang Denk <wd@denx.de>
Date: Mon Aug 11 00:17:52 2008 +0200
MAINTAINERS: sort entries
Signed-off-by: Wolfgang Denk <wd@denx.de>
commit cfc442d7913d4d1c3a9bf494f90c012c2f8c3bdc
Author: Roy Zang <tie-fei.zang@freescale.com>
Date: Thu Aug 7 18:19:28 2008 +0800
Add mpc7448hpc2 maintainer information
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
commit a9fe0c3e7ca48afa50d6a0db99fa91e7282d73d8
Author: Gururaja Hebbar K R <gururajakr@sanyo.co.in>
Date: Thu Aug 7 13:13:27 2008 +0530
common/cmd_load.c - Minor code & Coding Style cleanup
- os_data_header Variable is a carry over feature
& unused. So removed all instance of this variable
- Minor Code Style Update
Signed-off-by: Gururaja Hebbar <gururajakr@sanyo.co.in>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
commit 0d28f34bbe56d0971bd603789dcc6fe7adf11f14
Author: Magnus Lilja <lilja.magnus@gmail.com>
Date: Wed Aug 6 19:32:33 2008 +0200
Update the U-Boot wiki URL.
Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
commit aa5ffa16d7e4c461b7b77bf8e79d2ef5638cf754
Author: dirk.behme@googlemail.com <dirk.behme@googlemail.com>
Date: Sun Aug 10 17:56:36 2008 +0200
OneNAND: Remove base address offset usage
While locally preparing some U-Boot patches for ARM based OMAP3 boards, some
using OneNAND and some using NAND, we found some differences in OneNAND and
NAND command address handling.
As this might confuse users (it already confused us), we like to align OneNAND
and NAND address handling.
The issue is that cmd_onenand.c subtracts the onenand base address from the
addresses you type into the u-boot command line so, unlike nand, you can't
use addresses relative to the start of the onenand part e.g. this won't work:
onenand read 82000000 280000 400000
you have to use:
onenand read 82000000 20280000 400000
Looking at recent git, the only board currently using OneNAND is Apollon, and
for this the OneNAND base address is 0 (apollon.h)
#define CFG_ONENAND_BASE 0x00000000
so patch below won't break any existing boards and will align OneNAND and NAND
handling on boards where OneNAND base address is != 0.
Signed-off-by: Steve Sakoman <sakoman@gmail.com>
Signed-off-by: Manikandan Pillai <mani.pillai@ti.com>
Signed-off-by: Dirk Behme <dirk.behme@gmail.com>
commit c11528083ef6e55e76df742228c26e39d151813d
Author: Kumar Gala <galak@kernel.crashing.org>
Date: Thu Aug 7 09:28:20 2008 -0500
mpc85xx: workaround old binutils bug
The recent change to move the .bss outside of the image gives older
binutils (ld from eldk4.1/binutils-2.16) some headache:
ppc_85xx-ld: u-boot: Not enough room for program headers (allocated 3, need 4)
ppc_85xx-ld: final link failed: Bad value
We workaround it by being explicit about the program headers and not
assigning the .bss to a program header.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
commit 0bf202ec586d4466c900e987720fa635c594d689
Author: Wolfgang Denk <wd@denx.de>
Date: Sun Aug 10 01:26:26 2008 +0200
Revert "[new uImage] Add autostart flag to bootm_headers structure"
This reverts commit f5614e7926863bf0225ec860d9b319741a9c4004.
The commit was based on a misunderstanding of the (documented)
meaning of the 'autostart' environment variable. It might cause
boards to hang if 'autostart' was used, with the potential to brick
them. Go back to the documented behaviour.
Conflicts:
common/cmd_bootm.c
common/image.c
include/image.h
Signed-off-by: Wolfgang Denk <wd@denx.de>
commit 29f8f58ff40c67f7f2e11afd1715173094e52ac2
Author: Wolfgang Denk <wd@denx.de>
Date: Sat Aug 9 23:17:32 2008 +0200
TQM8xx{L,M}: try to normalize config files for TQM8xx? based board
- enable CFI driver where this was forgotten
- enable mtdparts support
- adjust default environment
etc.
Signed-off-by: Wolfgang Denk <wd@denx.de>
commit 41266c9b5a5f873df3ec891bb0907616958b5602
Author: Peter Tyser <ptyser@xes-inc.com>
Date: Tue Aug 5 10:51:57 2008 -0500
FIT: Fix handling of images without ramdisks
boot_get_ramdisk() should not treat the case when a FIT image does
not contain a ramdisk as an error.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Acked-by: Michal Simek <monstr@monstr.eu>
commit f77d92a3f56d88e63cc02226a1204b3bdbac6961
Author: Sergey Lapin <slapin@ossfans.org>
Date: Sat Aug 9 01:39:09 2008 +0400
DataFlash: AT45DB021 fix and AT45DB081 support
Fix for page size of AT45DB021. Also adding bigger AT45DB081
which comes with some newer boards.
Signed-off-by: Sergey Lapin <slapin@ossfans.org>
commit ba9324451b662dd393afa53e5cc36fc5d3d10966
Author: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
Date: Fri Aug 8 16:30:23 2008 +0900
sh: Update sh7763rdp config
Add sh_eth support to sh7763rdp.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
commit 21f971ec265f6042ec21636d55d06a6bc0751077
Author: Wolfgang Denk <wd@denx.de>
Date: Mon Jul 7 01:22:29 2008 +0200
TQM823L: re-enable logo support; update LCD_INFO text
Signed-off-by: Wolfgang Denk <wd@denx.de>
commit 3b8d17f0f082073346c0df017c9dfd6acdb40d6d
Author: Wolfgang Denk <wd@denx.de>
Date: Fri Aug 8 16:41:56 2008 +0200
TQM8xxL: fix support for second flash bank
When switching the TQM8xxL modules to use the CFI flash driver,
support for the second flash bank was broken because the CFI driver
did not support dynamically sized banks. This gets fixed now.
Signed-off-by: Wolfgang Denk <wd@denx.de>
commit 2a112b234d879f6390503a5f4e38246acce9d0b0
Author: Wolfgang Denk <wd@denx.de>
Date: Fri Aug 8 16:39:54 2008 +0200
CFI: allow for dynamically determined flash sizes and addresses
The CFI driver allowed only for static initializers in the
CFG_FLASH_BANKS_LIST definition, i. e. it did not allow to map
several flash banks contiguously if the bank sizes were not known in
advance, which kind of violates U-Boot's design philosophy.
(will be used for example by the TQM8xxL boards)
Signed-off-by: Wolfgang Denk <wd@denx.de>
commit d9d78ee46d9a396d0a81d00c2b003a9bd32c2e61
Author: Ben Warren <biggerbadderben@gmail.com>
Date: Thu Aug 7 23:26:35 2008 -0700
QE UEC: Fix compiler warnings
Moved static functions earlier in file so forward declarations are not needed.
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
commit d5d28fe4aad5f4535400647a5617c11039506467
Author: David Saada <David.Saada@ecitele.com>
Date: Mon Mar 31 02:37:38 2008 -0700
QE UEC: Add MII Commands
Add MII commands to the UEC driver. Note that once a UEC device is selected,
any device on its MDIO bus can be addressed.
Signed-off-by: David Saada <david.saada@ecitele.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
commit fd0f2f3796ff2a7a32d35deb1b7996e485849df7
Author: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
Date: Wed Jul 9 21:07:38 2008 +0900
usb: add support for R8A66597 usb controller
add support for Renesas R8A66597 usb controller.
This patch supports USB Host mode.
Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
Signed-off-by: Markus Klotzbuecher <mk@denx.de>
commit 1d10dcd041aaeae9fd7c821005692898a0303382
Author: Hunter, Jon <jon-hunter@ti.com>
Date: Sat Jul 26 18:59:16 2008 -0500
Add support for OMAP5912 and OMAP16xx to usbdcore_omap1510.c
Add support to drivers/usb/usbdcore_omap1510.c for OMAP5912 and OMAP16xx devices.
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Signed-off-by: Markus Klotzbuecher <mk@denx.de>
commit eab1007334b93a6209f1ec33615e26ef5311ede7
Author: Steven A. Falco <sfalco@harris.com>
Date: Wed Aug 6 15:42:52 2008 -0400
ppc4xx: Sequoia has two UARTs in "4-pin" mode. Configure the GPIOs as per schematic.
The Sequoia board has two UARTs in "4-pin" mode. This patch modifies the GPIO
configuration to match the schematic, and also sets the SDR0_PFC1 register to
select the corresponding mode for the UARTs.
Signed-off-by: Steven A. Falco <sfalco@harris.com>
Signed-off-by: Stefan Roese <sr@denx.de>
commit 6689484ccd43189322aaa5a1c6cd02cdd511ad7d
Author: Kenneth Johansson <kenneth@southpole.se>
Date: Tue Jul 15 12:13:38 2008 +0200
mpc5121: Move iopin features from board specific to common files.
And in the process eliminate some duplicate register defines.
Signed-off-by: Kenneth Johansson <kenneth@southpole.se>
commit ef11df6b66ecf5797e94ba322254b8fb7a4e2e12
Author: John Rigby <jrigby@freescale.com>
Date: Tue Aug 5 17:38:57 2008 -0600
mpc5121: squash some fdt fixup errors
On ADS5121 when booting linux the following errors are seen:
Unable to update property /soc5121@80000000:bus-frequency, err=FDT_ERR_NOTFOUND
Unable to update property /soc5121@80000000/ethernet@2800:local-mac-address, err=FDT_ERR_NOTFOUND
Unable to update property /soc5121@80000000/ethernet@2800:address, err=FDT_ERR_NOTFOUND
This is caused by ft_cpu_setup trying to deal with
both old and new soc node naming. This patch
fixes this by being smarter about what to
fixup.
Also do soc node fixups by compatible instead of by path.
A new board config called OF_SOC_COMPAT defined
to be "fsl,mpc5121-immr" replaces the old
OF_SOC node path that was defined to be "soc@80000000".
Old device trees still work, but the compatiblity
is conditional on CONFIG_OF_SUPPORT_OLD_DEVICE_TREES
which is on by default in include/configs/ads5121.h.
Signed-off-by: John Rigby <jrigby@freescale.com>
commit 81091f58f0c58ecd26c5b05de2ae20ca6cdb521c
Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Date: Sat Aug 2 23:48:30 2008 +0200
drivers/serial: Move conditional compilation to Makefile for CONFIG_* macros
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
commit 4cd7e6528f61ec669755c3754bb4f9779874fab3
Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Date: Sat Aug 2 23:48:32 2008 +0200
nios2/sysid: fix printf warning
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
commit 66da6fa0e35e7ee56628c85981709afe7180fc8e
Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Date: Sat Aug 2 23:48:33 2008 +0200
Fix remaining build issues with MPC8xx FADS boards.
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
commit 81d3f1fdddafd1eb53bbca8739f488d417eb3dd2
Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Date: Sat Aug 2 23:48:31 2008 +0200
nios2: fix phys_addr_t and phys_size_t support
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
commit 5fa62000db6d0b46ecdeadbeb50faf5197db49ef
Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Date: Sat Aug 2 23:48:34 2008 +0200
mvbc_p: Fix problem with '#if (CONFIG_CMD_KGDB)'
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
commit 1464eff77e7fdaed609ecf263a2423c9dcf96b1f
Author: Mark Jackson <mpfj@mimc.co.uk>
Date: Fri Aug 1 09:48:29 2008 +0100
Fix bitmap display for atmel lcd controller
The current lcd_display_bitmap() function does not work properly
for the Atmel LCD controller.
2 fixes need to be done:-
(a) when setting the colour map, use the lcd_setcolreg() function
as provided by the Atmel driver
(b) the data is never actually written to the lcd framebuffer !!
Signed-off-by: Mark Jackson <mpfj@mimc.co.uk>
commit 2a433c66b1e2770349fe4911be23c375f053ebd8
Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Date: Fri Aug 1 08:40:34 2008 +0200
qemu_mips: update README to follow qemu update about default machine
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
commit ac169d645f5f0e0b9a232563099209e92a355d8e
Author: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
Date: Thu Jul 31 19:53:21 2008 -0500
ColdFire: Fix compilation issue caused by a missing function
Implement usec2ticks() which is used by fsl_i2c.c in
lib_m68k/time.c
Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
commit 01ae85b58b51d2fb1fac5b93095f6042cf48ae7b
Author: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
Date: Thu Jul 31 19:53:06 2008 -0500
Fix compilation error for TASREG
TASREG is ColdFire platform, the include ppc4xx.h in
board/esd/common/flash.c causes conflict.
Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
commit 35d3bd3cc35c508a6823dac77e0fd126808e4fc7
Author: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
Date: Thu Jul 31 19:52:36 2008 -0500
Fix compilation error for MCF5275
Rename OBJ to COBJ in board/platform/Makefile
Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
commit 5c40548f01218360a1f1395198c50ff45f3035b5
Author: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
Date: Thu Jul 31 19:52:28 2008 -0500
Fix compile error caused by incorrect function return type
Rename int mii_init(void) to void mii_init(void) for idmr
ColdFire platform
Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
commit a58c78067c928976c082c758d3987e89ead5b191
Author: Wolfgang Denk <wd@denx.de>
Date: Fri Aug 1 12:06:22 2008 +0200
Fix build issues with MPC8xx FADS boards.
Signed-off-by: Wolfgang Denk <wd@denx.de>
commit 4b50cd12a3b3c644153c4cf393f4a4c12289e5aa
Author: Wolfgang Denk <wd@denx.de>
Date: Thu Jul 31 17:54:03 2008 +0200
Prepare v1.3.4-rc2: update CHANGELOG
Signed-off-by: Wolfgang Denk <wd@denx.de>
commit a48311557db6e7e9473a6163b44bb1e6c6ed64c4
Author: Mark Jackson <mpfj@mimc.co.uk>
Date: Thu Jul 31 16:09:00 2008 +0100
@ -5117,6 +5693,18 @@ Date: Mon May 5 14:06:11 2008 +0200
Signed-off-by: Jens Gehrlein <sew_s@tqs.de>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
commit 6324e5bec8825f7fee3026ffbd394454ae8b53fb
Author: Christian Eggers <ceggers@gmx.de>
Date: Wed May 21 21:29:10 2008 +0200
Fix endianess conversion in usb_ohci.c
Sorry, I forgot this line:
Signed-off-by: Christian Eggers <ceggers@gmx.de>
I think this must be swapped (result may be equal).
commit c918261c6d9f265f88baf70f8a73dfe6f0cb9596
Author: Christian Eggers <ceggers@gmx.de>
Date: Wed May 21 22:12:00 2008 +0200

50
MAINTAINERS
View File

@ -239,6 +239,10 @@ The LEOX team <team@leox.org>
ELPT860 MPC860T
Guennadi Liakhovetski <g.liakhovetski@gmx.de>
linkstation MPC8241
Dave Liu <daveliu@freescale.com>
MPC8315ERDB MPC8315
@ -416,14 +420,14 @@ Stephen Williams <steve@icarus.com>
JSE PPC405GPr
Roy Zang <tie-fei.zang@freescale.com>
mpc7448hpc2 MPC7448
John Zhan <zhanz@sinovee.com>
svm_sc8xx MPC8xx
Guennadi Liakhovetski <g.liakhovetski@gmx.de>
linkstation MPC8241
Feng Kan <fkan@amcc.com>
redwood PPC4xx
@ -530,6 +534,10 @@ Rolf Offermanns <rof@sysgo.de>
shannon SA1100
Kyungmin Park <kyungmin.park@samsung.com>
apollon ARM1136EJS
Peter Pearse <peter.pearse@arm.com>
integratorcp All current ARM supplied & supported core modules
-see http://www.arm.com/products/DevTools/Hardware_Platforms.html
@ -559,6 +567,13 @@ Robert Schwebel <r.schwebel@pengutronix.de>
csb226 xscale
innokom xscale
Michael Schwingen <michael@schwingen.org>
actux1 xscale
actux2 xscale
actux3 xscale
actux4 xscale
Andrea Scian <andrea.scian@dave-tech.it>
B2 ARM7TDMI (S3C44B0X)
@ -573,22 +588,11 @@ Richard Woodruff <r-woodruff2@ti.com>
omap2420h4 ARM1136EJS
Kyungmin Park <kyungmin.park@samsung.com>
apollon ARM1136EJS
Alex Züpke <azu@sysgo.de>
lart SA1100
dnp1110 SA1110
Michael Schwingen <michael@schwingen.org>
actux1 xscale
actux2 xscale
actux3 xscale
actux4 xscale
-------------------------------------------------------------------------
Unknown / orphaned boards:
@ -686,6 +690,10 @@ Matthias Fuchs <matthias.fuchs@esd-electronics.com>
TASREG MCF5249
Hayden Fraser <Hayden.Fraser@freescale.com>
M5253EVBE mcf52x2
TsiChung Liew <Tsi-Chung.Liew@freescale.com>
M52277EVB mcf5227x
@ -696,10 +704,6 @@ TsiChung Liew <Tsi-Chung.Liew@freescale.com>
M5475EVB mcf547x_8x
M5485EVB mcf547x_8x
Hayden Fraser <Hayden.Fraser@freescale.com>
M5253EVBE mcf52x2
#########################################################################
# AVR32 Systems: #
# #
@ -723,6 +727,10 @@ Haavard Skinnemoen <hskinnemoen@atmel.com>
# Board CPU #
#########################################################################
Yusuke Goda <goda.yusuke@renesas.com>
MIGO-R SH7722
Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
MS7750SE SH7750
@ -739,10 +747,6 @@ Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
MS7720SE SH7720
Yusuke Goda <goda.yusuke@renesas.com>
MIGO-R SH7722
#########################################################################
# Blackfin Systems: #
# #

2
Makefile
View File

@ -24,7 +24,7 @@
VERSION = 1
PATCHLEVEL = 3
SUBLEVEL = 4
EXTRAVERSION = -rc2
EXTRAVERSION =
U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
VERSION_FILE = $(obj)include/version_autogenerated.h

4
README
View File

@ -98,7 +98,7 @@ Where we come from:
- create ARMBoot project (http://sourceforge.net/projects/armboot)
- add other CPU families (starting with ARM)
- create U-Boot project (http://sourceforge.net/projects/u-boot)
- current project page: see http://www.denx.de/wiki/UBoot
- current project page: see http://www.denx.de/wiki/U-Boot
Names and Spelling:
@ -3903,7 +3903,7 @@ may be rejected, even when they contain important and valuable stuff.
Patches shall be sent to the u-boot-users mailing list.
Please see http://www.denx.de/wiki/UBoot/Patches for details.
Please see http://www.denx.de/wiki/U-Boot/Patches for details.
When you send a patch, please include the following information with
it:

2
board/ads5121/Makefile
View File

@ -27,7 +27,7 @@ $(shell mkdir -p $(OBJTREE)/board/freescale/common)
LIB = $(obj)lib$(BOARD).a
COBJS-y := $(BOARD).o iopin.o
COBJS-y := $(BOARD).o
COBJS-${CONFIG_FSL_DIU_FB} += ads5121_diu.o
COBJS-${CONFIG_FSL_DIU_FB} += ../freescale/common/fsl_diu_fb.o
COBJS-${CONFIG_FSL_DIU_FB} += ../freescale/common/fsl_logo_bmp.o

58
board/ads5121/ads5121.c
View File

@ -23,14 +23,12 @@
#include <common.h>
#include <mpc512x.h>
#include "iopin.h"
#include <asm/bitops.h>
#include <command.h>
#include <fdt_support.h>
#ifdef CONFIG_MISC_INIT_R
#include <i2c.h>
#endif
#include "iopin.h" /* for iopin_initialize() prototype */
/* Clocks in use */
#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \
@ -124,7 +122,7 @@ long int fixed_sdram (void)
u32 i;
/* Initialize IO Control */
im->io_ctrl.regs[MEM_IDX] = IOCTRL_MUX_DDR;
im->io_ctrl.regs[IOCTL_MEM/4] = IOCTRL_MUX_DDR;
/* Initialize DDR Local Window */
im->sysconf.ddrlaw.bar = CFG_DDR_BASE & 0xFFFFF000;
@ -237,6 +235,56 @@ int misc_init_r(void)
return 0;
}
static iopin_t ioregs_init[] = {
/* FUNC1=FEC_RX_DV Sets Next 3 to FEC pads */
{
IOCTL_SPDIF_TXCLK, 3, 0,
IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
},
/* Set highest Slew on 9 PATA pins */
{
IOCTL_PATA_CE1, 9, 1,
IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
},
/* FUNC1=FEC_COL Sets Next 15 to FEC pads */
{
IOCTL_PSC0_0, 15, 0,
IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
},
/* FUNC1=SPDIF_TXCLK */
{
IOCTL_LPC_CS1, 1, 0,
IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
},
/* FUNC2=SPDIF_TX and sets Next pin to SPDIF_RX */
{
IOCTL_I2C1_SCL, 2, 0,
IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
},
/* FUNC2=DIU CLK */
{
IOCTL_PSC6_0, 1, 0,
IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
},
/* FUNC2=DIU_HSYNC */
{
IOCTL_PSC6_1, 1, 0,
IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
},
/* FUNC2=DIUVSYNC Sets Next 26 to DIU Pads */
{
IOCTL_PSC6_4, 26, 0,
IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
}
};
int checkboard (void)
{
@ -246,7 +294,9 @@ int checkboard (void)
printf ("Board: ADS5121 rev. 0x%04x (CPLD rev. 0x%02x)\n",
brd_rev, cpld_rev);
/* initialize function mux & slew rate IO inter alia on IO Pins */
iopin_initialize();
iopin_initialize(ioregs_init, sizeof(ioregs_init) / sizeof(ioregs_init[0]));
return 0;
}

115
board/ads5121/iopin.c
View File

@ -1,115 +0,0 @@
/*
* (C) Copyright 2008
* Martha J Marx, Silicon Turnkey Express, mmarx@silicontkx.com
* mpc512x I/O pin/pad initialization for the ADS5121 board
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <linux/types.h>
#include "iopin.h"
/* IO pin fields */
#define IO_PIN_FMUX(v) ((v) << 7) /* pin function */
#define IO_PIN_HOLD(v) ((v) << 5) /* hold time, pci only */
#define IO_PIN_PUD(v) ((v) << 4) /* if PUE, 0=pull-down, 1=pull-up */
#define IO_PIN_PUE(v) ((v) << 3) /* pull up/down enable */
#define IO_PIN_ST(v) ((v) << 2) /* schmitt trigger */
#define IO_PIN_DS(v) ((v)) /* slew rate */
static struct iopin_t {
int p_offset; /* offset from IOCTL_MEM_OFFSET */
int nr_pins; /* number of pins to set this way */
int bit_or; /* or in the value instead of overwrite */
u_long val; /* value to write or or */
} ioregs_init[] = {
/* FUNC1=FEC_RX_DV Sets Next 3 to FEC pads */
{
IOCTL_SPDIF_TXCLK, 3, 0,
IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
},
/* Set highest Slew on 9 PATA pins */
{
IOCTL_PATA_CE1, 9, 1,
IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
},
/* FUNC1=FEC_COL Sets Next 15 to FEC pads */
{
IOCTL_PSC0_0, 15, 0,
IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
},
/* FUNC1=SPDIF_TXCLK */
{
IOCTL_LPC_CS1, 1, 0,
IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
},
/* FUNC2=SPDIF_TX and sets Next pin to SPDIF_RX */
{
IOCTL_I2C1_SCL, 2, 0,
IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
},
/* FUNC2=DIU CLK */
{
IOCTL_PSC6_0, 1, 0,
IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
},
/* FUNC2=DIU_HSYNC */
{
IOCTL_PSC6_1, 1, 0,
IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
},
/* FUNC2=DIUVSYNC Sets Next 26 to DIU Pads */
{
IOCTL_PSC6_4, 26, 0,
IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
}
};
void iopin_initialize(void)
{
short i, j, n, p;
u_long *reg;
immap_t *im = (immap_t *)CFG_IMMR;
reg = (u_long *)&(im->io_ctrl.regs[0]);
if (sizeof(ioregs_init) == 0)
return;
n = sizeof(ioregs_init) / sizeof(ioregs_init[0]);
for (i = 0; i < n; i++) {
for (p = 0, j = ioregs_init[i].p_offset / sizeof(u_long);
p < ioregs_init[i].nr_pins; p++, j++) {
if (ioregs_init[i].bit_or)
reg[j] |= ioregs_init[i].val;
else
reg[j] = ioregs_init[i].val;
}
}
return;
}

222
board/ads5121/iopin.h
View File

@ -1,222 +0,0 @@
/*
* (C) Copyright 2008
* Martha J Marx, Silicon Turnkey Express, mmarx@silicontkx.com
* mpc512x I/O pin/pad initialization for the ADS5121 board
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#define IOCTL_MEM 0x000
#define IOCTL_GP 0x004
#define IOCTL_LPC_CLK 0x008
#define IOCTL_LPC_OE 0x00C
#define IOCTL_LPC_RWB 0x010
#define IOCTL_LPC_ACK 0x014
#define IOCTL_LPC_CS0 0x018
#define IOCTL_NFC_CE0 0x01C
#define IOCTL_LPC_CS1 0x020
#define IOCTL_LPC_CS2 0x024
#define IOCTL_LPC_AX03 0x028
#define IOCTL_EMB_AX02 0x02C
#define IOCTL_EMB_AX01 0x030
#define IOCTL_EMB_AX00 0x034
#define IOCTL_EMB_AD31 0x038
#define IOCTL_EMB_AD30 0x03C
#define IOCTL_EMB_AD29 0x040
#define IOCTL_EMB_AD28 0x044
#define IOCTL_EMB_AD27 0x048
#define IOCTL_EMB_AD26 0x04C
#define IOCTL_EMB_AD25 0x050
#define IOCTL_EMB_AD24 0x054
#define IOCTL_EMB_AD23 0x058
#define IOCTL_EMB_AD22 0x05C
#define IOCTL_EMB_AD21 0x060
#define IOCTL_EMB_AD20 0x064
#define IOCTL_EMB_AD19 0x068
#define IOCTL_EMB_AD18 0x06C
#define IOCTL_EMB_AD17 0x070
#define IOCTL_EMB_AD16 0x074
#define IOCTL_EMB_AD15 0x078
#define IOCTL_EMB_AD14 0x07C
#define IOCTL_EMB_AD13 0x080
#define IOCTL_EMB_AD12 0x084
#define IOCTL_EMB_AD11 0x088
#define IOCTL_EMB_AD10 0x08C
#define IOCTL_EMB_AD09 0x090
#define IOCTL_EMB_AD08 0x094
#define IOCTL_EMB_AD07 0x098
#define IOCTL_EMB_AD06 0x09C
#define IOCTL_EMB_AD05 0x0A0
#define IOCTL_EMB_AD04 0x0A4
#define IOCTL_EMB_AD03 0x0A8
#define IOCTL_EMB_AD02 0x0AC
#define IOCTL_EMB_AD01 0x0B0
#define IOCTL_EMB_AD00 0x0B4
#define IOCTL_PATA_CE1 0x0B8
#define IOCTL_PATA_CE2 0x0BC
#define IOCTL_PATA_ISOLATE 0x0C0
#define IOCTL_PATA_IOR 0x0C4
#define IOCTL_PATA_IOW 0x0C8
#define IOCTL_PATA_IOCHRDY 0x0CC
#define IOCTL_PATA_INTRQ 0x0D0
#define IOCTL_PATA_DRQ 0x0D4
#define IOCTL_PATA_DACK 0x0D8
#define IOCTL_NFC_WP 0x0DC
#define IOCTL_NFC_RB 0x0E0
#define IOCTL_NFC_ALE 0x0E4
#define IOCTL_NFC_CLE 0x0E8
#define IOCTL_NFC_WE 0x0EC
#define IOCTL_NFC_RE 0x0F0
#define IOCTL_PCI_AD31 0x0F4
#define IOCTL_PCI_AD30 0x0F8
#define IOCTL_PCI_AD29 0x0FC
#define IOCTL_PCI_AD28 0x100
#define IOCTL_PCI_AD27 0x104
#define IOCTL_PCI_AD26 0x108
#define IOCTL_PCI_AD25 0x10C
#define IOCTL_PCI_AD24 0x110
#define IOCTL_PCI_AD23 0x114
#define IOCTL_PCI_AD22 0x118
#define IOCTL_PCI_AD21 0x11C
#define IOCTL_PCI_AD20 0x120
#define IOCTL_PCI_AD19 0x124
#define IOCTL_PCI_AD18 0x128
#define IOCTL_PCI_AD17 0x12C
#define IOCTL_PCI_AD16 0x130
#define IOCTL_PCI_AD15 0x134
#define IOCTL_PCI_AD14 0x138
#define IOCTL_PCI_AD13 0x13C
#define IOCTL_PCI_AD12 0x140
#define IOCTL_PCI_AD11 0x144
#define IOCTL_PCI_AD10 0x148
#define IOCTL_PCI_AD09 0x14C
#define IOCTL_PCI_AD08 0x150
#define IOCTL_PCI_AD07 0x154
#define IOCTL_PCI_AD06 0x158
#define IOCTL_PCI_AD05 0x15C
#define IOCTL_PCI_AD04 0x160
#define IOCTL_PCI_AD03 0x164
#define IOCTL_PCI_AD02 0x168
#define IOCTL_PCI_AD01 0x16C
#define IOCTL_PCI_AD00 0x170
#define IOCTL_PCI_CBE0 0x174
#define IOCTL_PCI_CBE1 0x178
#define IOCTL_PCI_CBE2 0x17C
#define IOCTL_PCI_CBE3 0x180
#define IOCTL_PCI_GNT2 0x184
#define IOCTL_PCI_REQ2 0x188
#define IOCTL_PCI_GNT1 0x18C
#define IOCTL_PCI_REQ1 0x190
#define IOCTL_PCI_GNT0 0x194
#define IOCTL_PCI_REQ0 0x198
#define IOCTL_PCI_INTA 0x19C
#define IOCTL_PCI_CLK 0x1A0
#define IOCTL_PCI_RST_OUT 0x1A4
#define IOCTL_PCI_FRAME 0x1A8
#define IOCTL_PCI_IDSEL 0x1AC
#define IOCTL_PCI_DEVSEL 0x1B0
#define IOCTL_PCI_IRDY 0x1B4
#define IOCTL_PCI_TRDY 0x1B8
#define IOCTL_PCI_STOP 0x1BC
#define IOCTL_PCI_PAR 0x1C0
#define IOCTL_PCI_PERR 0x1C4
#define IOCTL_PCI_SERR 0x1C8
#define IOCTL_SPDIF_TXCLK 0x1CC
#define IOCTL_SPDIF_TX 0x1D0
#define IOCTL_SPDIF_RX 0x1D4
#define IOCTL_I2C0_SCL 0x1D8
#define IOCTL_I2C0_SDA 0x1DC
#define IOCTL_I2C1_SCL 0x1E0
#define IOCTL_I2C1_SDA 0x1E4
#define IOCTL_I2C2_SCL 0x1E8
#define IOCTL_I2C2_SDA 0x1EC
#define IOCTL_IRQ0 0x1F0
#define IOCTL_IRQ1 0x1F4
#define IOCTL_CAN1_TX 0x1F8
#define IOCTL_CAN2_TX 0x1FC
#define IOCTL_J1850_TX 0x200
#define IOCTL_J1850_RX 0x204
#define IOCTL_PSC_MCLK_IN 0x208
#define IOCTL_PSC0_0 0x20C
#define IOCTL_PSC0_1 0x210
#define IOCTL_PSC0_2 0x214
#define IOCTL_PSC0_3 0x218
#define IOCTL_PSC0_4 0x21C
#define IOCTL_PSC1_0 0x220
#define IOCTL_PSC1_1 0x224
#define IOCTL_PSC1_2 0x228
#define IOCTL_PSC1_3 0x22C
#define IOCTL_PSC1_4 0x230
#define IOCTL_PSC2_0 0x234
#define IOCTL_PSC2_1 0x238
#define IOCTL_PSC2_2 0x23C
#define IOCTL_PSC2_3 0x240
#define IOCTL_PSC2_4 0x244
#define IOCTL_PSC3_0 0x248
#define IOCTL_PSC3_1 0x24C
#define IOCTL_PSC3_2 0x250
#define IOCTL_PSC3_3 0x254
#define IOCTL_PSC3_4 0x258
#define IOCTL_PSC4_0 0x25C
#define IOCTL_PSC4_1 0x260
#define IOCTL_PSC4_2 0x264
#define IOCTL_PSC4_3 0x268
#define IOCTL_PSC4_4 0x26C
#define IOCTL_PSC5_0 0x270
#define IOCTL_PSC5_1 0x274
#define IOCTL_PSC5_2 0x278
#define IOCTL_PSC5_3 0x27C
#define IOCTL_PSC5_4 0x280
#define IOCTL_PSC6_0 0x284
#define IOCTL_PSC6_1 0x288
#define IOCTL_PSC6_2 0x28C
#define IOCTL_PSC6_3 0x290
#define IOCTL_PSC6_4 0x294
#define IOCTL_PSC7_0 0x298
#define IOCTL_PSC7_1 0x29C
#define IOCTL_PSC7_2 0x2A0
#define IOCTL_PSC7_3 0x2A4
#define IOCTL_PSC7_4 0x2A8
#define IOCTL_PSC8_0 0x2AC
#define IOCTL_PSC8_1 0x2B0
#define IOCTL_PSC8_2 0x2B4
#define IOCTL_PSC8_3 0x2B8
#define IOCTL_PSC8_4 0x2BC
#define IOCTL_PSC9_0 0x2C0
#define IOCTL_PSC9_1 0x2C4
#define IOCTL_PSC9_2 0x2C8
#define IOCTL_PSC9_3 0x2CC
#define IOCTL_PSC9_4 0x2D0
#define IOCTL_PSC10_0 0x2D4
#define IOCTL_PSC10_1 0x2D8
#define IOCTL_PSC10_2 0x2DC
#define IOCTL_PSC10_3 0x2E0
#define IOCTL_PSC10_4 0x2E4
#define IOCTL_PSC11_0 0x2E8
#define IOCTL_PSC11_1 0x2EC
#define IOCTL_PSC11_2 0x2F0
#define IOCTL_PSC11_3 0x2F4
#define IOCTL_PSC11_4 0x2F8
#define IOCTL_HRESET 0x2FC
#define IOCTL_SRESET 0x300
#define IOCTL_CKSTP_OUT 0x304
#define IOCTL_USB2_VBUS_PWR_FAULT 0x308
#define IOCTL_USB2_VBUS_PWR_SELECT 0x30C
#define IOCTL_USB2_PHY_DRVV_BUS 0x310
extern void iopin_initialize(void);

5
board/amcc/sequoia/sequoia.c
View File

@ -92,6 +92,11 @@ int board_early_init_f(void)
#ifdef CONFIG_I2C_MULTI_BUS
sdr0_pfc1 |= ((sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL);
#endif
/* Two UARTs, so we need 4-pin mode. Also, we want CTS/RTS mode. */
sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_CTS_RTS;
sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_CTS_RTS;
mfsdr(SDR0_PFC2, sdr0_pfc2);
sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
SDR0_PFC2_SELECT_CONFIG_4;

16
board/freescale/mpc8540ads/u-boot.lds
View File

@ -26,6 +26,12 @@
OUTPUT_ARCH(powerpc)
/* Do we need any of these for elf?
__DYNAMIC = 0; */
PHDRS
{
text PT_LOAD;
bss PT_LOAD;
}
SECTIONS
{
/* Read-only sections, merged into text segment: */
@ -57,7 +63,7 @@ SECTIONS
*(.text)
*(.fixup)
*(.got1)
}
} :text
_etext = .;
PROVIDE (etext = .);
.rodata :
@ -66,7 +72,7 @@ SECTIONS
*(.rodata1)
*(.rodata.str1.4)
*(.eh_frame)
}
} :text
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
@ -118,12 +124,12 @@ SECTIONS
.bootpg ADDR(.text) + 0x7f000 :
{
cpu/mpc85xx/start.o (.bootpg)
} = 0xffff
} :text = 0xffff
.resetvec ADDR(.text) + 0x7fffc :
{
*(.resetvec)
} = 0xffff
} :text = 0xffff
. = ADDR(.text) + 0x80000;
@ -134,7 +140,7 @@ SECTIONS
*(.dynbss)
*(.bss)
*(COMMON)
}
} :bss
. = ALIGN(4);
_end = . ;

16
board/freescale/mpc8541cds/u-boot.lds
View File

@ -23,6 +23,12 @@
OUTPUT_ARCH(powerpc)
/* Do we need any of these for elf?
__DYNAMIC = 0; */
PHDRS
{
text PT_LOAD;
bss PT_LOAD;
}
SECTIONS
{
/* Read-only sections, merged into text segment: */
@ -54,7 +60,7 @@ SECTIONS
*(.text)
*(.fixup)
*(.got1)
}
} :text
_etext = .;
PROVIDE (etext = .);
.rodata :
@ -63,7 +69,7 @@ SECTIONS
*(.rodata1)
*(.rodata.str1.4)
*(.eh_frame)
}
} :text
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
@ -115,12 +121,12 @@ SECTIONS
.bootpg ADDR(.text) + 0x7f000 :
{
cpu/mpc85xx/start.o (.bootpg)
} = 0xffff
} :text = 0xffff
.resetvec ADDR(.text) + 0x7fffc :
{
*(.resetvec)
} = 0xffff
} :text = 0xffff
. = ADDR(.text) + 0x80000;
@ -131,7 +137,7 @@ SECTIONS
*(.dynbss)
*(.bss)
*(COMMON)
}
} :bss
. = ALIGN(4);
_end = . ;

16
board/freescale/mpc8544ds/u-boot.lds
View File

@ -23,6 +23,12 @@
OUTPUT_ARCH(powerpc)
/* Do we need any of these for elf?
__DYNAMIC = 0; */
PHDRS
{
text PT_LOAD;
bss PT_LOAD;
}
SECTIONS
{
/* Read-only sections, merged into text segment: */
@ -54,7 +60,7 @@ SECTIONS
*(.text)
*(.fixup)
*(.got1)
}
} :text
_etext = .;
PROVIDE (etext = .);
.rodata :
@ -63,7 +69,7 @@ SECTIONS
*(.rodata1)
*(.rodata.str1.4)
*(.eh_frame)
}
} :text
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
@ -115,12 +121,12 @@ SECTIONS
.bootpg ADDR(.text) + 0x7f000 :
{
cpu/mpc85xx/start.o (.bootpg)
} = 0xffff
} :text = 0xffff
.resetvec ADDR(.text) + 0x7fffc :
{
*(.resetvec)
} = 0xffff
} :text = 0xffff
. = ADDR(.text) + 0x80000;
@ -131,7 +137,7 @@ SECTIONS
*(.dynbss)
*(.bss)
*(COMMON)
}
} :bss
. = ALIGN(4);
_end = . ;

16
board/freescale/mpc8548cds/u-boot.lds
View File

@ -23,6 +23,12 @@
OUTPUT_ARCH(powerpc)
/* Do we need any of these for elf?
__DYNAMIC = 0; */
PHDRS
{
text PT_LOAD;
bss PT_LOAD;
}
SECTIONS
{
/* Read-only sections, merged into text segment: */
@ -54,7 +60,7 @@ SECTIONS
*(.text)
*(.fixup)
*(.got1)
}
} :text
_etext = .;
PROVIDE (etext = .);
.rodata :
@ -63,7 +69,7 @@ SECTIONS
*(.rodata1)
*(.rodata.str1.4)
*(.eh_frame)
}
} :text
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
@ -115,12 +121,12 @@ SECTIONS
.bootpg ADDR(.text) + 0x7f000 :
{
cpu/mpc85xx/start.o (.bootpg)
} = 0xffff
} :text = 0xffff
.resetvec ADDR(.text) + 0x7fffc :
{
*(.resetvec)
} = 0xffff
} :text = 0xffff
. = ADDR(.text) + 0x80000;
@ -131,7 +137,7 @@ SECTIONS
*(.dynbss)
*(.bss)
*(COMMON)
}
} :bss
. = ALIGN(4);
_end = . ;

16
board/freescale/mpc8555cds/u-boot.lds
View File

@ -23,6 +23,12 @@
OUTPUT_ARCH(powerpc)
/* Do we need any of these for elf?
__DYNAMIC = 0; */
PHDRS
{
text PT_LOAD;
bss PT_LOAD;
}
SECTIONS
{
/* Read-only sections, merged into text segment: */
@ -54,7 +60,7 @@ SECTIONS
*(.text)
*(.fixup)
*(.got1)
}
} :text
_etext = .;
PROVIDE (etext = .);
.rodata :
@ -63,7 +69,7 @@ SECTIONS
*(.rodata1)
*(.rodata.str1.4)
*(.eh_frame)
}
} :text
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
@ -115,12 +121,12 @@ SECTIONS
.bootpg ADDR(.text) + 0x7f000 :
{
cpu/mpc85xx/start.o (.bootpg)
} = 0xffff
} :text = 0xffff
.resetvec ADDR(.text) + 0x7fffc :
{
*(.resetvec)
} = 0xffff
} :text = 0xffff
. = ADDR(.text) + 0x80000;
@ -131,7 +137,7 @@ SECTIONS
*(.dynbss)
*(.bss)
*(COMMON)
}
} :bss
. = ALIGN(4);
_end = . ;

16
board/freescale/mpc8560ads/u-boot.lds
View File

@ -26,6 +26,12 @@
OUTPUT_ARCH(powerpc)
/* Do we need any of these for elf?
__DYNAMIC = 0; */
PHDRS
{
text PT_LOAD;
bss PT_LOAD;
}
SECTIONS
{
/* Read-only sections, merged into text segment: */
@ -57,7 +63,7 @@ SECTIONS
*(.text)
*(.fixup)
*(.got1)
}
} :text
_etext = .;
PROVIDE (etext = .);
.rodata :
@ -66,7 +72,7 @@ SECTIONS
*(.rodata1)
*(.rodata.str1.4)
*(.eh_frame)
}
} :text
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
@ -118,12 +124,12 @@ SECTIONS
.bootpg ADDR(.text) + 0x7f000 :
{
cpu/mpc85xx/start.o (.bootpg)
} = 0xffff
} :text = 0xffff
.resetvec ADDR(.text) + 0x7fffc :
{
*(.resetvec)
} = 0xffff
} :text = 0xffff
. = ADDR(.text) + 0x80000;
@ -134,7 +140,7 @@ SECTIONS
*(.dynbss)
*(.bss)
*(COMMON)
}
} :bss
. = ALIGN(4);
_end = . ;

16
board/freescale/mpc8568mds/u-boot.lds
View File

@ -23,6 +23,12 @@
OUTPUT_ARCH(powerpc)
/* Do we need any of these for elf?
__DYNAMIC = 0; */
PHDRS
{
text PT_LOAD;
bss PT_LOAD;
}
SECTIONS
{
/* Read-only sections, merged into text segment: */
@ -54,7 +60,7 @@ SECTIONS
*(.text)
*(.fixup)
*(.got1)
}
} :text
_etext = .;
PROVIDE (etext = .);
.rodata :
@ -63,7 +69,7 @@ SECTIONS
*(.rodata1)
*(.rodata.str1.4)
*(.eh_frame)
}
} :text
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
@ -115,12 +121,12 @@ SECTIONS
.bootpg ADDR(.text) + 0x7f000 :
{
cpu/mpc85xx/start.o (.bootpg)
} = 0xffff
} :text = 0xffff
.resetvec ADDR(.text) + 0x7fffc :
{
*(.resetvec)
} = 0xffff
} :text = 0xffff
. = ADDR(.text) + 0x80000;
@ -131,7 +137,7 @@ SECTIONS
*(.dynbss)
*(.bss)
*(COMMON)
}
} :bss
. = ALIGN(4);
_end = . ;

16
board/imx31_litekit/imx31_litekit.c
View File

@ -50,16 +50,16 @@ int board_init (void)
mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
mx31_gpio_mux(MUX_RTS1__UART1_CTS_B);
mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
/* SPI2 */
mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_SS2);
mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_SCLK);
mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_SPI_RDY);
mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_MOSI);
mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_MISO);
mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_SS0);
mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_SS1);
mx31_gpio_mux(MUX_CSPI2_SS2__CSPI2_SS2_B);
mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK);
mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B);
mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI);
mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO);
mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B);
mx31_gpio_mux(MUX_CSPI2_SS1__CSPI2_SS1_B);
/* start SPI2 clock */
__REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 4);

4
board/imx31_phycore/imx31_phycore.c
View File

@ -54,11 +54,11 @@ int board_init (void)
mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
mx31_gpio_mux(MUX_RTS1__UART1_CTS_B);
mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
/* setup pins for I2C2 (for EEPROM, RTC) */
mx31_gpio_mux(MUX_CSPI2_MOSI__I2C2_SCL);
mx31_gpio_mux(MUX_CSPI2_MISO__I2C2_SCL);
mx31_gpio_mux(MUX_CSPI2_MISO__I2C2_SDA);
gd->bd->bi_arch_number = 447; /* board id for linux */
gd->bd->bi_boot_params = (0x80000100); /* adress of boot parameters */

16
board/mx31ads/mx31ads.c
View File

@ -55,16 +55,16 @@ int board_init (void)
mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
mx31_gpio_mux(MUX_RTS1__UART1_CTS_B);
mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
/* SPI2 */
mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_SS2);
mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_SCLK);
mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_SPI_RDY);
mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_MOSI);
mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_MISO);
mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_SS0);
mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_SS1);
mx31_gpio_mux(MUX_CSPI2_SS2__CSPI2_SS2_B);
mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK);
mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B);
mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI);
mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO);
mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B);
mx31_gpio_mux(MUX_CSPI2_SS1__CSPI2_SS1_B);
/* start SPI2 clock */
__REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 4);

6
common/cmd_bootm.c
View File

@ -138,7 +138,6 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
memset ((void *)&images, 0, sizeof (images));
images.verify = getenv_yesno ("verify");
images.autostart = getenv_yesno ("autostart");
images.lmb = &lmb;
lmb_init(&lmb);
@ -362,10 +361,9 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
show_boot_progress (-9);
#ifdef DEBUG
puts ("\n## Control returned to monitor - resetting...\n");
if (images.autostart)
do_reset (cmdtp, flag, argc, argv);
do_reset (cmdtp, flag, argc, argv);
#endif
if (!images.autostart && iflag)
if (iflag)
enable_interrupts();
return 1;

15
common/cmd_load.c
View File

@ -424,7 +424,6 @@ write_record (char *buf)
#define untochar(x) ((int) (((x) - SPACE) & 0xff))
extern int os_data_count;
extern int os_data_header[8];
static void set_kerm_bin_mode(unsigned long *);
static int k_recv(void);
@ -631,11 +630,6 @@ void send_nack (int n)
}
/* os_data_* takes an OS Open image and puts it into memory, and
puts the boot header in an array named os_data_header
if image is binary, no header is stored in os_data_header.
*/
void (*os_data_init) (void);
void (*os_data_char) (char new_char);
static int os_data_state, os_data_state_saved;
@ -643,25 +637,28 @@ int os_data_count;
static int os_data_count_saved;
static char *os_data_addr, *os_data_addr_saved;
static char *bin_start_address;
int os_data_header[8];
static void bin_data_init (void)
{
os_data_state = 0;
os_data_count = 0;
os_data_addr = bin_start_address;
}
static void os_data_save (void)
{
os_data_state_saved = os_data_state;
os_data_count_saved = os_data_count;
os_data_addr_saved = os_data_addr;
}
static void os_data_restore (void)
{
os_data_state = os_data_state_saved;
os_data_count = os_data_count_saved;
os_data_addr = os_data_addr_saved;
}
static void bin_data_char (char new_char)
{
switch (os_data_state) {
@ -671,6 +668,7 @@ static void bin_data_char (char new_char)
break;
}
}
static void set_kerm_bin_mode (unsigned long *addr)
{
bin_start_address = (char *) addr;
@ -686,16 +684,19 @@ void k_data_init (void)
k_data_escape = 0;
os_data_init ();
}
void k_data_save (void)
{
k_data_escape_saved = k_data_escape;
os_data_save ();
}
void k_data_restore (void)
{
k_data_escape = k_data_escape_saved;
os_data_restore ();
}
void k_data_char (char new_char)
{
if (k_data_escape) {

4
common/cmd_mp.c
View File

@ -34,9 +34,9 @@ cpu_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
cpuid = simple_strtoul(argv[1], NULL, 10);
if (cpuid >= CONFIG_NR_CPUS) {
if (cpuid >= CONFIG_NUM_CPUS) {
printf ("Core num: %lu is out of range[0..%d]\n",
cpuid, CONFIG_NR_CPUS - 1);
cpuid, CONFIG_NUM_CPUS - 1);
return 1;
}

6
common/cmd_onenand.c
View File

@ -58,8 +58,6 @@ int do_onenand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
} else {
start = simple_strtoul(argv[2], NULL, 10);
end = simple_strtoul(argv[3], NULL, 10);
start -= (unsigned long)onenand_chip.base;
end -= (unsigned long)onenand_chip.base;
start >>= onenand_chip.erase_shift;
end >>= onenand_chip.erase_shift;
@ -92,8 +90,6 @@ int do_onenand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
size_t retlen = 0;
int oob = strncmp(argv[1], "read.oob", 8) ? 0 : 1;
ofs -= (unsigned long)onenand_chip.base;
if (oob)
onenand_read_oob(&onenand_mtd, ofs, len,
&retlen, (u_char *) addr);
@ -111,8 +107,6 @@ int do_onenand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
size_t len = simple_strtoul(argv[4], NULL, 16);
size_t retlen = 0;
ofs -= (unsigned long)onenand_chip.base;
onenand_write(&onenand_mtd, ofs, len, &retlen,
(u_char *) addr);
printf("Done\n");

3
common/env_onenand.c
View File

@ -66,7 +66,6 @@ void env_relocate_spec(void)
size_t retlen;
env_addr = CFG_ENV_ADDR;
env_addr -= (unsigned long) onenand_chip.base;
/* Check OneNAND exist */
if (onenand_mtd.oobblock)
@ -101,7 +100,6 @@ int saveenv(void)
instr.len = CFG_ENV_SIZE;
instr.addr = env_addr;
instr.addr -= (unsigned long)onenand_chip.base;
if (onenand_erase(&onenand_mtd, &instr)) {
printf("OneNAND: erase failed at 0x%08lx\n", env_addr);
return 1;
@ -111,7 +109,6 @@ int saveenv(void)
env_ptr->crc =
crc32(0, env_ptr->data, ONENAND_ENV_SIZE(onenand_mtd));
env_addr -= (unsigned long)onenand_chip.base;
if (onenand_write(&onenand_mtd, env_addr, onenand_mtd.oobblock, &retlen,
(u_char *) env_ptr)) {
printf("OneNAND: write failed at 0x%08x\n", instr.addr);

3
common/image.c
View File

@ -189,7 +189,6 @@ int image_check_dcrc (image_header_t *hdr)
return (dcrc == image_get_dcrc (hdr));
}
/**
* image_multi_count - get component (sub-image) count
* @hdr: pointer to the header of the multi component image
@ -833,7 +832,7 @@ int boot_get_ramdisk (int argc, char *argv[], bootm_headers_t *images,
rd_noffset = fit_conf_get_ramdisk_node (fit_hdr, cfg_noffset);
if (rd_noffset < 0) {
debug ("* ramdisk: no ramdisk in config\n");
return 1;
return 0;
}
}
#endif

2
common/lcd.c
View File

@ -793,7 +793,7 @@ static void *lcd_logo (void)
sprintf (info, "%s (%s - %s) ", U_BOOT_VERSION, __DATE__, __TIME__);
lcd_drawchars (LCD_INFO_X, LCD_INFO_Y, (uchar *)info, strlen(info));
sprintf (info, "(C) 2004 DENX Software Engineering");
sprintf (info, "(C) 2008 DENX Software Engineering GmbH");
lcd_drawchars (LCD_INFO_X, LCD_INFO_Y + VIDEO_FONT_HEIGHT,
(uchar *)info, strlen(info));

4
cpu/arm1136/mx31/generic.c
View File

@ -81,12 +81,12 @@ void mx31_gpio_mux(unsigned long mode)
{
unsigned long reg, shift, tmp;
reg = IOMUXC_BASE + (mode & 0xfc);
reg = IOMUXC_BASE + (mode & 0x1fc);
shift = (~mode & 0x3) * 8;
tmp = __REG(reg);
tmp &= ~(0xff << shift);
tmp |= ((mode >> 8) & 0xff) << shift;
tmp |= ((mode >> IOMUX_MODE_POS) & 0xff) << shift;
__REG(reg) = tmp;
}

2
cpu/mpc512x/Makefile
View File

@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(CPU).a
START = start.o
COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o serial.o fec.o i2c.o
COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o serial.o fec.o i2c.o iopin.o
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))

75
cpu/mpc512x/cpu.c
View File

@ -131,22 +131,67 @@ void watchdog_reset (void)
#endif
#ifdef CONFIG_OF_LIBFDT
void ft_cpu_setup(void *blob, bd_t *bd)
#ifdef CONFIG_OF_SUPPORT_OLD_DEVICE_TREES
/*
* fdt setup for old device trees
* fix up
* cpu clocks
* soc clocks
* ethernet addresses
*/
static void old_ft_cpu_setup(void *blob, bd_t *bd)
{
char *cpu_path = "/cpus/" OF_CPU;
char *eth_path = "/" OF_SOC "/ethernet@2800";
char *eth_path_old = "/" OF_SOC_OLD "/ethernet@2800";
/*
* avoid fixing up by path because that
* produces scary error messages
*/
do_fixup_by_path_u32(blob, cpu_path, "timebase-frequency", OF_TBCLK, 1);
do_fixup_by_path_u32(blob, cpu_path, "bus-frequency", bd->bi_busfreq, 1);
do_fixup_by_path_u32(blob, cpu_path, "clock-frequency", bd->bi_intfreq, 1);
do_fixup_by_path_u32(blob, "/" OF_SOC, "bus-frequency", bd->bi_ipsfreq, 1);
do_fixup_by_path(blob, eth_path, "local-mac-address", bd->bi_enetaddr, 6, 0);
/* this is so old kernels with old device trees will boot */
do_fixup_by_path_u32(blob, "/" OF_SOC_OLD, "bus-frequency", bd->bi_ipsfreq, 0);
do_fixup_by_path(blob, eth_path_old, "local-mac-address",
bd->bi_enetaddr, 6, 0);
do_fixup_by_path(blob, eth_path_old, "address", bd->bi_enetaddr, 6, 0);
/*
* old device trees have ethernet nodes with
* device_type = "network"
*/
do_fixup_by_prop(blob, "device_type", "network", 8,
"local-mac-address", bd->bi_enetaddr, 6, 0);
do_fixup_by_prop(blob, "device_type", "network", 8,
"address", bd->bi_enetaddr, 6, 0);
/*
* old device trees have soc nodes with
* device_type = "soc"
*/
do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
"bus-frequency", bd->bi_ipsfreq, 0);
}
#endif
static void ft_clock_setup(void *blob, bd_t *bd)
{
char *cpu_path = "/cpus/" OF_CPU;
/*
* fixup cpu clocks using path
*/
do_fixup_by_path_u32(blob, cpu_path,
"timebase-frequency", OF_TBCLK, 1);
do_fixup_by_path_u32(blob, cpu_path,
"bus-frequency", bd->bi_busfreq, 1);
do_fixup_by_path_u32(blob, cpu_path,
"clock-frequency", bd->bi_intfreq, 1);
/*
* fixup soc clocks using compatible
*/
do_fixup_by_compat_u32(blob, OF_SOC_COMPAT,
"bus-frequency", bd->bi_ipsfreq, 1);
}
void ft_cpu_setup(void *blob, bd_t *bd)
{
#ifdef CONFIG_OF_SUPPORT_OLD_DEVICE_TREES
old_ft_cpu_setup(blob, bd);
#endif
ft_clock_setup(blob, bd);
#ifdef CONFIG_HAS_ETH0
fdt_fixup_ethernet(blob, bd);
#endif
}
#endif

49
cpu/mpc512x/iopin.c Normal file
View File

@ -0,0 +1,49 @@
/*
* (C) Copyright 2008
* Martha J Marx, Silicon Turnkey Express, mmarx@silicontkx.com
* mpc512x I/O pin/pad initialization for the ADS5121 board
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <linux/types.h>
#include <mpc512x.h>
void iopin_initialize(iopin_t *ioregs_init, int len)
{
short i, j, p;
u_long *reg;
immap_t *im = (immap_t *)CFG_IMMR;
reg = (u_long *)&(im->io_ctrl.regs[0]);
if (sizeof(ioregs_init) == 0)
return;
for (i = 0; i < len; i++) {
for (p = 0, j = ioregs_init[i].p_offset / sizeof(u_long);
p < ioregs_init[i].nr_pins; p++, j++) {
if (ioregs_init[i].bit_or)
reg[j] |= ioregs_init[i].val;
else
reg[j] = ioregs_init[i].val;
}
}
return;
}

2
cpu/mpc8260/pci.c
View File

@ -457,7 +457,7 @@ void pci_mpc8250_init (struct pci_controller *hose)
void ft_pci_setup(void *blob, bd_t *bd)
{
do_fixup_by_prop_u32(blob, "device_type", "pci", 4,
"clock-frequency", bd->pci_clk, 1);
"clock-frequency", gd->pci_clk, 1);
}
#endif

4
cpu/mpc85xx/mp.c
View File

@ -147,7 +147,7 @@ static void pq3_mp_up(unsigned long bootpg)
out_be32(&gur->devdisr, devdisr);
/* release the hounds */
up = ((1 << CONFIG_NR_CPUS) - 1);
up = ((1 << CONFIG_NUM_CPUS) - 1);
bpcr = in_be32(&ecm->eebpcr);
bpcr |= (up << 24);
out_be32(&ecm->eebpcr, bpcr);
@ -157,7 +157,7 @@ static void pq3_mp_up(unsigned long bootpg)
/* wait for everyone */
while (timeout) {
int i;
for (i = 0; i < CONFIG_NR_CPUS; i++) {
for (i = 0; i < CONFIG_NUM_CPUS; i++) {
if (table[i * NUM_BOOT_ENTRY + BOOT_ENTRY_ADDR_LOWER])
cpu_up_mask |= (1 << i);
};

2
cpu/mpc85xx/release.S
View File

@ -173,7 +173,7 @@ __secondary_start_page:
.align L1_CACHE_SHIFT
.globl __spin_table
__spin_table:
.space CONFIG_NR_CPUS*ENTRY_SIZE
.space CONFIG_NUM_CPUS*ENTRY_SIZE
/* Fill in the empty space. The actual reset vector is
* the last word of the page */

25
cpu/mpc86xx/cpu_init.c
View File

@ -26,8 +26,10 @@
* cpu_init.c - low level cpu init
*/
#include <config.h>
#include <common.h>
#include <mpc86xx.h>
#include <asm/mmu.h>
#include <asm/fsl_law.h>
DECLARE_GLOBAL_DATA_PTR;
@ -121,3 +123,26 @@ int cpu_init_r(void)
{
return 0;
}
/* Set up BAT registers */
void setup_bats(void)
{
write_bat(DBAT0, CFG_DBAT0U, CFG_DBAT0L);
write_bat(IBAT0, CFG_IBAT0U, CFG_IBAT0L);
write_bat(DBAT1, CFG_DBAT1U, CFG_DBAT1L);
write_bat(IBAT1, CFG_IBAT1U, CFG_IBAT1L);
write_bat(DBAT2, CFG_DBAT2U, CFG_DBAT2L);
write_bat(IBAT2, CFG_IBAT2U, CFG_IBAT2L);
write_bat(DBAT3, CFG_DBAT3U, CFG_DBAT3L);
write_bat(IBAT3, CFG_IBAT3U, CFG_IBAT3L);
write_bat(DBAT4, CFG_DBAT4U, CFG_DBAT4L);
write_bat(IBAT4, CFG_IBAT4U, CFG_IBAT4L);
write_bat(DBAT5, CFG_DBAT5U, CFG_DBAT5L);
write_bat(IBAT5, CFG_IBAT5U, CFG_IBAT5L);
write_bat(DBAT6, CFG_DBAT6U, CFG_DBAT6L);
write_bat(IBAT6, CFG_IBAT6U, CFG_IBAT6L);
write_bat(DBAT7, CFG_DBAT7U, CFG_DBAT7L);
write_bat(IBAT7, CFG_IBAT7U, CFG_IBAT7L);
return;
}

119
cpu/mpc86xx/start.S
View File

@ -358,125 +358,6 @@ invalidate_bats:
sync
blr
/* setup_bats - set them up to some initial state */
/* Skip any BATS setup in early_bats */
.globl setup_bats
setup_bats:
addis r0, r0, 0x0000
/* IBAT 0 */
addis r4, r0, CFG_IBAT0L@h
ori r4, r4, CFG_IBAT0L@l
addis r3, r0, CFG_IBAT0U@h
ori r3, r3, CFG_IBAT0U@l
mtspr IBAT0L, r4
mtspr IBAT0U, r3
isync
/* DBAT 0 */
addis r4, r0, CFG_DBAT0L@h
ori r4, r4, CFG_DBAT0L@l
addis r3, r0, CFG_DBAT0U@h
ori r3, r3, CFG_DBAT0U@l
mtspr DBAT0L, r4
mtspr DBAT0U, r3
isync
/* IBAT 1 */
addis r4, r0, CFG_IBAT1L@h
ori r4, r4, CFG_IBAT1L@l
addis r3, r0, CFG_IBAT1U@h
ori r3, r3, CFG_IBAT1U@l
mtspr IBAT1L, r4
mtspr IBAT1U, r3
isync
/* DBAT 1 */
addis r4, r0, CFG_DBAT1L@h
ori r4, r4, CFG_DBAT1L@l
addis r3, r0, CFG_DBAT1U@h
ori r3, r3, CFG_DBAT1U@l
mtspr DBAT1L, r4
mtspr DBAT1U, r3
isync
/* IBAT 2 */
addis r4, r0, CFG_IBAT2L@h
ori r4, r4, CFG_IBAT2L@l
addis r3, r0, CFG_IBAT2U@h
ori r3, r3, CFG_IBAT2U@l
mtspr IBAT2L, r4
mtspr IBAT2U, r3
isync
/* DBAT 2 */
addis r4, r0, CFG_DBAT2L@h
ori r4, r4, CFG_DBAT2L@l
addis r3, r0, CFG_DBAT2U@h
ori r3, r3, CFG_DBAT2U@l
mtspr DBAT2L, r4
mtspr DBAT2U, r3
isync
/* IBAT 3 */
addis r4, r0, CFG_IBAT3L@h
ori r4, r4, CFG_IBAT3L@l
addis r3, r0, CFG_IBAT3U@h
ori r3, r3, CFG_IBAT3U@l
mtspr IBAT3L, r4
mtspr IBAT3U, r3
isync
/* DBAT 3 */
addis r4, r0, CFG_DBAT3L@h
ori r4, r4, CFG_DBAT3L@l
addis r3, r0, CFG_DBAT3U@h
ori r3, r3, CFG_DBAT3U@l
mtspr DBAT3L, r4
mtspr DBAT3U, r3
isync
/* IBAT 4 */
addis r4, r0, CFG_IBAT4L@h
ori r4, r4, CFG_IBAT4L@l
addis r3, r0, CFG_IBAT4U@h
ori r3, r3, CFG_IBAT4U@l
mtspr IBAT4L, r4
mtspr IBAT4U, r3
isync
/* DBAT 4 */
addis r4, r0, CFG_DBAT4L@h
ori r4, r4, CFG_DBAT4L@l
addis r3, r0, CFG_DBAT4U@h
ori r3, r3, CFG_DBAT4U@l
mtspr DBAT4L, r4
mtspr DBAT4U, r3
isync
/* IBAT 7 */
addis r4, r0, CFG_IBAT7L@h
ori r4, r4, CFG_IBAT7L@l
addis r3, r0, CFG_IBAT7U@h
ori r3, r3, CFG_IBAT7U@l
mtspr IBAT7L, r4
mtspr IBAT7U, r3
isync
/* DBAT 7 */
addis r4, r0, CFG_DBAT7L@h
ori r4, r4, CFG_DBAT7L@l
addis r3, r0, CFG_DBAT7U@h
ori r3, r3, CFG_DBAT7U@l
mtspr DBAT7L, r4
mtspr DBAT7U, r3
isync
sync
blr
/*
* early_bats:
*

14
drivers/mtd/cfi_flash.c
View File

@ -158,13 +158,13 @@ static uint flash_offset_cfi[2] = { FLASH_OFFSET_CFI, FLASH_OFFSET_CFI_ALT };
/* use CFG_MAX_FLASH_BANKS_DETECT if defined */
#ifdef CFG_MAX_FLASH_BANKS_DETECT
static ulong bank_base[CFG_MAX_FLASH_BANKS_DETECT] = CFG_FLASH_BANKS_LIST;
flash_info_t flash_info[CFG_MAX_FLASH_BANKS_DETECT]; /* FLASH chips info */
# define CFI_MAX_FLASH_BANKS CFG_MAX_FLASH_BANKS_DETECT
#else
static ulong bank_base[CFG_MAX_FLASH_BANKS] = CFG_FLASH_BANKS_LIST;
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* FLASH chips info */
# define CFI_MAX_FLASH_BANKS CFG_MAX_FLASH_BANKS
#endif
flash_info_t flash_info[CFI_MAX_FLASH_BANKS]; /* FLASH chips info */
/*
* Check if chip width is defined. If not, start detecting with 8bit.
*/
@ -1912,12 +1912,14 @@ unsigned long flash_init (void)
char *s = getenv("unlock");
#endif
#define BANK_BASE(i) (((unsigned long [CFI_MAX_FLASH_BANKS])CFG_FLASH_BANKS_LIST)[i])
/* Init: no FLASHes known */
for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
if (!flash_detect_legacy (bank_base[i], i))
flash_get_size (bank_base[i], i);
if (!flash_detect_legacy (BANK_BASE(i), i))
flash_get_size (BANK_BASE(i), i);
size += flash_info[i].size;
if (flash_info[i].flash_id == FLASH_UNKNOWN) {
#ifndef CFG_FLASH_QUIET_TEST

15
drivers/mtd/dataflash.c
View File

@ -56,7 +56,7 @@ int AT91F_DataflashInit (void)
switch (dfcode) {
case AT45DB021:
dataflash_info[i].Device.pages_number = 1024;
dataflash_info[i].Device.pages_size = 263;
dataflash_info[i].Device.pages_size = 264;
dataflash_info[i].Device.page_offset = 9;
dataflash_info[i].Device.byte_mask = 0x300;
dataflash_info[i].Device.cs = cs[i].cs;
@ -65,6 +65,19 @@ int AT91F_DataflashInit (void)
dataflash_info[i].id = dfcode;
found[i] += dfcode;;
break;
case AT45DB081:
dataflash_info[i].Device.pages_number = 4096;
dataflash_info[i].Device.pages_size = 264;
dataflash_info[i].Device.page_offset = 9;
dataflash_info[i].Device.byte_mask = 0x300;
dataflash_info[i].Device.cs = cs[i].cs;
dataflash_info[i].Desc.DataFlash_state = IDLE;
dataflash_info[i].logical_address = cs[i].addr;
dataflash_info[i].id = dfcode;
found[i] += dfcode;;
break;
case AT45DB161:
dataflash_info[i].Device.pages_number = 4096;
dataflash_info[i].Device.pages_size = 528;

6
drivers/mtd/onenand/onenand_base.c
View File

@ -680,13 +680,11 @@ int onenand_read_oob(struct mtd_info *mtd, loff_t from, size_t len,
* onenand_verify_page - [GENERIC] verify the chip contents after a write
* @param mtd MTD device structure
* @param buf the databuffer to verify
* @param block block address
* @param page page address
*
* Check DataRAM area directly
*/
static int onenand_verify_page(struct mtd_info *mtd, u_char * buf,
loff_t addr, int block, int page)
loff_t addr)
{
struct onenand_chip *this = mtd->priv;
void __iomem *dataram0, *dataram1;
@ -783,7 +781,7 @@ static int onenand_write_ecc(struct mtd_info *mtd, loff_t to, size_t len,
written += thislen;
/* Only check verify write turn on */
ret = onenand_verify_page(mtd, (u_char *) buf, to, block, page);
ret = onenand_verify_page(mtd, (u_char *) buf, to);
if (ret) {
MTDDEBUG (MTD_DEBUG_LEVEL0,
"onenand_write_ecc: verify failed %d\n", ret);

50
drivers/qe/uec.c
View File

@ -29,6 +29,7 @@
#include "uccf.h"
#include "uec.h"
#include "uec_phy.h"
#include "miiphy.h"
#if defined(CONFIG_QE)
@ -125,6 +126,13 @@ static uec_info_t eth4_uec_info = {
};
#endif
#define MAXCONTROLLERS (4)
static struct eth_device *devlist[MAXCONTROLLERS];
u16 phy_read (struct uec_mii_info *mii_info, u16 regnum);
void phy_write (struct uec_mii_info *mii_info, u16 regnum, u16 val);
static int uec_mac_enable(uec_private_t *uec, comm_dir_e mode)
{
uec_t *uec_regs;
@ -629,6 +637,39 @@ static void phy_change(struct eth_device *dev)
adjust_link(dev);
}
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
&& !defined(BITBANGMII)
/*
* Read a MII PHY register.
*
* Returns:
* 0 on success
*/
static int uec_miiphy_read(char *devname, unsigned char addr,
unsigned char reg, unsigned short *value)
{
*value = uec_read_phy_reg(devlist[0], addr, reg);
return 0;
}
/*
* Write a MII PHY register.
*
* Returns:
* 0 on success
*/
static int uec_miiphy_write(char *devname, unsigned char addr,
unsigned char reg, unsigned short value)
{
uec_write_phy_reg(devlist[0], addr, reg, value);
return 0;
}
#endif
static int uec_set_mac_address(uec_private_t *uec, u8 *mac_addr)
{
uec_t *uec_regs;
@ -1334,6 +1375,8 @@ int uec_initialize(int index)
return -EINVAL;
}
devlist[index] = dev;
uec->uec_info = uec_info;
sprintf(dev->name, "FSL UEC%d", index);
@ -1356,6 +1399,13 @@ int uec_initialize(int index)
return err;
}
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
&& !defined(BITBANGMII)
miiphy_register(dev->name, uec_miiphy_read, uec_miiphy_write);
#endif
return 1;
}
#endif /* CONFIG_QE */

2
drivers/usb/Makefile
View File

@ -25,6 +25,8 @@ include $(TOPDIR)/config.mk
LIB := $(obj)libusb.a
COBJS-$(CONFIG_USB_R8A66597_HCD) += r8a66597-hcd.o
COBJS-y += isp116x-hcd.o
COBJS-y += sl811_usb.o
COBJS-y += usb_ohci.o

919
drivers/usb/r8a66597-hcd.c Normal file
View File

@ -0,0 +1,919 @@
/*
* R8A66597 HCD (Host Controller Driver) for u-boot
*
* Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*
*/
#include <common.h>
#include <usb.h>
#include <asm/io.h>
#include "r8a66597.h"
#ifdef R8A66597_DEBUG
#define R8A66597_DPRINT printf
#else
#define R8A66597_DPRINT(...)
#endif
static const char hcd_name[] = "r8a66597_hcd";
static unsigned short clock = CONFIG_R8A66597_XTAL;
static unsigned short vif = CONFIG_R8A66597_LDRV;
static unsigned short endian = CONFIG_R8A66597_ENDIAN;
static struct r8a66597 gr8a66597;
static void set_devadd_reg(struct r8a66597 *r8a66597, u8 r8a66597_address,
u16 usbspd, u8 upphub, u8 hubport, int port)
{
u16 val;
unsigned long devadd_reg = get_devadd_addr(r8a66597_address);
val = (upphub << 11) | (hubport << 8) | (usbspd << 6) | (port & 0x0001);
r8a66597_write(r8a66597, val, devadd_reg);
}
static int r8a66597_clock_enable(struct r8a66597 *r8a66597)
{
u16 tmp;
int i = 0;
#if defined(CONFIG_SUPERH_ON_CHIP_R8A66597)
do {
r8a66597_write(r8a66597, SCKE, SYSCFG0);
tmp = r8a66597_read(r8a66597, SYSCFG0);
if (i++ > 1000) {
printf("register access fail.\n");
return -1;
}
} while ((tmp & SCKE) != SCKE);
r8a66597_write(r8a66597, 0x04, 0x02);
#else
do {
r8a66597_write(r8a66597, USBE, SYSCFG0);
tmp = r8a66597_read(r8a66597, SYSCFG0);
if (i++ > 1000) {
printf("register access fail.\n");
return -1;
}
} while ((tmp & USBE) != USBE);
r8a66597_bclr(r8a66597, USBE, SYSCFG0);
r8a66597_mdfy(r8a66597, clock, XTAL, SYSCFG0);
i = 0;
r8a66597_bset(r8a66597, XCKE, SYSCFG0);
do {
udelay(1000);
tmp = r8a66597_read(r8a66597, SYSCFG0);
if (i++ > 500) {
printf("register access fail.\n");
return -1;
}
} while ((tmp & SCKE) != SCKE);
#endif /* #if defined(CONFIG_SUPERH_ON_CHIP_R8A66597) */
return 0;
}
static void r8a66597_clock_disable(struct r8a66597 *r8a66597)
{
r8a66597_bclr(r8a66597, SCKE, SYSCFG0);
udelay(1);
#if !defined(CONFIG_SUPERH_ON_CHIP_R8A66597)
r8a66597_bclr(r8a66597, PLLC, SYSCFG0);
r8a66597_bclr(r8a66597, XCKE, SYSCFG0);
r8a66597_bclr(r8a66597, USBE, SYSCFG0);
#endif
}
static void r8a66597_enable_port(struct r8a66597 *r8a66597, int port)
{
u16 val;
val = port ? DRPD : DCFM | DRPD;
r8a66597_bset(r8a66597, val, get_syscfg_reg(port));
r8a66597_bset(r8a66597, HSE, get_syscfg_reg(port));
r8a66597_write(r8a66597, BURST | CPU_ADR_RD_WR, get_dmacfg_reg(port));
}
static void r8a66597_disable_port(struct r8a66597 *r8a66597, int port)
{
u16 val, tmp;
r8a66597_write(r8a66597, 0, get_intenb_reg(port));
r8a66597_write(r8a66597, 0, get_intsts_reg(port));
r8a66597_port_power(r8a66597, port, 0);
do {
tmp = r8a66597_read(r8a66597, SOFCFG) & EDGESTS;
udelay(640);
} while (tmp == EDGESTS);
val = port ? DRPD : DCFM | DRPD;
r8a66597_bclr(r8a66597, val, get_syscfg_reg(port));
r8a66597_bclr(r8a66597, HSE, get_syscfg_reg(port));
}
static int enable_controller(struct r8a66597 *r8a66597)
{
int ret, port;
ret = r8a66597_clock_enable(r8a66597);
if (ret < 0)
return ret;
r8a66597_bset(r8a66597, vif & LDRV, PINCFG);
r8a66597_bset(r8a66597, USBE, SYSCFG0);
r8a66597_bset(r8a66597, INTL, SOFCFG);
r8a66597_write(r8a66597, 0, INTENB0);
r8a66597_write(r8a66597, 0, INTENB1);
r8a66597_write(r8a66597, 0, INTENB2);
r8a66597_bset(r8a66597, endian & BIGEND, CFIFOSEL);
r8a66597_bset(r8a66597, endian & BIGEND, D0FIFOSEL);
r8a66597_bset(r8a66597, endian & BIGEND, D1FIFOSEL);
r8a66597_bset(r8a66597, TRNENSEL, SOFCFG);
for (port = 0; port < R8A66597_MAX_ROOT_HUB; port++)
r8a66597_enable_port(r8a66597, port);
return 0;
}
static void disable_controller(struct r8a66597 *r8a66597)
{
int i;
if (!(r8a66597_read(r8a66597, SYSCFG0) & USBE))
return;
r8a66597_write(r8a66597, 0, INTENB0);
r8a66597_write(r8a66597, 0, INTSTS0);
r8a66597_write(r8a66597, 0, D0FIFOSEL);
r8a66597_write(r8a66597, 0, D1FIFOSEL);
r8a66597_write(r8a66597, 0, DCPCFG);
r8a66597_write(r8a66597, 0x40, DCPMAXP);
r8a66597_write(r8a66597, 0, DCPCTR);
for (i = 0; i <= 10; i++)
r8a66597_write(r8a66597, 0, get_devadd_addr(i));
for (i = 1; i <= 5; i++) {
r8a66597_write(r8a66597, 0, get_pipetre_addr(i));
r8a66597_write(r8a66597, 0, get_pipetrn_addr(i));
}
for (i = 1; i < R8A66597_MAX_NUM_PIPE; i++) {
r8a66597_write(r8a66597, 0, get_pipectr_addr(i));
r8a66597_write(r8a66597, i, PIPESEL);
r8a66597_write(r8a66597, 0, PIPECFG);
r8a66597_write(r8a66597, 0, PIPEBUF);
r8a66597_write(r8a66597, 0, PIPEMAXP);
r8a66597_write(r8a66597, 0, PIPEPERI);
}
for (i = 0; i < R8A66597_MAX_ROOT_HUB; i++)
r8a66597_disable_port(r8a66597, i);
r8a66597_clock_disable(r8a66597);
}
static void r8a66597_reg_wait(struct r8a66597 *r8a66597, unsigned long reg,
u16 mask, u16 loop)
{
u16 tmp;
int i = 0;
do {
tmp = r8a66597_read(r8a66597, reg);
if (i++ > 1000000) {
printf("register%lx, loop %x is timeout\n", reg, loop);
break;
}
} while ((tmp & mask) != loop);
}
static void pipe_buffer_setting(struct r8a66597 *r8a66597,
struct usb_device *dev, unsigned long pipe)
{
u16 val = 0;
u16 pipenum, bufnum, maxpacket;
if (usb_pipein(pipe)) {
pipenum = BULK_IN_PIPENUM;
bufnum = BULK_IN_BUFNUM;
maxpacket = dev->epmaxpacketin[usb_pipeendpoint(pipe)];
} else {
pipenum = BULK_OUT_PIPENUM;
bufnum = BULK_OUT_BUFNUM;
maxpacket = dev->epmaxpacketout[usb_pipeendpoint(pipe)];
}
if (r8a66597->pipe_config & (1 << pipenum))
return;
r8a66597->pipe_config |= (1 << pipenum);
r8a66597_bset(r8a66597, ACLRM, get_pipectr_addr(pipenum));
r8a66597_bclr(r8a66597, ACLRM, get_pipectr_addr(pipenum));
r8a66597_write(r8a66597, pipenum, PIPESEL);
/* FIXME: This driver support bulk transfer only. */
if (!usb_pipein(pipe))
val |= R8A66597_DIR;
else
val |= R8A66597_SHTNAK;
val |= R8A66597_BULK | R8A66597_DBLB | usb_pipeendpoint(pipe);
r8a66597_write(r8a66597, val, PIPECFG);
r8a66597_write(r8a66597, (8 << 10) | bufnum, PIPEBUF);
r8a66597_write(r8a66597, make_devsel(usb_pipedevice(pipe)) |
maxpacket, PIPEMAXP);
r8a66597_write(r8a66597, 0, PIPEPERI);
r8a66597_write(r8a66597, SQCLR, get_pipectr_addr(pipenum));
}
static int send_setup_packet(struct r8a66597 *r8a66597, struct usb_device *dev,
struct devrequest *setup)
{
int i;
unsigned short *p = (unsigned short *)setup;
unsigned long setup_addr = USBREQ;
u16 intsts1;
int timeout = 3000;
u16 devsel = setup->request == USB_REQ_SET_ADDRESS ? 0 : dev->devnum;
r8a66597_write(r8a66597, make_devsel(devsel) |
(8 << dev->maxpacketsize), DCPMAXP);
r8a66597_write(r8a66597, ~(SIGN | SACK), INTSTS1);
for (i = 0; i < 4; i++) {
r8a66597_write(r8a66597, le16_to_cpu(p[i]), setup_addr);
setup_addr += 2;
}
r8a66597_write(r8a66597, ~0x0001, BRDYSTS);
r8a66597_write(r8a66597, SUREQ, DCPCTR);
while (1) {
intsts1 = r8a66597_read(r8a66597, INTSTS1);
if (intsts1 & SACK)
break;
if (intsts1 & SIGN) {
printf("setup packet send error\n");
return -1;
}
if (timeout-- < 0) {
printf("setup packet timeout\n");
return -1;
}
udelay(500);
}
return 0;
}
static int send_bulk_packet(struct r8a66597 *r8a66597, struct usb_device *dev,
unsigned long pipe, void *buffer, int transfer_len)
{
u16 tmp, bufsize;
u16 *buf;
size_t size;
R8A66597_DPRINT("%s\n", __func__);
r8a66597_mdfy(r8a66597, MBW | BULK_OUT_PIPENUM,
MBW | CURPIPE, CFIFOSEL);
r8a66597_reg_wait(r8a66597, CFIFOSEL, CURPIPE, BULK_OUT_PIPENUM);
tmp = r8a66597_read(r8a66597, CFIFOCTR);
if ((tmp & FRDY) == 0) {
printf("%s FRDY is not set (%x)\n", __func__, tmp);
return -1;
}
/* prepare parameters */
bufsize = dev->epmaxpacketout[usb_pipeendpoint(pipe)];
buf = (u16 *)(buffer + dev->act_len);
size = min((int)bufsize, transfer_len - dev->act_len);
/* write fifo */
r8a66597_write(r8a66597, ~(1 << BULK_OUT_PIPENUM), BEMPSTS);
if (buffer) {
r8a66597_write_fifo(r8a66597, CFIFO, buf, size);
r8a66597_write(r8a66597, BVAL, CFIFOCTR);
}
/* update parameters */
dev->act_len += size;
r8a66597_mdfy(r8a66597, PID_BUF, PID,
get_pipectr_addr(BULK_OUT_PIPENUM));
while (!(r8a66597_read(r8a66597, BEMPSTS) & (1 << BULK_OUT_PIPENUM)))
if (ctrlc())
return -1;
r8a66597_write(r8a66597, ~(1 << BULK_OUT_PIPENUM), BEMPSTS);
if (dev->act_len >= transfer_len)
r8a66597_mdfy(r8a66597, PID_NAK, PID,
get_pipectr_addr(BULK_OUT_PIPENUM));
return 0;
}
static int receive_bulk_packet(struct r8a66597 *r8a66597,
struct usb_device *dev,
unsigned long pipe,
void *buffer, int transfer_len)
{
u16 tmp;
u16 *buf;
const u16 pipenum = BULK_IN_PIPENUM;
int rcv_len;
int maxpacket = dev->epmaxpacketin[usb_pipeendpoint(pipe)];
R8A66597_DPRINT("%s\n", __func__);
/* prepare */
if (dev->act_len == 0) {
r8a66597_mdfy(r8a66597, PID_NAK, PID,
get_pipectr_addr(pipenum));
r8a66597_write(r8a66597, ~(1 << pipenum), BRDYSTS);
r8a66597_write(r8a66597, TRCLR, get_pipetre_addr(pipenum));
r8a66597_write(r8a66597,
(transfer_len + maxpacket - 1) / maxpacket,
get_pipetrn_addr(pipenum));
r8a66597_bset(r8a66597, TRENB, get_pipetre_addr(pipenum));
r8a66597_mdfy(r8a66597, PID_BUF, PID,
get_pipectr_addr(pipenum));
}
r8a66597_mdfy(r8a66597, MBW | pipenum, MBW | CURPIPE, CFIFOSEL);
r8a66597_reg_wait(r8a66597, CFIFOSEL, CURPIPE, pipenum);
while (!(r8a66597_read(r8a66597, BRDYSTS) & (1 << pipenum)))
if (ctrlc())
return -1;
r8a66597_write(r8a66597, ~(1 << pipenum), BRDYSTS);
tmp = r8a66597_read(r8a66597, CFIFOCTR);
if ((tmp & FRDY) == 0) {
printf("%s FRDY is not set. (%x)\n", __func__, tmp);
return -1;
}
buf = (u16 *)(buffer + dev->act_len);
rcv_len = tmp & DTLN;
dev->act_len += rcv_len;
if (buffer) {
if (rcv_len == 0)
r8a66597_write(r8a66597, BCLR, CFIFOCTR);
else
r8a66597_read_fifo(r8a66597, CFIFO, buf, rcv_len);
}
return 0;
}
static int receive_control_packet(struct r8a66597 *r8a66597,
struct usb_device *dev,
void *buffer, int transfer_len)
{
u16 tmp;
int rcv_len;
/* FIXME: limit transfer size : 64byte or less */
r8a66597_bclr(r8a66597, R8A66597_DIR, DCPCFG);
r8a66597_mdfy(r8a66597, 0, ISEL | CURPIPE, CFIFOSEL);
r8a66597_reg_wait(r8a66597, CFIFOSEL, CURPIPE, 0);
r8a66597_bset(r8a66597, SQSET, DCPCTR);
r8a66597_write(r8a66597, BCLR, CFIFOCTR);
r8a66597_mdfy(r8a66597, PID_BUF, PID, DCPCTR);
while (!(r8a66597_read(r8a66597, BRDYSTS) & 0x0001))
if (ctrlc())
return -1;
r8a66597_write(r8a66597, ~0x0001, BRDYSTS);
r8a66597_mdfy(r8a66597, MBW, MBW | CURPIPE, CFIFOSEL);
r8a66597_reg_wait(r8a66597, CFIFOSEL, CURPIPE, 0);
tmp = r8a66597_read(r8a66597, CFIFOCTR);
if ((tmp & FRDY) == 0) {
printf("%s FRDY is not set. (%x)\n", __func__, tmp);
return -1;
}
rcv_len = tmp & DTLN;
dev->act_len += rcv_len;
r8a66597_mdfy(r8a66597, PID_NAK, PID, DCPCTR);
if (buffer) {
if (rcv_len == 0)
r8a66597_write(r8a66597, BCLR, DCPCTR);
else
r8a66597_read_fifo(r8a66597, CFIFO, buffer, rcv_len);
}
return 0;
}
static int send_status_packet(struct r8a66597 *r8a66597,
unsigned long pipe)
{
r8a66597_bset(r8a66597, SQSET, DCPCTR);
r8a66597_mdfy(r8a66597, PID_NAK, PID, DCPCTR);
if (usb_pipein(pipe)) {
r8a66597_bset(r8a66597, R8A66597_DIR, DCPCFG);
r8a66597_mdfy(r8a66597, ISEL, ISEL | CURPIPE, CFIFOSEL);
r8a66597_reg_wait(r8a66597, CFIFOSEL, CURPIPE, 0);
r8a66597_write(r8a66597, ~BEMP0, BEMPSTS);
r8a66597_write(r8a66597, BCLR | BVAL, CFIFOCTR);
} else {
r8a66597_bclr(r8a66597, R8A66597_DIR, DCPCFG);
r8a66597_mdfy(r8a66597, 0, ISEL | CURPIPE, CFIFOSEL);
r8a66597_reg_wait(r8a66597, CFIFOSEL, CURPIPE, 0);
r8a66597_write(r8a66597, BCLR, CFIFOCTR);
}
r8a66597_mdfy(r8a66597, PID_BUF, PID, DCPCTR);
while (!(r8a66597_read(r8a66597, BEMPSTS) & 0x0001))
if (ctrlc())
return -1;
return 0;
}
static void r8a66597_check_syssts(struct r8a66597 *r8a66597, int port)
{
int count = R8A66597_MAX_SAMPLING;
unsigned short syssts, old_syssts;
R8A66597_DPRINT("%s\n", __func__);
old_syssts = r8a66597_read(r8a66597, get_syssts_reg(port) & LNST);
while (count > 0) {
wait_ms(R8A66597_RH_POLL_TIME);
syssts = r8a66597_read(r8a66597, get_syssts_reg(port) & LNST);
if (syssts == old_syssts) {
count--;
} else {
count = R8A66597_MAX_SAMPLING;
old_syssts = syssts;
}
}
}
static void r8a66597_bus_reset(struct r8a66597 *r8a66597, int port)
{
wait_ms(10);
r8a66597_mdfy(r8a66597, USBRST, USBRST | UACT, get_dvstctr_reg(port));
wait_ms(50);
r8a66597_mdfy(r8a66597, UACT, USBRST | UACT, get_dvstctr_reg(port));
wait_ms(50);
}
static int check_usb_device_connecting(struct r8a66597 *r8a66597)
{
int timeout = 10000; /* 100usec * 10000 = 1sec */
int i;
for (i = 0; i < 5; i++) {
/* check a usb cable connect */
while (!(r8a66597_read(r8a66597, INTSTS1) & ATTCH)) {
if (timeout-- < 0) {
printf("%s timeout.\n", __func__);
return -1;
}
udelay(100);
}
/* check a data line */
r8a66597_check_syssts(r8a66597, 0);
r8a66597_bus_reset(r8a66597, 0);
r8a66597->speed = get_rh_usb_speed(r8a66597, 0);
if (!(r8a66597_read(r8a66597, INTSTS1) & DTCH)) {
r8a66597->port_change = USB_PORT_STAT_C_CONNECTION;
r8a66597->port_status = USB_PORT_STAT_CONNECTION |
USB_PORT_STAT_ENABLE;
return 0; /* success */
}
R8A66597_DPRINT("USB device has detached. retry = %d\n", i);
r8a66597_write(r8a66597, ~DTCH, INTSTS1);
}
return -1; /* fail */
}
/* based on usb_ohci.c */
#define min_t(type, x, y) \
({ type __x = (x); type __y = (y); __x < __y ? __x: __y; })
/*-------------------------------------------------------------------------*
* Virtual Root Hub
*-------------------------------------------------------------------------*/
/* Device descriptor */
static __u8 root_hub_dev_des[] =
{
0x12, /* __u8 bLength; */
0x01, /* __u8 bDescriptorType; Device */
0x10, /* __u16 bcdUSB; v1.1 */
0x01,
0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */
0x00, /* __u8 bDeviceSubClass; */
0x00, /* __u8 bDeviceProtocol; */
0x08, /* __u8 bMaxPacketSize0; 8 Bytes */
0x00, /* __u16 idVendor; */
0x00,
0x00, /* __u16 idProduct; */
0x00,
0x00, /* __u16 bcdDevice; */
0x00,
0x00, /* __u8 iManufacturer; */
0x01, /* __u8 iProduct; */
0x00, /* __u8 iSerialNumber; */
0x01 /* __u8 bNumConfigurations; */
};
/* Configuration descriptor */
static __u8 root_hub_config_des[] =
{
0x09, /* __u8 bLength; */
0x02, /* __u8 bDescriptorType; Configuration */
0x19, /* __u16 wTotalLength; */
0x00,
0x01, /* __u8 bNumInterfaces; */
0x01, /* __u8 bConfigurationValue; */
0x00, /* __u8 iConfiguration; */
0x40, /* __u8 bmAttributes; */
0x00, /* __u8 MaxPower; */
/* interface */
0x09, /* __u8 if_bLength; */
0x04, /* __u8 if_bDescriptorType; Interface */
0x00, /* __u8 if_bInterfaceNumber; */
0x00, /* __u8 if_bAlternateSetting; */
0x01, /* __u8 if_bNumEndpoints; */
0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */
0x00, /* __u8 if_bInterfaceSubClass; */
0x00, /* __u8 if_bInterfaceProtocol; */
0x00, /* __u8 if_iInterface; */
/* endpoint */
0x07, /* __u8 ep_bLength; */
0x05, /* __u8 ep_bDescriptorType; Endpoint */
0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */
0x03, /* __u8 ep_bmAttributes; Interrupt */
0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
0x00,
0xff /* __u8 ep_bInterval; 255 ms */
};
static unsigned char root_hub_str_index0[] =
{
0x04, /* __u8 bLength; */
0x03, /* __u8 bDescriptorType; String-descriptor */
0x09, /* __u8 lang ID */
0x04, /* __u8 lang ID */
};
static unsigned char root_hub_str_index1[] =
{
34, /* __u8 bLength; */
0x03, /* __u8 bDescriptorType; String-descriptor */
'R', /* __u8 Unicode */
0, /* __u8 Unicode */
'8', /* __u8 Unicode */
0, /* __u8 Unicode */
'A', /* __u8 Unicode */
0, /* __u8 Unicode */
'6', /* __u8 Unicode */
0, /* __u8 Unicode */
'6', /* __u8 Unicode */
0, /* __u8 Unicode */
'5', /* __u8 Unicode */
0, /* __u8 Unicode */
'9', /* __u8 Unicode */
0, /* __u8 Unicode */
'7', /* __u8 Unicode */
0, /* __u8 Unicode */
' ', /* __u8 Unicode */
0, /* __u8 Unicode */
'R', /* __u8 Unicode */
0, /* __u8 Unicode */
'o', /* __u8 Unicode */
0, /* __u8 Unicode */
'o', /* __u8 Unicode */
0, /* __u8 Unicode */
't', /* __u8 Unicode */
0, /* __u8 Unicode */
'H', /* __u8 Unicode */
0, /* __u8 Unicode */
'u', /* __u8 Unicode */
0, /* __u8 Unicode */
'b', /* __u8 Unicode */
0, /* __u8 Unicode */
};
static int r8a66597_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
void *buffer, int transfer_len, struct devrequest *cmd)
{
struct r8a66597 *r8a66597 = &gr8a66597;
int leni = transfer_len;
int len = 0;
int stat = 0;
__u16 bmRType_bReq;
__u16 wValue;
__u16 wIndex;
__u16 wLength;
unsigned char data[32];
R8A66597_DPRINT("%s\n", __func__);
if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) {
printf("Root-Hub submit IRQ: NOT implemented");
return 0;
}
bmRType_bReq = cmd->requesttype | (cmd->request << 8);
wValue = cpu_to_le16 (cmd->value);
wIndex = cpu_to_le16 (cmd->index);
wLength = cpu_to_le16 (cmd->length);
switch (bmRType_bReq) {
case RH_GET_STATUS:
*(__u16 *)buffer = cpu_to_le16(1);
len = 2;
break;
case RH_GET_STATUS | RH_INTERFACE:
*(__u16 *)buffer = cpu_to_le16(0);
len = 2;
break;
case RH_GET_STATUS | RH_ENDPOINT:
*(__u16 *)buffer = cpu_to_le16(0);
len = 2;
break;
case RH_GET_STATUS | RH_CLASS:
*(__u32 *)buffer = cpu_to_le32(0);
len = 4;
break;
case RH_GET_STATUS | RH_OTHER | RH_CLASS:
*(__u32 *)buffer = cpu_to_le32(r8a66597->port_status |
(r8a66597->port_change << 16));
len = 4;
break;
case RH_CLEAR_FEATURE | RH_ENDPOINT:
case RH_CLEAR_FEATURE | RH_CLASS:
break;
case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
switch (wValue) {
case RH_C_PORT_CONNECTION:
r8a66597->port_change &= ~USB_PORT_STAT_C_CONNECTION;
break;
}
break;
case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
switch (wValue) {
case (RH_PORT_SUSPEND):
break;
case (RH_PORT_RESET):
r8a66597_bus_reset(r8a66597, 0);
break;
case (RH_PORT_POWER):
break;
case (RH_PORT_ENABLE):
break;
}
break;
case RH_SET_ADDRESS:
gr8a66597.rh_devnum = wValue;
break;
case RH_GET_DESCRIPTOR:
switch ((wValue & 0xff00) >> 8) {
case (0x01): /* device descriptor */
len = min_t(unsigned int,
leni,
min_t(unsigned int,
sizeof(root_hub_dev_des),
wLength));
memcpy(buffer, root_hub_dev_des, len);
break;
case (0x02): /* configuration descriptor */
len = min_t(unsigned int,
leni,
min_t(unsigned int,
sizeof(root_hub_config_des),
wLength));
memcpy(buffer, root_hub_config_des, len);
break;
case (0x03): /* string descriptors */
if (wValue == 0x0300) {
len = min_t(unsigned int,
leni,
min_t(unsigned int,
sizeof(root_hub_str_index0),
wLength));
memcpy(buffer, root_hub_str_index0, len);
}
if (wValue == 0x0301) {
len = min_t(unsigned int,
leni,
min_t(unsigned int,
sizeof(root_hub_str_index1),
wLength));
memcpy(buffer, root_hub_str_index1, len);
}
break;
default:
stat = USB_ST_STALLED;
}
break;
case RH_GET_DESCRIPTOR | RH_CLASS:
{
__u32 temp = 0x00000001;
data[0] = 9; /* min length; */
data[1] = 0x29;
data[2] = temp & RH_A_NDP;
data[3] = 0;
if (temp & RH_A_PSM)
data[3] |= 0x1;
if (temp & RH_A_NOCP)
data[3] |= 0x10;
else if (temp & RH_A_OCPM)
data[3] |= 0x8;
/* corresponds to data[4-7] */
data[5] = (temp & RH_A_POTPGT) >> 24;
data[7] = temp & RH_B_DR;
if (data[2] < 7) {
data[8] = 0xff;
} else {
data[0] += 2;
data[8] = (temp & RH_B_DR) >> 8;
data[10] = data[9] = 0xff;
}
len = min_t(unsigned int, leni,
min_t(unsigned int, data[0], wLength));
memcpy(buffer, data, len);
break;
}
case RH_GET_CONFIGURATION:
*(__u8 *) buffer = 0x01;
len = 1;
break;
case RH_SET_CONFIGURATION:
break;
default:
dbg("unsupported root hub command");
stat = USB_ST_STALLED;
}
wait_ms(1);
len = min_t(int, len, leni);
dev->act_len = len;
dev->status = stat;
return stat;
}
int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
int transfer_len)
{
struct r8a66597 *r8a66597 = &gr8a66597;
int ret = 0;
R8A66597_DPRINT("%s\n", __func__);
R8A66597_DPRINT("pipe = %08x, buffer = %p, len = %d, devnum = %d\n",
pipe, buffer, transfer_len, dev->devnum);
set_devadd_reg(r8a66597, dev->devnum, r8a66597->speed, 0, 0, 0);
pipe_buffer_setting(r8a66597, dev, pipe);
dev->act_len = 0;
while (dev->act_len < transfer_len && ret == 0) {
if (ctrlc())
return -1;
if (usb_pipein(pipe))
ret = receive_bulk_packet(r8a66597, dev, pipe, buffer,
transfer_len);
else
ret = send_bulk_packet(r8a66597, dev, pipe, buffer,
transfer_len);
}
if (ret == 0)
dev->status = 0;
return ret;
}
int submit_control_msg(struct usb_device *dev, unsigned long pipe,
void *buffer, int transfer_len, struct devrequest *setup)
{
struct r8a66597 *r8a66597 = &gr8a66597;
u16 r8a66597_address = setup->request == USB_REQ_SET_ADDRESS ?
0 : dev->devnum;
R8A66597_DPRINT("%s\n", __func__);
if (usb_pipedevice(pipe) == r8a66597->rh_devnum)
return r8a66597_submit_rh_msg(dev, pipe, buffer, transfer_len,
setup);
R8A66597_DPRINT("%s: setup\n", __func__);
set_devadd_reg(r8a66597, r8a66597_address, r8a66597->speed, 0, 0, 0);
if (send_setup_packet(r8a66597, dev, setup) < 0) {
printf("setup packet send error\n");
return -1;
}
if (usb_pipein(pipe))
if (receive_control_packet(r8a66597, dev, buffer,
transfer_len) < 0)
return -1;
if (send_status_packet(r8a66597, pipe) < 0)
return -1;
dev->status = 0;
return 0;
}
int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
int transfer_len, int interval)
{
/* no implement */
R8A66597_DPRINT("%s\n", __func__);
return 0;
}
void usb_event_poll(void)
{
/* no implement */
R8A66597_DPRINT("%s\n", __func__);
}
int usb_lowlevel_init(void)
{
struct r8a66597 *r8a66597 = &gr8a66597;
R8A66597_DPRINT("%s\n", __func__);
memset(r8a66597, 0, sizeof(r8a66597));
r8a66597->reg = CONFIG_R8A66597_BASE_ADDR;
disable_controller(r8a66597);
wait_ms(100);
enable_controller(r8a66597);
r8a66597_port_power(r8a66597, 0 , 1);
/* check usb device */
check_usb_device_connecting(r8a66597);
wait_ms(50);
return 0;
}
int usb_lowlevel_stop(void)
{
disable_controller(&gr8a66597);
return 0;
}

659
drivers/usb/r8a66597.h Normal file
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@ -0,0 +1,659 @@
/*
* R8A66597 HCD (Host Controller Driver) for u-boot
*
* Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*
*/
#ifndef __R8A66597_H__
#define __R8A66597_H__
#define SYSCFG0 0x00
#define SYSCFG1 0x02
#define SYSSTS0 0x04
#define SYSSTS1 0x06
#define DVSTCTR0 0x08
#define DVSTCTR1 0x0A
#define TESTMODE 0x0C
#define PINCFG 0x0E
#define DMA0CFG 0x10
#define DMA1CFG 0x12
#define CFIFO 0x14
#define D0FIFO 0x18
#define D1FIFO 0x1C
#define CFIFOSEL 0x20
#define CFIFOCTR 0x22
#define CFIFOSIE 0x24
#define D0FIFOSEL 0x28
#define D0FIFOCTR 0x2A
#define D1FIFOSEL 0x2C
#define D1FIFOCTR 0x2E
#define INTENB0 0x30
#define INTENB1 0x32
#define INTENB2 0x34
#define BRDYENB 0x36
#define NRDYENB 0x38
#define BEMPENB 0x3A
#define SOFCFG 0x3C
#define INTSTS0 0x40
#define INTSTS1 0x42
#define INTSTS2 0x44
#define BRDYSTS 0x46
#define NRDYSTS 0x48
#define BEMPSTS 0x4A
#define FRMNUM 0x4C
#define UFRMNUM 0x4E
#define USBADDR 0x50
#define USBREQ 0x54
#define USBVAL 0x56
#define USBINDX 0x58
#define USBLENG 0x5A
#define DCPCFG 0x5C
#define DCPMAXP 0x5E
#define DCPCTR 0x60
#define PIPESEL 0x64
#define PIPECFG 0x68
#define PIPEBUF 0x6A
#define PIPEMAXP 0x6C
#define PIPEPERI 0x6E
#define PIPE1CTR 0x70
#define PIPE2CTR 0x72
#define PIPE3CTR 0x74
#define PIPE4CTR 0x76
#define PIPE5CTR 0x78
#define PIPE6CTR 0x7A
#define PIPE7CTR 0x7C
#define PIPE8CTR 0x7E
#define PIPE9CTR 0x80
#define PIPE1TRE 0x90
#define PIPE1TRN 0x92
#define PIPE2TRE 0x94
#define PIPE2TRN 0x96
#define PIPE3TRE 0x98
#define PIPE3TRN 0x9A
#define PIPE4TRE 0x9C
#define PIPE4TRN 0x9E
#define PIPE5TRE 0xA0
#define PIPE5TRN 0xA2
#define DEVADD0 0xD0
#define DEVADD1 0xD2
#define DEVADD2 0xD4
#define DEVADD3 0xD6
#define DEVADD4 0xD8
#define DEVADD5 0xDA
#define DEVADD6 0xDC
#define DEVADD7 0xDE
#define DEVADD8 0xE0
#define DEVADD9 0xE2
#define DEVADDA 0xE4
/* System Configuration Control Register */
#define XTAL 0xC000 /* b15-14: Crystal selection */
#define XTAL48 0x8000 /* 48MHz */
#define XTAL24 0x4000 /* 24MHz */
#define XTAL12 0x0000 /* 12MHz */
#define XCKE 0x2000 /* b13: External clock enable */
#define PLLC 0x0800 /* b11: PLL control */
#define SCKE 0x0400 /* b10: USB clock enable */
#define PCSDIS 0x0200 /* b9: not CS wakeup */
#define LPSME 0x0100 /* b8: Low power sleep mode */
#define HSE 0x0080 /* b7: Hi-speed enable */
#define DCFM 0x0040 /* b6: Controller function select */
#define DRPD 0x0020 /* b5: D+/- pull down control */
#define DPRPU 0x0010 /* b4: D+ pull up control */
#define USBE 0x0001 /* b0: USB module operation enable */
/* System Configuration Status Register */
#define OVCBIT 0x8000 /* b15-14: Over-current bit */
#define OVCMON 0xC000 /* b15-14: Over-current monitor */
#define SOFEA 0x0020 /* b5: SOF monitor */
#define IDMON 0x0004 /* b3: ID-pin monitor */
#define LNST 0x0003 /* b1-0: D+, D- line status */
#define SE1 0x0003 /* SE1 */
#define FS_KSTS 0x0002 /* Full-Speed K State */
#define FS_JSTS 0x0001 /* Full-Speed J State */
#define LS_JSTS 0x0002 /* Low-Speed J State */
#define LS_KSTS 0x0001 /* Low-Speed K State */
#define SE0 0x0000 /* SE0 */
/* Device State Control Register */
#define EXTLP0 0x0400 /* b10: External port */
#define VBOUT 0x0200 /* b9: VBUS output */
#define WKUP 0x0100 /* b8: Remote wakeup */
#define RWUPE 0x0080 /* b7: Remote wakeup sense */
#define USBRST 0x0040 /* b6: USB reset enable */
#define RESUME 0x0020 /* b5: Resume enable */
#define UACT 0x0010 /* b4: USB bus enable */
#define RHST 0x0007 /* b1-0: Reset handshake status */
#define HSPROC 0x0004 /* HS handshake is processing */
#define HSMODE 0x0003 /* Hi-Speed mode */
#define FSMODE 0x0002 /* Full-Speed mode */
#define LSMODE 0x0001 /* Low-Speed mode */
#define UNDECID 0x0000 /* Undecided */
/* Test Mode Register */
#define UTST 0x000F /* b3-0: Test select */
#define H_TST_PACKET 0x000C /* HOST TEST Packet */
#define H_TST_SE0_NAK 0x000B /* HOST TEST SE0 NAK */
#define H_TST_K 0x000A /* HOST TEST K */
#define H_TST_J 0x0009 /* HOST TEST J */
#define H_TST_NORMAL 0x0000 /* HOST Normal Mode */
#define P_TST_PACKET 0x0004 /* PERI TEST Packet */
#define P_TST_SE0_NAK 0x0003 /* PERI TEST SE0 NAK */
#define P_TST_K 0x0002 /* PERI TEST K */
#define P_TST_J 0x0001 /* PERI TEST J */
#define P_TST_NORMAL 0x0000 /* PERI Normal Mode */
/* Data Pin Configuration Register */
#define LDRV 0x8000 /* b15: Drive Current Adjust */
#define VIF1 0x0000 /* VIF = 1.8V */
#define VIF3 0x8000 /* VIF = 3.3V */
#define INTA 0x0001 /* b1: USB INT-pin active */
/* DMAx Pin Configuration Register */
#define DREQA 0x4000 /* b14: Dreq active select */
#define BURST 0x2000 /* b13: Burst mode */
#define DACKA 0x0400 /* b10: Dack active select */
#define DFORM 0x0380 /* b9-7: DMA mode select */
#define CPU_ADR_RD_WR 0x0000 /* Address + RD/WR mode (CPU bus) */
#define CPU_DACK_RD_WR 0x0100 /* DACK + RD/WR mode (CPU bus) */
#define CPU_DACK_ONLY 0x0180 /* DACK only mode (CPU bus) */
#define SPLIT_DACK_ONLY 0x0200 /* DACK only mode (SPLIT bus) */
#define DENDA 0x0040 /* b6: Dend active select */
#define PKTM 0x0020 /* b5: Packet mode */
#define DENDE 0x0010 /* b4: Dend enable */
#define OBUS 0x0004 /* b2: OUTbus mode */
/* CFIFO/DxFIFO Port Select Register */
#define RCNT 0x8000 /* b15: Read count mode */
#define REW 0x4000 /* b14: Buffer rewind */
#define DCLRM 0x2000 /* b13: DMA buffer clear mode */
#define DREQE 0x1000 /* b12: DREQ output enable */
#if defined(CONFIG_SUPERH_ON_CHIP_R8A66597)
#define MBW 0x0800
#else
#define MBW 0x0400 /* b10: Maximum bit width for FIFO access */
#endif
#define MBW_8 0x0000 /* 8bit */
#define MBW_16 0x0400 /* 16bit */
#define BIGEND 0x0100 /* b8: Big endian mode */
#define BYTE_LITTLE 0x0000 /* little dendian */
#define BYTE_BIG 0x0100 /* big endifan */
#define ISEL 0x0020 /* b5: DCP FIFO port direction select */
#define CURPIPE 0x000F /* b2-0: PIPE select */
/* CFIFO/DxFIFO Port Control Register */
#define BVAL 0x8000 /* b15: Buffer valid flag */
#define BCLR 0x4000 /* b14: Buffer clear */
#define FRDY 0x2000 /* b13: FIFO ready */
#define DTLN 0x0FFF /* b11-0: FIFO received data length */
/* Interrupt Enable Register 0 */
#define VBSE 0x8000 /* b15: VBUS interrupt */
#define RSME 0x4000 /* b14: Resume interrupt */
#define SOFE 0x2000 /* b13: Frame update interrupt */
#define DVSE 0x1000 /* b12: Device state transition interrupt */
#define CTRE 0x0800 /* b11: Control transfer stage transition interrupt */
#define BEMPE 0x0400 /* b10: Buffer empty interrupt */
#define NRDYE 0x0200 /* b9: Buffer not ready interrupt */
#define BRDYE 0x0100 /* b8: Buffer ready interrupt */
/* Interrupt Enable Register 1 */
#define OVRCRE 0x8000 /* b15: Over-current interrupt */
#define BCHGE 0x4000 /* b14: USB us chenge interrupt */
#define DTCHE 0x1000 /* b12: Detach sense interrupt */
#define ATTCHE 0x0800 /* b11: Attach sense interrupt */
#define EOFERRE 0x0040 /* b6: EOF error interrupt */
#define SIGNE 0x0020 /* b5: SETUP IGNORE interrupt */
#define SACKE 0x0010 /* b4: SETUP ACK interrupt */
/* BRDY Interrupt Enable/Status Register */
#define BRDY9 0x0200 /* b9: PIPE9 */
#define BRDY8 0x0100 /* b8: PIPE8 */
#define BRDY7 0x0080 /* b7: PIPE7 */
#define BRDY6 0x0040 /* b6: PIPE6 */
#define BRDY5 0x0020 /* b5: PIPE5 */
#define BRDY4 0x0010 /* b4: PIPE4 */
#define BRDY3 0x0008 /* b3: PIPE3 */
#define BRDY2 0x0004 /* b2: PIPE2 */
#define BRDY1 0x0002 /* b1: PIPE1 */
#define BRDY0 0x0001 /* b1: PIPE0 */
/* NRDY Interrupt Enable/Status Register */
#define NRDY9 0x0200 /* b9: PIPE9 */
#define NRDY8 0x0100 /* b8: PIPE8 */
#define NRDY7 0x0080 /* b7: PIPE7 */
#define NRDY6 0x0040 /* b6: PIPE6 */
#define NRDY5 0x0020 /* b5: PIPE5 */
#define NRDY4 0x0010 /* b4: PIPE4 */
#define NRDY3 0x0008 /* b3: PIPE3 */
#define NRDY2 0x0004 /* b2: PIPE2 */
#define NRDY1 0x0002 /* b1: PIPE1 */
#define NRDY0 0x0001 /* b1: PIPE0 */
/* BEMP Interrupt Enable/Status Register */
#define BEMP9 0x0200 /* b9: PIPE9 */
#define BEMP8 0x0100 /* b8: PIPE8 */
#define BEMP7 0x0080 /* b7: PIPE7 */
#define BEMP6 0x0040 /* b6: PIPE6 */
#define BEMP5 0x0020 /* b5: PIPE5 */
#define BEMP4 0x0010 /* b4: PIPE4 */
#define BEMP3 0x0008 /* b3: PIPE3 */
#define BEMP2 0x0004 /* b2: PIPE2 */
#define BEMP1 0x0002 /* b1: PIPE1 */
#define BEMP0 0x0001 /* b0: PIPE0 */
/* SOF Pin Configuration Register */
#define TRNENSEL 0x0100 /* b8: Select transaction enable period */
#define BRDYM 0x0040 /* b6: BRDY clear timing */
#define INTL 0x0020 /* b5: Interrupt sense select */
#define EDGESTS 0x0010 /* b4: */
#define SOFMODE 0x000C /* b3-2: SOF pin select */
#define SOF_125US 0x0008 /* SOF OUT 125us Frame Signal */
#define SOF_1MS 0x0004 /* SOF OUT 1ms Frame Signal */
#define SOF_DISABLE 0x0000 /* SOF OUT Disable */
/* Interrupt Status Register 0 */
#define VBINT 0x8000 /* b15: VBUS interrupt */
#define RESM 0x4000 /* b14: Resume interrupt */
#define SOFR 0x2000 /* b13: SOF frame update interrupt */
#define DVST 0x1000 /* b12: Device state transition interrupt */
#define CTRT 0x0800 /* b11: Control transfer stage transition interrupt */
#define BEMP 0x0400 /* b10: Buffer empty interrupt */
#define NRDY 0x0200 /* b9: Buffer not ready interrupt */
#define BRDY 0x0100 /* b8: Buffer ready interrupt */
#define VBSTS 0x0080 /* b7: VBUS input port */
#define DVSQ 0x0070 /* b6-4: Device state */
#define DS_SPD_CNFG 0x0070 /* Suspend Configured */
#define DS_SPD_ADDR 0x0060 /* Suspend Address */
#define DS_SPD_DFLT 0x0050 /* Suspend Default */
#define DS_SPD_POWR 0x0040 /* Suspend Powered */
#define DS_SUSP 0x0040 /* Suspend */
#define DS_CNFG 0x0030 /* Configured */
#define DS_ADDS 0x0020 /* Address */
#define DS_DFLT 0x0010 /* Default */
#define DS_POWR 0x0000 /* Powered */
#define DVSQS 0x0030 /* b5-4: Device state */
#define VALID 0x0008 /* b3: Setup packet detected flag */
#define CTSQ 0x0007 /* b2-0: Control transfer stage */
#define CS_SQER 0x0006 /* Sequence error */
#define CS_WRND 0x0005 /* Control write nodata status stage */
#define CS_WRSS 0x0004 /* Control write status stage */
#define CS_WRDS 0x0003 /* Control write data stage */
#define CS_RDSS 0x0002 /* Control read status stage */
#define CS_RDDS 0x0001 /* Control read data stage */
#define CS_IDST 0x0000 /* Idle or setup stage */
/* Interrupt Status Register 1 */
#define OVRCR 0x8000 /* b15: Over-current interrupt */
#define BCHG 0x4000 /* b14: USB bus chenge interrupt */
#define DTCH 0x1000 /* b12: Detach sense interrupt */
#define ATTCH 0x0800 /* b11: Attach sense interrupt */
#define EOFERR 0x0040 /* b6: EOF-error interrupt */
#define SIGN 0x0020 /* b5: Setup ignore interrupt */
#define SACK 0x0010 /* b4: Setup acknowledge interrupt */
/* Frame Number Register */
#define OVRN 0x8000 /* b15: Overrun error */
#define CRCE 0x4000 /* b14: Received data error */
#define FRNM 0x07FF /* b10-0: Frame number */
/* Micro Frame Number Register */
#define UFRNM 0x0007 /* b2-0: Micro frame number */
/* Default Control Pipe Maxpacket Size Register */
/* Pipe Maxpacket Size Register */
#define DEVSEL 0xF000 /* b15-14: Device address select */
#define MAXP 0x007F /* b6-0: Maxpacket size of default control pipe */
/* Default Control Pipe Control Register */
#define BSTS 0x8000 /* b15: Buffer status */
#define SUREQ 0x4000 /* b14: Send USB request */
#define CSCLR 0x2000 /* b13: complete-split status clear */
#define CSSTS 0x1000 /* b12: complete-split status */
#define SUREQCLR 0x0800 /* b11: stop setup request */
#define SQCLR 0x0100 /* b8: Sequence toggle bit clear */
#define SQSET 0x0080 /* b7: Sequence toggle bit set */
#define SQMON 0x0040 /* b6: Sequence toggle bit monitor */
#define PBUSY 0x0020 /* b5: pipe busy */
#define PINGE 0x0010 /* b4: ping enable */
#define CCPL 0x0004 /* b2: Enable control transfer complete */
#define PID 0x0003 /* b1-0: Response PID */
#define PID_STALL11 0x0003 /* STALL */
#define PID_STALL 0x0002 /* STALL */
#define PID_BUF 0x0001 /* BUF */
#define PID_NAK 0x0000 /* NAK */
/* Pipe Window Select Register */
#define PIPENM 0x0007 /* b2-0: Pipe select */
/* Pipe Configuration Register */
#define R8A66597_TYP 0xC000 /* b15-14: Transfer type */
#define R8A66597_ISO 0xC000 /* Isochronous */
#define R8A66597_INT 0x8000 /* Interrupt */
#define R8A66597_BULK 0x4000 /* Bulk */
#define R8A66597_BFRE 0x0400 /* b10: Buffer ready interrupt mode select */
#define R8A66597_DBLB 0x0200 /* b9: Double buffer mode select */
#define R8A66597_CNTMD 0x0100 /* b8: Continuous transfer mode select */
#define R8A66597_SHTNAK 0x0080 /* b7: Transfer end NAK */
#define R8A66597_DIR 0x0010 /* b4: Transfer direction select */
#define R8A66597_EPNUM 0x000F /* b3-0: Eendpoint number select */
/* Pipe Buffer Configuration Register */
#define BUFSIZE 0x7C00 /* b14-10: Pipe buffer size */
#define BUFNMB 0x007F /* b6-0: Pipe buffer number */
#define PIPE0BUF 256
#define PIPExBUF 64
/* Pipe Maxpacket Size Register */
#define MXPS 0x07FF /* b10-0: Maxpacket size */
/* Pipe Cycle Configuration Register */
#define IFIS 0x1000 /* b12: Isochronous in-buffer flush mode select */
#define IITV 0x0007 /* b2-0: Isochronous interval */
/* Pipex Control Register */
#define BSTS 0x8000 /* b15: Buffer status */
#define INBUFM 0x4000 /* b14: IN buffer monitor (Only for PIPE1 to 5) */
#define CSCLR 0x2000 /* b13: complete-split status clear */
#define CSSTS 0x1000 /* b12: complete-split status */
#define ATREPM 0x0400 /* b10: Auto repeat mode */
#define ACLRM 0x0200 /* b9: Out buffer auto clear mode */
#define SQCLR 0x0100 /* b8: Sequence toggle bit clear */
#define SQSET 0x0080 /* b7: Sequence toggle bit set */
#define SQMON 0x0040 /* b6: Sequence toggle bit monitor */
#define PBUSY 0x0020 /* b5: pipe busy */
#define PID 0x0003 /* b1-0: Response PID */
/* PIPExTRE */
#define TRENB 0x0200 /* b9: Transaction counter enable */
#define TRCLR 0x0100 /* b8: Transaction counter clear */
/* PIPExTRN */
#define TRNCNT 0xFFFF /* b15-0: Transaction counter */
/* DEVADDx */
#define UPPHUB 0x7800
#define HUBPORT 0x0700
#define USBSPD 0x00C0
#define RTPORT 0x0001
#define R8A66597_MAX_NUM_PIPE 10
#define R8A66597_BUF_BSIZE 8
#define R8A66597_MAX_DEVICE 10
#if defined(CONFIG_SUPERH_ON_CHIP_R8A66597)
#define R8A66597_MAX_ROOT_HUB 1
#else
#define R8A66597_MAX_ROOT_HUB 2
#endif
#define R8A66597_MAX_SAMPLING 5
#define R8A66597_RH_POLL_TIME 10
#define BULK_IN_PIPENUM 3
#define BULK_IN_BUFNUM 8
#define BULK_OUT_PIPENUM 4
#define BULK_OUT_BUFNUM 40
#define check_bulk_or_isoc(pipenum) ((pipenum >= 1 && pipenum <= 5))
#define check_interrupt(pipenum) ((pipenum >= 6 && pipenum <= 9))
#define make_devsel(addr) (addr << 12)
struct r8a66597 {
unsigned long reg;
unsigned short pipe_config; /* bit field */
unsigned short port_status;
unsigned short port_change;
u16 speed; /* HSMODE or FSMODE or LSMODE */
unsigned char rh_devnum;
};
static inline u16 r8a66597_read(struct r8a66597 *r8a66597, unsigned long offset)
{
return inw(r8a66597->reg + offset);
}
static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597,
unsigned long offset, void *buf,
int len)
{
int i;
#if defined(CONFIG_SUPERH_ON_CHIP_R8A66597)
unsigned long fifoaddr = r8a66597->reg + offset;
unsigned long count;
unsigned long *p = buf;
count = len / 4;
for (i = 0; i < count; i++)
inl(p[i], r8a66597->reg + offset);
if (len & 0x00000003) {
unsigned long tmp = inl(fifoaddr);
memcpy((unsigned char *)buf + count * 4, &tmp, len & 0x03);
}
#else
unsigned short *p = buf;
len = (len + 1) / 2;
for (i = 0; i < len; i++)
p[i] = inw(r8a66597->reg + offset);
#endif
}
static inline void r8a66597_write(struct r8a66597 *r8a66597, u16 val,
unsigned long offset)
{
outw(val, r8a66597->reg + offset);
}
static inline void r8a66597_write_fifo(struct r8a66597 *r8a66597,
unsigned long offset, void *buf,
int len)
{
int i;
unsigned long fifoaddr = r8a66597->reg + offset;
#if defined(CONFIG_SUPERH_ON_CHIP_R8A66597)
unsigned long count;
unsigned char *pb;
unsigned long *p = buf;
count = len / 4;
for (i = 0; i < count; i++)
outl(p[i], fifoaddr);
if (len & 0x00000003) {
pb = (unsigned char *)buf + count * 4;
for (i = 0; i < (len & 0x00000003); i++) {
if (r8a66597_read(r8a66597, CFIFOSEL) & BIGEND)
outb(pb[i], fifoaddr + i);
else
outb(pb[i], fifoaddr + 3 - i);
}
}
#else
int odd = len & 0x0001;
unsigned short *p = buf;
len = len / 2;
for (i = 0; i < len; i++)
outw(p[i], fifoaddr);
if (odd) {
unsigned char *pb = (unsigned char *)(buf + len);
outb(*pb, fifoaddr);
}
#endif
}
static inline void r8a66597_mdfy(struct r8a66597 *r8a66597,
u16 val, u16 pat, unsigned long offset)
{
u16 tmp;
tmp = r8a66597_read(r8a66597, offset);
tmp = tmp & (~pat);
tmp = tmp | val;
r8a66597_write(r8a66597, tmp, offset);
}
#define r8a66597_bclr(r8a66597, val, offset) \
r8a66597_mdfy(r8a66597, 0, val, offset)
#define r8a66597_bset(r8a66597, val, offset) \
r8a66597_mdfy(r8a66597, val, 0, offset)
static inline unsigned long get_syscfg_reg(int port)
{
return port == 0 ? SYSCFG0 : SYSCFG1;
}
static inline unsigned long get_syssts_reg(int port)
{
return port == 0 ? SYSSTS0 : SYSSTS1;
}
static inline unsigned long get_dvstctr_reg(int port)
{
return port == 0 ? DVSTCTR0 : DVSTCTR1;
}
static inline unsigned long get_dmacfg_reg(int port)
{
return port == 0 ? DMA0CFG : DMA1CFG;
}
static inline unsigned long get_intenb_reg(int port)
{
return port == 0 ? INTENB1 : INTENB2;
}
static inline unsigned long get_intsts_reg(int port)
{
return port == 0 ? INTSTS1 : INTSTS2;
}
static inline u16 get_rh_usb_speed(struct r8a66597 *r8a66597, int port)
{
unsigned long dvstctr_reg = get_dvstctr_reg(port);
return r8a66597_read(r8a66597, dvstctr_reg) & RHST;
}
static inline void r8a66597_port_power(struct r8a66597 *r8a66597, int port,
int power)
{
unsigned long dvstctr_reg = get_dvstctr_reg(port);
if (power)
r8a66597_bset(r8a66597, VBOUT, dvstctr_reg);
else
r8a66597_bclr(r8a66597, VBOUT, dvstctr_reg);
}
#define get_pipectr_addr(pipenum) (PIPE1CTR + (pipenum - 1) * 2)
#define get_pipetre_addr(pipenum) (PIPE1TRE + (pipenum - 1) * 4)
#define get_pipetrn_addr(pipenum) (PIPE1TRN + (pipenum - 1) * 4)
#define get_devadd_addr(address) (DEVADD0 + address * 2)
/* USB HUB CONSTANTS (not OHCI-specific; see hub.h, based on usb_ohci.h) */
/* destination of request */
#define RH_INTERFACE 0x01
#define RH_ENDPOINT 0x02
#define RH_OTHER 0x03
#define RH_CLASS 0x20
#define RH_VENDOR 0x40
/* Requests: bRequest << 8 | bmRequestType */
#define RH_GET_STATUS 0x0080
#define RH_CLEAR_FEATURE 0x0100
#define RH_SET_FEATURE 0x0300
#define RH_SET_ADDRESS 0x0500
#define RH_GET_DESCRIPTOR 0x0680
#define RH_SET_DESCRIPTOR 0x0700
#define RH_GET_CONFIGURATION 0x0880
#define RH_SET_CONFIGURATION 0x0900
#define RH_GET_STATE 0x0280
#define RH_GET_INTERFACE 0x0A80
#define RH_SET_INTERFACE 0x0B00
#define RH_SYNC_FRAME 0x0C80
/* Our Vendor Specific Request */
#define RH_SET_EP 0x2000
/* Hub port features */
#define RH_PORT_CONNECTION 0x00
#define RH_PORT_ENABLE 0x01
#define RH_PORT_SUSPEND 0x02
#define RH_PORT_OVER_CURRENT 0x03
#define RH_PORT_RESET 0x04
#define RH_PORT_POWER 0x08
#define RH_PORT_LOW_SPEED 0x09
#define RH_C_PORT_CONNECTION 0x10
#define RH_C_PORT_ENABLE 0x11
#define RH_C_PORT_SUSPEND 0x12
#define RH_C_PORT_OVER_CURRENT 0x13
#define RH_C_PORT_RESET 0x14
/* Hub features */
#define RH_C_HUB_LOCAL_POWER 0x00
#define RH_C_HUB_OVER_CURRENT 0x01
#define RH_DEVICE_REMOTE_WAKEUP 0x00
#define RH_ENDPOINT_STALL 0x01
#define RH_ACK 0x01
#define RH_REQ_ERR -1
#define RH_NACK 0x00
/* OHCI ROOT HUB REGISTER MASKS */
/* roothub.portstatus [i] bits */
#define RH_PS_CCS 0x00000001 /* current connect status */
#define RH_PS_PES 0x00000002 /* port enable status*/
#define RH_PS_PSS 0x00000004 /* port suspend status */
#define RH_PS_POCI 0x00000008 /* port over current indicator */
#define RH_PS_PRS 0x00000010 /* port reset status */
#define RH_PS_PPS 0x00000100 /* port power status */
#define RH_PS_LSDA 0x00000200 /* low speed device attached */
#define RH_PS_CSC 0x00010000 /* connect status change */
#define RH_PS_PESC 0x00020000 /* port enable status change */
#define RH_PS_PSSC 0x00040000 /* port suspend status change */
#define RH_PS_OCIC 0x00080000 /* over current indicator change */
#define RH_PS_PRSC 0x00100000 /* port reset status change */
/* roothub.status bits */
#define RH_HS_LPS 0x00000001 /* local power status */
#define RH_HS_OCI 0x00000002 /* over current indicator */
#define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */
#define RH_HS_LPSC 0x00010000 /* local power status change */
#define RH_HS_OCIC 0x00020000 /* over current indicator change */
#define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */
/* roothub.b masks */
#define RH_B_DR 0x0000ffff /* device removable flags */
#define RH_B_PPCM 0xffff0000 /* port power control mask */
/* roothub.a masks */
#define RH_A_NDP (0xff << 0) /* number of downstream ports */
#define RH_A_PSM (1 << 8) /* power switching mode */
#define RH_A_NPS (1 << 9) /* no power switching */
#define RH_A_DT (1 << 10) /* device type (mbz) */
#define RH_A_OCPM (1 << 11) /* over current protection mode */
#define RH_A_NOCP (1 << 12) /* no over current protection */
#define RH_A_POTPGT (0xff << 24) /* power on to power good time */
#endif /* __R8A66597_H__ */

28
drivers/usb/usbdcore_omap1510.c
View File

@ -28,7 +28,7 @@
#include <common.h>
#if defined(CONFIG_OMAP1510) && defined(CONFIG_USB_DEVICE)
#if ((defined(CONFIG_OMAP1510) || defined(CONFIG_OMAP1610)) && defined(CONFIG_USB_DEVICE))
#include <asm/io.h>
#ifdef CONFIG_OMAP_SX1
@ -1109,21 +1109,43 @@ int udc_init (void)
*/
outw ((1 << 4) | (1 << 5), CLOCK_CTRL);
UDCREG (CLOCK_CTRL);
#ifdef CONFIG_OMAP1510
/* This code was originally implemented for OMAP1510 and
* therefore is only applicable for OMAP1510 boards. For
* OMAP5912 or OMAP16xx the register APLL_CTRL does not
* exist and DPLL_CTRL is already configured.
*/
/* Set and check APLL */
outw (0x0008, APLL_CTRL);
UDCREG (APLL_CTRL);
/* Set and check DPLL */
outw (0x2210, DPLL_CTRL);
UDCREG (DPLL_CTRL);
/* Set and check SOFT */
outw ((1 << 4) | (1 << 3) | 1, SOFT_REQ);
#endif
/* Set and check SOFT
* The below line of code has been changed to perform a
* read-modify-write instead of a simple write for
* configuring the SOFT_REQ register. This allows the code
* to be compatible with OMAP5912 and OMAP16xx devices
*/
outw ((1 << 4) | (1 << 3) | 1 | (inw(SOFT_REQ)), SOFT_REQ);
/* Short delay to wait for DPLL */
udelay (1000);
/* Print banner with device revision */
udc_rev = inw (UDC_REV) & 0xff;
#ifdef CONFIG_OMAP1510
printf ("USB: TI OMAP1510 USB function module rev %d.%d\n",
udc_rev >> 4, udc_rev & 0xf);
#endif
#ifdef CONFIG_OMAP1610
printf ("USB: TI OMAP5912 USB function module rev %d.%d\n",
udc_rev >> 4, udc_rev & 0xf);
#endif
#ifdef CONFIG_OMAP_SX1
i2c_read (0x32, 0x04, 1, &value, 1);

63
drivers/video/cfb_console.c
View File

@ -751,24 +751,10 @@ void video_puts (const char *s)
fb ++; \
}
#if !defined(VIDEO_FB_16BPP_PIXEL_SWAP)
#define FILL_15BIT_555RGB(r,g,b) { \
*(unsigned short *)fb = SWAP16((unsigned short)(((r>>3)<<10) | ((g>>3)<<5) | (b>>3))); \
fb += 2; \
}
#else
static int tgl;
static unsigned short p0;
#define FILL_15BIT_555RGB(r,g,b) { \
if (!tgl++) { \
p0 = SWAP16((unsigned short)(((r>>3)<<10) | ((g>>3)<<5) | (b>>3))); \
} else { \
tgl=0; \
*(unsigned long *)(fb-2) = (SWAP16((unsigned short)(((r>>3)<<10) | ((g>>3)<<5) | (b>>3)))<<16) | p0; \
} \
fb += 2; \
}
#endif
#define FILL_16BIT_565RGB(r,g,b) { \
*(unsigned short *)fb = SWAP16((unsigned short)((((r)>>3)<<11) | (((g)>>2)<<5) | ((b)>>3))); \
@ -796,6 +782,20 @@ static unsigned short p0;
}
#endif
#if defined(VIDEO_FB_16BPP_PIXEL_SWAP)
static void inline fill_555rgb_pswap(uchar *fb, int x,
u8 r, u8 g, u8 b)
{
ushort *dst = (ushort *)fb;
ushort color = (ushort)(((r >> 3) << 10) |
((g >> 3) << 5) |
(b >> 3));
if (x & 1)
*(--dst) = color;
else
*(++dst) = color;
}
#endif
/*
* Display the BMP file located at address bmp_image.
@ -927,11 +927,20 @@ int video_display_bitmap (ulong bmp_image, int x, int y)
break;
case GDF_15BIT_555RGB:
while (ycount--) {
#if defined(VIDEO_FB_16BPP_PIXEL_SWAP)
int xpos = x;
#endif
WATCHDOG_RESET ();
xcount = width;
while (xcount--) {
cte = bmp->color_table[*bmap++];
#if !defined(VIDEO_FB_16BPP_PIXEL_SWAP)
FILL_15BIT_555RGB (cte.red, cte.green, cte.blue);
#else
fill_555rgb_pswap (fb, xpos++, cte.red,
cte.green, cte.blue);
fb += 2;
#endif
}
bmap += padded_line;
fb -= (VIDEO_VISIBLE_COLS + width) * VIDEO_PIXEL_SIZE;
@ -993,10 +1002,19 @@ int video_display_bitmap (ulong bmp_image, int x, int y)
break;
case GDF_15BIT_555RGB:
while (ycount--) {
#if defined(VIDEO_FB_16BPP_PIXEL_SWAP)
int xpos = x;
#endif
WATCHDOG_RESET ();
xcount = width;
while (xcount--) {
#if !defined(VIDEO_FB_16BPP_PIXEL_SWAP)
FILL_15BIT_555RGB (bmap[2], bmap[1], bmap[0]);
#else
fill_555rgb_pswap (fb, xpos++, bmap[2],
bmap[1], bmap[0]);
fb += 2;
#endif
bmap += 3;
}
bmap += padded_line;
@ -1071,7 +1089,9 @@ void logo_plot (void *screen, int width, int x, int y)
int ycount = VIDEO_LOGO_HEIGHT;
unsigned char r, g, b, *logo_red, *logo_blue, *logo_green;
unsigned char *source;
unsigned char *dest = (unsigned char *)screen + ((y * width * VIDEO_PIXEL_SIZE) + x);
unsigned char *dest = (unsigned char *)screen +
((y * width * VIDEO_PIXEL_SIZE) +
x * VIDEO_PIXEL_SIZE);
#ifdef CONFIG_VIDEO_BMP_LOGO
source = bmp_logo_bitmap;
@ -1101,6 +1121,9 @@ void logo_plot (void *screen, int width, int x, int y)
}
while (ycount--) {
#if defined(VIDEO_FB_16BPP_PIXEL_SWAP)
int xpos = x;
#endif
xcount = VIDEO_LOGO_WIDTH;
while (xcount--) {
r = logo_red[*source - VIDEO_LOGO_LUT_OFFSET];
@ -1119,15 +1142,7 @@ void logo_plot (void *screen, int width, int x, int y)
*(unsigned short *) dest =
SWAP16 ((unsigned short) (((r >> 3) << 10) | ((g >> 3) << 5) | (b >> 3)));
#else
{
if (!tgl++) {
p0 = SWAP16 ((unsigned short) (((r >> 3) << 10) | ((g >> 3) << 5) | (b >> 3)));
} else {
*(unsigned long *)(dest-2) =
(SWAP16 ((unsigned short) (((r >> 3) << 10) | ((g >> 3) << 5) | (b >> 3)))<<16) | p0;
tgl=0;
}
}
fill_555rgb_pswap (dest, xpos++, r, g, b);
#endif
break;
case GDF_16BIT_565RGB:

31
include/asm-arm/arch-mx31/mx31-regs.h
View File

@ -126,17 +126,32 @@
#define MUX_CTL_CSPI2_SS2 0x87
#define MUX_CTL_CSPI2_MOSI 0x8b
/* The modes a specific pin can be in
* these macros can be used in mx31_gpio_mux() and have the form
/*
* Helper macros for the MUX_[contact name]__[pin function] macros
*/
#define IOMUX_MODE_POS 9
#define IOMUX_MODE(contact, mode) (((mode) << IOMUX_MODE_POS) | (contact))
/*
* These macros can be used in mx31_gpio_mux() and have the form
* MUX_[contact name]__[pin function]
*/
#define MUX_RXD1__UART1_RXD_MUX ((MUX_CTL_FUNC << 8) | MUX_CTL_RXD1)
#define MUX_TXD1__UART1_TXD_MUX ((MUX_CTL_FUNC << 8) | MUX_CTL_TXD1)
#define MUX_RTS1__UART1_RTS_B ((MUX_CTL_FUNC << 8) | MUX_CTL_RTS1)
#define MUX_RTS1__UART1_CTS_B ((MUX_CTL_FUNC << 8) | MUX_CTL_CTS1)
#define MUX_RXD1__UART1_RXD_MUX IOMUX_MODE(MUX_CTL_RXD1, MUX_CTL_FUNC)
#define MUX_TXD1__UART1_TXD_MUX IOMUX_MODE(MUX_CTL_TXD1, MUX_CTL_FUNC)
#define MUX_RTS1__UART1_RTS_B IOMUX_MODE(MUX_CTL_RTS1, MUX_CTL_FUNC)
#define MUX_CTS1__UART1_CTS_B IOMUX_MODE(MUX_CTL_CTS1, MUX_CTL_FUNC)
#define MUX_CSPI2_MOSI__I2C2_SCL ((MUX_CTL_ALT1 << 8) | MUX_CTL_CSPI2_MOSI)
#define MUX_CSPI2_MISO__I2C2_SCL ((MUX_CTL_ALT1 << 8) | MUX_CTL_CSPI2_MISO)
#define MUX_CSPI2_SS0__CSPI2_SS0_B IOMUX_MODE(MUX_CTL_CSPI2_SS0, MUX_CTL_FUNC)
#define MUX_CSPI2_SS1__CSPI2_SS1_B IOMUX_MODE(MUX_CTL_CSPI2_SS1, MUX_CTL_FUNC)
#define MUX_CSPI2_SS2__CSPI2_SS2_B IOMUX_MODE(MUX_CTL_CSPI2_SS2, MUX_CTL_FUNC)
#define MUX_CSPI2_MOSI__CSPI2_MOSI IOMUX_MODE(MUX_CTL_CSPI2_MOSI, MUX_CTL_FUNC)
#define MUX_CSPI2_MISO__CSPI2_MISO IOMUX_MODE(MUX_CTL_CSPI2_MISO, MUX_CTL_FUNC)
#define MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B \
IOMUX_MODE(MUX_CTL_CSPI2_SPI_RDY, MUX_CTL_FUNC)
#define MUX_CSPI2_SCLK__CSPI2_CLK IOMUX_MODE(MUX_CTL_CSPI2_SCLK, MUX_CTL_FUNC)
#define MUX_CSPI2_MOSI__I2C2_SCL IOMUX_MODE(MUX_CTL_CSPI2_MOSI, MUX_CTL_ALT1)
#define MUX_CSPI2_MISO__I2C2_SDA IOMUX_MODE(MUX_CTL_CSPI2_MISO, MUX_CTL_ALT1)
/*
* Memory regions and CS

41
include/configs/FPS850L.h
View File

@ -1,5 +1,5 @@
/*
* (C) Copyright 2000
* (C) Copyright 2000-2008
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
@ -65,10 +65,17 @@
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/fps850L/uImage\0" \
"hostname=FPS850L\0" \
"bootfile=FPS850L/uImage\0" \
"fdt_addr=40040000\0" \
"kernel_addr=40060000\0" \
"ramdisk_addr=40200000\0" \
"u-boot=FPS850L/u-image.bin\0" \
"load=tftp 200000 ${u-boot}\0" \
"update=prot off 40000000 +${filesize};" \
"era 40000000 +${filesize};" \
"cp.b 200000 40000000 ${filesize};" \
"sete filesize;save\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
@ -106,10 +113,14 @@
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_NFS
#define CONFIG_CMD_SNTP
#define CONFIG_NETCONSOLE
/*
* Miscellaneous configurable options
*/
@ -180,11 +191,15 @@
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
/* use CFI flash driver */
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE+flash_info[0].size }
#define CFG_FLASH_EMPTY_INFO
#define CFG_FLASH_USE_BUFFER_WRITE 1
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
@ -194,6 +209,20 @@
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
/*-----------------------------------------------------------------------
* Dynamic MTD partition support
*/
#define CONFIG_JFFS2_CMDLINE
#define MTDIDS_DEFAULT "nor0=TQM8xxL-0"
#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \
"128k(dtb)," \
"1664k(kernel)," \
"2m(rootfs)," \
"4m(data)"
/*-----------------------------------------------------------------------
* Hardware Information Block
*/

87
include/configs/FPS860L.h
View File

@ -1,5 +1,5 @@
/*
* (C) Copyright 2000-2005
* (C) Copyright 2000-2008
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
@ -65,10 +65,17 @@
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/fps850L/uImage\0" \
"hostname=FPS860L\0" \
"bootfile=FPS860L/uImage\0" \
"fdt_addr=40040000\0" \
"kernel_addr=40060000\0" \
"ramdisk_addr=40200000\0" \
"u-boot=FPS860L/u-image.bin\0" \
"load=tftp 200000 ${u-boot}\0" \
"update=prot off 40000000 +${filesize};" \
"era 40000000 +${filesize};" \
"cp.b 200000 40000000 ${filesize};" \
"sete filesize;save\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
@ -106,10 +113,14 @@
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_NFS
#define CONFIG_CMD_SNTP
#define CONFIG_NETCONSOLE
/*
* Miscellaneous configurable options
*/
@ -180,11 +191,15 @@
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
/* use CFI flash driver */
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE+flash_info[0].size }
#define CFG_FLASH_EMPTY_INFO
#define CFG_FLASH_USE_BUFFER_WRITE 1
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
@ -194,6 +209,20 @@
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
/*-----------------------------------------------------------------------
* Dynamic MTD partition support
*/
#define CONFIG_JFFS2_CMDLINE
#define MTDIDS_DEFAULT "nor0=TQM8xxL-0"
#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \
"128k(dtb)," \
"1664k(kernel)," \
"2m(rootfs)," \
"4m(data)"
/*-----------------------------------------------------------------------
* Hardware Information Block
*/
@ -306,9 +335,11 @@
#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \
OR_SCY_5_CLK | OR_EHTR)
/*
* FLASH timing:
*/
#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
OR_SCY_3_CLK | OR_EHTR | OR_BI)
#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
@ -337,12 +368,42 @@
/*
* Memory Periodic Timer Prescaler
*
* The Divider for PTA (refresh timer) configuration is based on an
* example SDRAM configuration (64 MBit, one bank). The adjustment to
* the number of chip selects (NCS) and the actually needed refresh
* rate is done by setting MPTPR.
*
* PTA is calculated from
* PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
*
* gclk CPU clock (not bus clock!)
* Trefresh Refresh cycle * 4 (four word bursts used)
*
* 4096 Rows from SDRAM example configuration
* 1000 factor s -> ms
* 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
* 4 Number of refresh cycles per period
* 64 Refresh cycle in ms per number of rows
* --------------------------------------------
* Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
*
* 50 MHz => 50.000.000 / Divider = 98
* 66 Mhz => 66.000.000 / Divider = 129
* 80 Mhz => 80.000.000 / Divider = 156
*/
/* periodic timer for refresh */
#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */
#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
#define CFG_MAMR_PTA 98
/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
/*
* For 16 MBit, refresh rates could be 31.3 us
* (= 64 ms / 2K = 125 / quad bursts).
* For a simpler initialization, 15.6 us is used instead.
*
* #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
* #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
*/
#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
@ -372,4 +433,6 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#define CONFIG_SCC1_ENET
#endif /* __CONFIG_H */

4
include/configs/MVBC_P.h
View File

@ -40,7 +40,7 @@
#define CONFIG_MISC_INIT_R 1
#define CFG_CACHELINE_SIZE 32
#ifdef (CONFIG_CMD_KGDB)
#ifdef CONFIG_CMD_KGDB
#define CFG_CACHELINE_SHIFT 5
#endif
@ -268,7 +268,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#undef CFG_LONGHELP
#define CFG_PROMPT "=> "
#ifdef (CONFIG_CMD_KGDB)
#ifdef CONFIG_CMD_KGDB
#define CFG_CBSIZE 1024
#else
#define CFG_CBSIZE 256

40
include/configs/NSCU.h
View File

@ -1,5 +1,5 @@
/*
* (C) Copyright 2000-2005
* (C) Copyright 2000-2008
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
@ -67,9 +67,16 @@
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/NSCU/uImage\0" \
"hostname=NSCU\0" \
"bootfile=${hostname}/uImage\0" \
"kernel_addr=40080000\0" \
"ramdisk_addr=40180000\0" \
"u-boot=${hostname}/u-image.bin\0" \
"load=tftp 200000 ${u-boot}\0" \
"update=prot off 40000000 +${filesize};" \
"era 40000000 +${filesize};" \
"cp.b 200000 40000000 ${filesize};" \
"sete filesize;save\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
@ -110,20 +117,24 @@
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ELF
#define CONFIG_CMD_IDE
#define CONFIG_CMD_NFS
#define CONFIG_CMD_SNTP
#define CONFIG_NETCONSOLE
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if 0
#define CONFIG_CMDLINE_EDITING 1 /* add command line history
*/
#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
#endif
#ifdef CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
@ -186,21 +197,26 @@
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
/* use CFI flash driver */
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE+flash_info[0].size }
#define CFG_FLASH_EMPTY_INFO
#define CFG_FLASH_USE_BUFFER_WRITE 1
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */
#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
/* Address and size of Redundant Environment Sector */
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
/*-----------------------------------------------------------------------
* Hardware Information Block
*/

31
include/configs/TQM823L.h
View File

@ -1,5 +1,5 @@
/*
* (C) Copyright 2000-2005
* (C) Copyright 2000-2008
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
@ -37,6 +37,8 @@
#define CONFIG_TQM823L 1 /* ...on a TQM8xxL module */
#ifdef CONFIG_LCD /* with LCD controller ? */
#define CONFIG_LCD_LOGO 1 /* print our logo on the LCD */
#define CONFIG_LCD_INFO 1 /* ... and some board info */
#define CONFIG_SPLASH_SCREEN /* ... with splashscreen support*/
#endif
@ -69,10 +71,17 @@
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/TQM823L/uImage\0" \
"hostname=TQM823L\0" \
"bootfile=TQM823L/uImage\0" \
"fdt_addr=40040000\0" \
"kernel_addr=40060000\0" \
"ramdisk_addr=40200000\0" \
"u-boot=TQM823L/u-image.bin\0" \
"load=tftp 200000 ${u-boot}\0" \
"update=prot off 40000000 +${filesize};" \
"era 40000000 +${filesize};" \
"cp.b 200000 40000000 ${filesize};" \
"sete filesize;save\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
@ -113,7 +122,9 @@
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ELF
#define CONFIG_CMD_IDE
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_NFS
#define CONFIG_CMD_SNTP
@ -122,6 +133,8 @@
#endif
#define CONFIG_NETCONSOLE
/*
* Miscellaneous configurable options
*/
@ -196,7 +209,7 @@
/* use CFI flash driver */
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE+flash_info[0].size }
#define CFG_FLASH_EMPTY_INFO
#define CFG_FLASH_USE_BUFFER_WRITE 1
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
@ -212,6 +225,18 @@
#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
/*-----------------------------------------------------------------------
* Dynamic MTD partition support
*/
#define CONFIG_JFFS2_CMDLINE
#define MTDIDS_DEFAULT "nor0=TQM8xxL-0"
#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \
"128k(dtb)," \
"1664k(kernel)," \
"2m(rootfs)," \
"4m(data)"
/*-----------------------------------------------------------------------
* Hardware Information Block
*/

28
include/configs/TQM823M.h
View File

@ -1,5 +1,5 @@
/*
* (C) Copyright 2000-2005
* (C) Copyright 2000-2008
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
@ -69,10 +69,17 @@
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/TQM823M/uImage\0" \
"hostname=TQM823M\0" \
"bootfile=TQM823M/uImage\0" \
"fdt_addr=40080000\0" \
"kernel_addr=400A0000\0" \
"ramdisk_addr=40280000\0" \
"u-boot=TQM823M/u-image.bin\0" \
"load=tftp 200000 ${u-boot}\0" \
"update=prot off 40000000 +${filesize};" \
"era 40000000 +${filesize};" \
"cp.b 200000 40000000 ${filesize};" \
"sete filesize;save\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
@ -113,11 +120,16 @@
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ELF
#define CONFIG_CMD_IDE
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_NFS
#define CONFIG_CMD_SNTP
#define CONFIG_NETCONSOLE
/*
* Miscellaneous configurable options
*/
@ -209,6 +221,18 @@
#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
/*-----------------------------------------------------------------------
* Dynamic MTD partition support
*/
#define CONFIG_JFFS2_CMDLINE
#define MTDIDS_DEFAULT "nor0=TQM8xxM-0"
#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \
"128k(dtb)," \
"1920k(kernel)," \
"5632(rootfs)," \
"4m(data)"
/*-----------------------------------------------------------------------
* Hardware Information Block
*/

29
include/configs/TQM850L.h
View File

@ -1,5 +1,5 @@
/*
* (C) Copyright 2000-2005
* (C) Copyright 2000-2008
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
@ -65,10 +65,17 @@
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/TQM850L/uImage\0" \
"hostname=TQM850L\0" \
"bootfile=TQM850L/uImage\0" \
"fdt_addr=40040000\0" \
"kernel_addr=40060000\0" \
"ramdisk_addr=40200000\0" \
"u-boot=TQM850L/u-image.bin\0" \
"load=tftp 200000 ${u-boot}\0" \
"update=prot off 40000000 +${filesize};" \
"era 40000000 +${filesize};" \
"cp.b 200000 40000000 ${filesize};" \
"sete filesize;save\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
@ -104,11 +111,15 @@
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ELF
#define CONFIG_CMD_IDE
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_NFS
#define CONFIG_CMD_SNTP
#define CONFIG_NETCONSOLE
/*
* Miscellaneous configurable options
*/
@ -183,7 +194,7 @@
/* use CFI flash driver */
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE+flash_info[0].size }
#define CFG_FLASH_EMPTY_INFO
#define CFG_FLASH_USE_BUFFER_WRITE 1
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
@ -199,6 +210,18 @@
#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
/*-----------------------------------------------------------------------
* Dynamic MTD partition support
*/
#define CONFIG_JFFS2_CMDLINE
#define MTDIDS_DEFAULT "nor0=TQM8xxL-0"
#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \
"128k(dtb)," \
"1664k(kernel)," \
"2m(rootfs)," \
"4m(data)"
/*-----------------------------------------------------------------------
* Hardware Information Block
*/

28
include/configs/TQM850M.h
View File

@ -1,5 +1,5 @@
/*
* (C) Copyright 2000-2005
* (C) Copyright 2000-2008
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
@ -63,10 +63,17 @@
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/TQM850M/uImage\0" \
"hostname=TQM850M\0" \
"bootfile=TQM850M/uImage\0" \
"fdt_addr=40080000\0" \
"kernel_addr=400A0000\0" \
"ramdisk_addr=40280000\0" \
"u-boot=TQM850M/u-image.bin\0" \
"load=tftp 200000 ${u-boot}\0" \
"update=prot off 40000000 +${filesize};" \
"era 40000000 +${filesize};" \
"cp.b 200000 40000000 ${filesize};" \
"sete filesize;save\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
@ -102,11 +109,16 @@
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ELF
#define CONFIG_CMD_IDE
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_NFS
#define CONFIG_CMD_SNTP
#define CONFIG_NETCONSOLE
/*
* Miscellaneous configurable options
*/
@ -198,6 +210,18 @@
#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
/*-----------------------------------------------------------------------
* Dynamic MTD partition support
*/
#define CONFIG_JFFS2_CMDLINE
#define MTDIDS_DEFAULT "nor0=TQM8xxM-0"
#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \
"128k(dtb)," \
"1920k(kernel)," \
"5632(rootfs)," \
"4m(data)"
/*-----------------------------------------------------------------------
* Hardware Information Block
*/

30
include/configs/TQM855L.h
View File

@ -1,5 +1,5 @@
/*
* (C) Copyright 2000-2005
* (C) Copyright 2000-2008
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
@ -68,10 +68,17 @@
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/TQM855L/uImage\0" \
"hostname=TQM855L\0" \
"bootfile=TQM855L/uImage\0" \
"fdt_addr=40040000\0" \
"kernel_addr=40060000\0" \
"ramdisk_addr=40200000\0" \
"u-boot=TQM855L/u-image.bin\0" \
"load=tftp 200000 ${u-boot}\0" \
"update=prot off 40000000 +${filesize};" \
"era 40000000 +${filesize};" \
"cp.b 200000 40000000 ${filesize};" \
"sete filesize;save\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
@ -108,11 +115,16 @@
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ELF
#define CONFIG_CMD_IDE
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_NFS
#define CONFIG_CMD_SNTP
#define CONFIG_NETCONSOLE
/*
* Miscellaneous configurable options
*/
@ -187,7 +199,7 @@
/* use CFI flash driver */
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE+flash_info[0].size }
#define CFG_FLASH_EMPTY_INFO
#define CFG_FLASH_USE_BUFFER_WRITE 1
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
@ -203,6 +215,18 @@
#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
/*-----------------------------------------------------------------------
* Dynamic MTD partition support
*/
#define CONFIG_JFFS2_CMDLINE
#define MTDIDS_DEFAULT "nor0=TQM8xxL-0"
#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \
"128k(dtb)," \
"1664k(kernel)," \
"2m(rootfs)," \
"4m(data)"
/*-----------------------------------------------------------------------
* Hardware Information Block
*/

28
include/configs/TQM855M.h
View File

@ -1,5 +1,5 @@
/*
* (C) Copyright 2000-2005
* (C) Copyright 2000-2008
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
@ -68,10 +68,17 @@
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/TQM855M/uImage\0" \
"hostname=TQM855M\0" \
"bootfile=TQM855M/uImage\0" \
"fdt_addr=40080000\0" \
"kernel_addr=400A0000\0" \
"ramdisk_addr=40280000\0" \
"u-boot=TQM855M/u-image.bin\0" \
"load=tftp 200000 ${u-boot}\0" \
"update=prot off 40000000 +${filesize};" \
"era 40000000 +${filesize};" \
"cp.b 200000 40000000 ${filesize};" \
"sete filesize;save\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
@ -141,12 +148,17 @@
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ELF
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_IDE
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_NFS
#define CONFIG_CMD_SNTP
#define CONFIG_NETCONSOLE
/*
* Miscellaneous configurable options
*/
@ -238,6 +250,18 @@
#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
/*-----------------------------------------------------------------------
* Dynamic MTD partition support
*/
#define CONFIG_JFFS2_CMDLINE
#define MTDIDS_DEFAULT "nor0=TQM8xxM-0"
#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \
"128k(dtb)," \
"1920k(kernel)," \
"5632(rootfs)," \
"4m(data)"
/*-----------------------------------------------------------------------
* Hardware Information Block
*/

26
include/configs/TQM860L.h
View File

@ -1,5 +1,5 @@
/*
* (C) Copyright 2000-2005
* (C) Copyright 2000-2008
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
@ -68,10 +68,17 @@
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/TQM860L/uImage\0" \
"hostname=TQM860L\0" \
"bootfile=TQM860L/uImage\0" \
"fdt_addr=40040000\0" \
"kernel_addr=40060000\0" \
"ramdisk_addr=40200000\0" \
"u-boot=TQM860L/u-image.bin\0" \
"load=tftp 200000 ${u-boot}\0" \
"update=prot off 40000000 +${filesize};" \
"era 40000000 +${filesize};" \
"cp.b 200000 40000000 ${filesize};" \
"sete filesize;save\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
@ -110,6 +117,7 @@
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ELF
#define CONFIG_CMD_IDE
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_NFS
#define CONFIG_CMD_SNTP
@ -190,7 +198,7 @@
/* use CFI flash driver */
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE+flash_info[0].size }
#define CFG_FLASH_EMPTY_INFO
#define CFG_FLASH_USE_BUFFER_WRITE 1
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
@ -206,6 +214,18 @@
#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
/*-----------------------------------------------------------------------
* Dynamic MTD partition support
*/
#define CONFIG_JFFS2_CMDLINE
#define MTDIDS_DEFAULT "nor0=TQM8xxL-0"
#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \
"128k(dtb)," \
"1664k(kernel)," \
"2m(rootfs)," \
"4m(data)"
/*-----------------------------------------------------------------------
* Hardware Information Block
*/

26
include/configs/TQM860M.h
View File

@ -68,15 +68,17 @@
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/TQM860M/uImage\0" \
"hostname=TQM860M\0" \
"bootfile=TQM860M/uImage\0" \
"fdt_addr=400C0000\0" \
"kernel_addr=40100000\0" \
"ramdisk_addr=40280000\0" \
"u-boot=TQM860M/u-image.bin\0" \
"load=tftp 200000 ${u-boot}\0" \
"update=protect off 40000000 +${filesize};" \
"erase 40000000 +${filesize};" \
"update=prot off 40000000 +${filesize};" \
"era 40000000 +${filesize};" \
"cp.b 200000 40000000 ${filesize};" \
"protect on 40000000 +${filesize}\0" \
"sete filesize;save\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
@ -115,10 +117,14 @@
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ELF
#define CONFIG_CMD_IDE
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_NFS
#define CONFIG_CMD_SNTP
#define CONFIG_NETCONSOLE
/*
* Miscellaneous configurable options
*/
@ -209,6 +215,18 @@
#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
/*-----------------------------------------------------------------------
* Dynamic MTD partition support
*/
#define CONFIG_JFFS2_CMDLINE
#define MTDIDS_DEFAULT "nor0=TQM8xxM-0"
#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \
"128k(dtb)," \
"1920k(kernel)," \
"5632(rootfs)," \
"4m(data)"
/*-----------------------------------------------------------------------
* Hardware Information Block
*/

30
include/configs/TQM862L.h
View File

@ -1,5 +1,5 @@
/*
* (C) Copyright 2000-2005
* (C) Copyright 2000-2008
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
@ -71,10 +71,17 @@
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/TQM862L/uImage\0" \
"hostname=TQM862L\0" \
"bootfile=TQM862L/uImage\0" \
"fdt_addr=40040000\0" \
"kernel_addr=40060000\0" \
"ramdisk_addr=40200000\0" \
"u-boot=TQM862L/u-image.bin\0" \
"load=tftp 200000 ${u-boot}\0" \
"update=prot off 40000000 +${filesize};" \
"era 40000000 +${filesize};" \
"cp.b 200000 40000000 ${filesize};" \
"sete filesize;save\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
@ -111,11 +118,16 @@
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ELF
#define CONFIG_CMD_IDE
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_NFS
#define CONFIG_CMD_SNTP
#define CONFIG_NETCONSOLE
/*
* Miscellaneous configurable options
*/
@ -190,7 +202,7 @@
/* use CFI flash driver */
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE+flash_info[0].size }
#define CFG_FLASH_EMPTY_INFO
#define CFG_FLASH_USE_BUFFER_WRITE 1
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
@ -206,6 +218,18 @@
#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
/*-----------------------------------------------------------------------
* Dynamic MTD partition support
*/
#define CONFIG_JFFS2_CMDLINE
#define MTDIDS_DEFAULT "nor0=TQM8xxL-0"
#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \
"128k(dtb)," \
"1664k(kernel)," \
"2m(rootfs)," \
"4m(data)"
/*-----------------------------------------------------------------------
* Hardware Information Block
*/

26
include/configs/TQM862M.h
View File

@ -71,10 +71,17 @@
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/TQM862M/uImage\0" \
"hostname=TQM862M\0" \
"bootfile=TQM862M/uImage\0" \
"fdt_addr=40080000\0" \
"kernel_addr=400A0000\0" \
"ramdisk_addr=40280000\0" \
"u-boot=TQM862M/u-image.bin\0" \
"load=tftp 200000 ${u-boot}\0" \
"update=prot off 40000000 +${filesize};" \
"era 40000000 +${filesize};" \
"cp.b 200000 40000000 ${filesize};" \
"sete filesize;save\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
@ -111,11 +118,16 @@
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ELF
#define CONFIG_CMD_IDE
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_NFS
#define CONFIG_CMD_SNTP
#define CONFIG_NETCONSOLE
/*
* Miscellaneous configurable options
*/
@ -207,6 +219,18 @@
#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
/*-----------------------------------------------------------------------
* Dynamic MTD partition support
*/
#define CONFIG_JFFS2_CMDLINE
#define MTDIDS_DEFAULT "nor0=TQM8xxM-0"
#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \
"128k(dtb)," \
"1920k(kernel)," \
"5632(rootfs)," \
"4m(data)"
/*-----------------------------------------------------------------------
* Hardware Information Block
*/

29
include/configs/TQM866M.h
View File

@ -80,15 +80,17 @@
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/TQM866M/uImage\0" \
"hostname=TQM866M\0" \
"bootfile=TQM866M/uImage\0" \
"fdt_addr=400C0000\0" \
"kernel_addr=40100000\0" \
"ramdisk_addr=40280000\0" \
"u-boot=TQM866M/u-image.bin\0" \
"load=tftp 200000 ${u-boot}\0" \
"update=protect off 40000000 +${filesize};" \
"erase 40000000 +${filesize};" \
"update=prot off 40000000 +${filesize};" \
"era 40000000 +${filesize};" \
"cp.b 200000 40000000 ${filesize};" \
"protect on 40000000 +${filesize}\0" \
"sete filesize;save\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
@ -157,9 +159,14 @@
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_I2C
#define CONFIG_CMD_ELF
#define CONFIG_CMD_IDE
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_NFS
#define CONFIG_CMD_SNTP
#define CONFIG_NETCONSOLE
/*
@ -252,6 +259,18 @@
#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
/*-----------------------------------------------------------------------
* Dynamic MTD partition support
*/
#define CONFIG_JFFS2_CMDLINE
#define MTDIDS_DEFAULT "nor0=TQM8xxM-0"
#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \
"128k(dtb)," \
"1920k(kernel)," \
"5632(rootfs)," \
"4m(data)"
/*-----------------------------------------------------------------------
* Hardware Information Block
*/

5
include/configs/ads5121.h
View File

@ -308,6 +308,7 @@
#define CONFIG_PHY_ADDR 0x1
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_FEC_AN_TIMEOUT 1
#define CONFIG_HAS_ETH0
/*
* Configure on-board RTC
@ -478,10 +479,10 @@
#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP 1
#define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES 1
#define OF_CPU "PowerPC,5121@0"
#define OF_SOC "soc@80000000"
#define OF_SOC_OLD "soc5121@80000000"
#define OF_SOC_COMPAT "fsl,mpc5121-immr"
#define OF_TBCLK (bd->bi_busfreq / 4)
#define OF_STDOUT_PATH "/soc@80000000/serial@11300"

2
include/configs/sbc8641d.h
View File

@ -58,6 +58,8 @@
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */
#undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup*/
#undef CONFIG_DDR_DLL /* possible DLL fix needed */
#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */

12
include/configs/sequoia.h
View File

@ -422,12 +422,12 @@
/* GPIO Core 1 */ \
{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO32 USB2D_OPMODE0 EBC_DATA(2) */ \
{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO33 USB2D_OPMODE1 EBC_DATA(3) */ \
{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N EBC_DATA(0) UART3_SIN*/ \
{GPIO1_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N EBC_DATA(1) UART3_SOUT*/ \
{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \
{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \
{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO34 UART0_8PIN_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO36 UART0_CTS_N EBC_DATA(0) UART3_SIN*/ \
{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO37 UART0_RTS_N EBC_DATA(1) UART3_SOUT*/ \
{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_8PIN_DTR_N UART1_SOUT */ \
{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_8PIN_RI_N UART1_SIN */ \
{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0) */ \
{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1) */ \
{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2) */ \

9
include/configs/sh7763rdp.h
View File

@ -38,7 +38,11 @@
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_NET
#define CONFIG_CMD_PING
#define CONFIG_CMD_ENV
#define CONFIG_CMD_NFS
#define CONFIG_CMD_JFFS2
#define CONFIG_BOOTDELAY -1
#define CONFIG_BOOTARGS "console=ttySC2,115200 root=1f01"
@ -113,4 +117,9 @@
#define TMU_CLK_DIVIDER (4) /* 4 (default), 16, 64, 256 or 1024 */
#define CFG_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
/* Ether */
#define CONFIG_SH_ETHER 1
#define CONFIG_SH_ETHER_USE_PORT (1)
#define CONFIG_SH_ETHER_PHY_ADDR (0x01)
#endif /* __SH7763RDP_H */

40
include/configs/virtlab2.h
View File

@ -1,5 +1,5 @@
/*
* (C) Copyright 2006
* (C) Copyright 2006-2008
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
@ -37,10 +37,6 @@
#define CONFIG_VIRTLAB2 1 /* ...on a virtlab2 module */
#define CONFIG_TQM8xxL 1
#ifdef CONFIG_LCD /* with LCD controller ? */
#define CONFIG_SPLASH_SCREEN /* ... with splashscreen support*/
#endif
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
#undef CONFIG_8xx_CONS_SMC2
#undef CONFIG_8xx_CONS_NONE
@ -70,9 +66,17 @@
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/TQM823L/uImage\0" \
"kernel_addr=40040000\0" \
"ramdisk_addr=40100000\0" \
"hostname=virtlab2\0" \
"bootfile=virtlab2/uImage\0" \
"fdt_addr=40040000\0" \
"kernel_addr=40060000\0" \
"ramdisk_addr=40200000\0" \
"u-boot=virtlab2/u-image.bin\0" \
"load=tftp 200000 ${u-boot}\0" \
"update=prot off 40000000 +${filesize};" \
"era 40000000 +${filesize};" \
"cp.b 200000 40000000 ${filesize};" \
"sete filesize;save\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
@ -114,6 +118,7 @@
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_IDE
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_NFS
#define CONFIG_CMD_SNTP
@ -122,15 +127,16 @@
#endif
#define CONFIG_NETCONSOLE
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if 0
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
#endif
#ifdef CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
@ -197,7 +203,7 @@
/* use CFI flash driver */
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE+flash_info[0].size }
#define CFG_FLASH_EMPTY_INFO
#define CFG_FLASH_USE_BUFFER_WRITE 1
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
@ -213,6 +219,18 @@
#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
/*-----------------------------------------------------------------------
* Dynamic MTD partition support
*/
#define CONFIG_JFFS2_CMDLINE
#define MTDIDS_DEFAULT "nor0=TQM8xxL-0"
#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \
"128k(dtb)," \
"1664k(kernel)," \
"2m(rootfs)," \
"4m(data)"
/*-----------------------------------------------------------------------
* Hardware Information Block
*/

2
include/dataflash.h
View File

@ -135,9 +135,9 @@ struct dataflash_addr {
int cs;
};
/*-------------------------------------------------------------------------------------------------*/
#define AT45DB161 0x2c
#define AT45DB021 0x14
#define AT45DB081 0x24
#define AT45DB321 0x34
#define AT45DB642 0x3c
#define AT45DB128 0x10

1
include/image.h
View File

@ -220,7 +220,6 @@ typedef struct bootm_headers {
#endif
int verify; /* getenv("verify")[0] != 'n' */
int autostart; /* getenv("autostart")[0] != 'n' */
struct lmb *lmb; /* for memory mgmt */
} bootm_headers_t;

251
include/mpc512x.h
View File

@ -347,41 +347,226 @@
/* IO Control Register
*/
#define IOCTL_MEM 0x000
#define IOCTL_GP 0x004
#define IOCTL_LPC_CLK 0x008
#define IOCTL_LPC_OE 0x00C
#define IOCTL_LPC_RWB 0x010
#define IOCTL_LPC_ACK 0x014
#define IOCTL_LPC_CS0 0x018
#define IOCTL_NFC_CE0 0x01C
#define IOCTL_LPC_CS1 0x020
#define IOCTL_LPC_CS2 0x024
#define IOCTL_LPC_AX03 0x028
#define IOCTL_EMB_AX02 0x02C
#define IOCTL_EMB_AX01 0x030
#define IOCTL_EMB_AX00 0x034
#define IOCTL_EMB_AD31 0x038
#define IOCTL_EMB_AD30 0x03C
#define IOCTL_EMB_AD29 0x040
#define IOCTL_EMB_AD28 0x044
#define IOCTL_EMB_AD27 0x048
#define IOCTL_EMB_AD26 0x04C
#define IOCTL_EMB_AD25 0x050
#define IOCTL_EMB_AD24 0x054
#define IOCTL_EMB_AD23 0x058
#define IOCTL_EMB_AD22 0x05C
#define IOCTL_EMB_AD21 0x060
#define IOCTL_EMB_AD20 0x064
#define IOCTL_EMB_AD19 0x068
#define IOCTL_EMB_AD18 0x06C
#define IOCTL_EMB_AD17 0x070
#define IOCTL_EMB_AD16 0x074
#define IOCTL_EMB_AD15 0x078
#define IOCTL_EMB_AD14 0x07C
#define IOCTL_EMB_AD13 0x080
#define IOCTL_EMB_AD12 0x084
#define IOCTL_EMB_AD11 0x088
#define IOCTL_EMB_AD10 0x08C
#define IOCTL_EMB_AD09 0x090
#define IOCTL_EMB_AD08 0x094
#define IOCTL_EMB_AD07 0x098
#define IOCTL_EMB_AD06 0x09C
#define IOCTL_EMB_AD05 0x0A0
#define IOCTL_EMB_AD04 0x0A4
#define IOCTL_EMB_AD03 0x0A8
#define IOCTL_EMB_AD02 0x0AC
#define IOCTL_EMB_AD01 0x0B0
#define IOCTL_EMB_AD00 0x0B4
#define IOCTL_PATA_CE1 0x0B8
#define IOCTL_PATA_CE2 0x0BC
#define IOCTL_PATA_ISOLATE 0x0C0
#define IOCTL_PATA_IOR 0x0C4
#define IOCTL_PATA_IOW 0x0C8
#define IOCTL_PATA_IOCHRDY 0x0CC
#define IOCTL_PATA_INTRQ 0x0D0
#define IOCTL_PATA_DRQ 0x0D4
#define IOCTL_PATA_DACK 0x0D8
#define IOCTL_NFC_WP 0x0DC
#define IOCTL_NFC_RB 0x0E0
#define IOCTL_NFC_ALE 0x0E4
#define IOCTL_NFC_CLE 0x0E8
#define IOCTL_NFC_WE 0x0EC
#define IOCTL_NFC_RE 0x0F0
#define IOCTL_PCI_AD31 0x0F4
#define IOCTL_PCI_AD30 0x0F8
#define IOCTL_PCI_AD29 0x0FC
#define IOCTL_PCI_AD28 0x100
#define IOCTL_PCI_AD27 0x104
#define IOCTL_PCI_AD26 0x108
#define IOCTL_PCI_AD25 0x10C
#define IOCTL_PCI_AD24 0x110
#define IOCTL_PCI_AD23 0x114
#define IOCTL_PCI_AD22 0x118
#define IOCTL_PCI_AD21 0x11C
#define IOCTL_PCI_AD20 0x120
#define IOCTL_PCI_AD19 0x124
#define IOCTL_PCI_AD18 0x128
#define IOCTL_PCI_AD17 0x12C
#define IOCTL_PCI_AD16 0x130
#define IOCTL_PCI_AD15 0x134
#define IOCTL_PCI_AD14 0x138
#define IOCTL_PCI_AD13 0x13C
#define IOCTL_PCI_AD12 0x140
#define IOCTL_PCI_AD11 0x144
#define IOCTL_PCI_AD10 0x148
#define IOCTL_PCI_AD09 0x14C
#define IOCTL_PCI_AD08 0x150
#define IOCTL_PCI_AD07 0x154
#define IOCTL_PCI_AD06 0x158
#define IOCTL_PCI_AD05 0x15C
#define IOCTL_PCI_AD04 0x160
#define IOCTL_PCI_AD03 0x164
#define IOCTL_PCI_AD02 0x168
#define IOCTL_PCI_AD01 0x16C
#define IOCTL_PCI_AD00 0x170
#define IOCTL_PCI_CBE0 0x174
#define IOCTL_PCI_CBE1 0x178
#define IOCTL_PCI_CBE2 0x17C
#define IOCTL_PCI_CBE3 0x180
#define IOCTL_PCI_GNT2 0x184
#define IOCTL_PCI_REQ2 0x188
#define IOCTL_PCI_GNT1 0x18C
#define IOCTL_PCI_REQ1 0x190
#define IOCTL_PCI_GNT0 0x194
#define IOCTL_PCI_REQ0 0x198
#define IOCTL_PCI_INTA 0x19C
#define IOCTL_PCI_CLK 0x1A0
#define IOCTL_PCI_RST_OUT 0x1A4
#define IOCTL_PCI_FRAME 0x1A8
#define IOCTL_PCI_IDSEL 0x1AC
#define IOCTL_PCI_DEVSEL 0x1B0
#define IOCTL_PCI_IRDY 0x1B4
#define IOCTL_PCI_TRDY 0x1B8
#define IOCTL_PCI_STOP 0x1BC
#define IOCTL_PCI_PAR 0x1C0
#define IOCTL_PCI_PERR 0x1C4
#define IOCTL_PCI_SERR 0x1C8
#define IOCTL_SPDIF_TXCLK 0x1CC
#define IOCTL_SPDIF_TX 0x1D0
#define IOCTL_SPDIF_RX 0x1D4
#define IOCTL_I2C0_SCL 0x1D8
#define IOCTL_I2C0_SDA 0x1DC
#define IOCTL_I2C1_SCL 0x1E0
#define IOCTL_I2C1_SDA 0x1E4
#define IOCTL_I2C2_SCL 0x1E8
#define IOCTL_I2C2_SDA 0x1EC
#define IOCTL_IRQ0 0x1F0
#define IOCTL_IRQ1 0x1F4
#define IOCTL_CAN1_TX 0x1F8
#define IOCTL_CAN2_TX 0x1FC
#define IOCTL_J1850_TX 0x200
#define IOCTL_J1850_RX 0x204
#define IOCTL_PSC_MCLK_IN 0x208
#define IOCTL_PSC0_0 0x20C
#define IOCTL_PSC0_1 0x210
#define IOCTL_PSC0_2 0x214
#define IOCTL_PSC0_3 0x218
#define IOCTL_PSC0_4 0x21C
#define IOCTL_PSC1_0 0x220
#define IOCTL_PSC1_1 0x224
#define IOCTL_PSC1_2 0x228
#define IOCTL_PSC1_3 0x22C
#define IOCTL_PSC1_4 0x230
#define IOCTL_PSC2_0 0x234
#define IOCTL_PSC2_1 0x238
#define IOCTL_PSC2_2 0x23C
#define IOCTL_PSC2_3 0x240
#define IOCTL_PSC2_4 0x244
#define IOCTL_PSC3_0 0x248
#define IOCTL_PSC3_1 0x24C
#define IOCTL_PSC3_2 0x250
#define IOCTL_PSC3_3 0x254
#define IOCTL_PSC3_4 0x258
#define IOCTL_PSC4_0 0x25C
#define IOCTL_PSC4_1 0x260
#define IOCTL_PSC4_2 0x264
#define IOCTL_PSC4_3 0x268
#define IOCTL_PSC4_4 0x26C
#define IOCTL_PSC5_0 0x270
#define IOCTL_PSC5_1 0x274
#define IOCTL_PSC5_2 0x278
#define IOCTL_PSC5_3 0x27C
#define IOCTL_PSC5_4 0x280
#define IOCTL_PSC6_0 0x284
#define IOCTL_PSC6_1 0x288
#define IOCTL_PSC6_2 0x28C
#define IOCTL_PSC6_3 0x290
#define IOCTL_PSC6_4 0x294
#define IOCTL_PSC7_0 0x298
#define IOCTL_PSC7_1 0x29C
#define IOCTL_PSC7_2 0x2A0
#define IOCTL_PSC7_3 0x2A4
#define IOCTL_PSC7_4 0x2A8
#define IOCTL_PSC8_0 0x2AC
#define IOCTL_PSC8_1 0x2B0
#define IOCTL_PSC8_2 0x2B4
#define IOCTL_PSC8_3 0x2B8
#define IOCTL_PSC8_4 0x2BC
#define IOCTL_PSC9_0 0x2C0
#define IOCTL_PSC9_1 0x2C4
#define IOCTL_PSC9_2 0x2C8
#define IOCTL_PSC9_3 0x2CC
#define IOCTL_PSC9_4 0x2D0
#define IOCTL_PSC10_0 0x2D4
#define IOCTL_PSC10_1 0x2D8
#define IOCTL_PSC10_2 0x2DC
#define IOCTL_PSC10_3 0x2E0
#define IOCTL_PSC10_4 0x2E4
#define IOCTL_PSC11_0 0x2E8
#define IOCTL_PSC11_1 0x2EC
#define IOCTL_PSC11_2 0x2F0
#define IOCTL_PSC11_3 0x2F4
#define IOCTL_PSC11_4 0x2F8
#define IOCTL_HRESET 0x2FC
#define IOCTL_SRESET 0x300
#define IOCTL_CKSTP_OUT 0x304
#define IOCTL_USB2_VBUS_PWR_FAULT 0x308
#define IOCTL_USB2_VBUS_PWR_SELECT 0x30C
#define IOCTL_USB2_PHY_DRVV_BUS 0x310
#ifndef __ASSEMBLY__
/* IO pin fields */
#define IO_PIN_FMUX(v) ((v) << 7) /* pin function */
#define IO_PIN_HOLD(v) ((v) << 5) /* hold time, pci only */
#define IO_PIN_PUD(v) ((v) << 4) /* if PUE, 0=pull-down, 1=pull-up */
#define IO_PIN_PUE(v) ((v) << 3) /* pull up/down enable */
#define IO_PIN_ST(v) ((v) << 2) /* schmitt trigger */
#define IO_PIN_DS(v) ((v)) /* slew rate */
typedef struct iopin_t {
int p_offset; /* offset from IOCTL_MEM_OFFSET */
int nr_pins; /* number of pins to set this way */
int bit_or; /* or in the value instead of overwrite */
u_long val; /* value to write or or */
}iopin_t;
void iopin_initialize(iopin_t *,int);
#endif
/* Indexes in regs array */
#define MEM_IDX 0x00
#define PATA_CE1_IDX 0x2e
#define PATA_CE2_IDX 0x2f
#define PATA_ISOLATE_IDX 0x30
#define PATA_IOR_IDX 0x31
#define PATA_IOW_IDX 0x32
#define PATA_IOCHRDY_IDX 0x33
#define PATA_INTRQ_IDX 0x34
#define PATA_DRQ_IDX 0x35
#define PATA_DACK_IDX 0x36
#define SPDIF_TXCLOCK_IDX 0x73
#define SPDIF_TX_IDX 0x74
#define SPDIF_RX_IDX 0x75
#define PSC0_0_IDX 0x83
#define PSC0_1_IDX 0x84
#define PSC0_2_IDX 0x85
#define PSC0_3_IDX 0x86
#define PSC0_4_IDX 0x87
#define PSC1_0_IDX 0x88
#define PSC1_1_IDX 0x89
#define PSC1_2_IDX 0x8a
#define PSC1_3_IDX 0x8b
#define PSC1_4_IDX 0x8c
#define PSC2_0_IDX 0x8d
#define PSC2_1_IDX 0x8e
#define PSC2_2_IDX 0x8f
#define PSC2_3_IDX 0x90
#define PSC2_4_IDX 0x91
#define IOCTRL_FUNCMUX_SHIFT 7
#define IOCTRL_FUNCMUX_FEC 1
#define IOCTRL_MUX_FEC (IOCTRL_FUNCMUX_FEC << IOCTRL_FUNCMUX_SHIFT)
/* Set for DDR */
#define IOCTRL_MUX_DDR 0x00000036

2
include/usb.h
View File

@ -171,7 +171,7 @@ struct usb_device {
#if defined(CONFIG_USB_UHCI) || defined(CONFIG_USB_OHCI) || \
defined(CONFIG_USB_OHCI_NEW) || defined (CONFIG_USB_SL811HS) || \
defined(CONFIG_USB_ISP116X_HCD)
defined(CONFIG_USB_ISP116X_HCD) || defined(CONFIG_USB_R8A66597_HCD)
int usb_lowlevel_init(void);
int usb_lowlevel_stop(void);

6
lib_arm/bootm.c
View File

@ -137,9 +137,6 @@ void do_bootm_linux (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[],
setup_end_tag (bd);
#endif
if (!images->autostart)
return ;
/* we assume that the kernel is in place */
printf ("\nStarting kernel ...\n\n");
@ -157,8 +154,7 @@ void do_bootm_linux (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[],
return;
error:
if (images->autostart)
do_reset (cmdtp, flag, argc, argv);
do_reset (cmdtp, flag, argc, argv);
return;
}

6
lib_avr32/bootm.c
View File

@ -221,9 +221,6 @@ void do_bootm_linux(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[],
params = setup_ethernet_tags(params);
setup_end_tag(params);
if (!images->autostart)
return ;
printf("\nStarting kernel at %p (params at %p)...\n\n",
theKernel, params_start);
@ -234,7 +231,6 @@ void do_bootm_linux(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[],
return;
error:
if (images->autostart)
do_reset (cmdtp, flag, argc, argv);
do_reset (cmdtp, flag, argc, argv);
return;
}

6
lib_blackfin/bootm.c
View File

@ -40,9 +40,6 @@ void do_bootm_linux(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[],
char *cmdline;
ulong ep = 0;
if (!images->autostart)
return;
#ifdef SHARED_RESOURCES
swap_to(FLASH);
#endif
@ -74,6 +71,5 @@ void do_bootm_linux(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[],
return;
error:
if (images->autostart)
do_reset (cmdtp, flag, argc, argv);
do_reset (cmdtp, flag, argc, argv);
}

6
lib_i386/bootm.c
View File

@ -84,9 +84,6 @@ void do_bootm_linux(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[],
}
if (!images->autostart)
return ;
#ifdef DEBUG
printf ("## Transferring control to Linux (at address %08x) ...\n",
(u32)base_ptr);
@ -100,7 +97,6 @@ void do_bootm_linux(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[],
return;
error:
if (images->autostart)
do_reset (cmdtp, flag, argc, argv);
do_reset (cmdtp, flag, argc, argv);
return;
}

5
lib_m68k/bootm.c
View File

@ -129,8 +129,6 @@ void do_bootm_linux(cmd_tbl_t * cmdtp, int flag,
show_boot_progress (15);
if (!images->autostart)
return;
/*
* Linux Kernel Parameters (passing board info data):
* r3: ptr to board info data
@ -144,8 +142,7 @@ void do_bootm_linux(cmd_tbl_t * cmdtp, int flag,
return ;
error:
if (images->autostart)
do_reset (cmdtp, flag, argc, argv);
do_reset (cmdtp, flag, argc, argv);
return ;
}

6
lib_microblaze/bootm.c
View File

@ -67,15 +67,11 @@ void do_bootm_linux (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[],
(ulong) theKernel);
#endif
if (!images->autostart)
return ;
theKernel (commandline);
/* does not return */
return;
error:
if (images->autostart)
do_reset (cmdtp, flag, argc, argv);
do_reset (cmdtp, flag, argc, argv);
return;
}

6
lib_mips/bootm.c
View File

@ -120,9 +120,6 @@ void do_bootm_linux (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[],
linux_env_set("eth1addr", cp);
}
if (!images->autostart)
return ;
/* we assume that the kernel is in place */
printf ("\nStarting kernel ...\n\n");
@ -131,8 +128,7 @@ void do_bootm_linux (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[],
return;
error:
if (images->autostart)
do_reset (cmdtp, flag, argc, argv);
do_reset (cmdtp, flag, argc, argv);
return;
}

6
lib_nios2/bootm.c
View File

@ -50,9 +50,6 @@ void do_bootm_linux(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[],
}
void (*kernel)(void) = (void (*)(void))ep;
if (!images->autostart)
return ;
/* For now we assume the Microtronix linux ... which only
* needs to be called ;-)
*/
@ -61,7 +58,6 @@ void do_bootm_linux(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[],
return;
error:
if (images->autostart)
do_reset (cmdtp, flag, argc, argv);
do_reset (cmdtp, flag, argc, argv);
return;
}

6
lib_ppc/bat_rw.c
View File

@ -25,9 +25,12 @@
#include <common.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/io.h>
int write_bat (ppc_bat_t bat, unsigned long upper, unsigned long lower)
{
sync();
switch (bat) {
case DBAT0:
mtspr (DBAT0L, lower);
@ -99,6 +102,9 @@ int write_bat (ppc_bat_t bat, unsigned long upper, unsigned long lower)
return (-1);
}
sync();
isync();
return (0);
}

5
lib_ppc/bootm.c
View File

@ -277,8 +277,6 @@ do_bootm_linux(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[],
#if defined(CFG_INIT_RAM_LOCK) && !defined(CONFIG_E500)
unlock_ram_in_cache();
#endif
if (!images->autostart)
return ;
#if defined(CONFIG_OF_LIBFDT)
if (of_flat_tree) { /* device tree; boot new style */
@ -311,8 +309,7 @@ do_bootm_linux(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[],
return ;
error:
if (images->autostart)
do_reset (cmdtp, flag, argc, argv);
do_reset (cmdtp, flag, argc, argv);
return ;
}

6
lib_sh/bootm.c
View File

@ -83,9 +83,6 @@ void do_bootm_linux (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[],
}
void (*kernel) (void) = (void (*)(void))ep;
if (!images->autostart)
return ;
/* Setup parameters */
memset(PARAM, 0, 0x1000); /* Clear zero page */
strcpy(COMMAND_LINE, bootargs);
@ -95,7 +92,6 @@ void do_bootm_linux (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[],
return;
error:
if (images->autostart)
do_reset (cmdtp, flag, argc, argv);
do_reset (cmdtp, flag, argc, argv);
return;
}

6
lib_sparc/bootm.c
View File

@ -204,9 +204,6 @@ void do_bootm_linux(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[],
bootargs = getenv("bootargs");
prepare_bootargs(bootargs);
if (!images->autostart)
return;
/* turn on mmu & setup context table & page table for process 0 (kernel) */
srmmu_init_cpu((unsigned int)kernel);
@ -220,7 +217,6 @@ void do_bootm_linux(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[],
while (1) ;
error:
if (images->autostart)
do_reset(cmdtp, flag, argc, argv);
do_reset(cmdtp, flag, argc, argv);
return;
}