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prepare joining at91rm9200 into at91 

* prepare joining at91 and at91rm9200
 * add modified copy of soc files to cpu/arm920t/at91 to make
   possible to compile at91rm9200 boards in at91 tree instead
   of at91rm9200
 * add header files with c structure defs for AT91 MC, ST and TC
 * the new cpu files are using at91 c structure soc access
 * please read README.soc-at91 for details

Signed-off-by: Jens Scharsig <js_at_ng@scharsoft.de>
This commit is contained in:
Jens Scharsig 2010-02-03 22:47:35 +01:00 committed by Tom Rix
parent 1b34f00c28
commit 98250e8e17
12 changed files with 825 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

47
cpu/arm920t/at91/Makefile Normal file
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@ -0,0 +1,47 @@
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(SOC).a
SOBJS += lowlevel_init.o
COBJS += reset.o
COBJS += timer.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
all: $(obj).depend $(LIB)
$(LIB): $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

164
cpu/arm920t/at91/lowlevel_init.S Normal file
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/*
* Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
* Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
*
* Modified for the at91rm9200dk board by
* (C) Copyright 2004
* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#include <asm/arch/hardware.h>
#include <asm/arch/at91_mc.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_pio.h>
#define ARM920T_CONTROL 0xC0000000 /* @ set bit 31 (iA) and 30 (nF) */
_MTEXT_BASE:
#undef START_FROM_MEM
#ifdef START_FROM_MEM
.word TEXT_BASE-PHYS_FLASH_1
#else
.word TEXT_BASE
#endif
.globl lowlevel_init
lowlevel_init:
ldr r1, =AT91_ASM_PMC_MOR
/* Main oscillator Enable register */
#ifdef CONFIG_SYS_USE_MAIN_OSCILLATOR
ldr r0, =0x0000FF01 /* Enable main oscillator */
#else
ldr r0, =0x0000FF00 /* Disable main oscillator */
#endif
str r0, [r1] /*AT91C_CKGR_MOR] */
/* Add loop to compensate Main Oscillator startup time */
ldr r0, =0x00000010
LoopOsc:
subs r0, r0, #1
bhi LoopOsc
/* memory control configuration */
/* this isn't very elegant, but what the heck */
ldr r0, =SMRDATA
ldr r1, _MTEXT_BASE
sub r0, r0, r1
add r2, r0, #80
pllloop:
/* the address */
ldr r1, [r0], #4
/* the value */
ldr r3, [r0], #4
str r3, [r1]
cmp r2, r0
bne pllloop
/* delay - this is all done by guess */
ldr r0, =0x00010000
/* (vs reading PMC_SR for LOCKA, LOCKB ... or MOSCS earlier) */
lock:
subs r0, r0, #1
bhi lock
ldr r0, =SMRDATA1
ldr r1, _MTEXT_BASE
sub r0, r0, r1
add r2, r0, #176
sdinit:
/* the address */
ldr r1, [r0], #4
/* the value */
ldr r3, [r0], #4
str r3, [r1]
cmp r2, r0
bne sdinit
/* switch from FastBus to Asynchronous clock mode */
mrc p15, 0, r0, c1, c0, 0
orr r0, r0, #ARM920T_CONTROL
mcr p15, 0, r0, c1, c0, 0
/* everything is fine now */
mov pc, lr
.ltorg
SMRDATA:
.word AT91_ASM_MC_EBI_CFG
.word CONFIG_SYS_EBI_CFGR_VAL
.word AT91_ASM_MC_SMC_CSR0
.word CONFIG_SYS_SMC_CSR0_VAL
.word AT91_ASM_PMC_PLLAR
.word CONFIG_SYS_PLLAR_VAL
.word AT91_ASM_PMC_PLLBR
.word CONFIG_SYS_PLLBR_VAL
.word AT91_ASM_PMC_MCKR
.word CONFIG_SYS_MCKR_VAL
/* here there's a delay */
SMRDATA1:
.word AT91_ASM_PIOC_ASR
.word CONFIG_SYS_PIOC_ASR_VAL
.word AT91_ASM_PIOC_BSR
.word CONFIG_SYS_PIOC_BSR_VAL
.word AT91_ASM_PIOC_PDR
.word CONFIG_SYS_PIOC_PDR_VAL
.word AT91_ASM_MC_EBI_CSA
.word CONFIG_SYS_EBI_CSA_VAL
.word AT91_ASM_MC_SDRAMC_CR
.word CONFIG_SYS_SDRC_CR_VAL
.word AT91_ASM_MC_SDRAMC_MR
.word CONFIG_SYS_SDRC_MR_VAL
.word CONFIG_SYS_SDRAM
.word CONFIG_SYS_SDRAM_VAL
.word AT91_ASM_MC_SDRAMC_MR
.word CONFIG_SYS_SDRC_MR_VAL1
.word CONFIG_SYS_SDRAM
.word CONFIG_SYS_SDRAM_VAL
.word CONFIG_SYS_SDRAM
.word CONFIG_SYS_SDRAM_VAL
.word CONFIG_SYS_SDRAM
.word CONFIG_SYS_SDRAM_VAL
.word CONFIG_SYS_SDRAM
.word CONFIG_SYS_SDRAM_VAL
.word CONFIG_SYS_SDRAM
.word CONFIG_SYS_SDRAM_VAL
.word CONFIG_SYS_SDRAM
.word CONFIG_SYS_SDRAM_VAL
.word CONFIG_SYS_SDRAM
.word CONFIG_SYS_SDRAM_VAL
.word CONFIG_SYS_SDRAM
.word CONFIG_SYS_SDRAM_VAL
.word AT91_ASM_MC_SDRAMC_MR
.word CONFIG_SYS_SDRC_MR_VAL2
.word CONFIG_SYS_SDRAM1
.word CONFIG_SYS_SDRAM_VAL
.word AT91_ASM_MC_SDRAMC_TR
.word CONFIG_SYS_SDRC_TR_VAL
.word CONFIG_SYS_SDRAM
.word CONFIG_SYS_SDRAM_VAL
.word AT91_ASM_MC_SDRAMC_MR
.word CONFIG_SYS_SDRC_MR_VAL3
.word CONFIG_SYS_SDRAM
.word CONFIG_SYS_SDRAM_VAL
/* SMRDATA1 is 176 bytes long */
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */

59
cpu/arm920t/at91/reset.c Normal file
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@ -0,0 +1,59 @@
/*
* (C) Copyright 2002
* Lineo, Inc. <www.lineo.com>
* Bernhard Kuhn <bkuhn@lineo.com>
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Alex Zuepke <azu@sysgo.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/at91_st.h>
void board_reset(void) __attribute__((__weak__));
void reset_cpu(ulong ignored)
{
at91_st_t *st = (at91_st_t *) AT91_ST_BASE;
#if defined(CONFIG_AT91RM9200_USART)
/*shutdown the console to avoid strange chars during reset */
serial_exit();
#endif
if (board_reset)
board_reset();
/* Reset the cpu by setting up the watchdog timer */
writel(AT91_ST_WDMR_RSTEN | AT91_ST_WDMR_EXTEN | AT91_ST_WDMR_WDV(2),
&st->wdmr);
writel(AT91_ST_CR_WDRST, &st->cr);
/* and let it timeout */
while (1)
;
/* Never reached */
}

163
cpu/arm920t/at91/timer.c Normal file
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@ -0,0 +1,163 @@
/*
* (C) Copyright 2002
* Lineo, Inc. <www.lineo.com>
* Bernhard Kuhn <bkuhn@lineo.com>
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Alex Zuepke <azu@sysgo.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/io.h>
#include <asm/hardware.h>
#include <asm/arch/at91_tc.h>
#include <asm/arch/at91_pmc.h>
/* the number of clocks per CONFIG_SYS_HZ */
#define TIMER_LOAD_VAL (CONFIG_SYS_HZ_CLOCK/CONFIG_SYS_HZ)
static u32 timestamp;
static u32 lastinc;
int timer_init(void)
{
at91_tc_t *tc = (at91_tc_t *) AT91_TC_BASE;
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
/* enables TC1.0 clock */
writel(1 << AT91_ID_TC0, &pmc->pcer); /* enable clock */
writel(0, &tc->bcr);
writel(AT91_TC_BMR_TC0XC0S_NONE | AT91_TC_BMR_TC1XC1S_NONE |
AT91_TC_BMR_TC2XC2S_NONE , &tc->bmr);
writel(AT91_TC_CCR_CLKDIS, &tc->tc[0].ccr);
/* set to MCLK/2 and restart the timer
when the value in TC_RC is reached */
writel(AT91_TC_CMR_TCCLKS_CLOCK1 | AT91_TC_CMR_CPCTRG, &tc->tc[0].cmr);
writel(0xFFFFFFFF, &tc->tc[0].idr); /* disable interupts */
writel(TIMER_LOAD_VAL, &tc->tc[0].rc);
writel(AT91_TC_CCR_SWTRG | AT91_TC_CCR_CLKEN, &tc->tc[0].ccr);
lastinc = 0;
timestamp = 0;
return 0;
}
/*
* timer without interrupts
*/
void reset_timer(void)
{
reset_timer_masked();
}
ulong get_timer(ulong base)
{
return get_timer_masked() - base;
}
void set_timer(ulong t)
{
timestamp = t;
}
void __udelay(unsigned long usec)
{
udelay_masked(usec);
}
void reset_timer_masked(void)
{
/* reset time */
at91_tc_t *tc = (at91_tc_t *) AT91_TC_BASE;
lastinc = readl(&tc->tc[0].cv) & 0x0000ffff;
timestamp = 0;
}
ulong get_timer_raw(void)
{
at91_tc_t *tc = (at91_tc_t *) AT91_TC_BASE;
u32 now;
now = readl(&tc->tc[0].cv) & 0x0000ffff;
if (now >= lastinc) {
/* normal mode */
timestamp += now - lastinc;
} else {
/* we have an overflow ... */
timestamp += now + TIMER_LOAD_VAL - lastinc;
}
lastinc = now;
return timestamp;
}
ulong get_timer_masked(void)
{
return get_timer_raw()/TIMER_LOAD_VAL;
}
void udelay_masked(unsigned long usec)
{
u32 tmo;
u32 endtime;
signed long diff;
tmo = CONFIG_SYS_HZ_CLOCK / 1000;
tmo *= usec;
tmo /= 1000;
endtime = get_timer_raw() + tmo;
do {
u32 now = get_timer_raw();
diff = endtime - now;
} while (diff >= 0);
}
/*
* This function is derived from PowerPC code (read timebase as long long).
* On ARM it just returns the timer value.
*/
unsigned long long get_ticks(void)
{
return get_timer(0);
}
/*
* This function is derived from PowerPC code (timebase clock frequency).
* On ARM it returns the number of timer ticks per second.
*/
ulong get_tbclk(void)
{
return CONFIG_SYS_HZ;
}

4
cpu/arm920t/cpu.c
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@ -33,6 +33,10 @@
#include <command.h>
#include <asm/system.h>
#ifdef CONFIG_AT91_LEGACY
#warning Your board is using legacy AT91RM9200 SoC access. Please update!
#endif
static void cache_flush(void);
int cleanup_before_linux (void)

23
doc/README.at91-soc
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@ -39,3 +39,26 @@ The method for updating
3. add new structures for SoC access
4. Convert arch, driver and boards file to new SoC
5. remove legacy code, if all boards and drives are ready
Join AT91 and AT91RM9200 SoC
==============================
Approximately 95 percent of AT91 and AT91RM9200 SoC parts are the same.
So, we should use the chance, to join both archs togetter.
To do this follow step needed:
1. change Makefile
@$(MKCONFIG) $(@:_config=) arm arm920t board vendor at91rm9200
to
@$(MKCONFIG) $(@:_config=) arm arm920t board vendor at91
2. remove CONFIG_AT91_LEGACY in board config
3. convert boards file to new SoC access
4. convert or change drivers
To support the joining process, a new SoC dir (at91) has been adding to
arm920t arch directory. This directory contains files like at91rm9200 dir, but
uses the new c structure Soc access. The advantage of this is, we don't merge
old Soc access code and new code while the board are not converted.
Finally we can delete the whole at91rm9200 dir, if all board support the
new AT91-SoC access.

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include/asm-arm/arch-at91/at91_mc.h Normal file
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/*
* Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef AT91_MC_H
#define AT91_MC_H
#define AT91_ASM_MC_EBI_CSA (AT91_MC_BASE + 0x60)
#define AT91_ASM_MC_EBI_CFG (AT91_MC_BASE + 0x64)
#define AT91_ASM_MC_SMC_CSR0 (AT91_MC_BASE + 0x70)
#define AT91_ASM_MC_SDRAMC_MR (AT91_MC_BASE + 0x90)
#define AT91_ASM_MC_SDRAMC_TR (AT91_MC_BASE + 0x94)
#define AT91_ASM_MC_SDRAMC_CR (AT91_MC_BASE + 0x98)
#ifndef __ASSEMBLY__
typedef struct at91_ebi {
u32 csa; /* 0x00 Chip Select Assignment Register */
u32 cfgr; /* 0x04 Configuration Register */
u32 reserved[2];
} __attribute__ ((packed)) at91_ebi_t;
#define AT91_EBI_CSA_CS0A 0x0001
#define AT91_EBI_CSA_CS1A 0x0002
#define AT91_EBI_CSA_CS3A 0x0008
#define AT91_EBI_CSA_CS4A 0x0010
typedef struct at91_sdramc {
u32 mr; /* 0x00 SDRAMC Mode Register */
u32 tr; /* 0x04 SDRAMC Refresh Timer Register */
u32 cr; /* 0x08 SDRAMC Configuration Register */
u32 ssr; /* 0x0C SDRAMC Self Refresh Register */
u32 lpr; /* 0x10 SDRAMC Low Power Register */
u32 ier; /* 0x14 SDRAMC Interrupt Enable Register */
u32 idr; /* 0x18 SDRAMC Interrupt Disable Register */
u32 imr; /* 0x1C SDRAMC Interrupt Mask Register */
u32 icr; /* 0x20 SDRAMC Interrupt Status Register */
u32 reserved[3];
} __attribute__ ((packed)) at91_sdramc_t;
typedef struct at91_smc {
u32 csr[8]; /* 0x00 SDRAMC Mode Register */
} __attribute__ ((packed)) at91_smc_t;
#define AT91_SMC_CSR_RWHOLD(x) ((x & 0x7) << 28)
#define AT91_SMC_CSR_RWSETUP(x) ((x & 0x7) << 24)
#define AT91_SMC_CSR_ACSS_STANDARD 0x00000000
#define AT91_SMC_CSR_ACSS_1CYCLE 0x00010000
#define AT91_SMC_CSR_ACSS_2CYCLE 0x00020000
#define AT91_SMC_CSR_ACSS_3CYCLE 0x00030000
#define AT91_SMC_CSR_DRP 0x00008000
#define AT91_SMC_CSR_DBW_8 0x00004000
#define AT91_SMC_CSR_DBW_16 0x00002000
#define AT91_SMC_CSR_BAT_8 0x00000000
#define AT91_SMC_CSR_BAT_16 0x00001000
#define AT91_SMC_CSR_TDF(x) ((x & 0xF) << 8)
#define AT91_SMC_CSR_WSEN 0x00000080
#define AT91_SMC_CSR_NWS(x) (x & 0x7F)
typedef struct at91_bfc {
u32 mr; /* 0x00 SDRAMC Mode Register */
} __attribute__ ((packed)) at91_bfc_t;
typedef struct at91_mc {
u32 rcr; /* 0x00 MC Remap Control Register */
u32 asr; /* 0x04 MC Abort Status Register */
u32 aasr; /* 0x08 MC Abort Address Status Reg */
u32 mpr; /* 0x0C MC Master Priority Register */
u32 reserved1[20]; /* 0x10-0x5C */
at91_ebi_t ebi; /* 0x60 - 0x6C EBI */
at91_smc_t smc; /* 0x70 - 0x8C SMC User Interface */
at91_sdramc_t sdramc; /* 0x90 - 0xBC SDRAMC User Interface */
at91_bfc_t bfc; /* 0xC0 BFC User Interface */
u32 reserved2[15];
} __attribute__ ((packed)) at91_mc_t;
#endif
#endif

14
include/asm-arm/arch-at91/at91_pio.h
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@ -19,17 +19,21 @@
#define AT91_ASM_PIO_RANGE 0x200
#define AT91_ASM_PIOC_ASR \
(AT91_PIO_BASE + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x70)
#define AT91_ASM_PIOC_BSR \
(AT91_PIO_BASE + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x74)
#define AT91_ASM_PIOC_PDR \
(AT91_PIO_BASE + AT91_PIO_PORTC*AT91_ASM_PIO_RANGE + 0x04)
(AT91_PIO_BASE + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x04)
#define AT91_ASM_PIOC_PUDR \
(AT91_PIO_BASE + AT91_PIO_PORTC*AT91_ASM_PIO_RANGE + 0x60)
(AT91_PIO_BASE + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x60)
#define AT91_ASM_PIOD_PDR \
(AT91_PIO_BASE + AT91_PIO_PORTD*AT91_ASM_PIO_RANGE + 0x04)
(AT91_PIO_BASE + AT91_PIO_PORTD * AT91_ASM_PIO_RANGE + 0x04)
#define AT91_ASM_PIOD_PUDR \
(AT91_PIO_BASE + AT91_PIO_PORTD*AT91_ASM_PIO_RANGE + 0x60)
(AT91_PIO_BASE + AT91_PIO_PORTD * AT91_ASM_PIO_RANGE + 0x60)
#define AT91_ASM_PIOD_ASR \
(AT91_PIO_BASE + AT91_PIO_PORTD*AT91_ASM_PIO_RANGE + 0x70)
(AT91_PIO_BASE + AT91_PIO_PORTD * AT91_ASM_PIO_RANGE + 0x70)
#ifndef __ASSEMBLY__

46
include/asm-arm/arch-at91/at91_st.h Normal file
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@ -0,0 +1,46 @@
/*
* Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef AT91_ST_H
#define AT91_ST_H
typedef struct at91_st {
u32 cr;
u32 pimr;
u32 wdmr;
u32 rtmr;
u32 sr;
u32 ier;
u32 idr;
u32 imr;
u32 rtar;
u32 crtr;
} __attribute__ ((packed)) at91_st_t ;
#define AT91_ST_CR_WDRST 1
#define AT91_ST_WDMR_WDV(x) (x & 0xFFFF)
#define AT91_ST_WDMR_RSTEN 0x00010000
#define AT91_ST_WDMR_EXTEN 0x00020000
#endif

77
include/asm-arm/arch-at91/at91_tc.h Normal file
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@ -0,0 +1,77 @@
/*
* Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef AT91_TC_H
#define AT91_TC_H
typedef struct at91_tcc {
u32 ccr; /* 0x00 Channel Control Register */
u32 cmr; /* 0x04 Channel Mode Register */
u32 reserved1[2];
u32 cv; /* 0x10 Counter Value */
u32 ra; /* 0x14 Register A */
u32 rb; /* 0x18 Register B */
u32 rc; /* 0x1C Register C */
u32 sr; /* 0x20 Status Register */
u32 ier; /* 0x24 Interrupt Enable Register */
u32 idr; /* 0x28 Interrupt Disable Register */
u32 imr; /* 0x2C Interrupt Mask Register */
u32 reserved3[4];
} __attribute__ ((packed)) at91_tcc_t;
#define AT91_TC_CCR_CLKEN 0x00000001
#define AT91_TC_CCR_CLKDIS 0x00000002
#define AT91_TC_CCR_SWTRG 0x00000004
#define AT91_TC_CMR_CPCTRG 0x00004000
#define AT91_TC_CMR_TCCLKS_CLOCK1 0x00000000
#define AT91_TC_CMR_TCCLKS_CLOCK2 0x00000001
#define AT91_TC_CMR_TCCLKS_CLOCK3 0x00000002
#define AT91_TC_CMR_TCCLKS_CLOCK4 0x00000003
#define AT91_TC_CMR_TCCLKS_CLOCK5 0x00000004
#define AT91_TC_CMR_TCCLKS_XC0 0x00000005
#define AT91_TC_CMR_TCCLKS_XC1 0x00000006
#define AT91_TC_CMR_TCCLKS_XC2 0x00000007
typedef struct at91_tc {
at91_tcc_t tc[3]; /* 0x00 TC Channel 0-2 */
u32 bcr; /* 0xC0 TC Block Control Register */
u32 bmr; /* 0xC4 TC Block Mode Register */
} __attribute__ ((packed)) at91_tc_t;
#define AT91_TC_BMR_TC0XC0S_TCLK0 0x00000000
#define AT91_TC_BMR_TC0XC0S_NONE 0x00000001
#define AT91_TC_BMR_TC0XC0S_TIOA1 0x00000002
#define AT91_TC_BMR_TC0XC0S_TIOA2 0x00000003
#define AT91_TC_BMR_TC1XC1S_TCLK1 0x00000000
#define AT91_TC_BMR_TC1XC1S_NONE 0x00000004
#define AT91_TC_BMR_TC1XC1S_TIOA0 0x00000008
#define AT91_TC_BMR_TC1XC1S_TIOA2 0x0000000C
#define AT91_TC_BMR_TC2XC2S_TCLK2 0x00000000
#define AT91_TC_BMR_TC2XC2S_NONE 0x00000010
#define AT91_TC_BMR_TC2XC2S_TIOA0 0x00000020
#define AT91_TC_BMR_TC2XC2S_TIOA1 0x00000030
#endif

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include/asm-arm/arch-at91/at91rm9200.h Normal file
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@ -0,0 +1,135 @@
/*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __AT91RM9200_H__
#define __AT91RM9200_H__
/* Periperial Identifiers */
#define AT91_ID_SYS 1 /* System Peripheral */
#define AT91_ID_PIOA 2 /* PIO port A */
#define AT91_ID_PIOB 3 /* PIO port B */
#define AT91_ID_PIOC 4 /* PIO port C */
#define AT91_ID_PIOD 5 /* PIO port D BGA only */
#define AT91_ID_USART0 6 /* USART 0 */
#define AT91_ID_USART1 7 /* USART 1 */
#define AT91_ID_USART2 8 /* USART 2 */
#define AT91_ID_USART3 9 /* USART 3 */
#define AT91_ID_MCI 10 /* Multimedia Card Interface */
#define AT91_ID_UDP 11 /* USB Device Port */
#define AT91_ID_TWI 12 /* Two Wire Interface */
#define AT91_ID_SPI 13 /* Serial Peripheral Interface */
#define AT91_ID_SSC0 14 /* Synch. Serial Controller 0 */
#define AT91_ID_SSC1 15 /* Synch. Serial Controller 1 */
#define AT91_ID_SSC2 16 /* Synch. Serial Controller 2 */
#define AT91_ID_TC0 17 /* Timer Counter 0 */
#define AT91_ID_TC1 18 /* Timer Counter 1 */
#define AT91_ID_TC2 19 /* Timer Counter 2 */
#define AT91_ID_TC3 20 /* Timer Counter 3 */
#define AT91_ID_TC4 21 /* Timer Counter 4 */
#define AT91_ID_TC5 22 /* Timer Counter 5 */
#define AT91_ID_UHP 23 /* OHCI USB Host Port */
#define AT91_ID_EMAC 24 /* Ethernet MAC */
#define AT91_ID_IRQ0 25 /* Advanced Interrupt Controller */
#define AT91_ID_IRQ1 26 /* Advanced Interrupt Controller */
#define AT91_ID_IRQ2 27 /* Advanced Interrupt Controller */
#define AT91_ID_IRQ3 28 /* Advanced Interrupt Controller */
#define AT91_ID_IRQ4 29 /* Advanced Interrupt Controller */
#define AT91_ID_IRQ5 30 /* Advanced Interrupt Controller */
#define AT91_ID_IRQ6 31 /* Advanced Interrupt Controller */
#define AT91_USB_HOST_BASE 0x00300000
#define AT91_TC_BASE 0xFFFA0000
#define AT91_UDP_BASE 0xFFFB0000
#define AT91_MCI_BASE 0xFFFB4000
#define AT91_TWI_BASE 0xFFFB8000
#define AT91_EMAC_BASE 0xFFFBC000
#define AT91_USART_BASE 0xFFFC0000 /* 4x 0x4000 Offset */
#define AT91_SCC_BASE 0xFFFD0000 /* 4x 0x4000 Offset */
#define AT91_SPI_BASE 0xFFFE0000
#define AT91_AIC_BASE 0xFFFFF000
#define AT91_DBGU_BASE 0xFFFFF200
#define AT91_PIO_BASE 0xFFFFF400 /* 4x 0x200 Offset */
#define AT91_PMC_BASE 0xFFFFFC00
#define AT91_ST_BASE 0xFFFFFD00
#define AT91_ST_BASE 0xFFFFFD00
#define AT91_RTC_BASE 0xFFFFFE00
#define AT91_MC_BASE 0xFFFFFF00
/* AT91RM9200 Periperial Multiplexing A */
/* Port A */
#define AT91_PMX_AA_EREFCK 0x00000080
#define AT91_PMX_AA_ETXCK 0x00000080
#define AT91_PMX_AA_ETXEN 0x00000100
#define AT91_PMX_AA_ETX0 0x00000200
#define AT91_PMX_AA_ETX1 0x00000400
#define AT91_PMX_AA_ECRS 0x00000800
#define AT91_PMX_AA_ECRSDV 0x00000800
#define AT91_PMX_AA_ERX0 0x00001000
#define AT91_PMX_AA_ERX1 0x00002000
#define AT91_PMX_AA_ERXER 0x00004000
#define AT91_PMX_AA_EMDC 0x00008000
#define AT91_PMX_AA_EMDIO 0x00010000
#define AT91_PMX_AA_TXD2 0x00810000
#define AT91_PMX_AA_TWD 0x02000000
#define AT91_PMX_AA_TWCK 0x04000000
/* Port B */
#define AT91_PMX_BA_ERXCK 0x00080000
#define AT91_PMX_BA_ECOL 0x00040000
#define AT91_PMX_BA_ERXDV 0x00020000
#define AT91_PMX_BA_ERX3 0x00010000
#define AT91_PMX_BA_ERX2 0x00008000
#define AT91_PMX_BA_ETXER 0x00004000
#define AT91_PMX_BA_ETX3 0x00002000
#define AT91_PMX_BA_ETX2 0x00001000
/* Port B */
#define AT91_PMX_CA_BFCK 0x00000001
#define AT91_PMX_CA_BFRDY 0x00000002
#define AT91_PMX_CA_SMOE 0x00000002
#define AT91_PMX_CA_BFAVD 0x00000004
#define AT91_PMX_CA_BFBAA 0x00000008
#define AT91_PMX_CA_SMWE 0x00000008
#define AT91_PMX_CA_BFOE 0x00000010
#define AT91_PMX_CA_BFWE 0x00000020
#define AT91_PMX_CA_NWAIT 0x00000040
#define AT91_PMX_CA_A23 0x00000080
#define AT91_PMX_CA_A24 0x00000100
#define AT91_PMX_CA_A25 0x00000200
#define AT91_PMX_CA_CFRNW 0x00000200
#define AT91_PMX_CA_NCS4 0x00000400
#define AT91_PMX_CA_CFCS 0x00000400
#define AT91_PMX_CA_NCS5 0x00000800
#define AT91_PMX_CA_CFCE1 0x00001000
#define AT91_PMX_CA_NCS6 0x00001000
#define AT91_PMX_CA_CFCE2 0x00002000
#define AT91_PMX_CA_NCS7 0x00002000
#define AT91_PMX_CA_D16_31 0xFFFF0000
#define AT91_CPU_NAME "AT91RM9200"
#endif

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include/asm-arm/arch-at91/hardware.h
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#include <asm/sizes.h>
#if defined(CONFIG_AT91RM9200)
#include <asm/arch/at91rm9200.h>
#include <asm/arch-at91/at91rm9200.h>
#elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20)
#include <asm/arch/at91sam9260.h>
#define AT91_BASE_SPI AT91SAM9260_BASE_SPI0